Digital VLSI Design

Lecture 5:
Moving to the Physical Domain
Semester A, 2016-17
Lecturer: Dr. Adam Teman

12/12/2016

Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
please feel free to email adam.teman@biu.ac.il and I will address this as soon as possible.
 1
3 5 6
Moving to 2 4
MSV Hierarchical Power
Physical Design MMMC Floorplanning
Design Design Planning

Moving to Physical Design

2
 Definition and Planning
So, what’s next?
Design and Verification
• We’ve basically finished the Front-End of the design process
Logic Synthesis
and we will now start the Back-End:
• To start, we will move between tools with a logical approach Physical Design
to ones with a physical approach to design implementation.
• Then, we will make a physical foundation for our design Signoff and Tapeout
by drawing up a floorplan.
Silicon Validation
• This will include making decisions where “big” or “important” pieces
will sit, such as IPs, I/Os, Power grids, special routes, etc.
• After that, we can place our gates taking into account congestion and timing.
• With our flip-flops in place, we can go about designing a clock-tree.
• And finally, we can route all our nets, according to DRCs, timing, noise, etc.
• Before tapeout, we will clean things up, verify, etc.
 Definition and Planning

An illustrative view of Physical Design

Design and Verification
Logic Synthesis
Physical Design
Signoff and Tapeout
move to
Silicon Validation
P&R tool

Design Import

Floorplan
Initial floorplan Power Planning Placement
and Pad ring
Placement

CTS

Route

Finish Design

4
Prepare Tapeout Detailed Route Clock Tree Synthesis
 Moving from Logical to Physical Design Import

• Define design (.v) Floorplan

• Define design constraints/targets (.sdc)
Placement
• Define operating conditions/modes (MMMC)
CTS
• Define technology and libraries (.lef)
• Define physical properties (Floorplan) Route

Finish Design

Verilog netlist Physical Design

Flow
GDSII

5
SDC constraints
 Design Import

Moving from Logical to Physical Floorplan

Placement

CTS
• During synthesis, our world view was a bit idealistic. OFF
Route
• We didn’t care about power supplies. 0.9V
Finish Design
• We didn’t care about physical connections/entities. 0.7V 0.9V

• We didn’t care about clock non-idealities.

MV with power gating
• Therefore, in order to start physical implementation: (shut down)
• Define “global nets” and how they connect to physical instances.
• Provide technology rules and cell abstracts (.lef files)
• Provide physical cells, unnecessary for logical functionality:
• Tie cells, P/G Pads, DeCaps, Filler cells, etc.
• Define hold constraints and all operating modes and conditions (MMMC)
• Hold was “easy to meet” with an ideal clock, so we didn’t really check it…
• Set up “low power” definitions, such as voltage domains, power gates, body
taps, etc.

6
 Design Import

More than one operating mode Floorplan

Placement

CTS
• During synthesis, we (usually) target timing for a worst-case scenario. Route

• But, what is “worst-case”? Finish Design

• Intuitively, that would be a slow corner, (i.e., SS, VDD-10%, 125C)

• No need for hold checking, since clock is ideal (No skew = No hold)
• But, what if there is an additional operating mode? Mode TEST_MODE FREQ
• For example, a test (scan) mode. Functional 0 1 GHz
• Do we have to close timing at the same (high) Test 1 10 MHz
clock speed?
• No problem, we’ll just deal with both modes separately
• Prepare an additional SDC and rerun STA/optimization.
set_case_analysis 1 [get_ports TEST_MODE]
create_clock –period [expr TCLK/100] –name TEST_CLK [get_ports TEST_CLK]
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 Design Import

Many, many, corners… Floorplan

Placement

CTS
Mode VDD1 FREQ1 VDD2 FREQ2
• But real SoCs are much more complex: Route
F1 1.2 V 2 GHz 0.8 V 500 MHz
• Many operating modes. Finish Design
F2 0.8 V 400 MHz 0.8 V 400 MHz
• Many voltage domains.
F3 Off Off 0.5 V 50 MHz
• With real clock, need to check hold. TEST 1.2 V 10 MHz 1.2 V 10 MHz
• We easily get to hundreds of corners
• Setup and hold for every mode.
• Hold can be affected by SI 
check hold for all corners
• Temperature inversion – what is the worst case?
• RC Extraction – what is the worst case?
• Leakage – what is the worst case?
• Aaaaarrrrrgggghhhh!
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 Design Import

The corner crisis Floorplan

Placement

• Traditional approach not feasible CTS

Route

Finish Design

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 1
3 5 6
Moving to 2 4
MSV Hierarchical Power
Physical Design MMMC Floorplanning
Design Design Planning

Multi-Mode Multi-Corner
Or how to deal with the corner crisis!

10
 Design Import

Multi-Mode, Multi-Corner Floorplan

Placement

CTS
• MMMC to the rescue! Route

• It’s implemented in a slightly (!) confusing way, Finish Design

but it really simplifies things.

• The basic concept is that we create analysis views that can then be selected for
setup and hold (max and min) constraints.
Analysis View = “Turbo” Analysis View = “Low Power” Analysis View = “Turbo - Hold”

VDD=1.2V VDD=0.5V VDD=1.3V

Freq=2 GHz Freq=50 MHz Freq=2 GHz
Corner=SS Corner=SS Corner=FF
Temp=125 C Temp=125 C Temp= -40 C
OpMode=“Turbo” OpMode=“LP” OpMode=“Turbo”

Setup checks: “Turbo” and “Sleep” Modes

Hold checks: “Turbo – Hold” Mode
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 Design Import

Multi-Mode, Multi-Corner Floorplan

Placement

CTS
• Defining Analysis Views is done in hierarchical fashion. Route

• An analysis view is constructed from a Finish Design

delay corner and a constraint mode.

create_analysis_view –name turbo \
–constraint_mode turbo_mode –delay_corner slow_corner_vdd12
create_analysis_view –name low_power \
–constraint_mode low_power_mode –delay_corner slow_corner_vdd05
create_analysis_view –name turbo_hold \
–constraint_mode turbo_mode –delay_corner fast_corner_vdd13

set_analysis_view –setup {turbo low_power} –hold {turbo_hold}

• A delay corner tells the tool how the delays are supposed to be calculated.
Therefore it contains timing libraries and extraction rules.
• A constraint mode is basically the relevant SDC commands/conditions for the
particular operating mode.
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 Design Import

Multi-Mode, Multi-Corner Floorplan

Placement

CTS
• So now, let’s define the lower levels of the MMMC hierarchy. Route

• A constraint mode is simply a list of relevant SDC files. When you move Finish Design

between analysis views, the STA tool will automatically apply the relevant
constraints to the design.
create_constraint_mode –name turbo_mode –sdc_files {turbo.sdc}
create_constraint_mode –name low_power_mode –sdc_files {low_power.sdc}

• A delay corner is a bit more complex. It comprises a library set an RC corner

and a few other things that we won’t discuss right now.
create_delay_corner –name slow_corner_vdd12 \
–rc_corner {RCmax} –library_set {ss_1p2V_125C}
create_delay_corner –name slow_corner_vdd05 \
–rc_corner {RCmax} –library_set {ss_0p5V_125C}
create_delay_corner –name fast_corner_vdd13 \
–rc_corner {RCmin} –library_set {ff_1p3V_m40C}
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 Design Import

Multi-Mode, Multi-Corner Floorplan

Placement

CTS
• Confused yet? Well, we still have more to go. Route

• A library set is a collection of the .lib characterizations that should be Finish Design

used for timing the relevant gates. This includes the standard cells and
other macros, such as RAMs and I/Os. There also may be special “SI”
characterizations for noise.
create_library_set -name ss_1p2V_125C \
-timing [list ${sc_libs}/ss_1p2V_125.lib ${mem_libs}/ss_1p2V_125.lib \
${io_libs}/ss_1p8V_125.lib] –si ${sc_libs}/ss_1p2V_125.si
• And finally, an RC corner is a collection of the rules for RC extraction.
There may be a “capacitance table” for quick extraction and a “QRC
rulefile” for accurate extraction. The temperature is also defined in the
RC corner, but it is taken into account in the .lib file, as well.
create_rc_corner -name RCmax -cap_table ${tech}/RCmax.CapTbl} -T {125} \
-qx_tech_file ${tech}/RCmax.qrctech
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 Design Import

Multi-Mode, Multi-Corner - Summary Floorplan

Placement

CTS

Route

Finish Design
Constraint
Analysis View 1 Mode 1
Constraint
Mode 1
Analysis View 2 Constraint
Selected Mode 3
Setup Views
Analysis View 3
Library Set 1
Selected Hold Analysis View 4 Library Set 2
Views Library Set 3
Delay
Analysis View 5 Corner 1
Delay
Analysis View 6 Corner 1 RC Corner 1
Delay
Corner 3 RC Corner 2
RC Corner 3

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 Design Import

…So you think that was complicated? Floorplan

Placement

CTS
• What if I have multiple voltage domains? Route

• Now, for example, in a certain operating mode, one inverter is operated Finish Design

at 1.2V, while another one, only a few microns away, is at 0.6V.

• How do I define that library set?
• Even worse…
• What happens if I want to power down a certain module?
• What if I want to power down a module, but retain the state (i.e., the
value stored in the flip flops)?
• How do I transfer data between two voltage domains?
• Arrrrrgggghhhh!

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 1
3 5 6
Moving to 2 4
MSV Hierarchical Power
Physical Design MMMC Floorplanning
Design Design Planning

A bit about
Multiple Voltage Domains
Often referred to as “Low Power Design” Methodologies

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 Design Import

Multiple Domain Design Floorplan

Placement

CTS
• Define power domains Route

• create power domain names Finish Design

• list of cells connected to RAM

VDD1, VDD2,GND1,… IP
• draw the power domains PD1
core
• Place macros PD2
PD3
• Take into account:
• routing congestion ROM
• orientation
• Manual usually better then auto
• Place switches
• For the power down domains
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 Design Import

Multiple Domain Design – Level Shifters Floorplan

Placement

CTS

Route
VDD1 VDD2 logic model Finish Design
IN OUT

VSS

0.7 – 1.08
Dual H-L and L-H level shifter
LS

LS

VDD1
LS

LS

LS
0.9 0.7 VSS
IN OUT a possible
LS
FP view
VDD1
VDD2

VSS

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 Design Import

Multiple Domain Design –VDDPower Gating Floorplan

Placement
Global VDD
CTS
sleep_control (on/off)
Route

Finish Design

VDD VVDD1 VVDD2 VDD

domain domain
VSS

VDD
VDD

VDDV

VDD
Global VDD
VVDD1 VVDD2

VVDD1 VVDD2

VDD VDD

VVDD1 VVDD2

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 Design Import

How do we define this? Floorplan

Placement

CTS
• Well, we probably will leave that to an advanced course or your MSc Route

research… Finish Design

• But, in general, there is a command format for this.

• Well, actually two.
• Cadence calls theirs CPF (Common Power Format), and it’s surprisingly
(…confusingly) similar to MMMC.
• Synopsys calls theirs UPF (Unified Power Format), and it’s surprisingly
similar to SDC.
• I guess neither is very common or unified…
• Luckily for you, we will not talk any more about this right now .
• Instead, we’ll start with the basics of Floorplanning.
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 1
3 5 6
Moving to 2 4
MSV Hierarchical Power
Physical Design MMMC Floorplanning
Design Design Planning

Floorplanning
 Floorplanning Goals and Objectives
Design Import
• Floorplanning is a mapping between
the logical description (the netlist) Floorplan
and the physical description (the floorplan).
Placement
• Goals of floorplanning:
• Arrange the blocks on a chip, CTS
• Decide the location of the I/O pads,
• Decide the location and number of the power pads, Route
• Decide the type of power distribution
• Decide the location and type of clock distribution. Finish Design

• Objectives of floorplanning are:

• Minimize the chip area
• Minimize delay
• Minimize routing congestion
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 Fullchip Design Overview
• Chip size
Core placement
• Number of Gates area

• Number of Metal layers The location of

• Interface to the outside the core, I/O
areas P/G pads
• Hard IPs/Macros and the P/G grid RAM
IP
• Power Delivery P/G
Rings
ROM
Grid
• Multiple Voltages Straps

• Clocking Scheme
Periphery
• Flat or Hierarchical? (I/O) area

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 Design Import

Floorplanning Inputs and Outputs Floorplan

Placement

• Inputs
CTS
• Outputs Route
• Design netlist (required) • Die/block area Finish Design
• Area requirements (required) • I/Os placed
• Power requirements (required) • Macros placed
• Timing constraints (required) • Power grid designed
• Physical partitioning information • Power pre-routing
(required)
• Standard cell
• Die size vs. performance vs. placement areas
schedule trade-off (required)
• I/O placement (optional) • Design ready for
• Macro placement information standard cell placement
(optional)

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 Design Import

IO Ring Floorplan

Placement

CTS
• The pinout is often decided by front-end designers, with input from Route

physical design and packaging engineers. Finish Design

• I/Os do not tend to scale with Moore’s Law IO

and therefore, they are very expensive
(in terms of area).
• I/Os are not only needed for connecting
signals to the outside world, but also to core
provide power
to the chip.
• Therefore, I/O planning is a critical and very
central stage in Floorplanning the chip.
• Let’s leave it at that for a bit, and revisit the I/Os a little later…
26
 Design Import

How do we choose our chip size? Floorplan

Placement

CTS

Route

Finish Design

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 Design Import

Utilization Floorplan

Placement

CTS
• Utilization refers to the percentage of core area that is Route
taken up by standard cells. Finish Design
• A typical starting utilization might be 70%
• This can very a lot depending on the design
Low standard-cell
• High utilization can make it difficult to close a design utilization
• Routing congestion,
• Negative impact during optimization legalization stages.
• Local congestion
• Can occur with pin dense cells like multiplexers, so
utilization is not completely sufficient for determining
die size.
• Run a quick trial route to check for routing congestion
• Refine the synthesis or increase routing resources High standard-cell
utilization
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 Uniquifying the Netlist
• When moving to the physical domain, the netlist must be unique
• A unique netlist, means that each sub-module is only referenced once.
• In the example, the non-unique netlist cannot optimize instance m1/u1 without
changing instance m2/u1
module amod (); bmod module amod1 ();
bmod BUFFD1 u1 ();
BUFFD1 u1 ();
endmodule endmodule
m1 m2 m1 m2
module bmod (); module amod2 ();
amod m1 ; u1 u1 u1 u1 BUFFD1 u1 ();
amod m2 ; endmodule
endmodule
Non-unique Unique module bmod ();
amod1 m1 ;
• A synthesized netlist must be uniquified before placement amod2 m2 ;
endmodule
can begin. This can be done either by the synthesizer or
during design import.
29
 Design Import

Hard Macro Placement Floorplan

Placement

• When placing large macros we must consider impacts on routing,

CTS

Route
timing and power. Usually push them to the sides of the floorplan. Finish Design
• Placement algorithms generally perform better with a single large
rectangular placement area.
• For wire-bond place power hungry macros away from the chip center.
• After placing hard macros, mark them as FIXED.
Possible
routing
congestion
hotspots

30
 Design Import

Placement Regions Floorplan

Placement

CTS
• Sometimes, we want to “help” the tool put certain Route

logic in certain regions or cluster them together. Finish Design

• Place and Route tools define several types of

placement regions:
• Soft guide – try to cluster these cells together
without a defined area.
• Guide – try to place the cells in the defined area.
• Region – must place the cells in the defined area,
but other cells may also be placed there.
• Fence – must place the cells in the defined area and
keep out all other cells.

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 Design Import

Placement Blockages and Halos Floorplan

Placement

CTS
• Placement blockages halos are areas that Route
the tools should not place any cells. Finish Design
Keepout margin
• These, too, have several types:
• Hard Blockage – no cells can be placed
inside.
• Soft Blockage – cannot be used during
placement, but may be used during
optimization. RAM5
• Partial Blockage – an area with lower
utilization.
• Halo (padding) – an area outside a
macro that should be kept clear of
standard cells. Pins are on left
and right
32
 Design Import

Placement Blockages and Halos Floorplan

Placement

CTS

Route

Finish Design

Hard blockage
always created on
all four sides

Soft blockage created

only for the channels
between the macros or
between the macro
and the core boundary

33
 Design Import

Routing Blockage Floorplan

Placement

CTS
• Similar to placement blockage, Route

routing blockage can be defined. Finish Design

• Blockage is defined for a given (75,95)

layer.

Routing
blockage

(20,20)

34
 Design Import

Guidelines for a good floorplan Floorplan

Placement
Use blockage to
Single large improve pin CTS
core area RAMS out of the
way in the corner accessibility Route

Finish Design
Large RAM 1 RAM 2 RAM 3
routing
channels
RAM RAM 4 RAM 5 RAM 6
Avoid
Standard cells area constrictive
channels
RAM

RAM Avoid many pins

•q
in the narrow RAM 8
channel. RAM 7
Rotate for pin
PLL MY_SUB_BLOCK accessibility

Pins away
from corners
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 1
3 5 6
Moving to 2 4
MSV Hierarchical Power
Physical Design MMMC Floorplanning
Design Design Planning

A bit about
Hierarchical Design
Or how do you deal with a really big chip

36
 Design Import

Flat vs. Hierarchical Design

Fullchip Design Floorplan

Placement

Blk 1 Blk 2 Blk 3 CTS

• If the design is too big, partition it into hierarchies Route

• Advantages P&R P&R P&R Finish Design

Flow Flow Flow
• Faster runtime, less memory needed for EDA tools
• Faster eco turn-around time
• Ability to do design re-use Fullchip Timing &
Verification
• Disadvantages
• Much more difficult for fullchip timing closure (ILMs) I/O Pad
• More intensive design planning needed,
IP Macro
feedthrough generation, repeater insertion,
timing constraint budgeting.
Block / Tile

37
 Design Import

Hierarchical Design – Time Budgeting Floorplan

Placement

CTS
• Chip level constraints must be mapped correctly to block level Route

constraints as I/O constraints Finish Design

set_input_delay 1.5 [get_port IN1]
1.5ns IN1

Block Boundary
• Interface Logic Models (ILMs) help simplify and speed-up design

A X A X

B Y B Y

Clk

Original Netlist Interface Logic Model (ILM)

38
 Design Import

Hierarchical Design – Pin Assignment Floorplan

Placement

CTS
• Pin constraints include parameters, such as: Route

• Layers, spacing, size, overlap Finish Design

• Net groups, pin guides

• Pins can be assigned: Pins at partition
corners can make
routing difficult
• Placement-based (flightlines)
• Route-based (trial route,
boundary crossings).
• Pin guides
Pin guide 1
• Can be used to influence automatic
pin placement of particular net groups
Pin guide 2

Partition
39
 Design Import

Hierarchical Design - Feedthrough Floorplan

Placement

• For channel-less designs or designs with limited channel resources

CTS

Route

Finish Design

Net1
I/O Pin IN
Net2
OUT IN

Partition A Partition B Partition C

Feedthrough
Candidates

Net1 Net1a Net1b

I/O Pin IN
Net2 Net2a
OUT IN

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 1
3 5 6
Moving to 2 4
MSV Hierarchical Power
Physical Design MMMC Floorplanning
Design Design Planning

Power Planning
 Design Import

Power Consumption and Reliability Floorplan

Placement

CTS
Dynamic Power IR-Drop /
Route
Voltage Drop
Average Power Finish Design
problem

Static Power Fail

(Leakage Power)
Electromigration
Power density (EM)
problem in the
Floorplan Long run
+
Design of the grid

1 out of 5 chips fail due to excessive power consumption

42
 Design Import

IR Drop Floorplan

Placement

CTS
• The drop in supply voltage over the length of the supply line Route

• A resistance matrix of the power grid is constructed Finish Design

• The average current of each gate is considered

• The matrix is solved for the current at each node,
to determine the IR-drop.

VDD
VDD Pad Ideal voltage level

Minimum
Tolerance
Level
Actual voltage level
43
 Design Import

Electromigration (EM) Floorplan

Placement

CTS
• Electromigration refers to the gradual displacement of the Route

metal atoms of a conductor as a result of the current flowing Finish Design

through that conductor.

• Transfer of electron momentum
• Can result in catastrophic failure do to either
• Open : void on a single wire
• Short : bridging between to wires
• Even without open or short, EM can cause
performance degradation
• Increase/decrease in wire RC

44
 Design Import

Power Distribution More (Wider) Power Lines:

• Less Static (IR) drop
Floorplan

Placement

• Less Dynamic (dI/dt) drop CTS

• Power Distribution Network functions • Less Electromigration Route

• Carry current from pads to transistors on chip Finish Design

BUT
• Maintain stable voltage with low noise
• Provide average and peak power demands
• Provide current return paths for signals More (Wider) Power Lines:
• Avoid electromigration & self-heating wearout • Fewer (signal) routing
• Consume little chip area and wire resources
(i.e., higher congestion)
• Easy to lay out

45
 Design Import

Power Distribution Challenge Floorplan

Placement

CTS
• Assume we have a 1mm long power rail in M1. Route

• Square resistance is given to be 0.1 ohm/square Finish Design

3
• If we make a 100nm wide rail,  10 m
what is the resistance of the wire? R  R L W  0.1  9
100 10 m
 1000

• Now, given a max current of 1mA/1um, due to 1mA

I max  100nm  0.1mA
Electromigration, what is the IR drop when 1μm
conducting such a current through this wire?
IRdrop  I max  Rwire  104 103  100mV

• So what do we do?
• Make the power rails as wide and as thick as possible!

46
 Design Import

Hot Spots Floorplan

Placement

CTS
• We generally map the IR drop of a chip using a color map to Route

highlight “hot spots”, where the IR drop is bad. Finish Design

Source:
Cadence

Initial IR Drop Mapping After adding a single wire!

47
 Design Import

Power and Ground Routing Floorplan

Placement

CTS
• Each standard cell or macro has power and ground Route

signals, i.e., VDD (power) and GND (ground) Finish Design

• They need to be connected as well

• Power/Ground mesh will allow multiple paths
from P/G sources to destinations
• Less series resistance
• Hierarchical power and ground meshes
from upper metal layers to lower metal layers
• Multiple vias between layers
• You can imagine that they are HUGE NETWORKS!
• In general, P/G routings are pretty regular
• P/G routing resources are usually reserved
48
 Design Import

Standard Approaches to Power Routing Floorplan

Placement

CTS
• Power Grid Route
• Interconnected vertical and horizontal power bars. Finish Design
• Common on most high-performance designs.
• Often well over half of total metal on upper thicker layers used for
VDD/GND.
• Dedicated VDD/GND planes.
• Very expensive.
• Only used on Alpha 21264.
• Simplified circuit analysis.
• Dropped on subsequent Alphas.
• Some thoughts/trends:
• P/G I/O pad co-optimization with classic physical design
• Decoupling capacitors to reduce P/G related voltage drop
• Multiple voltage/frequency islands make the P/G problem
and clock distributions more challenging
49
 Design Import

Power Grid Creation Floorplan

Placement

CTS
• Tradeoff IR drop and EM versus Route
routing resources Power lines
Finish Design
• Require power budget
• initial power estimation
• average current, max current density
Mx Mx
• Need to determine
• General grid structure (gating or multi-voltage?) Mx-1 Mx-1
• Number and location of power pads (per voltage)
• Metal layers to be used
• Width and spacing of straps Mx-2 Mx-2
• Via stacks versus available routing tracks
• Rings / no rings
• Hierarchical block shielding
• Run initial power network analysis to confirm design
50 Signal routing area
 Design Import

Power Grid Creation – Macro Placement Floorplan

Placement

CTS

Route

Finish Design

Blocks with the

highest
performance and
highest power
consumption

Close to border power

pads (IR drop)
Away from each other
(EM)

51
 Design Import

Summary – Floorplanning in Encounter Floorplan

Placement

CTS
• In the exercise, we will go over this, hand on, but in general, the Route

floorplanning flow is: Finish Design

• Initialize Design:
• Define Verilog netlist, MMMC (timing, sdc, extraction, etc.), LEF, IO placement
• Specify floorplan
• Define floorplan size, aspect ratio, target utilization
• Place hard macros
• Absolute or relative placement
• Define halos and blockages around macros
• Define regions and blockages
• If necessary, define placement regions and placement blockage
• If necessary, define routing blockage

52
 Design Import

Summary – Floorplanning in Encounter Floorplan

Placement

CTS
• Define Global nets Route
• Tell the tool what the names of the global nets (VDD, GND) are and what their
Finish Design
names are in the IPs.
• Create Power Rings
• Often rings for VDD, GND are placed around the chip periphery, as well as around
each individual hard IP.
• Build Power Grid
• Connect standard cell ‘follow pins’
• Build power stripes on metal layers
• Make sure power connects to hard IPs robustly
• Assign Pins
• If working on a block (not fullchip), assign pins to the periphery of the floorplan.

53
 Main References
• IDESA
• Rabaey
• EPFL Tutorial
• Experience!

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