IEEE INTERNET OF THINGS JOURNAL, VOL. 5, NO.

2, APRIL 2018 1011

An Ultra Low-Power Memristive Neuromorphic

Circuit for Internet of Things Smart Sensors
Arash Fayyazi, Mohammad Ansari , Mehdi Kamal , Ali Afzali-Kusha , and Massoud Pedram

Abstract—In this paper, we propose an ultra low-power ana- Internet. In the second approach, the sensory data are col-
log neuromorphic circuit to be trained to process sensory data in lected and processed in a local low-power processor and only
the Internet of Things smart sensors where low-power and area- the meaningful data is transmitted over the Internet. While
efficient computing is required. To reduce the operating voltage
of the circuit while maintaining the performance, we focus on the first approach provides a more detailed access to the envi-
designing a memristive neuromorphic circuit without employing ronment, it is not suitable for applications where the energy
operational amplifiers. Therefore, we use the CMOS inverters and communicational bandwidth is limited. On the other hand,
as the neurons in our memristive neuromorphic circuit. We also the second approach is effective only in the cases where the
propose ultra low-power mixed-signal input/output interfaces to local processor has a low power (energy) consumption and
make the circuit connectable to other digital components such as
embedded processor. To assess the efficacy of the proposed cir- can perform complex tasks (e.g., recognition). There are sev-
cuit and its interfaces which include memristive neural network eral paradigms to implement such processors. Among the
based A/D and D/A converters, HSPICE simulations are utilized. emerged architectures in this field, neuromorphic processors
The results indicate that at the operating voltage of ±0.25 V, which have been inspired by the amazing brain operation,
at least 108× (278×) reduction in the power consumption of has received much attention [4], [5]. The neuromorphic pro-
the output (input) interface compared to that of the conven-
tional structures is achieved. Additionally, the effectiveness of the cessors, which are energy efficient, high speed, and scalable,
neuromorphic circuit enhanced by the proposed interfaces is eval- have shown a great appropriateness for processing complex
uated under some applications such as image recognition, human tasks such as recognition, clustering, and classification. Also,
behavior analysis, and air quality predictions. The results of the the neuromorphic circuits have tolerance to error and variation
study reveal that the designed neuromorphic circuits, along with which makes them efficient for very large scale integration
the proposed A/D and D/A converters, provide an average power
saving (speedup) of 2960× (37×) over the ASIC implementation implementation [6]. In addition, due to the learning capability
in a 90-nm CMOS technology. of the neuromorphic circuits, it is possible to train a single
smart sensor for different applications such as analyzing the
Index Terms—Internet of Things (IoT), memristor, neuromor-
phic computing, smart sensor. combination of traffic, pollution, weather, and congestion sen-
sory data [7]. The most attractive neuromorphic architecture
is the one based on the artificial neural networks (ANNs) [8].
There are two implementations for the ANNs which are ana-
I. I NTRODUCTION log and digital. The analog ANNs are often faster and more
HE INTERNET of Things (IoT) is a paradigm, which
T aims to bring Internet connectivity to everyday life
objects. This is achieved by equipping the objects with micro-
power efficient compared to the digital implementations [8].
Neurons and synapses are the main components of an
ANN. There are multiple choices for implementing the neu-
controllers, communicational transceivers, and proper protocol ron of the analog neural network circuit such as operational
stacks [1]. The IoT which may be invoked in many applica- amplifiers (op-amps), analog comparators, and inverters. The
tions, such as telemonitoring, telemetry, and healthcare, makes inverter-based implementation would result in lower area and
use of sensors as unavoidable parts. In Fig. 1, two possible power consumption. Also, it has been widely accepted that
approaches to send the sensory data to the client over the memristor can be a promising element for the implementa-
IoT are illustrated [2], [3]. In the first approach, the raw sen- tion of such analog brain-inspired circuits [9]. It is due to
sory data (e.g., temperature, humidity, and image pixels) are its nonvolatile nature, low power consumption, dense fabrica-
converted to digital form and sent to the client side over the tion, and plasticity in resistance [10]. It should be reminded
that memristor is the fourth fundamental circuit element which
Manuscript received August 11, 2017; revised September 28, 2017 relates electric charge (q) and magnetic flux (ϕ) [11] and can
and December 1, 2017; accepted January 23, 2018. Date of publication
January 30, 2018; date of current version April 10, 2018. The work of act as a resistive memory. Since 2008, several fabrications of
A. Fayyazi, M. Ansari, M. Kamal, and A. Afzali-Kusha was supported by the memristor devices have been reported (e.g., [12] and [13]).
Iran National Science Foundation. (Corresponding author: Ali Afzali-Kush.) The resistance of the memristor could be altered by apply-
A. Fayyazi, M. Ansari, M. Kamal, and A. Afzali-Kusha are with the
School of Electrical and Computer Engineering, University of Tehran, ing voltage pulses. The amplitude and duration of the voltage
Tehran 14395-515, Iran (e-mail: a.fayyazi@ut.ac.ir; mo.ansari@ut.ac.ir; pulse determine the amount of the change in the resistance.
mehdikama@ut.ac.ir; afzali@ut.ac.ir). Generally, the amplitude of the applied voltage should be
M. Pedram is with the Department of Electrical Engineering, University of
Southern California, Los Angeles, CA 90089 USA (e-mail: pedram@usc.edu). larger than a threshold voltage (write threshold voltage of the
Digital Object Identifier 10.1109/JIOT.2018.2799948 memristor) to alter the resistance of the memristor [14].
2327-4662 c 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1012 IEEE INTERNET OF THINGS JOURNAL, VOL. 5, NO. 2, APRIL 2018

(a)

(b)

Fig. 1. (a) Raw sensory data transmission. (b) Reducing the communication traffic by transmitting meaningful data only.

There are several structures including memristive

bridge [15] and crossbar [16]–[18] for implementing synaptic
weight storage. In this paper, we propose to use the mem-
ristive crossbar structure as synapses because of its dense
layout [18] and CMOS-inverters as neurons due to their
higher power and area efficiency. In this structure, each row is
connected to an input and each memristor connects a row to
a column. Hence, the voltage (current) of each column could
Fig. 2. Power consumption of a neuromorphic circuit proposed in [19].
be considered as weighted sum of the inputs. Therefore, the
memristor conductances determine the weights.
The neural operations in the memristive crossbar circuit are
essentially made by analog signals of current and conduc- we propose a neural network-based ADC which has the flex-
tance. This requires analog to digital and digital to analog ibility of converting input voltages with different ranges and
converters (ADCs and DACs) to couple the neuromorphic cir- desired resolutions. Due to the feedforward structure of the
cuit to digital components. The conversions, however, make up proposed ADC, it also removes the problem of spurious states
a large portion of the total power consumption and chip area of of the conventional Hopfield ADCs. Finally, the whole neuro-
the reconfigurable digital neuromorphic accelerator or digi- morphic circuit is employed in some IoT applications to show
tal neuromorphic processor [6], [19] as shown in Fig. 2. This its efficacy.
mandates the use of efficient ADCs and DACs for different The contributions of this paper may be listed as follows.
tasks such as synapse readout in these mixed signal systems. 1) Proposing a neuromorphic circuit that accepts digital I/O
There are prior works (e.g., [16] and [17]) in which the capa- and utilizes inverters as neurons and memristive crossbar
bility of memristive structures for implementing the ADC and as synaptic weights.
DAC has been shown. The neural network approach for imple- 2) Extracting an analytical model of the proposed neuro-
menting the ADC and DAC has some advantages over the morphic circuit to be utilized in the training phase.
conventional structures in terms of the area, power efficiency, 3) Proposing a memristive DAC structure without utilizing
and flexibility [20]. However, some problems like spurious active elements to reduce the power consumption and
states and utilization of op-amp, reduce the efficacy of such boost the performance of the neuromorphic circuit.
converters. Therefore, to solve such problems, in this paper, by 4) Proposing a scheme for merging the DAC into the
focusing on inverter-based neuromorphic circuits, we propose neuromorphic circuit to achieve higher DAC resolutions.
a DAC structure which employs memristors to generate the 5) Providing a modified backpropagation algorithm to train
corresponding analog output. This structure could be merged the neuromorphic circuit by considering the circuit level
to the memristive crossbar of the neuromorphic circuit. We constraints.
also provide a modified backpropagation algorithm to comply 6) Proposing a memristive neural network-based ADC
with the proposed structure. This structure is faster and more without oscillations or spurious states, while it has the
power efficient compared to the conventional DAC structure flexibility of converting input voltages with different
considered for using in neuromorphic circuits. Additionally, ranges and desired resolutions.
FAYYAZI et al.: ULTRA LOW-POWER MEMRISTIVE NEUROMORPHIC CIRCUIT FOR IoT SMART SENSORS 1013

Fig. 4. Implementation of synaptic weights for each neuron.

layer, the input of the jth thneuron (netj ) is

N 
 
netj = Vip wjip + Vin wjin . (1)
i=1
Fig. 3. Block diagram of the proposed memristive neuromorphic circuit with
its interfaces.
Based on (1), we propose the circuit of Fig. 4 to imple-
ment a single neuron and its synaptic weights with two CMOS
inverters and a column of the memristive crossbar. Each input
of this circuit (e.g., xi ) is differential which contains inverted
7) Reducing the number of employed memristors in
(Vin ) and noninverted (Vip ) signals. In this circuit, the voltage
the ADC structure compared to the state-of-the-art
of the node netj (the input of the inverter of column j) is
memristor-based ADCs which provides faster and more
power efficient ADC structure. N 
 
The rest of this paper is organized as follows. Section II dis- Vnetj = ζ Vip σjip + Vin σjin (2)
cusses the details of the proposed neuromorphic circuit as well i=1
as DAC and ADC hardware implementations. The efficacy and where σjip (σjin ) is the conductance of the memristor located
accuracy of the proposed neuromorphic circuit is studied in in noninverted (inverted) row i and column j, and Vnetj is the
Section III. Finally, this paper is concluded in Section IV. voltage of the node netj and parameter ζ is defined by
1
ζ =  . (3)
N
i=1 σjip + σjin
II. P ROPOSED N EUROMORPHIC C IRCUIT
The block diagram of a two-layer ANN implemented by Based on (1), two memristors are employed per weight
the proposed memristive neuromorphic structure is shown in which enables implementing both positive and negative
Fig. 3. This structure consists of an input interface, an output weights. In the suggested inverter-based neuromorphic circuit,
interface, a programming interface, and two layers of analog the first inverter acts as activation function and performs the
inverter-based memristive neural network. The weights of the nonlinear operation on the weighted sum. However, because in
ANN are calculated using our proposed training framework this implementation, both positive and negative values of the
which is realized using a software in an off chip machine. neuron output (the input of the neuron in the next layer) are
Before the first usage of the circuit, the calculated weights are needed, another inverter is utilized to generate the noninverted
written to the memristive crossbar through the programming output (Op ). Hence, all of the neurons of this structure, except
interface hardware. The programming interface also initializes the ones in the output layer, include two inverters. It should be
the input and output interfaces. After the weight are written to noted that due to the much higher efficiency of the inverters
the crossbar and the input/output interfaces are initialized, the compared to the op-amps, the inverter-based design, even with
programming interface is turned off and its outputs become complementary inputs, is more efficient. Since a neuron output
float, the ANN is powered on, and normal operation mode of in the output layer is considered as a primary analog output
the circuit begins. The programming interface also includes of the network, one inverter is utilized for this neuron. In this
switches (row and column selectors in Fig. 3) to select the paper, the operating voltage of the inverters is ±Vdd /2. Note
proper memristor to write and protect other memristors from that the bias input of the neuron may be implemented by con-
unwanted write. In the rest of this section, the details of these sidering an additional constant input for the neuron. Also, in
components, as well as the method for training the neural order to map the neural network weights to the neuromorphic
network are discussed. circuit, we equate (1) and (2).

B. Input Interface
A. Neuron Circuit With Memristive Synapses The input interface should convert the input digital sig-
Assume a neural network layer with Vip , Vin (i = 1, . . . , N) nals to analog ones, hence, a DAC is needed. There are
inputs and wjip , wjin synaptic weights. In this neural network several implementations for DAC (e.g., [19], [20], and [22]).
1014 IEEE INTERNET OF THINGS JOURNAL, VOL. 5, NO. 2, APRIL 2018

Fig. 5. Memristive DAC structure with resistive load (e.g., memristor

crossbar).

In order to reduce the power consumption while maintaining

the performance, we suggest implementing the DAC without
active components such as op-amp. The proposed n-bit DAC Fig. 6. Dividing DAC into multiple parts and merging it into the
neuromorphic circuit for higher resolutions.
structure is depicted in Fig. 5. In this structure, the voltage
of the digital inputs of the DAC (D0 − D2n−1 ) are scaled and
accumulated in the node A0 through the binary weighted resis- and finally
tors (R, 2R, . . . , 2n−1 R) which could be implemented using
memristors in a small area. The voltage of the analog output 2n − 1 α
R < Rmax = × × RLoad . (11)
node may be found from the KCL equation of 2n−1 n(1 − α)
 VA0 − VDi
n−1 Hence, in designing the DAC, the R value should be selected
nVA0
+ =0 (4) based on RLoad and α. In the cases where Rmax is smaller than
RLoad 2n−1−i R the minimum resistance of the available memristor, we should
i=0
where VDi is the voltage of the ith digital input, and RLoad employ memristors with minimum resistance in parallel. It is
is the equivalent load resistance of the memristive crossbar noteworthy that due to the compactness and small layout size
driven by the DAC. Using (4), one may found (real) VA0 as of the memristor, the overhead area of using parallel memris-
  tors is much smaller than the area occupied by the transistors
n−1 VDi
i=0 2n−1−i R of an op-amp.
VA0 =  . (5)
n
RLoad + n−1 1
i=0 2n−1−i R
The resistance of the binary weighted memristors grows
exponentially when the resolution of DAC increases
On the other hand, in the ideal DAC (without loading),
(R, 2R, . . . , 2n−1 R). Since the resistance of the memristors
input/output voltage relation is given by
are limited (bounded between the maximum and minimum

n−1
VA0 − VDi resistances), a large number of memristors may be needed. To
ideal
= 0. (6)
2n−1−i R overcome this problem, for higher resolutions, we suggest that
i=0
the memristive branches of DAC grouped into 4-bit (partial)
Which may be used to obtain ideal VA0 as clusters and use a second stage for combining the results of
n−1 VDi n−1 i
i=0 n−1−i 2 V Di the partial clusters.
VA0ideal = n−1 2 1 R = i=0 . (7) The second stage of the DAC (which is considered as the
i=0 n−1−i
(2 − 1)
n
2 R last stage) is merged into the first layer of the neural network
Hence, the relative error between the ideal and real outputs as shown in Fig. 6. In order to train the neural network, the
of the DAC is expressed by model of the DAC circuit is extracted and the correspond-
VA0ideal − VA0 ing analog outputs to digital inputs are computed. In this
Error =
VA0ideal approach, the outputs of DAC are considered as inputs for the
VA0 neural network. Based on these inputs and target outputs, the
= 1−
VA0ideal neuromorphic circuit is trained by employing the backpropa-
n gation algorithm [23] and function mapped weights [24]. The
RLoad
= n−1 . (8) training algorithm determines proper memristor states.
n
RLoad + 1
i=0 2n−1−i ,R
Assuming that the input error tolerance of the neural C. Modified Backpropagation Algorithm
network is α, the maximum value of R (Rmax ) may be To train the neural network, we utilize a circuit aware train-
determined from ing framework where the backpropagation algorithm of [23]
n
RLoad was modified to consider the physical characteristics of the
n−1 < α. (9)
n
+ 1 neuromorphic circuit. While the modified algorithm maintains
RLoad i=0 2n−1−i .R
the integrity of the gradient descent search in the backprop-
Rearranging the above inequality, one finds agation algorithm, it also effectively deals with the physical
n (2n − 1) constraints in the memristive circuits, such as the limited range
(1 − α) < α (10)
RLoad 2n−1 .R of memristor conductance.
FAYYAZI et al.: ULTRA LOW-POWER MEMRISTIVE NEUROMORPHIC CIRCUIT FOR IoT SMART SENSORS 1015

The backpropagation algorithm employs the gradient and for each hidden layer as
descent optimization approach to minimize the cost function ⎡ ⎤
and determines the network weights [23]. The cost function      
(i.e., J) may be defined by wijkp = ηfj netj ⎣ i+1 ⎦ 
δm g wmj g wijkp Oki−1
p
m∈(i+1)th layer
 2
J= tj − OLj (12) (18)
j
where f is the activation function, and g (wijk ) is defined by
p
where tj is the expected output of the jth neuron of the last (∂g(wijk ))/(∂wijk ). Also, δm is the portion of error of the kth
p p
layer and L represents the last layer. neuron of output layer, and Om and tm are the actual and
In this case, the output of the jth neuron in ith layer is target output of the mth neuron. Finally, netm is the weighted
defined by sum of the inputs of the mth neuron. After the training phase,
  the calculated weights should be deployed to the memristive
 i i
i−1 i−1
Oj = f j
i i
wjkp Okp + wjkn Okn + βp bp + β bn
i i i i
(13) crossbar. Although the above equations have been expressed
n
k for the case of the P weights, very similar equations may be
written for the N weights.
where fji is the activation function of the jth neuron in ith layer After the training phase, the weights should be written to
and wijk (wijk ) is the weight from the kth (inverted) neuron the memristive crossbar. In this paper, the scheme of [25] is
p n
in the (i − 1)th layer to the jth neuron in the ith layer. Also, assumed to be implemented in the programming interface for
bip (bin ) is the bias in the ith layer and βpi (βni x) is its correspond- writing the memristors. It solves the problems of device varia-
ing weight. In this paper, VDD /2 (−V DD /2) is considered for tion and stochastic write and has the relative accuracy of 1%.
the bias bip (bin ) in all layers. Also, the memristor model proposed in [14] for the device
The weight updating rule (for the case of the P weights) of [13] which has a good endurance and retention is utilized.
may be defined by In this model, the I–V characteristic (and hence the conduc-
tance) of the memristor is determined by its state variable.
wijkp new = wijkp old + ηwijkp (14) Therefore, the extracted conductance values should be mapped
to the corresponding state parameter of the memristor for the
where wijk is the weight after updating, wijk is the weight use in the SPICE simulations. The I–V characteristic of the
p new p old
before updating, wijk
is change value, and η is the learning memristor model is formulated as [14]
p
rate. In order to address the physical constraints, we propose 
a1 .x(t).sinh(b.V(t)), V(t) ≥ 0
using a weight mapping function. To employ this method, the I(t) = (19)
function which maps the unconstrained ANN weights to the a2 .x(t).sinh(b.V(t)), V(t) < 0
implementation weights (memristor conductance in this paper) where b, a1 , and a2 are the fitting parameters and x(t) is the
was incorporated in the update rules of the backpropaga- state variable. For this element, the I–V relation is not linear
tion algorithm. Since the value of the memristor conductance making the mapping of the conductance σ to the state variable
should be between a minimum (σmin ) and a maximum (σmax ) x not very easy (σ (t) = I(t)/V(t)). To simplify the extraction
value (both of them are greater than zero) and also we need of x from σ , we suggest employing the first two terms of the
a continuously differentiable weight mapping function (which Taylor series of (19). Based on this approximation which has
can be utilized in updating rule), we select a biased binary a maximum error of only 0.1%, I(t) may be expressed as
sigmoid function as g which is defined by ⎧  
  ⎨ a1 x(t) bV(t) + b3 V 3 (t) , V(t) ≥ 0
K  6 
g wijkp = σmin + (15) I(t) = (20)
−wi ⎩ a2 x(t) bV(t) + b3 V 3 (t) , V(t) < 0
1 + e jkp 6

where σjki = g(wijk ) and K is a constant number and is equal and σ (t) as
p p
to the difference between the σmax and σmin . ⎧  
⎨ b+ b3 V 2 (t)
For applying the proposed restriction approach in backprop- I(t) a1 x(t)
 6 , V(t) ≥ 0
σ (t) = = (21)
agation algorithm, the output model of neuron [i.e., (13)] is V(t) ⎩ a2 x(t) b + b3 V 2 (t)
, V(t) < 0.
6
modified to
  Since σ (t) depends on V(t) which is determined by the
    
Oij = fji g wijkp Oki−1
p
+ g wijkn Oki−1
n
+ βpi bip + βni bin . inputs of the neuromorphic circuit and memristor conductance
k values (weights), additional simulations are required to deter-
(16) mine V(t). In order to make σ (t) independent of V(t) and
2 /2 instead
reduce the training time, here, we suggest using Vmax
Based on (16), for the output layer, the weight change value of V (t) where Vmax is the maximum voltage which could be
2
may be written as applied across each memristor. This voltage is smaller than
     the circuit operating voltage which is less than 1 V in cur-
wLjkp = ηf j netj tj − OLj g wjkp OkL−1
p
(17) rent technologies. Since the parameter b is small (typically
1016 IEEE INTERNET OF THINGS JOURNAL, VOL. 5, NO. 2, APRIL 2018

0.05) [14], and hence b3  b, the error of this approximation

is negligible. Using this explanation, (21) is rewritten as
⎧  
⎨ a1 x(t) b + b3 Vmax
2
1 , V(t) ≥ 0
σ (t) = =  2 
12
(22)
R(t) ⎩ a2 x(t) b + b3 Vmax
, V(t) < 0.
12

In this paper, based on our experiments, we consider the

values of 200 K for the RLoad and 0.1 for the parameter
α. Using these values in (11) yields Rmax equal to 10.4 K.
Also, the memristors used in this paper have the minimum
resistance value of ∼125 K [13]. Thus, as mentioned before,
to realize proper resistance values, the memristors with the
minimum value may be used in parallel. More specifically,
for implementing R, 16 memristors in parallel which provide
a resistance value of 7.8 K are utilized. Also, note that the
voltage of VDi is smaller than the write threshold voltage of the
memristors to avoid unwanted write to the memristors during
the D/A conversion. We also assume that the circuit of [25],
which has the relative accuracy of 1%, is used for writing the
memristors. Note that due to the using of feedback in this write
circuit, the effects of memristors variations are compensated. Fig. 7. (a) LTNN ADC neural network model, (b) reconstructed LTNN
structure to show its feedforward nature, and (c) the implementation of the
LTNN ADC using memristor and CMOS inverter. Note that the biases are
removed in our proposed circuit by choosing differential supply voltage and
D. Output Interface modifying the weights of the neural network.
To transmit the generated analog outputs of the proposed
ANN, they should be converted to digital form. Therefore,
an ADC should be employed. We propose a memristive The net weights for the LTNN weight matrix may be
inverter-based implementation of neural network ADC. Our defined as
structure is based on low triangle neural network ADC (LTNN  j
ADC [26], [27]) which avoids the problem of spurious states −2 , for j>i
Tij = (23)
of Hopfield ADC. An n bit LTNN ADC, which is shown in 0, for j≤i

Fig. 7(a), has n neurons and its design is based on the method Ii = − x − 2 ,
i
i = 0, 1, 2, . . . , n − 1 (24)
of successive approximation. At the beginning, the most sig-
nificant bit is determined and then the approximation becomes where Tij is the conductance of the memristor which connects
finer and finer as successive bits are determined continuing the the output of the jth neuron to the input of the ith neuron of
sequence until the least significant bit (LSB) is determined. ADC, and x is the analog voltage to be converted. Also, Ii is
Thus, specifying the value of an output bit requires the infor- the input bias current of the neuron iwhich could be provided
mation of the higher bits determined earlier. Therefore, the ith through the memristor of (relative) conductance 1 connected to
bit neuron has non zero weights coming from only the higher the input voltage x and through the memristor of conductance
bit neurons, and hence, the weight matrix of the network is 2i connected to a −1V reference potential [28].
lower triangular. We use an inverter as the activation function for the neurons
This network does not have any feedback due to this lower of the ADC network. This is due to its lowest power con-
triangular structure and is essentially a feedforward network. sumption and smallest delay among the conventional analog
This feedforward nature of LTNN ADC is apparent if it is implementations of the activation functions (including com-
restructured as in Fig. 7(b). Obviously, like any feedforward parator or op-amp). It switches when the voltage on their
neural network, the LTNN ADC will not have a problem of inputs equal to (Vdd + Vss )/2 where Vdd and Vss are the pos-
oscillations or spurious states, as for a given analog input, there itive and negative supply voltages, respectively. Note that Vss
will be a unique output state for all the neurons regardless of equals −V dd in the differential mode. Therefore, the biases and
the initial conditions of the neurons. Consequently, they are their corresponding (connected) weights can be removed since
useful when continuous conversion is required [26], [27]. In inverter imposed a bias due to its switch point ((V dd +Vss )/2).
addition, LTNN ADC guarantees to find the global optimum Also, since the analog input voltage range of the LTNN in [28]
solution [26], [27], and unlike the structure of [20], there is is [0,2n − 1] while in the case of our neuromorphic circuit,
no need for an additional reset state before each conversion. the range of the input voltage (denoted by x) of the ADC is
Also, it should be noted that, for both LTNN and Hopfield [0, Vdd ] (single-ended) or [−Vdd /2, Vdd /2] (differential), the
ADCs, the delay increases linearly with number of bits owing input weights must be multiplied by 2n /Vdd where n is the
to the fact that both have n neurons for an n-bit resolution. resolution of the ADC. Therefore, for an n-bit proposed LTNN
FAYYAZI et al.: ULTRA LOW-POWER MEMRISTIVE NEUROMORPHIC CIRCUIT FOR IoT SMART SENSORS 1017

TABLE I
AVERAGE D ELAY AND P OWER C ONSUMPTION OF THE P ROPOSED DAC
S TRUCTURE C OMPARED TO THE T WO S TATE - OF - THE -A RT DAC

ADC [Fig. 7 (c)] the weights are determined by

(a)

−2j ,
for j > i
Tij = (25)
0, for j ≤ i
 n
Ii = − 2 /Vdd x, i = 0, 1, 2, . . . , n − 1. (26)

III. R ESULTS AND D ISCUSSION

In this section, first, we evaluate the accuracy and
performance of the proposed DAC and ADC which are used
in input and output interfaces, respectively. Then, we assess
the efficacy of the proposed neuromorphic circuit utilizing
the input/output interfaces under five applications. Next, the (b)
robustness of the proposed circuit in the presence of weight
uncertainty (which is due to the memristor parameters vari- Fig. 8. (a) DNL and (b) INL of the proposed 4-bit DAC structure.
ations and stochastic write operation) is studied. Finally, the
effectiveness of the proposed neuromorphic circuit in a range
of operating voltage levels is evaluated. All the HSPICE
simulations of this section have been performed using the B. A/D Converter (Output Interface)
memristor model provided in [14] and in a 90-nm technology. We perform HSPICE circuit simulations to validate the
Additionally, the parasitic effects of the write circuit switches functionality of the proposed ADC by implementing a 4-bit
were considered in the simulations by adding large inverters LTNN ADC. The analog input voltage range in this experiment
(5× larger than a minimum sized inverter) to each row and was from −0.25 V to 0.25 V (corresponding to the considered
column of the circuit. Note that the write circuit is off during inverter-based neuromorphic circuit) leading to the conversion
the normal work of the neuromorphic circuit. step size of 0.03125 V. In the proposed structure, the max-
imum resistance is 8× larger than the minimum resistance,
while in the circuit of [20], the maximum resistance is 64×
A. D/A Converter (Input Interface) larger than the minimum resistance. This ratio is important
First, the delay and power consumption of the proposed because the maximum and minimum resistance of the mem-
4-bit DAC structure are compared to the delays and powers of ristors are limited by the physical constraints and the minimum
the DAC structure proposed in [19] and [20]. For the average resistance in the circuit should be kept high enough to prevent
power, we consider all the input combinations. The results, excessive loading on the inverters. The input voltage and the
which are given in Table I, show that the proposed memris- corresponding digital output code of the neural-based ADC are
tive DAC consumes 278× lower power than the one in [20] shown in Fig. 9. Also, the worst-case delay for the conversa-
with active components. Additionally, the proposed structure tion was about 3.9 ns and the average total power (including
has a substantially lower delay compared to those of DACs leakage and dynamic power) was 6.4 μW for power supplies
proposed in [19] and [20]. The smaller delay may be mainly of +0.25 and −0.25V. The power and delay measurements
attributed to the small RC delays of the binary weighted mem- are performed using transient HSPICE simulation of the cir-
ristors as well as the memristive crossbar and small parasitic cuit by applying stepwise analog inputs ranging from Vss to
capacitances of the inverters. Also, the differential nonlinear- Vdd to the circuit.
ity (DNL) (the maximum deviation of an actual analog output Table II compares the average power consumption and con-
step, between adjacent input codes, from the ideal step value version time of the proposed ADC with those of the ADC
of 1 LSB [29]) and integral nonlinearity (INL) (the maximum in [20] and some common non-neural structures used as ADC
deviation, at any point in the transfer function, of the out- in [4] and [15]. The power consumption of the proposed cir-
put voltage level from its ideal value [29]) of the proposed cuit is at least 100× smaller than that of the other designs
memristive DAC structure is depicted in Fig. 8(a) and (b), while its delay is only 0.9 ns higher than that of the flash
respectively. ADC. Additionally, compared to the other ADC designs, our
1018 IEEE INTERNET OF THINGS JOURNAL, VOL. 5, NO. 2, APRIL 2018

Fig. 10. (a) Input image of the Sobel filter. (b) Original output of the Sobel
filter. (c) Output of the designed neuromorphic circuit.

Fig. 9. Transfer characteristics of the 4-bit memristive LTNN ADC.

TABLE II
C IRCUIT L EVEL C HARACTERISTICS OF THE P ROPOSED ADC S TRUCTURE

(a) (b)

Fig. 11. (a) Circuit speedup and (b) power saving of the designed neuromor-
phic circuits over their digital ASIC counterparts for different applications.
Note that figures are depicted in logarithmic scale.

deployed on the field in an Italian city. Hourly responses aver-

ages are recorded along with gas concentrations references
from a certified analyzer [32].
proposed ADC has the lowest area due to the fact that it has the Table III shows the configuration, delay, power, energy per
lowest neuron area (using inverter instead of op-amp or com- operation, and accuracy of the extracted inverter-based mem-
parator) as well as the lowest numbers of memristor among ristive neuromorphic circuits in each studied application. The
the state-of-the-art neural-based ADCs. accuracy of the circuits for approximate computing applica-
tions (i.e., FFT, Sobel, and Air Quality) is reported in terms
of the mean square error (MSE) while for the classification
C. Proposed Neuromorphic Circuit applications, it is reported in terms of the classification accu-
In this section, we evaluate the effectiveness of the proposed racy (CA). Also, in the configuration column, the first and
inverter-based neuromorphic circuits under several applica- last numbers show the number of input and output bits of
tions. This circuit was employed as a neuromorphic processor the neuromorphic circuit, respectively. The middle numbers
in a smart sensor node. MNIST classification [30], the kernel represent the number of neurons of each layer of the neural
part of two approximate computing applications from Axbench network. Additionally, the delay and power consumption have
package [31], a time-series regression application [32], and been extracted by the HSPICE simulations for the supply volt-
time-series mobile health (MHealth) dataset [33] were cho- age levels of ±0.25 V. The measured MSE of the HSPICE
sen to be run on the neuromorphic circuit. We have used the simulation output shows the accuracy of the proposed cir-
input data provided in the Axbench package, MHealth, and Air cuit. Also, note that the reported delays include DAC, neural
Quality dataset for training (80% of data samples) and test- network, and ADC delays. It also should be noted that in the
ing (20% of data samples). In the case of MNIST application, classification applications, due to the fact that the desired out-
1000 of 14 × 14 pixel images, which were compressed forms puts have only two values, the ADC stage could be bypassed
of the 28 by 28 images in the MNIST database, were utilized (see Fig. 3) and turned off to save power.
for the training and testing. The MHealth dataset comprises As the results reveal, the neuromorphic circuit, which is
body motion and vital signs recordings from ten volunteers trained for MNIST application, has the largest power con-
of diverse profile while performing several physical activi- sumption since it has the largest number of inputs and outputs.
ties. Sensors placed on the subject’s chest, right wrist, and left Also, the results show small delay, and very small power, and
ankle are used to measure the motion experienced by diverse energy per operation for the designed neuromorphic circuits.
body parts, namely, acceleration, rate of turn, and magnetic Note that the number of the elements in the critical delay
field orientation [33]. The Air Quality dataset contains the path of the memristive ANN is a function of the number of
responses from an array of five metal oxide chemical sen- ANN layers (not the number of its neurons). As an example,
sors embedded in an air quality chemical multisensor device for all of the ANNs in this paper (which have one hidden
FAYYAZI et al.: ULTRA LOW-POWER MEMRISTIVE NEUROMORPHIC CIRCUIT FOR IoT SMART SENSORS 1019

TABLE III
E VALUATED B ENCHMARKS , THE T RAINED N EURAL N ETWORK C ONFIGURATION , AND HSPICE S IMULATION R ESULTS

TABLE IV
layer), regardless of the size of the network, the delay path C OMPARISON OF W RITE O PERATION IN M EMRISTIVE
contains only two memristors and three inverters. Therefore, A RRAY AND SRAM C ACHE
the delay of the circuit does not change considerably by chang-
ing the size of the network. Also, the total power consumption
of the proposed neuromorphic circuit with DAC and ADC
is even less than that of the previously proposed DACs and
ADCs provided in Tables I and II. On average, the delay,
power, and energy per operation of the extracted neuromor-
phic circuits (including DAC and ADC stages) were 6.3 ns,
815.4 μW, and 196.8 fJ, respectively. It should be noted that lower than those of the ASIC design. For instance, Table IV
the reported small MSE values have a negligible effect on compares the write operation of each weight in a 32 × 8 bit
the final output of the benchmark whose kernel part is per- SRAM cache and a 32 × 8 memristive crossbar (considering
formed by the proposed neuromorphic circuit. For instance, as an average of 12 consecutive writes for precise tuning of each
shown in Fig. 10, the error (image difference [19]) of the final weight [25]).
image generated from the neuromorphic circuit (using the val-
ues from accurate HSPICE simulation) is only 7% compared D. Effect of Process Variation, Limitted Write Precision, and
to the original Sobel filter [31]. Input Noise
Next, in Fig. 11, the delay and power of the memristive For the most of the applications, the output accuracy (e.g.,
neuromorphic circuit are compared with those of the corre- MSE or CA) strongly depends on how accurately the resistive
sponding ANN ASIC implementation. For obtaining the power state can be set during the actual fabrication since there is
and delay results of the digital ASIC designs, Synopsis Design considerable variability in this process [25]. Thus, to show the
Compiler tool was used. The ASIC designs were fully com- effect of this uncertainty on the accuracy of the neuromorphic
binational where 256 × 8 bit LUTs were used to implement circuit, we added random noises to the conductance of all of
the ASIC neurons. To make the ASIC design as similar as the memristors in the network and measured the network error
possible to the memristive ANN, one LUT is used for imple- in the presence of these changes. The varied conductance was
menting each neuron to make the design completely parallel. defined by
The weighted sum of the inputs is considered as the 8-bit
ConductanceNoisy = (1 + σ X)ConductanceNormal (27)
address input of the LUT which is programmed such that its
8-bit output is equal to the sigmoid function of its address where X is a random number that has Gaussian distribution
input. The comparison reveals that using the proposed cir- with standard deviation of σ and mean of 0 (X ∼ N[0, 1]).
cuit results in considerable power savings while improving For this paper, the considered memristor variations (i.e., σ )
the performance over the fully digital ASIC design based on were 5%, 10%, and 20% of the nominal values of the con-
the 90-nm CMOS technology. It is noteworthy that due to ductance and 500 Monte Carlo samples where simulated. The
consecutive write operations in the memristive ANN (which values of the CA and MSE of the network outputs in the
is needed for precise tuning of weights [25]), its initialization presence of memristor variation are illustrated in Fig. 12. As
may be slower than that of the ASIC design. However, the ini- the results show, with 20% memristor variation, the average
tialization energy and power of the memristive design are still MSE is still below 0.009 for all of the approximate computing
1020 IEEE INTERNET OF THINGS JOURNAL, VOL. 5, NO. 2, APRIL 2018

(a) (b)

Fig. 12. (a) CA and (b) MSE of inverter-based memristive neuromorphic circuits in presence of process variation, input noise, and considering limited write
precision of the memristor.

applications. Also, the maximum CA degradation due to the

considered variations for MNIST and MHealth applications is
about 2%. To assess the effect of the electrical noise on the
analog parts of the circuit, we injected a random noise with
σ = 30 mV at the analog inputs of the circuit (outputs of the
DAC stage) and measured the accuracy of the circuits under
this condition. The results, which are shown in Fig. 12, reveal
that even in the presence of the injected noise, the accuracy of
the circuit remains higher than 93%. Also, the MSE remains (a) (b)
below 0.008 for all of the applications. Finally, in order to
examine the effect of the limited write precision of memris-
tors, we quantized the conductance of memristors with 4-bit
precision. As Fig. 12 demonstrates, the limited write precision
of the memristors has a very small effect on the accuracy
of the circuit. Fig. 12 also shows that even with considering
all of these effects together (process variation, limited write
precision, and input noise), the accuracy of the circuit is still
above 92%. Note that, as mentioned before, the error of writ- (c) (d)
ing on memristors by employing the circuit proposed in [25]
is below 1%. Hence, the impact of the memristor variabil- Fig. 13. Effect of supply voltage scaling on (a) delay, (b) power, (c) MSE,
ity on the output accuracy of the network is negligible. Also, and (d) energy per operation of the proposed neuromorphic circuit. Note that
the values are normalized based on the measured parameters at 0.5 V rail-to-
there are some algorithms (e.g., [35] and [36]) that could be rail supply voltage.
used to decrease the effect of process variation, not only in
the memristors but also in the CMOS inverters. For exam-
ple, in [36], the neurons (CMOS inverters) characteristics were values are normalized based on those of the circuit operat-
extracted from the manufactured chip, and then, the network ing at supply voltage of 0.5 V (i.e., ±0.25 V). The results
weights of chip were adjusted based on the extracted infor- reveal that decreasing the supply voltage by 300 mV reduces
mation. Finally, to compensate the resistance shifting issue of power consumption by about 11× and made a 5× increase in
the bias memristors, which is caused by their constant passing the delay of the circuit. Since the circuit was trained at 0.5-V
current direction [37], the low-cost inline calibration scheme supply voltage, the minimum MSE was achieved in this supply
of [38] may be implemented in the programming interface. voltage and due to the supply voltage scaling, a small incre-
ment in MSE was observed. Also, the energy decreased with
E. Supply Voltage Scaling decreasing the supply voltage. However, for the supply volt-
For energy harvesting applications, it is important for IoT ages below 0.3 V the energy was increased with decreasing
nodes to be operable in a wide range of supply voltage levels. the supply voltage due to the considerable delay increase.
To examine the tolerance of the proposed neuromorphic cir-
cuit under supply voltage scaling, we have swept the rail to IV. C ONCLUSION
rail supply voltage of the circuit from 0.2 V to 0.8 V. In this In this paper, we presented an ultra low-power memristive
paper, the neuromorphic circuit which was trained for the FFT neuromorphic circuit based on the circuit of [39] that may be
application at 0.5-V supply voltage has been considered. The deployed in IoT. We also proposed mixed-signal interfaces,
normalized delay, power, MSE, and energy per operation val- which could be efficiently integrated into the proposed neu-
ues are shown in Fig. 13(a)–(d), respectively. Note that these romorphic circuit. The proposed interfaces that consisted of
FAYYAZI et al.: ULTRA LOW-POWER MEMRISTIVE NEUROMORPHIC CIRCUIT FOR IoT SMART SENSORS 1021

memristive D/A and A/D converters, reduced the area, and [17] C. Yakopcic, R. Hasan, T. M. Taha, M. R. McLean, and D. Palmer,
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1022 IEEE INTERNET OF THINGS JOURNAL, VOL. 5, NO. 2, APRIL 2018

Arash Fayyazi received the B.Sc. degree in elec- Ali Afzali-Kusha received the B.Sc. degree in
trical engineering–electronics from the Ferdowsi electrical engineering from the Sharif University
University of Mashhad, Mashhad, Iran, in 2014, of Technology, Tehran, Iran, in 1988, the M.Sc.
and the M.Sc. degree in electrical engineering– degree in electrical engineering from the University
electronics from the University of Tehran, Tehran, of Pittsburgh, Pittsburgh, PA, USA, in 1991, and
Iran, in 2017. He is currently pursuing the Ph.D. the Ph.D. degree in electrical engineering from
degree at the Ming Hsieh Department of Electrical the University of Michigan, Ann Arbor, MI, USA,
Engineering, University of Southern California, Los in 1994.
Angeles, CA, USA. He was a Post-Doctoral Fellow with the
His current research interests include learning in University of Michigan, from 1994 to 1995. He
neuromorphic hardware, low power designs, and has been with the University of Tehran, since
machine-learning-based VLSI design. 1995, where he is currently a Professor with the School of Electrical and
Computer Engineering and the Director of the Low-Power High-Performance
Nanosystems Laboratory. He was a Research Fellow with the University of
Toronto, Toronto, ON, Canada, and the University of Waterloo, Waterloo,
ON, Canada, in 1998 and 1999, respectively. His current research interests
include low-power high-performance design methodologies from the physical
design level to the system level, new memory, as well as digital design and
Mohammad Ansari was born in Tehran, Iran, in implementation paradigms.
1989. He received the B.Sc. and M.Sc. degrees
in electrical engineering (electronics) from the
University of Tehran, Tehran, in 2011 and 2013,
respectively, where he is currently pursuing the
Ph.D. degree at the Electrical and Computer
Massoud Pedram received the Ph.D. degree in
Engineering Department.
electrical engineering and computer sciences from
His current research interests include neuromor-
the University of California at Berkeley, Berkeley,
phic computing, low power digital designs, SRAM CA, USA, in 1991.
design, and FinFET circuit design.
He is currently the Stephen and
Etta Varra Professor with the Ming Hsieh
Department of Electrical Engineering, University,
Southern California, Los Angeles, CA, USA. He
holds 10 U.S. patents and has authored 4 books,
12 book chapters, and over 140 archival and
350 conference papers. His current research
Mehdi Kamal received the B.Sc. degree in com- interests include low-power electronics, energy-efficient processing, and
puter engineering from the Iran University of cloud computing to photovoltaic cell power generation, energy storage, and
Science and Technology, Tehran, Iran, in 2005, the power conversion, and RT level optimization of very large scale integration
M.Sc. degree in computer engineering from the circuits to synthesis and physical design of quantum circuits.
Sharif University of Technology, Tehran, in 2007, Prof. Pedram and his students were the recipients of six conference
and the Ph.D. degree in computer engineering from and two IEEE T RANSACTIONS Best Paper Awards for research. He was
the University of Tehran, Tehran, in 2013. a recipient of the 1996 Presidential Early Career Award for Scientists and
He is currently an Assistant Professor with the Engineers and an ACM Distinguished Scientist. He currently serves as the
School of Electrical and Computer Engineering, Editor-in-Chief of the ACM Transactions on Design Automation of Electronic
University of Tehran. His current research interests Systems. He has served on the Technical Program Committee of a number of
include reliability in nanoscale design, approximate premiere conferences in his field. He was the founding Technical Program
computing, neuromorphic computing, design for manufacturability, embedded Co-Chair of the 1996 International Symposium on Low-Power Electronics
systems design, and low-power design. and Design and the 2002 International Symposium on Physical Design.