A Hybrid Multilevel Inverter with Both Staircase and PWM Switching Schemes

Hossein Sepahvand Mostafa Khazraei

Student Member, IEEE Student Member, IEEE

Mehdi Ferdowsi Keith Corzine

Member, IEEE Senior Member, IEEE

Missouri University of Science and Technology

Rolla, MO 65409 USA

Abstract—In this paper, a new method to control multilevel industry as they can achieve higher output voltages with low-
converters is proposed. The considered multilevel converter voltage power switches [10, 11]. The cascaded H-bridge
consists of a three-phase three-level diode-clamped converter multilevel converter has been applied to high-power and
(main converter). Two H-bridge cells are then connected in
high-quality applications including static VAR generation
series with each output phase of the main converter. The
operation of the main converter and one of the cascading H- (SVG) [7, 12], active filters, reactive power compensators
bridge cells is based on the staircase switching method. The [13], photovoltaic power conversion [7, 14], and
firing angles of these converters are selected in a way that the dc uninterruptable power supplies (UPS).
voltage required for the last H-bridge cell is minimized. The In this paper, a fifteen-level converter, consisting of a
switching pattern of the second H-bridge cell is based on the
pulse-width modulation method. This last cell generates the three-phase three-level diode-clamped inverter and two series
remaining parts of the desired sinusoidal output voltage. The H-bridge cells on each phase is studied. First, a three-phase
combination of these converters and their switching methods three-level diode-clamped inverter is used as the main
result in an output waveform with low harmonics. Here, a inverter. Then, each phase of the main inverter is cascaded
fifteen-level converter is designed based on this approach. with two H-bridge cells. The main inverter and the first H-
Simulation results and laboratory measurements verify the bridge cell generate a staircase waveform. Their switching
effectiveness of the proposed topology and modulation method.
angles are selected in a way to minimize the voltage level of
Index Terms—Fundamental switching; H-bridge cell; the dc source which is required to feed the second H-bridge
Inverter; Multilevel inverter; Pulse width modulation cell. The second H-bridge cell which operates based on the
pulse-width modulation (PWM) method generates the
I. INTRODUCTION difference between the reference signal and what the main
Multilevel power electronic converters are mainly utilized and first H-bridge converters generate. Minimizing the dc
to synthesize a desired single- or three-phase voltage source required for the second H-bridge cell is accomplished
waveform. The desired output voltage is obtained by by reducing the peaks of the remaining parts of the desired
combining several individual dc voltage sources [1]. In sinusoidal waveform. Simulation results and laboratory
general, by increasing the number of levels, the synthesized measurements verify the effectiveness of the proposed
voltage waveform becomes closer to its sinusoidal reference. topology and modulation method.
The main advantages of such converters are the low harmonic
distortion of the generated output voltage, low II. TOPOLOGY AND SIMULATION OF THE FIFTEEN-LEVEL
electromagnetic emissions, high efficiency, the capability to CONVERTER
operate at higher voltage ranges, and modularity [1-7]. The inverter topology which is used in this paper consists
Furthermore, due to high VA (volt-amp) ratings of multilevel of two cascaded H-bridge cells per phase and a three-phase
converters, they are one of the best choices for electric motor diode-clamped inverter. The topology of the fifteen-level
drives in hybrid power-trains [2, 3, 8, 9]. inverter is shown in Fig. 1. For the sake of simplicity, the H-
In general, multilevel converters are categorized into bridge cells of only one of the phases of the converter are
diode-clamped, flying capacitor, and cascaded H-bridge depicted here. In this topology, the main converter is a diode-
topologies [1, 3-5]. The cascaded H-bridge multilevel clamped three phase inverter fed with a dc voltage source of
converter consists of two or more H-bridge cells connected in 8 . Each phase of the main converter is connected in series
series [1, 6]. These types of converters are widely accepted in with two H-bridge converters to form the final voltage of

978-1-4244-5287-3/10/$26.00 ©2010 IEEE 4364

 7Vdc
H-bridge2

Vdc + 6Vdc

−V3a + 5Vdc

4Vdc

3Vdc

2Vdc

Vdc
π 2π
0
H-bridge1
+ -Vdc
V2a
2Vdc − Va -2Vdc

-3Vdc

-4Vdc

-5Vdc

-6Vdc

-7Vdc

3 Phase
Main Inverter
Fig. 2. Staircase output voltage waveform made by the combination of
the main converter and H-bridge1 along with the desired sinusoidal
8Vdc a +
b
V − waveform
n
c
− 1a

H-bridge2 is the subtraction of the staircase waveform from

the desired sinusoidal waveform.
Fig. 1. Topology of the conveter
The reference of H-bridge2 can be defined as
. . (1)
each phase of the multi-level converter. The voltage source
feeding the second H-bridge is chosen to be one fourth (i.e. where m denotes the modulation index (with a range of 0 to
2 ) of the voltage source of the main converter. Based on 1), is the maximum possible peak output voltage of the
the firing method proposed in this paper, the dc voltage of the converter, is the output voltage of the main converter, and
second H-bridge cell can be as low as half of what feeds the is the output voltage of H-bridge1. In order to generate a
first H-bridge cell (i.e. ). The main converter and the first smooth waveform, H-bridge2 should cover half of the voltage
H-bridge cell (H-bridge1) on each phase operate under the jump changing the state of switches of the main converter and
staircase waveform generation mode. However the second H- H-bridge1 at the instance when equals . For
bridge (H-bridge2) of each phase operates in PWM based this task, a simple method is used by defining a variable as
method of switching. The switching angles of the main and .
the first H- bridge cell are selected in a way to minimize the sin 0.5 (2)
2
voltage of the dc source of the last H-bridge (H-bridge2). The
sum of the output waveforms of the main inverter and H- where floor is a common function that rounds to the nearest
bridge1 ( ) for phase a along with the desired integer toward minus infinity. By this definition
sinusoidal waveform (reference) are shown in Fig. 2. can be described as
.2 2 .2 (3)
A. Selecting dc Voltage Sources for the Converters and where is the status of the main converter and is the
Switching Fundamentals of H-bridge2 status of H-bridge1. Also, , ∈ {−1, 0, 1}. For example,
By selecting the dc voltage source feeding H-bridge1 (see when is -1 the output voltage of the main converter is
Fig. 1) to be one fourth of the dc voltage source feeding the 4 and when is 1 the output voltage of H-bridge2 is
three-phase converter, the maximum output voltage of H- 2 . Table I shows all possible combinations of and
bridge1 will be half of the maximum output voltage of the for each State. When the state is 1 or -1, there are two
main converter with respect to the neutral point (between the possible combinations. In the simulation and experimental
two capacitors). If a staircase switching method is used for section of this paper, the combinations with asterisk signs are
the three-phase inverter and H-bridge1, using these two used. Based on the topology and voltage ratios of the
converters, it is possible to synthesize a seven-level cascaded converters, the maximum voltage that can be
waveform similar to the waveform which is shown in Fig. 2. generated by this converter is 7 ; therefore, 7 .
Since the ultimate goal is to generate a sinusoidal waveform,
B. Simulation Results
the second H-bridge (H- bridge2) can be switched based on a
PWM method to make the remaining parts of the desired The converter is modeled and simulated in
sinusoidal waveform. In other words, the PWM reference for MATLAB/Simulink to verify the operation of the proposed

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 (a)
72
V 1 a (V)

0
-72
0.01 0.02 0.03
(b)
36
V 2 a (V)

-36
0.01 0.02 0.03
(c)
V 1 a +V 2 a (V)

72
0
-72
0.01 0.02 0.03
(d)
PWM Ref (V)

18
0
-18
0.01 0.02 0.03
(e)
18
V 3 a (V)

0
-18
0.01 0.02 0.03
(f)
126
72
V a (V)

0
-72
-126
0.01 0.02 0.03
time (s)

Fig. 3. (a) Main converter output, (b) H-bridge1 output, (c) desired sinusoidal waveform and sum of the main and H-bridge1 converters, (d) PWM reference
of H-bridge2, (e) H-bridge2 output, and (f) total output waveform of phase

TABLE I
ALL COMBINATIONS OF S1 AND S2 FOR EACH STATE
method. Fig. 3 shows the output waveforms of all inverters
for = 18V and m =0.9. In Figs. 3(a) and (b) the output S1 (Main) S2 (H-bridge1)
waveform of the main and H-bridge1 converters are shown, State
weight:×2 weight:×1
respectively. The desired sinusoidal waveform and sum of the 3 1 1
voltages generated by the main and H-bridge1 converters
2 1 0
( ) are shown in Fig. 3(c). Note that the sinusoidal
reference waveform crosses the middle of the jumps in the 0 1
1
staircase waveform. The difference between the desired 1* -1*
output waveform and ( ) is shown in Fig. 3(d). As it 0 0 0
is shown, the maximum value of the PWM reference is 18 V 0 -1
-1
which is . In Figs. 3(e) and (f), the output of H-bridge2 -1* 1*
and the total output of the converter are shown, respectively. -2 -1 0
-3 -1 -1

III. EXPERIMENTAL RESULTS switching frequency for H-bridge2 is 6 kHz. Experimental

In order to verify the simulation results, a hardware result for the converter when m is equal to 0.9 is shown in
prototype of the system is developed. The voltage source of Fig. 4. Fig. 4(a) shows the output of phase a of the converter
the main converter is 144 V. Accordingly, 36 V and 18 V ( ). Fig. 4(b) shows the output waveform of the main
voltage sources are used for H-bridge1 and H-bridge2, converter with respect to the neutral point ( ). Figs. 4(c)
respectively. The control scheme is implemented in a and (d) illustrate the output waveform of H-bridge1 ( ) and
TMS320F2812 digital signal processor (DSP) which is H-bridge2 ( ), respectively. Fig. 5 shows the converter’s
connected to the IGBTs using fiber optic cables. The output voltage when m is equal to 0.75.

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 (a) (a)
120 120
V a (V)

V a (V)
60 60
0 0
-60 -60
-120 -120
0.01 0.02 0.03 0.01 0.02 0.03
(b) (b)
80 80
V 1 a (V)

V 1 a (V)
40 40
0 0
-40 -40
-80 -80
0.01 0.02 0.03 0.01 0.02 0.03
(c) (c)
40 40
V 2 a (V)

V 2 a (V)
0 0
-40 -40
0.01 0.02 0.03 0.01 0.02 0.03
(d) (d)
30 30
V 3 a (V)

V 3 a (V)
0 0

-30 -30
0.01 0.02 0.03 0.01 0.02 0.03
time (s) time (s)

Fig. 4. Experimental results for m=0.9 (a) total output waveform of multi- Fig. 5. Experimental results for m=0.75 (a) total output waveform of
level converter, (b) output waveform of the main converter, (c) output multi-level converter, (b) output waveform of the main converter, (c)
waveform of H-bridge1, and (d) output waveform of H-bridge2 output waveform of H-bridge1, and (d) output waveform of H-bridge2

IV. CONCLUSION
[5] L. Franquelo, J. Rodriguez, J. Leon, S. Kouro, R. Portillo, and M. Prats,
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