(Md. Rabiul Islam MMC Design
(Md. Rabiul Islam MMC Design
(Md. Rabiul Islam MMC Design
Md. RabiulIslam
YouguangGuo
JianguoZhu
Power Converters
for Medium
Voltage
Networks
Green Energy and Technology
More information about this series at http://www.springer.com/series/8059
Md. Rabiul Islam Youguang Guo Jianguo Zhu
13
Md. Rabiul Islam
Youguang Guo
Jianguo Zhu
School of Electrical, Mechanical and
Mechatronic Systems
Faculty of Engineering and Information
Technology
University of Technology Sydney (UTS)
Ultimo
NSW
Australia
Medium and large-scale renewable power plants require large areas of land, and
are usually installed in offshore or remote areas, far from cities, in order to cap-
ture large amount of energy. For power transmission and grid integration, the low
voltage, e.g., 690 V for a typical wind turbine generator, at which the electricity is
generated from renewable energy sources is transformed to the medium-voltage
(e.g., 1133-kV) commonly by using the step-up transformers. In many cases, the
power transformers operated at the frequency of 50/60Hz are heavy, large, and
inefficient. These technological drawbacks would have significant impacts on off-
shore and remote renewable power plants where the costs of installation and regu-
lar maintenance are extremely high.
With the fast development of power electronics, it is becoming a reality to
replace the combination of low voltage inverter and step-up-transformer by a
medium-voltage converter for direct grid connection to reduce the system volume
and weight, as well as the cost. Traditionally, two- and three-level converters are
commonly used for high power applications. When applied to medium-voltage
systems, very expensive semiconductor switching devices of high-voltage ratings
are required. To reduce the cost, multilevel converters made of cascaded switch-
ing devices of relatively low-voltage ratings are developed. In comparison with
the conventional two- and three-level converters, the multilevel converters present
lower switching losses, lower voltage stress on switching devices, and higher qual-
ity output power, and thus suit better the medium-voltage applications. Although
several multilevel converter topologies have been developed in the last few dec-
ades, most of them are not suitable for medium-voltage applications as their
number of auxiliary components scales quadratically with the number of levels.
Because of some special features (e.g., the number of components scales linearly
with the number of levels, and individual modules are identical and completely
modular in construction hence enabling high-level number attainability) the modu-
lar multilevel cascaded (MMC) converter topology can be considered as a possible
candidate for medium voltage applications. However, the MMC converter requires
multiple isolated DC sources that must be balanced, and as a result its application
is not straightforward, especially in wind power generation systems. Moreover,
v
vi Preface
the multilevel converter requires a number of switching and control PWM signals,
which cannot be generated by a digital signal processor (DSP) because the cur-
rently available DSP can only provide about six pairs of PWM channels. In this
instance, a field programmable gate array (FPGA) becomes the natural choice.
Most of the available design techniques require special software such as HDL
coder, System generator, PSIM and ModelSim, which increases the developmental
time and cost.
Chapter 1 of this book discusses various aspects, such as historical growth of
two dominating renewable, i.e., wind and solar, energy sources, the existing tech-
nologies, technical challenges, and possible solutions for large-scale power gen-
eration from these energy sources.
An extensive literature survey has been conducted in Chap.2 focusing on vari-
ous aspects of medium-voltage converter development for step-up-transformer-less
direct grid integration of photovoltaic (PV) power plants. The main objective is
to show how power electronic converter topologies, power electronic devices, and
control complexities have affected the development of medium-voltage converters,
and how to make an excellent choice of the suitable converter topologies for step-
up-transformer-less grid integration through medium-voltage converters, which is
really a critical problem and highly affects the converter performance and cost.
The main aim of Chap.3 is to find out a suitable converter topology, which can
interconnect the renewable generation units directly to the medium-voltage grid
with the commercially available matured semiconductor devices. Different multi-
level converter topologies, such as the neutral point clamped (NPC), flying capaci-
tor (FC), and MMC converters, have been considered and compared for the design
of an 11-kV converter system. The comparison is made in terms of the number of
semiconductors, semiconductor cost and commercial availability, total harmonic
distortions (THDs), filter size and control complexity of the converters. The per-
formance is analyzed and compared in the MATLAB/Simulink environment.
To couple a renewable energy source to the MMC converter, a high-frequency
magnetic-link with multiple secondary windings can be an excellent option and
is explored in Chap.4. The high-frequency magnetic-link is used to generate the
isolated balanced multiple DC supplies for all of the H-bridge inverter cells of
the MMC converter from a single low voltage power source. Compared with the
conventional power frequency transformers operated at 50 or 60Hz, the high-fre-
quency magnetic-links (in the range of a few kilohertz to megahertz) have much
smaller and lighter magnetic cores and windings, and thus much lower costs.
The capability of parallel processing of the FPGA affords the opportunity to
the switching controller to update all gate signals simultaneously. Various design
techniques and software environments are available for the modeling of switching
control schemes with the FPGA technology. Most of the techniques require spe-
cial software, which increases the development time and cost. In Chap.5, the most
common software such as the MATLAB/Simulink and Xilinx ISE-based alterna-
tive design technique is proposed, which may reduce the developmental time and
cost of the switching controller.
Preface vii
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Most Dominating Renewable Power Sources . . . . . . . . . . . . . . . . . . 1
1.1.1 Historical Growth of Wind Power Generation Capacity . . . . 2
1.1.2 Technical Challenges and Possible Solutions . . . . . . . . . . . . 3
1.1.3 Historical Growth of Solar PV Power Generation Capacity. . . 7
1.1.4 Technical Challenges of Solar PV Power
Generation Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.5 Possible Solution to Technical Challenges for
Large-Scale Renewable Generation Systems. . . . . . . . . . . . . 10
1.2 Major Objectives of the Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Contribution of the Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Organization of the Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ix
x Contents
7.2.3
Design and Analysis of 15-Level 11-kV Converter. . . . . . . . 248
7.2.4
Design and Analysis of 19-Level 11-kV Converter. . . . . . . . 250
7.2.5
Design and Analysis of 21-Level 11-kV Converter. . . . . . . . 254
7.2.6
Selection of Number of Levels for 11-kV
Converter Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
7.3 Design and Analysis of 33-kV Converter Systems . . . . . . . . . . . . . . 258
7.3.1 Design and Analysis of 15-Level 33-kV Converter. . . . . . . . 259
7.3.2 Design and Analysis of 23-Level 33-kV Converter. . . . . . . . 261
7.3.3 Design and Analysis of 29-Level 33-kV Converter. . . . . . . . 262
7.3.4 Design and Analysis of 43-Level 33-kV Converter. . . . . . . . 265
7.3.5 Design and Analysis of 55-Level 33-kV Converter. . . . . . . . 270
7.3.6 Selection of Optimal Number of Levels
for 33-kV Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
xiii
xiv Figures
Fig. 3.51 Three reference signals and four level-shifted carrier signals. . . . . 90
Fig. 3.52 Level-shifted modulation technique for a three-phase
seven-level NPC converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Fig. 3.53 Generation of gate pulse PS7 with level-shifted carrier. . . . . . . . . . 92
Fig. 3.54 Generation of gate pulse PS2 with level-shifted carrier. . . . . . . . . . 92
Fig. 3.55 MATLAB/Simulink model to generate
sinusoidal reference signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Fig. 3.56 SPWM modulation scheme for three-phase five-level converter. . . 93
Fig. 3.57 MATLAB/Simulink model to generate third-harmonic
injected sinusoidal reference signals for three-phase
five-level converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Fig. 3.58 Third-harmonic injected pulse width modulation
schemes for three-phase five-level converter. . . . . . . . . . . . . . . . . . 94
Fig. 3.59 MATLAB/Simulink model to generate trapezoidal
reference signals for three-phase five-level converter. . . . . . . . . . . 94
Fig. 3.60 Trapezoidal pulse width modulation schemes for
three-phase five-level converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Fig. 3.61 MATLAB/Simulink model to generate sixty degree
sinusoidal reference signals for three-phase five-level converter . . . 95
Fig. 3.62 Sixty degree pulse width modulation schemes
for three-phase five-level converter. . . . . . . . . . . . . . . . . . . . . . . . . 95
Fig. 3.63 Calculated THD at different level numbers ranging
from seven-level to 19-level [1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Fig. 3.64 Line voltage of five-level neutral point clamped converter. . . . . . . 98
Fig. 3.65 Frequency spectrum of five-level neutral point
clamped converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Fig. 3.66 Line voltage of 11-level neutral point clamped converter. . . . . . . . 99
Fig. 3.67 Frequency spectrum of 11-level neutral point clamped converter. . . 100
Fig. 3.68 Line voltage of five-level flying capacitor converter. . . . . . . . . . . . 100
Fig. 3.69 Frequency spectrum of five-level flying capacitor converter. . . . . . 100
Fig. 3.70 Line voltage of 11-level flying capacitor converter. . . . . . . . . . . . . 100
Fig. 3.71 Frequency spectrum of 11-level flying capacitor converter. . . . . . . 101
Fig. 3.72 Line voltage of five-level modular multilevel cascaded converter. . . 101
Fig. 3.73 Frequency spectrum of five-level modular multilevel
cascaded converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Fig. 3.74 Line voltage of 11-level modular multilevel cascaded converter. . . 102
Fig. 3.75 Frequency spectrum of 11-level modular multilevel
cascaded converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Fig. 3.76 Number of auxiliary devices in NPC and FC converters [32]. . . . . 104
Fig. 3.77 Overall comparisons of multilevel converters [32] . . . . . . . . . . . . . 104
Fig. 4.1 Power circuit of a 3-phase 13-level MMC converter. . . . . . . . . . . . 110
Fig. 4.2 Common magnetic-link-based medium-voltage
converter for wind power generation systems [8] . . . . . . . . . . . . . . 111
Fig. 4.3 Cascaded high-frequency magnetic-link-based
medium-voltage converter for wind power generation systems. . . . 112
xviii Figures
Fig. 5.31 Schematic symbol of the comparator and PWM pulse generator
unit, which also has an output terminal called DBA_L to access
the deadband wave against PWM waves at pwm_L_T
and pwm_L_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Fig. 5.32 Basic block diagram of FPGA-based 5-level converter
control algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Fig. 5.33 Basic block diagram of FPGA-based 3-phase 5-level
converter control circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Fig. 5.34 Gate pulses and deadband signals for switches in phase A,
where the narrow pulses represent the deadband (adjustable
in software environment). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Fig. 5.35 Gate pulses and deadband signals for switches in phase B,
where the narrow pulses represent the deadband (adjustable
in software environment). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Fig. 5.36 Gate pulses and deadband signals for switches in phase C,
where the narrow pulses represent the deadband (adjustable
in software environment). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Fig. 5.37 Assigning I/O pins via I/O port properties. . . . . . . . . . . . . . . . . . . . 177
Fig. 5.38 Assigning I/O pins by dragging into package view. . . . . . . . . . . . . 177
Fig. 5.39 I/O ports viewer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Fig. 5.40 Design summary/report viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Fig. 5.41 Design summary/pinout report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Fig. 5.42 RTL schematic viewer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Fig. 5.43 View technology schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Fig. 5.44 Photograph of FPGA board with PC connection through
USB cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Fig. 5.45 iMPACT process view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Fig. 5.46 Photograph of the FPGA-based switching controller section . . . . . 183
Fig. 5.47 Measured gate pulses for the top H-bridge cell in phase A:
1 left top, 2 left bottom, 3 right top, and 4 right bottom . . . . . . . . . 183
Fig. 5.48 Measured gate pulses for the bottom H-bridge cell in phase A:
1 left top, 2 left bottom, 3 right top, and 4 right bottom . . . . . . . . . 184
Fig. 5.49 Measured gate pulses for the top H-bridge cell in phase B: 1
left top, 2 left bottom, 3 right top, and 4 right bottom. . . . . . . . . . . 184
Fig. 5.50 Measured gate pulses for the bottom H-bridge cell in phase B:
1 left top, 2 left bottom, 3 right top, and 4 right bottom. . . . . . . . . 185
Fig. 5.51 Measured gate pulses for the top H-bridge cell in phase C:
1 left top, 2 left bottom, 3 right top, and 4 right bottom . . . . . . . . . 185
Fig. 5.52 Measured gate pulses for the bottom H-bridge cell in phase C:
1 left top, 2 left bottom, 3 right top, and 4 right bottom . . . . . . . . . 186
Fig. 5.53 Measured phase voltage of a prototype 5-level converter. . . . . . . . 186
Fig. 5.54 Simulated phase voltage of a prototype 5-level converter. . . . . . . . 186
Fig. 6.1 Multi-coil generator-based wind turbine power generation
systems [3, 7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Fig. 6.2 Multiple generator-based wind turbine system: single-phase
layout [6, 7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
xxii Figures
Fig. 7.41 Line voltage frequency spectrum of 19-level MMC converter . . . . 253
Fig. 7.42 Three line voltages of three-phase 19-level MMC converter. . . . . . 253
Fig. 7.43 Current waveform in an IGBT of 19-level MMC converter . . . . . . 253
Fig. 7.44 Semikron 1.7 IGBT module SKM 600GA176D. . . . . . . . . . . . . . . 254
Fig. 7.45 Line voltage of 21-level MMC converter. . . . . . . . . . . . . . . . . . . . . 255
Fig. 7.46 Line voltage frequency spectrum of 21-level MMC converter . . . . 255
Fig. 7.47 Three line voltages of 21-level MMC converter . . . . . . . . . . . . . . . 256
Fig. 7.48 Graphical representation converter performance
parameters [9, 10]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Fig. 7.49 Total performance indexes of different 11-kV MMC converters . . . 257
Fig. 7.50 Phase voltage of 33-kV 15-level MMC converter. . . . . . . . . . . . . . 259
Fig. 7.51 Three line voltages of three-phase 33-kV 15-level MMC
converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Fig. 7.52 Line voltage frequency spectrum of 33-kV 15-level
MMC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Fig. 7.53 Photograph of ABB 6.5-kV IGBT module 5SNA 0400J650100. . . 261
Fig. 7.54 Circuit diagram of a 33-kV 23-level MMC converter. . . . . . . . . . . 262
Fig. 7.55 Phase-shifted carrier-based switching scheme for 23-level
MMC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Fig. 7.56 Phase voltage of 23-level MMC converter. . . . . . . . . . . . . . . . . . . . 263
Fig. 7.57 Line voltages of 23-level MMC converter. . . . . . . . . . . . . . . . . . . . 264
Fig. 7.58 Line voltage frequency spectrum of 23-level MMC converter . . . . 264
Fig. 7.59 Phase voltage of 29-level MMC converter. . . . . . . . . . . . . . . . . . . . 264
Fig. 7.60 Line voltages of 29-level MMC converter. . . . . . . . . . . . . . . . . . . . 265
Fig. 7.61 Line voltage frequency spectrum of 29-level MMC converter . . . . 265
Fig. 7.62 Circuit diagram of a 43-level MMC converter. . . . . . . . . . . . . . . . . 266
Fig. 7.63 Switching control scheme of 43-level MMC converter. . . . . . . . . . 267
Fig. 7.64 Voltage across an IGBT in 43-level 33-kV MMC converter. . . . . . 268
Fig. 7.65 Output voltage of an H-bridge inverter cell in 43-level
33-kV MMC converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Fig. 7.66 Phase voltage of 43-level MMC converter. . . . . . . . . . . . . . . . . . . . 268
Fig. 7.67 Line voltages of 43-level MMC converter. . . . . . . . . . . . . . . . . . . . 269
Fig. 7.68 Line voltage frequency spectrum of 43-level MMC converter . . . . 269
Fig. 7.69 IGBT current of 43-level MMC converter. . . . . . . . . . . . . . . . . . . . 269
Fig. 7.70 Phase voltage of 55-level MMC converter. . . . . . . . . . . . . . . . . . . . 270
Fig. 7.71 Line voltages of 55-level MMC converter. . . . . . . . . . . . . . . . . . . . 270
Fig. 7.72 Line voltage frequency spectrum of 55-level MMC converter . . . . 271
Fig. 7.73 Graphical representation converter parameters [10, 21] . . . . . . . . . 271
Fig. 7.74 Total indexes of different 33-kV converters. . . . . . . . . . . . . . . . . . . 273
Tables
xxvii
xxviii Tables
xxix
xxx Symbols
T Temperature (C)
P Change of PV array output power (W)
V Change of PV array output voltage (V)
Vrms PV inverter output AC voltage (V)
R Reservation factor
VA Minimum PV array voltage (V)
Vdc DC-link voltage of converter (V)
Van, Vbn, Vcn Phase voltages of converter
n Neutral point
a, b, c Terminals of three-phase system
Vcom@100FIT Device commutation voltage for a device reliability
of 100 FIT (V)
m Converter number of levels
m f Frequency modulation index
fm Frequency of reference signals (Hz)
fca Frequency of carrier signals (Hz)
Am Peak to peak amplitude of reference signal
Ac Peak to peak amplitude of carrier signal with
phase-shifting
map Amplitude modulation index with phase-shifting
B n Number of H-bridge inverter cell on a particular
phase leg
ps Carrier phase-shifting (Degree)
mal Amplitude modulation index with level-shifting
Acl Peak-to-peak amplitude of carrier signal with
level-shifting
Vll(rms) Grid line to line voltage (V)
Vdc(min) Minimum voltage of each DC-link capacitor (V)
Vdc(nom) Nominal voltage of each DC-link capacitor (V)
Ip(rms) Converter phase current (A)
Sc Apparent output power of the converter (VA)
nc Number of series-connected flying capacitor cells
Vc Capacitor voltage ripple (V)
Idc Converter DC output current (A)
Id Normalized index value
y Given value
ymin Minimum value
ymax Maximum value
Pcore Core loss (W)
f Frequency (Hz)
B Flux density (T)
k, y, z Coefficients of Steinmetz's equation
Vmax Maximum excitation voltage (V)
max Maximum flux (Wb)
Symbols xxxi
pi
Angular resolution (Degree)
Ln Number of entries for a cycle
Aout Amplitude of the output signal
Phase angle (Degree)
k2 Clock divider value for reference generator unit
Doff Diode off time (s)
Vr(P-P) Peak-to-peak rms output voltage (V)
fs Frequency of the source voltage (Hz)
r Ripple factor
TJ, TC, TA Temperatures of junction, case, and ambient (C)
JA, JC, CS, SA Thermal resistances of total, transistor, insulator,
and heatsink (C/W)
PD Power dissipation (W)
RT, CT Timing resistor and capacitor (, F)
Dmax Desired maximum duty cycle
D% Percentage of duty cycle
Thigh, Thigh Switch on and off time (s)
fH Frequency of the medium frequency inverter (Hz)
Ploss_inv Power losses in the inverter section (W)
Pc_inv, Psw_inv Conduction and Switching losses (W)
Psw_inv_2, Psw_inv_M Switching loss of 2-level and multilevel
converters (W)
fc_2, fc_M Carrier frequencies of 2-level and multilevel con-
verters (Hz)
Pc_sw, Pc_D Conduction losses of IGBT and diode (W)
ma Amplitude modulation index
pf Power factor
Symbols xxxiii
A Ampere
ABB ASEA Brown Boveri
AC Alternating current
ALOs Arithmetic and logic operations
AMSC American Superconductor Corporation
ASIC Application-specific integrated circuit
AUD Australian dollar
BDFM Brushless doubly-fed machine
BSCCO Bismuth strontium calcium copper oxide
DC Direct current
DDS Direct digital synthesis
DFIG Doubly-fed induction generator
DMM Digital Multimeter
DSP Digital signal processor
DTC Direct torque control
DVUF Device voltage utilization factor
EMC Electromagnetic compatibility
EMI Electromagnetic interference
FC Flying capacitor
FPGA Field programmable gate array
g/cm3 Gram per cubic centimeter
GW Gigawatt
HDL Hardware description language
HFT High frequency transformer
HT Height
HTS High temperature superconductor
HVAC High voltage alternating current
HVDC High voltage direct current
Hz Hertz
I/O Input and (or) output
IBM International Business Machines
xxxv
xxxvi Acronyms
IC Integrated circuit
ID Inner diameter
IGBTs Insulated gate bipolar transistors
I-V Current versus voltage
k Kilo
kB Kilobyte
kg kilogram
kHz Kilohertz
km Kilometer
km2 Square kilometer
kV kilovolt
kVA Kilo volt ampere
kVAR Kilo volt ampere reactive
kW Kilo watt
kWh Kilowatt hour
LC Inductor-capacitor
LED Light emitting diode
LEs Logic elements
LUT Look-up table
LVRT Low voltage ride through
m2 Square meter
m3 Cubic meter
MHz Megahertz
MMC Modular multilevel cascaded
MOSFET Metal oxide semiconductor field effect transistor
MPP Maximum power point
MPPT Maximum power point tracker
MRI Magnetic resonance imaging
MVA Mega volt ampere
MW Megawatt
NCD Native circuit description
nF/kWp Nino farad per kilo watt peak
NGD Native generic database
NPC Neutral point clamped
NRE Nonrecurring engineering
OD Outer diameter
PM Permanent magnet
PMG Permanent magnet generator
PMSG Permanent magnet synchronous generator
PV Photovoltaic
P-V Power versus voltage
PWM Pulse width modulation
rms Root mean square
RTL Register transfer level
SCIG Squirrel-cage induction generator
Acronyms xxxvii
xxxix
xl Authors Biography
xli
Chapter 1
Introduction
The energy and environment represent two major areas of current global crisis,
and it is more and more widely recognized that renewable energy sources, espe-
cially wind and solar energy, can offer effective solutions to these enormous chal-
lenges [1] as the wind and solar power development is experiencing dramatic
growth [26]. Over 318GW of wind power generation and over 130GW solar
photovoltaic (PV) power generation have been installed by 2013. Accordingly, the
cumulative growth of wind and solar PV installation has directly pushed the wind
turbine and solar PV converter technologies into a more competitive area [712].
In this propitious climate, it is therefore essential for scientists and engineering
researchers to find the most effective converter technologies for integration of the
wind and solar power generation systems into the main power grids.
Wind speed varies continuously with time and height because of the changes in
the thermal conditions of air masses. The motion of air masses is not only a global
phenomenon but also a regional and local phenomenon. The annual peak hours are
normally around 2,5003,000h at good sites. A wind turbine generator converts
wind energy to electricity energy. If A is the cross-sectional area through which
the air of velocity V flows, and d is the air density, the theoretical power P avail-
able in a wind stream can be calculated from [13, 14]
1
P= d AV 3 . (1.1)
2
Usually, offshore winds tend to flow at higher speeds than onshore winds. This
allows the turbine to produce more electricity as the possible energy produced
from the wind is proportional to the cube of the wind speed. Also unlike onshore
wind, offshore breezes can be strong in the afternoon, matching the time when
load demands are at peak level. Moreover, wind farms cover large areas of land.
The land area covered by a 3.6-MW turbine can be almost 0.37km2, such that
54 turbines would cover about a land area of 20km2. Table1.1 summarizes the
land covered by some offshore wind farms [15]. For example, the Anholt offshore
wind power plant is a Danish offshore wind power plant with nameplate capacity
of 400MW officially inaugurated in September 2013, which covers a land area
of 88km2. It is the third largest offshore wind farm in the world and the largest in
Denmark. Siemens supplied, installed, and commissioned 111 wind turbines, each
with a capacity of 3.6MW and a rotor diameter of 120m. Figure1.1 shows a pho-
tograph of the Anholt offshore wind power plant. Since offshore wind farms can
save land rental expense which is equivalent to 1018% of the total operating and
maintenance costs of a wind farm, offshore-based wind farms have attracted great
attention in the last few years. Considering the wind speed and capacitance effect
of the transmission-line cables, offshore wind turbines are usually installed about
Fig.1.1A photograph of Anholt offshore wind power plant was officially inaugurated in
September 2013 [16]
727km from the shore. Figure1.2 shows an ideal model of smart power systems
with offshore wind farms.
According to the statistical data, the cumulative installed capacity of offshore
wind farms in 2008, 2010, and 2012 is 1.50, 3.08, and 5.41GW, respectively.
The global annually installed capacity of offshore wind farms is summarized in
Table 1.2. The capacity therefore almost doubled in every 2years [18], whereas
the cumulative installed capacity of total (onshore and offshore) wind power gen-
eration in 2008, 2010, and 2012 was substantially less than this at 120.26, 197.68,
and 282.43GW, respectively. The global annually installed capacity of farms is
summarized in Table1.3. It is expected that the global offshore installed capac-
ity will increase to approximately 20GW by 2015 and rise sharply to 104GW
by 2025. According to the Global Wind Energy Council and Green Peace
International estimations, it is possible to mitigate 20% of global electricity
demand with wind power [19].
Fig.1.2An ideal model of renewable power source-based smart power systems [17]
Transformer
Generator Converter
380~690 V
Grid
Pitch
drive
Switching &
turbine control
step up the voltage for long-distance transmission. Figure1.3 shows the traditional
wind turbine with step-up transformer. In an offshore wind turbine power genera-
tion system, this transformer is usually installed at a height of about 80m inside
the nacelle together with other equipment, such as the generator and power con-
verter. The tower provides support to the rotating parts and nacelle (the stationary
parts). The nacelle weight of a 5-MW turbine is about 300t, while the rotor repre-
sents only about 120t. Therefore, the tower diameter and strength depend mostly
on the weight of the nacelle and expected wind loads. The tower cost accounts for
26%, the largest component, of the total turbine component cost [20]. The tower
is normally held by a heavy foundation to ensure that it withstands the overturning
moment created from the turbine. The foundation size of a 2.3-MW wind turbine
is 314m2, and the approximate weight is 2,000t or more [21]. In an offshore area,
the cost of installation is extremely high. On average, approximately 20% of the
capital costs are associated with the installation [22, 23]. During the past decade,
Van Oord has been involved in many offshore wind farm projects in North West
Europe, providing construction services such as foundation and turbine installa-
tion, cable installation, and scour protection. Van Oord has an innovative and
advanced transport and installation vessel named Aeolus. The vessel is 139m
long and 38m wide with a draft of 5.7m. The vessel is equipped with a crane
capable of hoisting 900t at 30m radius and has accommodation for 74 persons.
Aeolus is used for the installation of foundations and turbines. Figure1.4 shows a
photograph of wind turbine installation process. Therefore, a reduction in mechan-
ical loading represents an enormous saving of tower construction and turbine
installation costs. Moreover, regular monitoring and maintenance are also critical
in offshore applications. For example, an offshore wind farm requires about 20%
higher operating and maintenance cost compared with an onshore farm. Figure1.5
shows photograph of offshore wind power plant under maintenance. As the power
rating and the distance of the wind park from the shore increase, the engineering
6 1Introduction
Fig.1.4A photograph of installation process of offshore wind power plant with the vessel
Aeolus [24]
challenges associated with the installation and maintenance of the power genera-
tion systems also grow. Recently, many researchers/scientists have begun to focus
on a number of areas including proposing new converters to eliminate the step-up
transformers, applying medium-frequency transformers to reduce the weight and
volume of step-up transformers, and superconducting wind generators to reduce
the weight and volume of wind turbine generators. These steps are aimed at reduc-
ing the weight and volume of the wind turbine generator system. The weight and
1.1 Most Dominating Renewable Power Sources 7
volume reduction of wind turbine power generation system still needs further
investigation because the wind power has become one of the main renewable
energy sources for future electricity supply within smart microgrids.
Solar energy is the second main renewable energy source for future electricity sup-
ply. Solar PV generates electricity in well over 100 countries and continues to be
the fastest growing renewable resource in the world. By the end of 2011, a total
of 69.68GW PV power capacity had been installed, sufficient to generate around
80billionkWh/year and enough to cover the annual power supply needs for
more than 20million households as reported by European Photovoltaic Industry
Association (EPIA). Solar PV installations substantially increased over the last
5years. The annual installation of new PV power capacity rose from 16.80GW
in 2010 to 29.66GW in 2011, and in 2009, it was only 7.43GW. The globally
installed PV power capacity is summarized in Table1.4 [26]. According to statisti-
cal data, the cumulative installed capacity of solar PV generation in 2007, 2009,
and 2011 was 9.44, 23.21, and 69.68GW, respectively. This means that the capac-
ity of solar PV generation effectively tripled every 2years.
Since 2007, medium- and large-scale PV power plants have attracted great
interest and PV power plants of more than 10MW in capacity have now become
a reality. More than 200 PV power plants have already been installed in the world,
each of them generating an output of more than 10MW. Of these plants, 34 are
located in Spain and 26 in Germany. The number of PV power plants will con-
tinue to rise. The literature indicates that more than 250 PV power plants will be
installed within the next few years [27]. Future PV power plants will have higher
power capacity. Indeed, some are to have a capacity in excess of 250MW. These
multi-megawatt PV power plants require large areas of land. Owing to this, they
are usually installed in remote areas, far from cities. The 20MW PV power plant
in Beneixama, Spain, used about 200 SINVERT 100M inverters and installed
approximately 100,000 PV modules in a land area of 500,000m2 [27]. Therefore,
for power transmission, a medium-voltage grid is usually used. Figure1.6 shows
the photograph of Beneixama 20MW PV power plant.
Although different power electronic converters have been developed in the last few
decades using conventional topologies for solar PV systems, it is hard to connect
the traditional converters to the grids directly as the distortion in generated out-
put voltages is high and a single switch cannot stand at grid voltage level. With
the rapid growth of grid-connected PV generations, the total harmonic distortions
(THDs) generated from PV inverters is becoming a major concern [28]. In this
regard, conventional systems utilizing the power frequency step-up transformer,
filter, and booster not only increase the size, weight, and loss but also increase the
cost and complexity of the system installation and operation. Swiss solar company
Tritec built a PV power plant with 5.2MW of power for the commercial company
Migros. The installation feeds directly from the roofs of the Migros-Verteilbetriebs
1.1 Most Dominating Renewable Power Sources 9
To ensure that the goals of smart grids are met, the current industrial trend is to
move away from these heavy and large-size passive components to compact and
lightweight systems that use more and more semiconductor devices controlled by
advanced digital controls. In comparison with the conventional two-level convert-
ers, multilevel converters present lower switching losses, lower voltage stress on
switching devices, and better power quality. They also enable the development
of medium-voltage converters using matured and cheap power semiconductor
devices. The development of multilevel medium-voltage converters enables the
connection of renewable energy systems directly to the grid without using large,
heavy, and costly power transformers. Although several multilevel converter
topologies have been used in low-voltage applications, most of them are not suit-
able for medium-voltage applications. Because of some special features, such as
the number of components scaling linearly with the number of levels and high-
level number attainability by the use of identical modules, the modular multilevel-
cascaded (MMC) converter topology can be considered as a possible candidate for
medium-voltage applications [31] to connect renewable power generation units to
the medium-voltage grid directly. Since the component number and control com-
plexity increase linearly with the number of levels, the optimal selection of the
number of converter levels is important in order to achieve the best performance/
cost ratio for the medium-voltage converter systems. For example, the 19-level
and 43-level converters are found to be optimal for 11- and 33-kV systems,
respectively [32]. However, the MMC converter requires multiple isolated DC
sources that must be balanced, and therefore, its application is not straightforward,
especially in wind power generation systems [33, 34]. Moreover, the multilevel
converter requires a number of switching and control pulse width modulation
(PWM) signals, which cannot be generated by the available digital signal proces-
sor (DSP) because the available DSP can only at present provide about 6 pairs of
PWM channels. Furthermore, the DSP runs a sequential program in its micropro-
cessor, i.e., all the gate pulses cannot be updated with the same clock pulse [35].
Therefore, the DSP-based system requires an additional control strategy to com-
pensate the time delay [36].
(To the best knowledge of the authors, they are the first who have presented
high-frequency magnetic link to generate multiple isolated and balanced DC
supplies for the MMC converter.)
6. the development and testing within a laboratory of a scaled down high-frequency-
link MMC converter which converters 210V DC into 3-phase 1kVrms 50Hz AC.
(To the best knowledge of the authors, they are the first who have experimen-
tally verified a high-frequency magnetic-link MMC medium-voltage converter
for direct grid integration of renewable generation systems.)
Chapter 2 presents a review of the traditional system, which requires a step-up trans-
former to interconnect the renewable generation systems to the grid, and the other
recently proposed converter topologies for transformer-less grid interconnection in
order to show a complete picture of the importance of size and weight reduction,
and performance improvement of power converter systems. In order to develop a
common converter for both wind and PV power generation systems, after a thorough
investigation of all possible converter topologies covering almost all types of existing
power converters, it is concluded that the multilevel converter topology with high-
frequency magnetic link would be the most feasible option for developing medium-
voltage converters for direct grid connection of wind and PV power systems.
Chapter 3 is dedicated to the method to find a suitable multilevel converter
topology, which can connect the renewable generation units directly to the
medium-voltage grid with mature semiconductor devices. Different multilevel con-
verter topologies, such as the neutral point clamped (NPC), flying capacitor (FC),
and MMC converters, have been considered for the design of an 11-kV converter
system. The comparison is made in terms of the number of semiconductors, sem-
iconductor cost and availability, THDs, filter size, and control complexity of the
converters. The performance is analyzed and compared through numerical analysis
in the MATLAB/Simulink environment. To generate the switching pulses, a level-
shifted carrier-based switching scheme is used for NPC topologies and a phase-
shifted carrier-based switching scheme is used for the FC and MMC converter
topologies with a carrier frequency of 12kHz and a modulation index of 0.80.98.
To couple the renewable energy source to the MMC converter, a common high-
frequency magnetic link with multiple secondary windings is considered and elec-
tromagnetic performance is reported in Chap. 4. The medium-frequency link is
used to generate the isolated balanced multiple DC supplies for the MMC con-
verter from a single low-voltage power source. Compared with the conventional
transformers operated at the power frequency (50 or 60Hz), the high-frequency
(in the range of a few kHz to MHz) transformers have much smaller and lighter
magnetic cores and windings and thus much lower costs.
The multilevel converter requires a number of switching and control PWM sig-
nals, which cannot be generated by the available DSP because the available DSP
1.4 Organization of the Book 13
can only at present provide about 6 pairs of PWM channels. In this instance, the
field programmable gate array (FPGA) is the natural choice for medium-voltage
multilevel converters. However, most of the available design techniques require
special software such as the HDL coder, system generator, PSIM and ModelSim,
which increases the development time and cost. In Chap. 5, a fully digital switch-
ing controller is developed for 3-phase 5-level converters. The SK 30GH 123
IGBTs are used to develop a prototype multilevel converter, and an XC3S500E
FPGA is used to develop the switching controller. The most common software
such as the MATLAB/Simulink and Xilinx ISE based design technique is used
which may reduce the developmental time and cost of the switching controller.
The simulation results serve as a preliminary validation of the proposed design
technique, which will be finally verified by the experimental results. The devel-
oped switching scheme can be used for any multilevel converter configuration
with minimum changes in software environment. Moreover, the proposed design
techniques and implementation issues may be useful for designing any other mod-
ern power converter.
To verify the feasibility of the high-frequency-link MMC medium-voltage con-
verter, in Chap. 6, a scaled down 1.73 kVA laboratory prototype test platform with
modular 5-level cascaded converter is developed, which converts 210V DC (recti-
fied generator voltage) into 3-phase 1kVrms 50Hz AC. The design and implemen-
tation of the prototyping, test platform, and the experimental results are analyzed
and discussed. It is expected that the proposed new technology would have great
potential for future renewable generation systems and smart grid applications.
The high number of levels means that medium-voltage attainability will be
possible to connect the renewable generation units to the medium-voltage grid
directly and it will also be possible to improve the output power quality. Since the
number of components and control complexity increase linearly with the num-
ber of levels, the optimal selection of the number of converter levels is important
for the best performance/cost ratio of the medium-voltage converter systems. In
Chap. 7, an 11-kV system and a 33-kV system are designed and analyzed tak-
ing into account the specified system performance, control complexity, and cost
and market availability of the power semiconductors. It is found that the 19-level
and 43-level converters are optimal for 11- and 33-kV systems, respectively. The
detailed designs and analysis of an 11-kV MMC converter and a 33-kV MMC
converter systems are presented.
Chapter 8 draws the conclusions for the whole book and proposes possible
future works for the further development of the technology.
References
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14 1Introduction
3. Sahu BK, Hiloidhari M, Baruah D (2013) Global trend in wind power with special focus on
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20:306321
13. Du Z, Gu W (2009) Aerodynamics analysis of wind power. In: Proceedings of the 2009
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China, pp 13
14. Islam MR, Guo YG, Zhu JG (2010) Steady state characteristic simulation of DFIG for wind
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09/04/denmark-ribbon-cut-at-anholt-offshore-wind-farm/. Accessed on 13 May 2014
17. www.drmrenfrew.files.wordpress.com
18. Earth Policy Institute. Climate, energy and transportation, world cumulative wind turbine
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systems
References 15
2.1Introduction
The worlds energy demand is growing remarkably due to the fast growth of popu-
lation and economy in the developing countries. The energy sector is facing an
accelerating amalgam crisis of the worldwide established fossil and atomic energy
systems. Natural gas, coal, and crude oil are the main fossil fuels for the current
world energy supply. Crude oil is the most important fossil fuel among the three
main fossil flues. Figure2.1 shows the trend of world oil consumption [1]. Coal is
the second most important consumable fossil fuel. Figure2.2 shows the world coal
consumption [1]. Due to very high oil price, coal has been becoming an attractive
fossil fuel in the recent years. Figure2.3 shows the world consumption of natural
gas [1]. Almost a constant growth rate has been observed for the natural gas con-
sumption in the past decades.
90
Consumption (Million
80
barrels/day)
World Oil Consumption
70
60
50
1985 1990 1995 2000 2005
Year
120
Quadrillion BTU
100
80
60
1980 1985 1990 1995 2000 2005
Year
3000
Consumption (Million
2000
1500
1000
1980 1985 1990 1995 2000 2005
Year
The increasing energy demand is not only diminishing the reserve of fos-
sil fuels, but also affecting the environment. Carbon dioxide (CO2) gas is gener-
ated from burning of fossil fuels, which significantly contributes to the increase
of average global temperatures, i.e., global warming. Figure2.4 shows the world
CO2 emission from fossil fuel burning [1]. Scientists worldwide are now seeking
2.1Introduction 19
4000
2000
0
1950 1960 1970 1980 1990 2000 2010
Year
Biodiesel
38.6 %
Solar PV Average Annual World
35.2 % Energy Growth Rates
by Source
Wind
27.9 %
Geothermal
22.1 %
Fuel
Ethanol
15.1 %
Natural Coal
Hydro Gas
Oil Nuclear 3.9 %
2.3 % 2.4 %
1.1 % 0.7 %
solutions to these two enormous challenges (energy and environment) from renew-
able or clean energy sources, which are richly available in almost every country.
Many countries have set targets for renewable energy use to meet the increas-
ing energy demand and also to reduce the global warming effect. For example, the
target shares of total energy from renewables by 2020 in Sweden, Finland, Austria,
and Australia are 49, 38, 34, and 20%, respectively [2]. Therefore, average annual
growth rates of renewable sources are much higher than those of conventional
sources in recent years. Figure2.5 shows the average annual world energy growth
rates [1]. Solar photovoltaic (PV) represents the second highest growth rate due to
its abundance source and technological development of PV cell, e.g., reduction of
PV module cost. Average module cost was USD 100/W and USD 29/W in 1975
and 1980, respectively, and reduced to less than USD 3.5/W in 2004. Figure2.6
shows the average PV module cost [1].
20 2 Power Converters for Small- to Large-Scale Photovoltaic
80 Less than
Less than
30 USD/Watt 5 USD/Watt
60
40
About 3.5
20 USD/Watt
5 USD/Watt
0
1975 1980 1985 1990 1995 2000 2005
Year
Since 2007, medium- and large-scale PV power plants have attracted a high
degree of attention and the power plants of more than 10MW in capacity have
now become a reality. These multi-megawatt PV power plants require large areas
of land, and thus, they are usually installed in remote areas, far from cities. For
power transmission, a step-up transformer is usually used in the PV inverter sys-
tem to feed in the solar energy into a medium-voltage (MV) grid (e.g., 636kV).
The transformer steps up the inverter output voltage from 300V AC to grid volt-
age level (e.g., 636kV). Although these special transformers are compact com-
pared with conventional distribution transformers, they are still large and heavy for
remote area PV applications. The large-size and heavy weight step-up transformer
may increase the system weight and volume and can be expensive and complex for
installation and maintenance. The MV inverter may offer the best possible solution
to interconnect the PV array to the MV grid directly [3]. Moreover, it may also
be possible to ensure electrical isolation through the inverter, which is important
for the interconnection of MV grid and PV array [4]. Recently, advanced mag-
netic materials, such as amorphous and nanocrystalline alloys, have attracted sig-
nificant attention to develop high-frequency magnetic links for MV inverters [5].
Compared with the power frequency transformer (operated at 50/60Hz), the high-
frequency magnetic links (in the range of a few kHzMHz) have much smaller and
lighter magnetic cores and windings and thus much lower cost. Therefore, the MV
inverter for step-up-transformer-less direct grid interconnection of PV systems has
become a favorable choice, since the installation of large-scale PV power plants
started commercially in 2007.
This chapter incorporates PV power generation technologies, including tradi-
tional power conditioning systems, two-level low-voltage converter topologies,
the limitations of power frequency step-up transformer-based grid integration of
renewable generation systems in remote area applications, and advanced converter
topologies for MV applications. Therefore, an extensive literature survey has been
conducted focusing on many different aspects of MV converter development for
2.1Introduction 21
Fig.2.7A photograph of
PV cell, which may produce
0.5V DC
Fig.2.8A photograph of
24-V PV module, where 72
cells are interconnected
Cell
22 2 Power Converters for Small- to Large-Scale Photovoltaic
When PV arrays are used to harvest solar energy, two important factors could limit
the implementation of PV systems, i.e., high cost and low efficiency in energy
conversion. The conversion efficiency of the current solar PV modules is typically
only about 1017% [6]. In PV systems, the PV array represents about 57% of
the total cost of the system, and the battery storage system corresponds to 30%
of the cost. Other system components such as inverters and maximum power
point tracker (MPPT) contribute to only 7% of the total cost [7]. Due to the low
2.2 Solar Photovoltaic Arrays 23
Rshcell
D Vcell
IL
conversion efficiency and high cost of solar array, it is very desirable to operate the
PV panel at the maximum power point (MPP). An ideal solar cell can be modeled
by a current source in parallel with a diode. In practice, no solar cell is ideal and
hence a shunt resistance and a series resistance are added to the model as shown
in Fig.2.10, where Rscell is the intrinsic series resistance of usually a very small
value, and Rshcell is the equivalent shunt resistance of usually a very large value.
For a single silicon solar cell, the nonlinear IV characteristic can be presented
as [8, 9]
Vcell + Icell Rscell
Icell = IL Io exp (G(Vcell + Icell Rscell )) 1 (2.1)
Rshcell
where
G = AiqKT ,
q is the electronic charge (=1.6021019C),
Ai=Bi is the ideality factor (=1.92),
K is the Boltzmanns constant (=1.381023J/K),
T is the PV cell temperature,
Icell is the cell output current,
Vcell is the cell output voltage,
Io is the cell saturation current which can be presented as
3
T qEGO 1 1
Io = Ior exp (2.2)
Tr Bi K Tr T
IL is the light-generated current which can be presented as
Rad
IL = ISC + KISC (TC 28) (2.3)
1,000
The array temperature Tc is approximately given by [9]
TC = Tair + 0.3 Rad % (2.4)
D Vcell
IL
Solar energy sources have variable daily and seasonal patterns. For exam-
ple, monthly average global solar insolation at Dhaka City of Bangladesh var-
ies between 3.92 and 7.71kWh/m2/day. The maximum amount of insolation
2.2 Solar Photovoltaic Arrays 25
Fig.2.12Monthly average
4.5
3.5
Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec
Month
Fig.2.13Daily average
Average bright sunshine hours
9
bright sunshine hour at
Dhaka City of Bangladesh; 8
recording period: 19611980
7
[11]
6
3
Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec
Month
It is also observed from the powervoltage curve of the solar PV module that on
the right hand side, when the voltage is almost constant, the slope of power versus
26 2 Power Converters for Small- to Large-Scale Photovoltaic
5
2
1000 W/m
Current, I (A)
4
800 W/m 2
3
600 W/m2
2
0
0 2 4 6 8 10 12 14 16 18 20 22
Voltage, V (V)
70
60 1000 W/m 2
800 W/m 2
50
Power, P (W)
600 W/m2
40
30
20
10
0
0 2 4 6 8 10 12 14 16 18 20 22
Voltage, V (V)
voltage is negative (P/V<0), whereas on the left hand side, the slope is posi-
tive (P/V>0), as illustrated in Fig.2.18 [12, 13]. Thus, the PV array has an
optimum operating point called the MPP, which varies depending on array tem-
perature and the present insolation level. The irradiance mainly affects the output
current, and the temperature mainly affects the terminal voltage of the PV array,
so that the effects of both factors have to be considered when designing a PV sys-
tem. However, the intermittent nature of PV sources, in terms of the power and
output voltage, is a major issue when connected to the grid. Therefore, solar PV
system requires a power conditioning circuit known as PV inverter that is capable
of extracting the maximum power from PV source and feeds the adjusted power to
the load and/or grid to their satisfaction.
2.2 Solar Photovoltaic Arrays 27
5
o
Current, I (A) 75 C
4
o
50 C
3 o
25 C
2
0
0 5 10 15 20
Voltage, V (V)
70
60
50
Power, P (W)
o
75 C
40
o
30 50 C
o
20 25 C
10
0
0 5 10 15 20
Voltage, V (V)
Fig.2.18Maximum power
point (MPP) determination: dP/dV=0
The slope is positive on the
left side of the PV curve,
Power, P (W)
dP
V>
MPP
<0
Voltage, V (V)
28 2 Power Converters for Small- to Large-Scale Photovoltaic
PV array
AC line
Cs Cd
Fig.2.20Most commonly L
iL io
used DC to DC boost
converter circuit
VL
+
+
-
+ Diode
Vi Vo
Cs Cd
- Transistor -
Fig.2.21Equivalent iL L
circuit of a DC to DC boost
converter when transistor is + + vL - +
turned on Vi Cs Co Vo
- -
Fig.2.22Equivalent iL L
circuit of a DC to DC boost
converter when the transistor + vL -
+ +
is turned off
Vi Cs Co Vo
- -
Fig.2.23Voltage across
inductor L for time period T
vi
A
toff
0
ton t
B
(vi-vo)
T
For steady-state operation, the integral of inductor voltage vL over one time period
T must be zero, i.e., the areas A and B in Fig.2.23 must be equal.
Therefore,
Vi ton + (Vi Vo ) toff = 0 (2.9)
Dividing both sides by T, and rearranging all terms, we have
Vo T 1
= = (2.10)
Vi toff 1D
Assuming the circuit is 100% efficient, i.e., the input power (Pi) and output power
(Po) are equal, (Pi=Po), or
Vi Ii = Vo Io (2.11)
one obtains
Io
= (1 D) (2.12)
Ii
30 2 Power Converters for Small- to Large-Scale Photovoltaic
iL
IL
0
t
T
t on toff
D1
L D2
PV array
AC line
Cs Cd
L
D2
PV array
T1 T3
AC line
Cs Lr Cr
C
D1 T2
In the continuous operation mode, the inductor current never falls to zero in one
switching cycle, i.e., either the transistor or diode is conducting. Figure2.24
shows the inductor current in the continuous conduction mode.
Several modified topologies, such as a time-sharing dual-mode PV inverter [15]
in Fig.2.25 and a soft-switched DC to DC boost converter-based inverter [16] in
Fig. 2.26, were proposed to improve the efficiency of the fundamental circuit. In
the time-sharing dual-mode PV inverter, when the PV array output voltage is larger
than the DC-link voltage, the transistor is always in the off state and the input cur-
rent flows through the bypass diode D1 but does not flow through the boost inductor
2.3 Inverters in Small-Scale Solar PV Systems 31
L and free-wheeling diode D2. In this way, the proposed circuit can avoid the con-
duction losses of boost inductor, L, and the free-wheeling diode D2. When the input
voltage is smaller than the DC-link voltage, the bypass diode D1 behaves as open
circuit and the circuit operates as a fundamental two-stage PV inverter circuit. In the
soft-switched DC to DC boost converter-based PV inverter, there are two stages: the
converter stage and inverter stage. All the switches in both the converter and inverter
stages can be turned on and off with zero voltage switching, which can reduce the
switching losses significantly. The operating principle of the proposed soft switch-
ing inverter was presented with a few switching modes [16] as the following:
Mode 1 When the transistor in DC-link capacitor C is turned on with zero volt-
age switching, the DC-link capacitor begins to discharge and linearly
decreases the main inductor L current.
Mode 2 When the transistors T1, T2, and T3 are turned on with zero voltage
switching, the DC-link capacitor begins to discharge.
Mode 3 When T1 and T2 are turned on with zero voltage switching, the resonance
between resonance inductor, Lr, and resonance capacitor, Cr, is started and
the main inductor current is minimized. When the resonance is finished,
the current of resonant inductor, Lr, flows through diodes, D1 and D2.
Mode 4 When T1 and T2 are turned off with zero voltage switching, resonance
is started. The resonant capacitor Cr is charged by the current flowing
through inductors, L and Lr. The resonance stops when the voltage of res-
onant capacitor, Cr, equals the output voltage. The DC-link capacitor is
charged by L and Lr through the parallel diode of T3.
Fig.2.27Basic circuit of
half-bridge topology-based
PV inverter L D
PV array
AC line
C1
Cs C2
Q
Fig.2.28Sunny Boy
5000TL model half-bridge L
D
topology-based PV inverter
PV array
Cin c
L
D
PV array
AC line
C
Cin c
Inverter
L
D
PV array
Cin c
(boost) converter raises the voltage of the PV array and also serves the operation of
MPPT. Driven by the proper reference signals generated by the control algorithm
to modulate the pulse width of the switching signal of switch Q, the half-bridge
inverter inverts the DC power to 50 or 60Hz AC power. Figure2.28 illustrates the
half-bridge topology-based three-string PV inverter, Sunny Boy 5000TL, commer-
cially developed by SMA [20]. The half-bridge inverter-based topology requires
less switching devices, but its DC-link voltage needs to be twice the grid voltage
peak. The inverter topologies do not have electrical isolation between the array and
the grid, which is critical in case of fault and safety of personnel.
The insulation can be achieved through a power frequency transformer at
the grid side of the PV inverter which may also serve voltage step-up operation.
2.3 Inverters in Small-Scale Solar PV Systems 33
Filter
L
PV array
AC line
Cin
HFT-L
Inverter Rectifier Inverter
with MPPT
This power frequency transformer is heavy and large, increasing the PV inverter
installation cost and requiring regular monitoring and maintenance. Increasing
the operating frequency will lead to a compact and lightweight magnetic com-
ponent of isolation transformers [4, 5, 21]. Several medium- and high-frequency
(HF) transformer-based inverter topologies were developed and made available
commercially. Figure2.29 shows a high-frequency link-based inverter system
[10]. The DC PV array power is converted to 50 or 60Hz AC line power through
an isolated high-frequency transformer link. The DC voltage of the PV array is
firstly converted to high-frequency AC by a high-frequency inverter, which is then
transformer-coupled and converted to 50 or 60Hz AC through a high-frequency
rectifier, filter, and a full-bridge inverter. The multistage power conversion may
increase the cost of the converter and decrease the efficiency of the system, but
it can significantly reduce the weight and volume of the power conversion sys-
tem and minimize grid isolation issues. In 2010, Lu etal. [22, 23] proposed a pla-
nar high-frequency transformer-based PV inverter system as shown in Fig.2.30.
Higher output power from multiple PV arrays can be achieved by connecting each
PV array to its own DC to AC converter and single-phase transformer. The prima-
ries of the high-frequency transformer links are connected in an open delta ener-
gized by high-frequency voltage from DC to AC converters, where the converter
DC/DC converter
DC/AC
Inverter
0o
AC output
PV modules
DC/AC DC/AC
Inverter Inverter
120o
DC/AC
Inverter
240o
HF transformer
L
PV array
Cin c
HFT
L
PV array
AC line
C in c
HFT
Inverter
L
PV array
Cin c
HFT
output voltages are phase shifted each other by 120. The secondaries of the high-
frequency transformer links are connected in a wye configuration, and the output
is connected to a 50 or 60Hz DC to AC converter through a high-frequency three-
phase rectifier. The detailed design and analysis of the HF planar transformer were
reported in [24, 25]. The Original Equipment Manufacturer commercially devel-
oped the high-frequency transformer-based three-string PV inverter, PowerLynx
Powerlink PV 4.5kW, as shown in Fig.2.31 [26].
DC bus DC bus
Load # 1 Load # N
Module 1 Module N
Fig.2.33Full-bridge with
MPPT-based circuit topology
of single-stage inverter PV array
AC line
Cin
Inverter
with MPPT
Inverter
PV array
C1
AC line
PV array
C2
Fig.2.34Circuit topology of single-stage inverter: NPC with grid neutral connected to the mid-
dle point of DC link
CPV
PV array
RG
C
PV array
CPV
RG
AC lines
Fig.2.36Single-stage
power circuit with boost
converter Lb
PV array
AC line
Cd
Inverter with
boost converter
Fig.2.37Single-stage
power circuit with universal
converter L
D1
PV array
AC line
Cd D2
Surge Inverter
protection
Solar panels L
Public network
=
DC switch
EMI filter
LCL filter
AC switch
EMI filter
~ N
Public network
= L1
~ L2
L3
SINVERT PVM
inverter N
PE
Overvoltage
protection
M8
For medium- and large-scale solar PV electricity generation, there are two well-
established inverter technologies: the centralized and string technologies as shown
in Figs.2.40 and 2.41, respectively.
In the centralized PV inverter technology, each string consists of a series of PV
modules to reach the voltage requirement without amplification and then a few
strings are parallel connected to a common inverter circuit. The number of strings
mainly depends on the power levels. This technology eliminates the amplifica-
tion stage, but possesses some major limitations, such as voltage mismatch loss
2.4 Medium- and Large-Scale Solar PV Systems 39
AC output
PV modules DC/AC
Inverter
PV modules
String diodes
PV modules
PV modules
DC
AC output
DC
DC/AC
Inverter
DC
DC
between PV modules and power losses due to common MPPT [26]. In order to
control every string individually, the string technology uses a DC to DC converter
for each string, which improves the system efficiency. In order to minimize the
voltage mismatch in the strings, a battery-integrated boost converter was pro-
posed to eliminate the voltage regulation stage [39]. The block diagram of battery-
integrated boost converter is shown in Fig.2.42, and the proposed converter-based
PV inverter system is shown in Fig.2.43. The detailed analysis of the proposed
converter is presented in [40].
The ABB central inverters are especially designed for medium-scale PV power
plants. The PVS800 version is a 3-phase inverter with a power capacity in the
40 2 Power Converters for Small- to Large-Scale Photovoltaic
Battery
D
L
Vout
S _
PV
+
D
L1
Vout_1
C
S _
PV 1
+
Battery 2
AC output
L2
DC/AC
Vout_2 Inverter
C
S _
PV 2
+
Battery n
D
Ln
Vout_n
C
S _
PV n
PVS800 Inverter 1
Switch
DC
EMC filter
DC switch
EMC filter
LCL filter
AC
PV array
Medium-voltage
Controller
network
transformer
Medium
step-up
voltage
PVS800 Inverter 2
Switch
DC
EMC filter
DC switch
EMC filter
LCL filter
AC
PV array
Controller
and pollution which can block cooling ducts. Due to the use of traditional two-
level inverter, the harmonic content in the output power is high. Usually, high-
frequency pulse-width-modulated (PWM) gate signals are used to drive switching
devices to reduce the harmonic content. Due to high-harmonic content and high-
frequency stitching, the system requires a heavy LCL filter circuit and an electro-
magnetic compatibility (EMC) filter, which may increase the losses and cost of the
system.
Besides its low-voltage system, Siemens also developed the SINVERT
PVS inverter-based system for medium-scale PV plants. The AC output voltage
and power capacity of PVS version inverters are in the range of 288370V and
500630kW, respectively, as summarized in Table2.2. The 12.52MW central
inverters were designed by paralleling 24 PVS inverters through transformer and
switchgear at the grid side. The design and grid connection of 2-inverters-based
system is illustrated in Fig.2.45 [43]. Siemens developed GEAFOL castresin
transformers for grid connection of PV arrays. With GEAFOL, it is possible to
avoid the limitations associated with liquid-filled transformers while retaining the
SINVERT PVS 1
Medium voltage
Switch
Input 1
step-up
transformer
DC
EMC filter
EMC filter
Input 2
Filter
Input 3
AC
PV array
Medium-voltage
Controller
network
SINVERT PVS 2
Medium voltage
Switch
step-up
Input 1
transformer
DC
EMC filter
EMC filter
Input 2 Filter
Input 3
AC
PV array
Controller
Fig.2.46Quasi-Z source
C2
converter-based medium-
L1 L2
voltage PV inverter (one of 3 D
phases)
C3 C1
PV array 1 H-bridge 1
C2
L1 L2
D
Medium-voltage
network
C3 C1
PV array 2 H-bridge 2
C2
L1 L2
D
C3 C1
PV array n H-bridge n
or 60Hz), the medium-frequency transformer link has much smaller and lighter
magnetic cores and windings and thus much lower costs.
In 2012, by combining a quasi-Z source inverter into an MMC as shown in
Fig.2.46, a medium-voltage PV inverter was proposed in [49].
The proposed inverter does not have isolation between PV array and medium-
voltage grid. Multiphase isolated DC to DC converter-based MMC inverter topol-
ogy as shown in Fig.2.47 was proposed in [50, 51]. In the proposed configuration,
the voltage balancing is the challenging issue, since each H-bridge cell is con-
nected to a PV array through a DC to DC converter. A common DC link may be
one of the possible solutions to minimize the voltage imbalance problem, and a
single DC-link-based inverter in Fig.2.48 was presented in [52, 53]. Although this
design may reduce the voltage balancing problem in the grid side, the generation
of common DC-link voltage from different PV arrays makes the inverter operation
complex and limits the range of MPPT operation.
As an alternative approach to minimize the voltage imbalance problem with a
wide range of MPPT operation, a common magnetic link was proposed [3]. The
boost converter is considered for the MPPT operation. The array DC power is con-
verted to a high-frequency AC through a high-frequency inverter. The inverter also
44 2 Power Converters for Small- to Large-Scale Photovoltaic
DC
C2 C1
DC
PV array 1 H-bridge 1
DC
Medium-voltage
network
C2 C1
DC
PV array 2 H-bridge 2
DC
C2 C1
DC
PV array n H-bridge n
Common DC-link
DC
DC
DC
DC
DC
PV array 1
AC
DC
H-bridge 1
DC
Medium-voltage
DC
DC
PV array 2
DC
AC
network
DC
DC
H-bridge 2
PV array 3
DC
DC
DC
AC
DC
DC
H-bridge k
PV array n
Module A-1
MPPT
L D
Cdc
Cdc Cin
Q
Module A-2
Phase-A
Cdc
PV array-1 High-frequency
inverter
MPPT
Cdc
L D
Module A-N
Cdc Cin
Q
Module B-1
Cdc
A
Module B-2
Phase-B
MPPT B
Cdc
C
L D
Cdc Cin
Q
Cdc
PV array-3 High-frequency
n
inverter
Common magnetic-link
Module B-N
Module C-1
Cdc
Module C-2
MPPT
Phase-C
Cdc
L D
Cdc Cin
Q
Cdc
PV array-N High-frequency
inverter
Module C-N
2.5Summary
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Chapter 3
Power Converter Topologies
for Grid-Integrated Medium-Voltage
Applications
3.1Introduction
3.2Two-Level Converters
3.2.1Single-Phase Converter
3.2.1.1Half-Bridge Converter
Figure3.1 illustrates the circuit diagram of half-bridge converter consisting of two
switching devices, e.g., insulated gate bipolar device (IGBT) and a three-wire DC
power supply. The switching devices can be controlled in a smart way for progres-
sively wider pulses at the positive peak and narrower pulses at the negative peak,
which may help to filter out high-frequency switching harmonics. The unipolar
pulse width modulation (PWM) scheme with a sinusoidal reference and a triangu-
lar carrier can be used to operate switching devices. The comparator of the modu-
lation scheme compares the reference signal with the carrier signal and generates
Boolean output of 0 or 1. This generated gate pulse may operate the top IGBT of
the half-bridge converter. The bottom IGBT can be operated by the inverted gate
pulse of the Boolean output. Figure3.2 shows the modulation scheme of half-
bridge converter. The freewheeling diodes permit current flow even if all switches
are open and lagging currents flow in case of inductive loads.
The two switching devices of a half-bridge converter should not be on at the
same time, to avoid the direct short circuit between the terminals of DC power
supply. The peak load voltage, VL, of half-bridge converter can be expressed as
Vs
VL = mi (3.1)
2
where mi is the modulation index and Vs the DC power supply voltage. Table3.1
summarizes the operation of half-bridge converter circuit. The output voltage
waveform is shown in Fig.3.3.
Fig.3.1Circuit diagram of
half-bridge voltage source Vs + Top
converter _C1 IGBT
2
+
0 Load
Vs
_ + VL _
Vs +
2 _C2 Bottom
IGBT
54 3 Power Converter Topologies for Grid
0.5
Signals
0
Gate pules
Reference
-0.5 Carrier
-1
0 2 4 6 8 10 12
Time (ms)
200
100 Reference
Voltage (V)
0
Inverter
output
-100
-200
0 2 4 6 8 10 12 14 16
Time (ms)
If T is the time period and Tp the time when the top switch is in the on state
during a cycle, the rms output voltage, VL(rms), of the half-bridge PWM converter
can be deduced as
3.2 Two-Level Converters 55
1
T
VL(rms) = VL2 dt
T 0
1 Tp V 2 T
V 2
2 s 2 s
= mi dt + mi dt
T 0 4 Tp 4
(3.2)
2 T T
m V2 p
i s
= dt + dt
4T 0 Tp
mi Vs 1 Tp 1
= [t] + [t]TTp
2 T 0 T
mi Vs 1
= T p 0 + T Tp
2 T
mi Vs
=
2 (3.3)
Figure 3.4 plots the frequency spectrum of output voltage, which contains about
146% THD with a carrier frequency of 1kHz. Although the half-bridge converter
requires less number of switching devices, the requirements of double voltage-rated
DC power supply and large-size line filter may limit the use of this converter. The
peak inverse voltage (PIV) of the switching devices is equal to the total DC power
supply voltage, Vs. Maximum 1.44kV converter can be designed with the commer-
cially available IGBTs. Table3.2 summarizes the possible maximum output volt-
ages of half-bridge converters with commercially available switching devices.
3.2.1.2Full-Bridge Converter
0.4
0.3
0.2
0.1
0
0 2 4 6 8 10
Frequency (kHz)
Table3.2Maximum rms output voltage of half-bridge converters with modulation index at 0.8
Voltage rating of IGBT Vcom@100FIT (V) Voltage rating of DC Converter rms output
(V) supply (V) voltage (V)
6,500 3,600 3,600 1,440
4,500 2,250 2,250 900
3,300 1,800 1,800 720
2,500 1,200 1,200 480
1,700 900 900 360
Vs + T1 T3
_C1
2
+
Load
Vs
_
Vs + + VL _
2 _C2 T2
T4
structure with capital letter H, it is also called H-bridge converter. The switching
device pairs T1T2 and T3T4 can be switched on and off alternately with each
pair providing the opposite polarity of voltage across the load. The two switch-
ing devices of the same arm should not be on at the same time, to avoid direct
short circuit between the terminals of the DC power supply. The switching devices
can be controlled in a smart way for progressively wider pulses at the center and
narrower pulses at the edges of half-cycle output voltage waveform, which may
help to filter out high-frequency switching harmonics. The modulation scheme as
depicted in Fig.3.2 can also be used to switch the switching pairs. The Boolean
output by comparison of carrier signal and positive half-cycle of the reference sig-
nal may switch T1 and T2 simultaneously. The Boolean output by comparison of
carrier signal and negative half-cycle of the reference signal may switch T3 and T4
simultaneously. Table3.3 shows the switching scheme of a full-wave converter.
The output voltage waveform of full-bridge converter has three voltage levels,
e.g., 200, 0, and 200V in the voltage waveform as shown in Fig.3.6. Due to the
higher number of voltage levels, the THD is much lower than that of half-bridge
3.2 Two-Level Converters 57
200
100 Reference
Voltage (V)
0
Inverter
-100 output
-200
10 15 20 25
Time (ms)
0.5
Normalized amplitude
0.4
0.3
0.2
0.1
0
0 2 4 6 8 10
Frequency (kHz)
converter. At 1kHz PWM switching frequency, the full-bridge converter may pro-
vide an output voltage with less than 80% THD. Figure3.7 shows the frequency
spectrum of output voltage of the full-bridge converter.
If the output PWM voltage waveform as shown in Fig.3.6 is approximated by
square wave as shown in Fig.3.8, the rms value of the output voltage can be calcu-
lated as
1 T 2
VL(rms) = V dt
T 0 L
1 T2
T
2 2
= mi Vs2 dt + mi Vs2 dt (3.4)
T 0 T
2
T
2 2
= mi2 Vs2 dt
T 0
= mi Vs (3.5)
58 3 Power Converter Topologies for Grid
200
100 Approximated
Voltage (V)
T/2
0
T/2
-200
10 15 20 25
Time (ms)
Table3.4Maximum rms output voltage of full-bridge converters with modulation index at 0.8
Voltage rating of IGBT Vcom@100FIT Voltage rating of DC Converter rms output
(V) (V) supply (V) voltage (V)
6,500 3,600 3,600 2,880
4,500 2,250 2,250 1,800
3,300 1,800 1,800 1,440
2,500 1,200 1,200 960
1,700 900 900 720
3.2.2Three-Phase Converter
Vs + T1 T3 T5
_C1
2
+ Va
a Vb
Vs b
_ c Vc
Vs +
2 _C2 T4 T6
T2
Carrier
-0.5
-1
0 2 4 6 8 10 12 14 16
Time (ms)
supply is through a rectifier circuit. The triangular carrier signal is compared with
the sinusoidal modulating signal. When the modulating signal is greater than the
carrier, pulse 1 is high (1) and pulse 2 is low (0). Single carrier and three modulat-
ing or reference signals (120 phase shift between each other) may generate six
gate pulses to drive the converter. Figure3.10 shows the PWM switching scheme
of the 3-phase bridge converter. The Boolean output through comparison of Ref A
with carrier signal may switch T1, and its inverted output may switch T2. The gate
pulse generated from Ref B and carrier may switch T3, and its inverted gate pulse
may switch T4. Similarly, Ref C and carrier may generate gate pulses for T5 and
T6. The line-to-line voltage waveform of 3-phase bridge converter is almost the
same as that of the full-bridge converter. Figure3.11 shows the line-to-line out-
put voltage waveform of 3-phase bridge converter. Similar to the single-phase full-
bridge converter, the line-to-line voltage of the 3-phase bridge converter contains
about 80% THD. Figure3.12 shows the frequency spectrum of the output line-
to-line voltage. The maximum output voltage generation capacity is also similar
to the single-phase full-bridge converter, e.g., maximum 2.88kV (rms) converter
60 3 Power Converter Topologies for Grid
200
100
Voltage (V) Reference
Output voltage
-100
-200
0 2 4 6 8 10 12 14 16
Time (ms)
0.5
Normalized amplitude
0.4
0.3
0.2
0.1
0
0 2 4 6 8 10
Frequency (kHz)
with 6.5kV IGBTs. Although the 3-phase bridge converter requires 33% addi-
tional switching devices, it can handle about 73% more power than that of the sin-
gle-phase full-bridge converter. Therefore, the 3-phase converter could be a smart
choice for medium- and high-power applications. If Vll is the converter line-to-
line voltage and Il the line current, the power handling capacity of the 3-phase
2-level converter can be calculated as
PT = 3Vll Il . (3.6)
The main aim of any modulation technique is to obtain desired output having a
maximum fundamental component with minimum harmonics and less switch-
ing losses. The space vector pulse width modulation (SV-PWM) method is an
3.2 Two-Level Converters 61
advanced PWM method, and it is possibly the best among all the PWM techniques
for high-power applications. Compared to sinusoidal pulse width modulation
(SPWM), SV-PWM offers 15% higher DC-voltage utilization and 33% fewer
communications per cycle. Moreover, it can obtain a better harmonic performance
and less switching loss.
In each cycle of SV-PWM, the desired output voltage is approximated by a
time average of three voltage vectors, in which two are nonzero voltage vectors
adjacent to the reference and the third is a zero vector. The strategy of sequencing
these three switching vectors within each cycle will affect the current ripple, the
switching losses and the spectrum of the output voltages and currents. Moreover,
the switching sequence is not unique. Since the SV-PWM offers superior perfor-
mance with respect to other modulation techniques, it is important to establish the
sequencing strategy which is well suited for the systems.
In SV-PWM, the converter is controlled through the concept of converter states.
Each converter state corresponds to a certain combination of switches. There are
two switches in each leg of a 2-level 3-phase converter. The switches in one leg
cannot be both on or off at the same time (the former leads to a short circuit of
the associated phase, and the latter results in an open circuit). There are three con-
verter legs in a 3-phase system, so the total number of converter states is eight.
Figure 3.13 shows the eight possible combinations of on and off patterns
of 3-phase 2-level converter. The on and off states of the lower switches are the
inverted states of the upper ones. The phase voltages corresponding to the eight
combinations of switching patterns can be calculated. This transformation results
in six nonzero voltage vectors and two zero vectors. The nonzero vectors form the
axes of a hexagon containing six sectors (V1 V6) as shown in Fig.3.13. The
angle between any adjacent two nonzero voltage vectors is 60. The zero vec-
tors are at the origin and give a zero voltage vector to the output. The envelope of
the hexagon formed by the nonzero vectors is the locus of the maximum output
Se
r
cto
cto
Se
(000)
1
V0 V7
(111) V1
V4
(011) (100) d axis
r4
r6
cto
cto
Se
Se
Sector 5
V5
(101)
V6
(001)
62 3 Power Converter Topologies for Grid
voltage. If versus is the DC supply voltage of 3-phase 2-level converter, the length
of six active space vectors can be calculated as
2
Vs (3.7)
3
When the upper switch on a phase leg is on, i.e., T1, T3, or T5 is 1, the correspond-
ing lower switch should be off, i.e., T2, T4, or T6 is 0. In the 2-level SV-PWM,
V0 and V7 generate the same line voltage (which is zero) and hence are redun-
dant states. The eight possible switching states and corresponding phase as well as
the line voltages are shown in Table3.5. One can choose one or both of the zero
voltage vectors, as suited, to reduce the number of switching or manipulate har-
monics. These two zero vectors are the only redundant space vectors for a 2-level
SV-PWM. As the number of levels of the SV-PWM implementation increases, the
number of redundant space vectors increases, which can be exploited to achieve
the desired performance characteristics.
Usually, when creating space vectors, the three time varying quantities are sinu-
soids of the same amplitude and frequency that have 120 phase shifts between
each other. When this is the case, the space vector at any given time maintains
its magnitude. As time increases, the angle of the space vector increases, causing
the vector to rotate with frequency equal to the frequency of the sinusoids. Each
of the converter states can be mapped into the dq plane by applying Parks trans-
formation to the phase voltages as given. The vectorial representation of a given
3-phase system as shown in Fig.3.14 can be carried out by the relation (3.9) to
(3.15) [4]. Figure3.15 describes the technique to calculate the d-axis component
corresponding to 3-phase voltages. The q-axis component can be calculated from
(3.12), which can be deduced from Fig.3.16.
Vd = Van Vbn cos 60 Vcn cos 60 (3.8)
1 1
= Van Vbn Vcn (3.9)
2 2
Vq = 0 + Vbn cos 30 Vcn cos 30 (3.10)
3.2 Two-Level Converters 63
3 3
= 0Van + Vbn Vcn (3.11)
2 2
1 21 21 Van
Vd Vbn (3.12)
=
Vq 0 23 23 Vcn
|Vref | = Vd2 + Vq2 (3.13)
Vq
= tan 1 (3.14)
Vd
b Vq Vref
Vd a d axis
600
Van Vd
600
Vcn
Fig.3.16q-axis component
calculation Vq
Vbn
300
900
Van
0
30
Vcn
64 3 Power Converter Topologies for Grid
Fig.3.17Algorithm to
Read
select the sector
Yes
0 0 < 60 0 Sector1
No
Yes
600 < 1200 Sector2
No
Yes
1200 < 1800 Sector3
No
Yes
1800 < 2400 Sector4
No
Yes
240 0 < 300 0 Sector5
No
Sector6
Equation (3.14) is used to calculate , and the reference vector is located accord-
ing to an algorithm as shown in Fig.3.17.
The only difference among PWM schemes that use adjacent vectors is the
selection of the zero vector(s) and the sequence in which the vectors are applied
within the switching cycle. The degrees of freedom we have in the selection of a
switching pattern are as follows:
selection of the zero vector whether or not we would use V7 (111) or V0 (000) or
both sequencing of the vectors, and
splitting of the duty cycles of the vectors without additional commutations.
Considering the degrees of freedom, there are four most commonly used switching
patterns:
seven switching states,
three switching states (with only one zero vector),
three switching states (with both zero vectors), and
four switching states.
The number of commutations and switching states in one sampling period is six or
seven, respectively, as shown in Fig.3.18. Both zero vectors (V7 and V0) are used
3.2 Two-Level Converters 65
Vo V1 V2 V7 V2 V1 Vo
To /4 T1 /2 T2 /2 To /2 T2 /2 T1 /2 To /4
Ts
200
100
Voltage (V)
-100
-200
5 10 15 20
Time (ms)
in each sector, where V7 is placed in the middle and V0 at both side of the pattern.
For example, if the reference is located in the first sector, the possible switching
sequence could be V0V1V2V7V2V1V0, etc. The switching scheme has been
implemented in MATLAB/Simulink environment. The output line-to-line voltage
of 3-phase 2-level converter with this switching scheme is shown in Fig.3.19. Due
to the symmetry in the switching waveform this scheme shows the lowest THD.
Compared with SPWM, seven switching states switching scheme gives about
45% less harmonic distortion. Figure3.20 shows the frequency spectrum of line-
to-line voltage, where about 55% THD was measured. Figure3.21 plots the line
current of 3-phase 2-level converter with seven switching states switching scheme-
based SV-PWM.
66 3 Power Converter Topologies for Grid
0.1
0
0 2 4 6 8 10
Frequency (kHz)
20
10
Current (A)
-10
-20
5 10 15 20 25 30
Time (ms)
Since the selection of the nonzero vectors is based on the desired output voltage
vector and the phase and magnitude of the current are determined by the load, it
is not always possible to avoid switching the phase carrying the highest current.
In such a case, the phase carrying the second highest current is not switched on
so that the switching losses are still reduced. In this scheme, the number of com-
mutations in one sampling period is four and there are only three switching states
in Ts. With this strategy, the switching sequence is repeated in each cycle as long
as the reference vector is within the same sector. For the case when a reference is
in sector 1, the switching sequence is given in Fig.3.22. If V7 is selected as the
zero vector, each switching cycle will have two commutations in the inverter leg b
and two in leg c (a total of 4), while leg a will have the upper switch on during the
entire cycle. If the zero vector is V0, the number of commutations (i.e., transitions)
3.2 Two-Level Converters 67
V1 V2 V7 V1 V2 V7
T1 T2 To T1 T2 To
Ts Ts
200
100
Voltage (V)
-100
-200
5 10 15 20 25
Time (s)
Fig.3.23Output line-to-line voltage with three-state switching pattern (only one zero vector)
per cycle will be the same, but the inverter leg that will cease to commutate in
sector 1 will be leg c. This redundancy of zero vectors allows for a reduction of
commutation losses. Selection of the zero vector should be done so as to avoid
commutation in the inverter leg carrying the largest current. The output line-to-
line voltage of 3-phase 2-level converter with three switching states switching
pattern (only one zero vector) is shown in Fig.3.23. Figure3.24 shows the fre-
quency spectrum of output line-to-line voltage. Compared with the seven-state
switching scheme, three switching states switching pattern (only one zero vector)
gives significantly higher harmonics, i.e., about 20% more. Still it is about 15%
lower than that of the SPWM scheme. Figure3.25 plots the line current, which is
68 3 Power Converter Topologies for Grid
0.1
0
0 2 4 6 8 10
Frequency (kHz)
20
10
Current (A)
-10
-20
20 25 30 35 40 45
Time (ms)
Fig.3.25Line current with three-state switching pattern (only one zero vector)
more distorted compared with the line current in Fig.3.21 with the same circuit
parameters.
One can modify the switching sequence between the voltage vectors, so that each
transfer from one state to the other involves only one commutation. Figure3.26
shows the switching pattern of three-state switching (both zero vectors but alterna-
tively). This requires the use of both zero vectors (V7 and V0) in a given sector and
a reversal of the switching sequence every cycle. In this scheme, the zero vectors
V7 and V0 are used alternatively in adjacent cycles, so that the effective switching
frequency is halved. However, the sampling period is still Ts.
3.2 Two-Level Converters 69
V1 V2 V7 V2 V1 Vo
T1 T2 To T2 T1 To
Ts Ts
200
100
Voltage (V)
-100
-200
5 10 15 20 25
Time (ms)
The benefit is a reduction of commutations (to three). The switching losses for
this scheme are expected to be ideally 50% as compared to those of the seven-
state switching scheme, but the THD is significantly higher due to the existence of
the harmonics at half of the sampling frequency. About 68% THD was measured
on the line-to-line output voltage. In this scheme, the number of commutations in
one sampling period is three and there are only three switching states in Ts. The
output line-to-line voltage of 3-phase 2-level converter with three-state switch-
ing (both zero vectors alternatively) is shown in Fig.3.27. Although the harmonic
70 3 Power Converter Topologies for Grid
0.1
0
0 2 4 6 8 10
Frequency (kHz)
Fig.3.28Harmonic spectrum of line-to-line voltage with three-state switching (both zero vec-
tors alternatively)
20
10
Current (A)
-10
-20
20 25 30 35 40 45
Time (ms)
Fig.3.29Line current of 3-phase 2-level converter with three-state switching (both zero vectors
alternatively)
performance of this switching pattern is similar with the three-state switching pat-
tern (only one zero vector), the number of commutation is higher (3 times in a
period). Figure3.28 shows the harmonic spectrum of output line-to-line voltage
with three-state switching (both zero vectors alternatively). The line current wave-
form is also almost the same as in Fig.3.25. Figure3.29 shows the line current
waveform with three-state switching (both zero vectors alternatively).
Both zero vectors, V7 and V0, are used to reduce the number of commutations per
switching cycle. The switching sequence is reversed after each switching cycle
within a sector. For example, if the reference is in the first sector, the possible
switching sequence can be V0V1V2V7V7V2V1V0, as shown in Fig.3.30.
3.2 Two-Level Converters 71
Vo V1 V2 V7 V7 V2 V1 Vo
Ts Ts
200
100
Voltage (V)
-100
-200
5 10 15 20
Time (s)
The main advantage of this approach is that it requires only three commutations
per cycle and gives symmetrical pulses.
The benefit is a reduction of commutations (to three). The switching losses for
this scheme are expected to be ideally 50% as compared to those of the seven-
state switching scheme, but the THD is significantly higher due to the existence
of the harmonics at half of the sampling frequency. In this scheme, the number
of commutations in one sampling period is three and there are only four switch-
ing states in Ts. The output line-to-line voltage of 3-phase 2-level converter with
four-state switching scheme is shown in Fig.3.31. The harmonic performance of
this switching scheme is slightly better than those of three-state switching pattern
(only one zero vector) and three-state switching (both zero vectors alternatively).
72 3 Power Converter Topologies for Grid
0.1
0
0 2 4 6 8 10
Frequency (Hz)
20
10
Current (A)
-10
-20
20 25 30 35 40 45
Time (s)
About 65% THD was measured. Figure3.32 shows the frequency spectrum of
line-to-line voltage. The line current waveform is also slightly less distorted than
those in Figs.3.25 and 3.29. Figure3.33 shows the line current waveform with
four-state switching pattern.
and 50% switching losses, respectively. In this way, the three-state and four-state
switching patterns are the best choice for power converters.
3.3Multilevel Converters
The multilevel converters are power electronic circuits that can provide output
voltage with more than two levels and be operated in inverter or rectifier mode.
The 3-level converter is the lowest level number multilevel converter. Although the
number of levels of output phase voltage of 3-level converter is the same as that
of line-to-line voltage of 2-level full-bridge converter, the line-to-line voltage of
3-level converter consists of five-voltage levels. There are three basic topologies in
the multilevel converter: NPC, FC, and MMC. In 1975, the concept of multilevel
converter topology was proposed [5], and in the last few decades, several multi-
level converter topologies have been patented [6, 7]. In order to achieve high volt-
age using low-voltage switching devices, the multilevel converter topology uses
a number of switching devices with low-voltage DC sources. The proper control
of the switching devices superimposes these multiple DC sources in a staircase
(time shifted) form in order to achieve high voltage at the output. The renew-
able energy sources, such as wind turbine generators, solar PV arrays, and fuel
cells, can be used as the multiple DC-voltage sources. The NPC and FC convert-
ers require single DC supply, but the MMC converter requires multiple isolated
and balanced supplies. High-frequency magnetic link could be a possible option
to generate multiple DC supplies for MMC converter from single source. In mul-
tilevel converters, the rated voltage of the switching devices depends on the rating
of the DC-voltage sources to which they are connected. Therefore, the rated volt-
age of switching devices is much lower compared with a 2-level converter. The
power circuits of one phase of different 3-phase multilevel converters are shown
in Fig.3.34. According to different switching states, it is possible to achieve high-
voltage level on the output voltage by adding up the DC-voltage sources compared
with the 2-level inverters.
According to the output voltage waveform of two level, the quality of output
voltage depends only on the sampling frequency (on X-axis), so that a higher sam-
pling frequency means better voltage waveform, or closer to the sine wave refer-
ence. On the other hand, increasing the switching frequency would increase the
switching loss and cause electromagnetic compatibility (EMC) problems. The
74 3 Power Converter Topologies for Grid
(a) (b)
SA7 SA7
C C
SA5 SA5
DA1
CA4
CA1
a CA5 a Vdc SA2 SA4 a
Vdc Vdc
SA2 SA2
DA4
C C
SA4 SA4
CA3 H-bridge cell 2
DA5 SA5 SA7
SA6 SA6
CA6
higher switching frequency means higher dv/dt, which would decrease the stabil-
ity and reliability of the switching devices. Moreover, the semiconductor devices
also have limited range of switching frequencies. The switching frequency of the
most commonly available power IGBTs is at 10kHz or lower. For example, the
recommended switching frequency of Semikron 1,200V 123 NTP, 126 Trench,
12E4HD, and 12V IGBTs are 9, 5, 9, and 12kHz, respectively. The 7-level con-
verter output voltage waveform is depicted in Fig.3.35. In the voltage waveform,
there is an additional parameter to control the quality of the output voltage wave-
form, i.e., the number of voltage levels. Both the X- and Y-axes can be controlled
to improve the converter performance effectively. The switching frequency can be
reduced to a low value with an increase to the number of voltage levels, making
the converter more stable and reliable and making it possible to use low-voltage-
rated matured and low-cost semiconductor devices.
Synthesizing a staircase output voltage, which is closer to the sinusoidal volt-
age reference compared with the 2-level converter output, allows for a reduction in
the harmonic content in voltage waveforms, which would lead to the size and cost
reduction of the line filter circuit of power conversion systems. Each level of the
staircase consists of a few PWM pulses, as shown in Fig.3.36.
Like the 2-level converter, the carrier signal frequency of the PWM genera-
tor can be adjusted to control the quality of the output waveform. However, the
number of levels of the staircase waveform mostly affects the quality of the out-
put voltage waveform. Figure3.37 plots the THDs of 11 and 33kV converters
with different numbers of converter levels. For an 11kV converter, 19-level or
3.3 Multilevel Converters 75
15
Line voltage Reference
10
Voltage (kV)
5
-5
-10
-15
20 30 40 50 60 70 80
Time (ms)
Level 5
200
Level 4
100
Voltage (V)
Level 3
0
PWM output
(before filter circuit)
Level 2
-100
-200
Level 1
0 5 10 15 20 25 30
Time (ms)
higher level converter may provide output power with less than 5% THD, which
inherently satisfies the IEEE and IEC standards. For a 33kV system, 21-level or
higher level converter may satisfy the 5% THD requirements without using line
filter. Although the number of semiconductor devices increases with the number
of converter levels, the high-level converter enables the use of low-voltage devices,
which are not only low cost but also matured forms of technology. Table3.7 lists
the market prices of some available power IGBTs.
Therefore, the semiconductor cost of multilevel converters is lower than that of
the equivalent 2-level converters operated at the same power rating. Figure3.38
plots the per-unit prices of switching devices. It can be seen from Fig.3.38 that
the 2.5kV or lower-rated IGBTs cost much lower than the high-voltage ones.
The highest voltage rating of the commercially available IGBT is 6.5kV, and this
is suitable for 2.88kV or lower-voltage converter systems with the traditional
76 3 Power Converter Topologies for Grid
10
33 kV 11 kV
8 converter converter
THD (%)
6
5 % limit (IEEE 1547, IEC61727)
Unchanged
4
2
10 20 30 40 50
Number of levels
circuit operations, the method uses switching aid circuits, such as snubber and/
or active gate control circuits, which increases the switching loss. The switch-
ing loss mostly depends on the communication voltage of the switching devices,
which can be much lower with multilevel converter topologies than that of the
2-level converters. Moreover, multilevel converters require no switching aid cir-
cuits, which improve the commutation times. Therefore, multilevel converters give
lower switching losses than those of the 2-level converters. A power loss compari-
son between the MMC converter and 2-level converter was analyzed, and it was
reported that the switching losses of MMC converters were much lower than those
of the 2-level series-connected converters operating under the same conditions [9].
Among the variety of topologies for multilevel converter structures reported in
the recent decades, the NPC, FC, and MMC converter with separate DC sources
are three commonly used structures. Most of the other topologies for multilevel
converters have been designed through the modification or combination of these
three basic topologies. A brief description of these three multilevel converter
topologies is presented in Sects. 2.12.3.
In order to increase the converter voltage rating without increasing the voltage
rating of switching devices, the NPC converter topology was introduced in 1981
[10]. A 3-phase 7-level NPC converter circuit is shown in Fig.3.39. A phase leg
of a 7-level converter consists of six pairs of switching devices and five pairs of
diodes. Each switch in a pair works in complimentary mode, and the respective
diode pair provides access to the midpoint. There are seven switching states to
synthesize the 7-level phase voltage. If it is assumed that each auxiliary diode volt-
age rating is the same as the active switching device voltage rating, the number of
diodes required for each phase leg will be (2m4).
3
V)
.7 k .4 k
A
Per unit price (k AUD)
at 1 0
age t at
vol
t ren
2 d cur
Rate ate
d
R
0
0 1 2 3 4 5 6
Rated voltage or current (kV or kA)
peak value and 13 levels to peak-to-peak value. The difference between two suc-
cessive voltage levels is equal to the voltage across each DC-link capacitor. The
three phases of the NPC converter share a common DC bus voltage, which has
been subdivided by (m 1) capacitors into equally m-levels. Each phase leg of
the NPC converter requires (2m2) active switching devices, and the commuta-
tion voltage of each active switching device is (m1) times lower than the total
DC-bus voltage. For example, in total, there are six DC-link capacitors in a 7-level
NPC converter and the voltage across each capacitor is Vdc/6.
In 1998, the NPC converter-based high-power AC motor drive system was
proposed [11]. In 2002, another application of the NPC converter for high-power
medium-voltage variable speed motor drives was proposed [12]. The NPC con-
verter has also attracted significant attention because it serves as an interface
between a high-voltage DC transmission line and an AC transmission line [13].
C
SA9 SB9 SC9
D1 D1 D1
B n
DC C
D6 D6 D6
C SA4 SB4 SC4
D7 D7 D7
SA6 SB6 SC6
D8 D8 D8
SA8 SB8 SC8
C D9 D9 D9
SA10 SB10 SC10
The NPC converter topology has the ability to connect the neutral point to the
middle point of the DC link thereby reducing the ground leakage currents and ena-
bling this topology to form back-to-back connection. Accordingly, in the recent
years, the back-to-back NPC converters have also been largely utilized in the grid
interfacing of renewable energy sources such as wind turbine generators and solar
PV arrays. In total, there are (6m 12) auxiliary diodes required for a 3-phase
m-level converter.
When the number of converter levels is sufficiently high, the number of diodes
required will make the system impractical to implement. This is due to that the
diode reverse recovery of these huge clamping diodes becomes a critical fac-
tor. The reverse recovery problem can be reduced by using the newly developed
silicon carbide diode which has negligible reverse recovery time. However, this
technology is still under development. Only 40A or lower-rated silicon carbide
diodes are currently available on the market. All the converters in this chapter are
designed with 250A rated diodes, as the silicon carbide technology is still not
available for these designs. On the other hand, these special diodes significantly
increase the semiconductor cost of the converter (a 3-phase 43-level NPC con-
verter requires 246 diodes). For example, the unit price of a 600V 40A silicon
carbide diode is about 25 USD. Therefore, the reverse recovery problem is still
a challenging issue for designing medium- or high-voltage converters with NPC
converter topology. In addition to the requirement for several auxiliary diodes,
the capacitor voltage balancing is one of the notable drawbacks of NPC topol-
ogy. Unbalanced capacitor voltages may cause distortions in output waveform
and damage switching devices due to the over voltage breakdown of switching
devices. For this reason, many researchers are turning their attention to develop-
ing extra circuits and control algorithms [14], but these circuits and algorithms are
for no more than five levels. Moreover, the boost switch may limit the voltage and
power rating of the converter. Therefore, this topology is not suitable for medium-
or high-voltage applications, where a higher number of levels are required.
In 1992, FC converter was proposed [15]. The overall structure of the FC con-
verter is comparable with that of the NPC converter except that the converter uses
auxiliary capacitors instead of auxiliary diodes. The circuit topology of a 3-phase
7-level FC converter is shown in Fig.3.41.
A phase leg of the 7-level converter consists of six pairs of switching devices
and five branches of capacitors. An m-level FC converter has an m-level output
phase voltage and a (2m 1)-level output line voltage. The three phases of the
FC converter may share a common DC-bus voltage similar to the NPC converter,
which has been subdivided by (m1) capacitors into equal m-levels. Each phase
leg of the FC converter requires (2m2) active switching devices, and the com-
mutation voltage of each active switching device is (m 1) times lower than
3.3 Multilevel Converters 81
Fig.3.40Output line-to- 7
6
s
line voltage of 7-level NPC
el
5
ev
converter 10 4
el
Voltage (kV)
g
3
ta
ol
2
V
1
0
-10
5 10 15 20 25 30 35
Time (ms)
the total DC-bus voltage. In addition to the DC-link capacitors, the FC converter
requires large number of auxiliary capacitors. If the voltage rating of the capaci-
tors is equal to that of the active switching devices, the number of auxiliary capac-
itors required for each phase leg will be (m23m+2)/2 [16]. There are several
possible switching states to synthesize a desired output. The optimal switching
states may ensure good performance and reduce power losses of the converter as
well.
Due to some features (e.g., the control of real and reactive power and the capa-
bility to ride through short-duration outage and voltage sags), the FC-voltage
source converter has found its application in power systems. In 2002, an FC mul-
tilevel-voltage source converter-based unified power-flow controller was proposed
[17]. In 2007, a 3-level FC multilevel converter-based high-voltage direct current
power transmission system was presented [18]. However, the number of auxil-
iary capacitors required is quadratically related to the number of levels. When the
number of converter levels is sufficiently high, the number of capacitors required
makes the system impractical to implement. The large number of capacitors not
only increases the converter size and weight but also significantly reduces the life-
time of the converter. Due to the regulation of the capacitor voltages, the FC multi-
level converter requires complex control strategies. Moreover, the pre-charging of
clamping capacitors with the required voltage level may increase the complexity
and cost, and decrease the performance of the converter.
C C7 C7 C7
SA5 SB5 SC5
C4 C4 C4
C2 C2 C2
SA1 SB1 SC1
C C8 C8 C5 C8 C5
A
DC C1
C5 B n
C1
C1
SB2 C
C13 SA2 C13 C13 SC2
C9 C9 C9
Load
C SA4 SB4 SC4
C3 C3 C3
Because of their special features (e.g., the number of components scales lin-
early with the number of levels, and individual modules are identical and com-
pletely modular in construction hence enabling high-level number attainability),
the MMC converter topology has been considered the best possible candidate for
medium- to high-voltage high-power applications. In 1990, a single-phase MMC
converter structure was presented for plasma stabilization applications [21]. In
1997, Robicon Corporation presented a medium-voltage high-power 3-phase
MMC converter for motor drive applications [22]. The complicated multi-winding
phase-shifted power-frequency transformer was used to deliver electric power to
all the floating H-bridge inverter cells. In 1996, an MMC-based static synchronous
compensator for reactive power control was presented [23]. In 1999, the converter
was proposed for heavy-duty electric and hybrid-electric vehicles that have large
electric motor drives [24]. A series of isolated batteries were used to deliver elec-
tric power to all the floating H-bridge inverter cells.
A phase shift or level shift can be introduced between the carrier signals of con-
tiguous cells to produce a phase-shifted or level-shifted switching pattern between
them. In this way, a stepped multilevel waveform is generated. For the m-level
converter, (m1) phase-shifted or line-shifted carriers with the same frequency
fca are required. If fm is the frequency of the reference signal, the frequency modu-
lation index of the converter can be calculated as
fca
mf = . (3.15)
fm
3.3.4.1Phase-Shifted Carrier-Based Switching Scheme
The phase-shifted carriers are specially conceived for FC [25] and MMC [22]
converters. Since each FC cell is a 2-level converter, and each H-bridge cell is a
3-level inverter, the traditional bipolar (using one carrier signal that is compared
to the reference to decide between two different voltage levels, typically the
positive and negative busbars of a voltage source converter) and unipolar PWM
techniques can be used, respectively. Due to the modularity of these topologies,
each cell can be modulated independently using the same reference signal in a
phase. If Ac the peak-to-peak amplitude of the carrier signals and Am the peak-
to-peak amplitude of the reference signal, the amplitude modulation index can be
calculated as
Am
map = . (3.16)
Ac
Figure 3.43 shows the block diagram of the phase-shifted switching scheme for
the 7-level converter. This modulation scheme requires three reference signals;
84 3 Power Converter Topologies for Grid
120 shifted by each other and one for a particular phase leg. The number of car-
rier signals depends on the number of converter levels; in total, there are (m1)/2
carrier signals in an m-level converter. The carrier phase shifting for that particular
cell or pair can be calculated as [26]
360
ps = . (3.17)
(m 1)
The MATLAB/Simulink model to generate 3-phase-shifted carrier signals for a
3-phase 7-level converter is illustrated in Fig.3.44. These three-generated carriers
may be used to drive the left-side H-bridge arms of three H-bridge inverter cells
on a phase leg. Figure3.45 plots the three-generated carrier signals. The inverted
carrier signals may be used to generate gate pulses to drive the right-side H-bridge
leg of three H-bridge inverter cells on a phase leg. Figure3.46 plots the inverted
carrier signals. In total, there are six carrier signals and three reference signals in
the modulation scheme of 3-phase 7-level converter. Figure3.47 plots all the car-
rier and reference signals of a 3-phase 7-level converter.
Each compare unit generates one switching signal for the top switching device
of a half-bridge cell or a pair. The inverted form of this switching signal drives
the bottom switching device. Figure3.48 shows the gate pulse generation tech-
nique for the top switching device. The technique to generate gate pulse for the
bottom switching device is illustrated in Fig.3.49. For the left half-bridge cell, one
3.3 Multilevel Converters 85
Reference signal
generator (3-phases)
SA1
>= 0 SB1
SC1
Comp
0o shifted carrier SA2
signal generator SB2
NOT
SC2
Inv
SA3
>= 0 SB3
Inv SC3
Comp
SA4
SB4
NOT
SC4
Inv
SA5
>= 0 SB5
SC5
Comp
60o shifted carrier SA6
signal generator SB6
NOT
SC6
Inv
SA7
>= 0 SB7
Inv SC7
Comp
SA8
SB8
NOT
SC8
Inv
SA9
>= 0 SB9
SC9
Comp
120o shifted carrier SA10
signal generator SB10
NOT
SC10
Inv
SA11
>= 0 SB11
Inv SC11
Comp
SA12
SB12
NOT
SC12
Inv
Gate pulses
Fig.3.43Phase-shifted switching scheme for the 3-phase 7-level FC and MMC multilevel
converters
1
sin asin 2/pi 1
theta
1
0 -K-
3
sin asin 2/pi 2
60 -K-
2
Scope1
d
ifted
shifte
0 o sh
0.5
o
Carrier signals
120
0
hifted
-0.5
60 o s
-1
0 2 4 6 8 10
Time (ms)
1
Inverted carrier signals
0.5
-0.5
-1
0 2 4 6 8 10
Time (s)
0.5
Signals
-0.5
-1
0 2 4 6 8 10
Time (ms)
Fig.3.47Three reference signals and six phase-shifted carrier signals-based modulation scheme
of 3-phase 7-level converter
3.3 Multilevel Converters 87
Signals 0.5
-0.5
-1 Carrier Reference
0 5 10 15 20
Time (ms)
0.5
Signals
-0.5
-1 Carrier Reference
0 5 10 15 20
Time (ms)
is asserted when the reference signal value is greater than or equal to the carrier
signal value, and the other is asserted when the reference signal value is less than
the carrier signal value. For the right half-bridge cell, one is asserted when the
inverted carrier signal value is greater than or equal to the reference signal value,
and the other is asserted when the inverted carrier signal value is less than the ref-
erence signal value. Figure3.50 shows the MATLAB/Simulink model to generate
the gate pulses for a 3-phase 7-level converter.
For the FC converter, the advantage of the even power distribution is that once
the FCs are properly charged (initialized to their corresponding values), no imbal-
ance will be produced due to the self-balancing property of this topology and as a
result there is no need to control the DC-link voltages [27, 28]. Another interest-
ing feature is that the total output voltage has a switching pattern with k (number
of the power cells) times the frequency of the switching pattern of each cell. This
multiplicative effect is produced by the phase shifts of the carriers. Hence, lower
THD is obtained at the output, using the k times lower frequency carriers. With
88 3 Power Converter Topologies for Grid
In the level-shifted scheme, the carriers are arranged in vertical shifts instead of
the horizontal shift. Each carrier is set between two voltage levels, and hence, it is
named as level shifted. Since each carrier is associated with two levels, the same
principle of bipolar PWM can be applied which takes into account the fact that the
control signal has to be directed to the appropriate semiconductors in order to gen-
erate the corresponding levels [29]. The carriers span the whole amplitude range
that can be generated by the converter.
The level-shifted carrier-based modulation scheme is especially useful for NPC
converters, since each carrier can be easily associated with two power switches
of the converter [30]. Moreover, the level-shifted carrier-based modulation scheme
provides less distorted line voltages because all carriers are in phase in contrast
to the phase-shifted carrier-based modulation scheme. Although the level-shifted
carrier-based modulation scheme may provide reasonable performance, the com-
plexity of control signal assignment to the appropriate semiconductors makes it
unpopular for MMC multilevel converter applications. Further, the level-shifted
carrier-based modulation scheme generates more distorted input current in the
MMC converter and a capacitor voltage imbalance in the FC converter [30].
Figure3.51 plots the reference and carrier signals for a 3-phase 7-level NPC con-
verter. In the level-shifted scheme, the carriers on a particular phase leg are level
shifted by
Am
ls = . (3.18)
(m 1)
The peak-to-peak amplitude of carrier signals can be calculated by
Am
Acl = . (3.19)
(m 1)
Figure3.52 shows the block diagram of the level shifted switching scheme for the
3-phase 7-level converter.
Each comparator unit generates one switching signal for the top switch-
ing device of a pair. The inverted form of this switching signal drives the bottom
switching device. Figure3.53 shows the gate pulse generation technique for the
top switching device. The technique to generate gate pulse for the bottom switch-
ing device is illustrated in Fig.3.54. For the top pair, one is asserted when the ref-
erence signal value is greater than or equal to the carrier signal value, and the other
is asserted when the reference signal value is less than the carrier signal value.
For the second top pair, one is asserted when the shifted carrier signal value is
3.3 Multilevel Converters 89
3
1 TT1
3
Ust 3
3
3
>=
3
NOT TT2
3
0 Com
Inv
3 TT3
3
3
3
>=
-1 3
1 Com1 NOT TT4
3
Inv1
1
3 TT5
3
3
3
>=
3
2 Com2 NOT TT6
3
Inv2
-1
2 theta 2
3 TT7
wt 3
3
3
>=
Com3
3
3 NOT TT8
3
Inv3
3 TT9
3
3 3
3
>=
3
4 Com4 NOT TT10
3
Inv4
Carriers
-1
Generator
3
3 TT11
3
3
>=
3
5 Com5 NOT TT12
3
Inv5
greater than or equal to the reference signal value, and the other is asserted when
the shifted carrier signal value is less than the reference signal value. In multilevel
converters with level-shifted carriers, the amplitude modulation index can be cal-
culated as
Am
mal = . (3.20)
(m 1)Acl
90 3 Power Converter Topologies for Grid
0.5
Signals
-0.5
-1
0 5 10 15 20 25 30
Time (ms)
SA3
>= 0 SB3
3/6 SC3
Comp
SA10
SB10
NOT
SC10
Inv
SA1
>= 0 SB1
5/6 SC1
Comp
SA12
Reference signal SB12
NOT
generator (3-phases) SC12
Inv
Gate pulses
0.5
Signals Carrier
0
Gate pulse PS7
-0.5
Reference
-1
0 5 10 15 20
Time (ms)
0.5
Carrier
Signals
0
Gate pulse PS2
-0.5
Reference
-1
0 5 10 15 20
Time (ms)
2*pi
m
Freq 1
sin Ust
12:34
[0 -2*pi/3 2*pi/3]
Phase -K-
deg. ->rad
0.5
Signals
-0.5
-1
0 5 10 15 20
Time (ms)
2*pi
m
Freq
sin
12:34
t
1
Ust
[0 -2*pi/3 2*pi/3]
3
Phase -K-
-K-
deg. ->rad sin
shown in Fig.3.59. The parameters of the reference signals such as the frequency,
maximum amplitude, and phase displacement can easily be controlled in the
Simulink environment. This modulation scheme also uses flatting top references,
which significantly reduce the switching losses of the converter. Figure3.60 plots
the trapezoidal reference signals.
Sixty degree pulse width modulation scheme also use sinusoidal references but
their amplitudes are limited to 60, clamped the magnitude of the reference signal,
sin at a constant value while is higher than 60. The limiting of the peak value
actually makes the top of the reference signals flattened. The MATLAB/Simulink
model to generate sinusoidal reference signals can also be used to generate 60
reference signals. An extra amplitude limiter may be added in the model as shown
in Fig.3.61. Figure3.62 plots the reference and carrier signals for SDPWM
scheme.
The modulation schemes are applied on the 7-level to 19-level MMC converter
systems, and performance is analyzed in the MATLAB/Simulink environment.
94 3 Power Converter Topologies for Grid
0.5
Signals
0
-0.5
-1
0 5 10 15 20
Time (ms)
Fig. 3.58Third-harmonic injected pulse width modulation schemes for 3-phase 5-level
converter
2*pi
m
Freq
1
sin asin Ust
12:34
[0 -2*pi/3 2*pi/3]
Phase -K-
deg. ->rad
0.5
Signals
-0.5
-1
0 5 10 15 20
Time (ms)
2*pi
m
Freq 1
sin Ust
12:34
t
[0 -2*pi/3 2*pi/3]
Phase -K-
deg. ->rad
0.5
Signals
-0.5
-1
0 5 10 15 20
Time (ms)
Fig.3.62Sixty degree pulse width modulation schemes for 3-phase 5-level converter
Of these four modulation schemes, the THPWM-based SPWM scheme gives the
best harmonic performance, as shown in Fig.3.63. The SDPWM and TRPWM
schemes have higher lower-order harmonic content than the SPWM and THPWM
schemes. In addition, the SPWM has shown a higher reduction rate for the high-
level number.
voltage and m the number of levels of the converter, the minimum DC-link voltage
of each H-bridge inverter cell or each DC-link capacitor can be calculated as
Vll(rms)
Vdc(min) = 2 . (3.21)
(m 1)
To determine the nominal DC-link voltage of each H-bridge inverter cell or each
DC-link capacitor, a voltage reserve of 4% is assumed, i.e.,
Vdc(nom) = 1.04 Vdc(min) . (3.22)
If Ip(rms) is the converter phase current, the apparent output power (for Wye con-
nection) can be calculated from
Sc = 3Vll(rms) Ip(rms) . (3.23)
14
Study on 11 kV converter
12
TRPWM SPWM
SDPWM THPWM
10
THD (%)
6
5 % limit
2
7 8 10 12 14 15 16 18 19
Number of levels
Fig.3.63Calculated THD at different level numbers ranging from 7-level to 19-level [1]
Fig.3.64Line voltage of
15
ence
5-level neutral point clamped
ge
volta
converter 10
Refer
Voltage (kV)
Line
5
0
D
% TH
-5
17.26
-10
-15
20 30 40 50 60 70 80
Time (ms)
Fig.3.65Frequency
Normalized amplitude
0.02
0
0 5000 10000 15000
Frequency (Hz)
outputs. All 11-level converter output voltage waveforms are very close to the ref-
erence sine wave while the NPC converter performance is better than the others.
Furthermore, from the output figures, it is clear that increasing the number of levels
means improving the converter performance. It is assumed that each blocking diode
voltage rating is the same as the active device voltage rating. A total of 54 diodes
are required for an 11-level NPC converter. The large number of diodes affects
3.4 Selection of Multilevel Converter Topology for Medium-Voltage Applications 99
Fig.3.66Line voltage 15
ge
e
enc
volta
of 11-level neutral point
10 1
fer
clamped converter
Re
Line
Voltage (kV)
5
D
% TH
-5
7.07
-10 -1
-15
20 30 40 50 60 70 80
Time (ms)
the reverse recovery of the clamping diodes, and this is a major design challenge
in high-voltage high-power systems. A list of the number of power components
required for each converter topology is shown in Table3.11. As already stated, the
availability of IGBT and diode modules is also considered when designing the con-
verter. For the 5-level NPC, FC and MMC converter topology, each IGBT switch is
formed from the series connection of two 4.5kV IGBTs so the number of IGBTs
is 48. To enable a converter output phase current of 250A, the simulation result is
used to determine the current rating of the power semiconductors.
A total of 6 and 45 clamping capacitors are required for each phase of the 5-level
and 11-level FC converters, respectively. These large numbers increase the con-
verter size and cost. In addition, they reduce the overall lifetime of the converter.
The capacitor voltage balancing problem also becomes a challenging issue with
such a high number of components. An 11kV 5-level FC converter also requires 4
DC-link capacitors with a rated voltage of 4,044V. Each voltage level contributes
4,044V to the line- or phase-voltage waveforms. The line voltage waveform of a
5-level FC converter is shown in Fig.3.68. Due to capacitor voltage imbalance, the
voltage waveform of the FC converter is severely distorted compared with that of
the NPC converter. Therefore, the harmonic performance is not as good as that of
the NPC converter. Figure3.69 illustrates the harmonic spectrum of the 5-level FC
converter. In addition to 135 auxiliary capacitors, an 11kV 11-level FC converter
requires 10 DC-link capacitors with a rated voltage of 1,618V.
Each voltage level contributes 1,618V to the line- or phase-voltage waveforms.
The line voltage waveform of an 11-level FC converter is shown in Fig.3.70.
Although, the 11-level converter output voltage waveform matches the reference
sine signal, the performance is not as good as that of the NPC converter. The output
line voltage frequency spectrum of an 11-level FC converter is shown in Fig.3.71.
100 3 Power Converter Topologies for Grid
Fig.3.67Frequency
Normalized amplitude
spectrum of 11-level neutral 0.04
point clamped converter
0.02
0
0 5000 10000 15000
Frequency (Hz)
Fig.3.68Line voltage
15
of 5-level flying capacitor
ence
ge
converter 10
volta
Refer
Voltage (kV)
Line
0
D
-5 % TH
17.80
-10
-15
20 30 40 50 60 70 80
Time (ms)
Fig.3.69Frequency
Normalized amplitude
0.02
0
0 5000 10000 15000
Frequency (Hz)
Fig.3.70Line voltage of 15
Reference
converter 10 1
Voltage (kV)
00
D
% TH
-5
7.28
-10 -1
-15
20 30 40 50 60 70 80
Time (ms)
3.4 Selection of Multilevel Converter Topology for Medium-Voltage Applications 101
There are no blocking diodes or clamping capacitors in the MMC converter topol-
ogy. The number of components scales linearly with the number of levels. Hence,
the overall number of components is much lower than that of other multilevel
converter topologies. The individual modules are similar and totally modular in
construction, which makes it easy to implement for any number of levels. The
higher number of attainable levels provides more scope for reducing harmonics.
The high number of levels means that it is possible to connect the converter to
the medium-voltage grid directly. However, unlike the NPC and FC converters, the
MMC converter requires multiple isolated and balanced DC supplies. For exam-
ple, a 3-phase 11-level MMC converter requires 15 isolated and balanced DC sup-
plies. As the number of voltage levels increases, the voltage rating of these DC
supplies decreases to a low level and this is favorable for some applications. The
voltage rating of these DC supplies actually determines the voltage ratings of the
active switching devices for each H-bridge inverter cell. The voltage balancing of
multiple DC supplies is important for good output voltage waveforms. The output
line voltage waveform of a 5-level MMC converter is shown in Figs.3.72, and
3.73 shows its frequency spectrum. As calculated, an 11kV 11-level MMC con-
verter generates a 9-level line voltage waveform with 18.13% THDs. The DC sup-
plies voltage rating of an 11kV 11-level MMC converter is 1,618V. The available
Fig.3.71Frequency
Normalized amplitude
0.02
0
0 5000 10000 15000
Frequency (Hz)
Fig.3.72Line voltage of 15
5-level modular multilevel
ence
ge
10
volta
cascaded converter
Voltage (kV)
Refer
5
Line
0
D
% TH
-5
18.13
-10
-15
20 30 40 50 60 70 80
Time (ms)
102 3 Power Converter Topologies for Grid
Fig.3.73Frequency
Normalized amplitude
spectrum of 5-level modular 0.06
multilevel cascaded converter
0.04
0.02
0
0 5000 10000 15000
Frequency (Hz)
Fig.3.74Line voltage of 15
11-level modular multilevel
Reference
Line voltage
cascaded converter 10
Voltage (kV)
5
0
-5 THD%
7.70
-10
-15
20 30 40 50 60 70 80
Time (ms)
3.3kV IGBT may be used to design the 11kV 11-level converter because this
IGBT is recommended for 1,800V maximum applications.
With these IGBTs, 90% DVUF can be ensured and this is important to con-
firm the high performance/cost of the power converter. Figure3.74 plots the line
voltage waveform of an 11-level MMC converter. There are 20 steps in the peak-
to-peak line voltage waveform, and each step contributes 1,618V to the line volt-
age of 32,360V peak-to-peak. The 11kV 11-level MMC converters give 7.70%
THDs, which is the highest among the three multilevel converter topologies. The
frequency spectrum of the line voltage of an 11-level MMC converter is depicted
in Fig.3.75.
The MMC converter does not require any auxiliary devices whereas NPC and FC
converters require a huge number of auxiliary diodes and capacitors. Although
at the 3-level, the number of auxiliary devices of the FC converter is compara-
ble with that of the NPC converter, at a higher number of levels, it is a few times
higher. For example, 3-phase 3-level FC and NPC converters require three and
six auxiliary devices, respectively, and 3-phase 17-level FC and NPC converters
3.4 Selection of Multilevel Converter Topology for Medium-Voltage Applications 103
Fig.3.75Frequency
Normalized amplitude
spectrum of 11-level modular 0.04
multilevel cascaded converter
0.02
0
0 5000 10000 15000
Frequency (Hz)
0
2 4 6 8 10 12 14 16 18
Number of levels
Fig.3.77Overall
comparisons of multilevel 2.25
converters [32]
1.80
1.56
1.17 1.28
11-level MMC
1.06
11-level NPC
5-level MMC
11-level FC
5-level NPC
5-level FC
and logic operations (ALOs) for the switching section is calculated through the
MATLAB/Simulink environment. The number of ALOs is used to compare the
complexity of the converters, as summarized in Table3.12.
Based on the performance, control complexity, and semiconductor cost, an
overall comparative study is carried out among the converter topologies men-
tioned. If y is the given value, ymin the minimum value, and ymax the maximum
value in a group of data, the normalized index value can be calculated as
y ymin
Id = . (3.25)
ymax ymin
Table3.13 summarizes the index values of Table3.12. The lower the complexity,
cost and THDs, the better the converter, i.e., a lower index value indicates a better
3.4 Selection of Multilevel Converter Topology for Medium-Voltage Applications 105
converter performance/cost. The total index values of all converters are plotted in
Fig.3.77. For the lower-level number converter, the NPC converter topology may
be the best choice. But for the higher-level number converter, the MMC converter
topology may be the best choice. Moreover, in the MMC converter, the individual
modules are identical and completely modular in construction, and thus, in case
of a fault in one of these modules, it is possible to replace it quickly and easily.
Therefore, the MMC is the proper converter topology to design a medium-voltage
converter for the step-up transformer-less direct grid connection of renewable gen-
eration systems (Fig.3.77).
3.5Summary
Among the three basic multilevel converter topologies, the NPC converter topol-
ogy gives the best harmonic performance. The number of auxiliary diodes in an
NPC converter linearly increases with the number of converter level. This large
number of diodes affects the reverse recovery of the clamping diodes which is a
major design challenge in medium- or high-voltage applications. Therefore, the
NPC converter topology is not suitable for medium- or high-voltage applications
where a higher number of converter level is required.
The harmonic performance of the FC converter topology is slightly better than
that of the MMC converter. In the FC converter, the number of required auxiliary
capacitors is quadratically related to the number of converter levels. When the
number of converter levels is high, the number of required capacitors will make
the system impractical to implement. The FC converter requires an extra con-
trol circuit to pre-charge the clamping capacitors with the required voltage level,
which decreases the system performance and increases the complexity and cost
of the converter. These clamping capacitors increase the weight and volume of the
converter and significantly reduce its lifetime. Therefore, the use of FC converter
is still within the 5-level converter topology.
Unlike the NPC and FC converter, the MMC converter does not require any
auxiliary diodes or capacitors. The MMC converter would be the natural choice to
design medium-voltage power converters for step-up transformer-less grid integra-
tion of renewable generation units, because there is no requirement for any aux-
iliary devices, and individual modules are identical and completely modular in
construction. The MMC converters can enable high-level number attainability as
well as significant reduction in the semiconductor cost of the converter.
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Chapter 4
Design and Characterization
of High-Frequency Magnetic Links Used
in Power Electronic Converters
4.1Introduction
a
b
c
SA5 SA7 SB7 SC5 SC7 n
SB5
all cascaded modules have different power ratings. This diminishes the modular-
ity and thus limits the high-level attainability and increases the cost of the con-
verter. In this converter system, the high-frequency magnetic link generates
multiple sources from a single source with different voltages and power ratings.
Moreover, in the asymmetric cascaded multilevel converter system, only the auxil-
iary H-bridges are connected through the high-frequency magnetic link. The main
H-bridges are supplied directly from the source, which means that there is no elec-
trical isolation between the grid and load. Therefore, the use of this converter is
limited to the isolated winding motor applications [6]. For step-up-transformer-
less grid-connected renewable generation systems, the medium-voltage converter
should have the capability to ensure electrical isolation and minimize the common
mode issues. In this case, all H-bridge modules (auxiliary and main) require con-
necting through the high-frequency magnetic link.
In 2013, a high-frequency magnetic link with multiple identical secondary wind-
ings was proposed to interconnect wind turbine generator with MMC converter [7].
The identical secondary windings of the common magnetic link generate multiple
isolated sources for the MMC converter. Figure4.2 shows the basic block diagram
of common high-frequency magnetic-link-based medium-voltage converter system.
Although the common magnetic link may ensure equal voltages at the secondary ter-
minals, the topology diminishes modularity of the power conversion system, which
is very important for medium- or high-voltage high-power system. The implementa-
tion of high-power high-frequency inverter is the main challenging issue. Moreover,
the leakage inductance may also limit the power capacity of the high-frequency
magnetic link. In this regard, identical multiple four windings (single primary and
three secondaries) high-frequency magnetic links can be connected in cascaded form
to have same current passing through all primary windings of all magnetic links.
Module-2
Generator A
+ H-bridge
Power B H-bridge H-bridge
HF P inverter
A B inverter C inverter
G Frequency
Rectifier Cd inverter with rectifier with rectifier with rectifier
C
HF magnetic-link Phase-A Phase-B Phase-C
Module-N
A
B H-bridge H-bridge H-bridge
P inverter
A B inverter C inverter
with rectifier with rectifier with rectifier
C
HF magnetic-link Phase-A Phase-B Phase-C
Figure 4.3 shows the basic block diagram of cascaded high-frequency magnetic-
link-based MMC converter. The cascaded magnetic links give freedom to use mul-
tiple low-power magnetic cores other than a single high-power core, which helps to
increase the modularity and reduce the leakage inductances. Still this topology uses
single high-frequency inverter to energize all high-frequency magnetic links, whose
implementation is really critical when the power level is high.
In order to keep the modularity of whole power conversion system, the high-
frequency magnetic link as well as high-frequency inverter should also be mod-
ular. Each identical magnetic link can be excited by identical high-frequency
inverter. All high-frequency inverters may be energized by the same power source,
which helps generate equal voltage at the secondary terminals and ensure bal-
anced DC supplies for the MMC converter. In this topology, each module consists
of a high-frequency inverter, a four windings magnetic link, and three H-bridge
inverters with high-frequency rectifiers. Each module may provide three-level
line-to-line voltage. Figure4.4 shows a modular converter for medium-voltage
grid connection of wind turbine generators. With this topology, it is very simple to
change the converter power level by addition or subtraction of modules.
In power frequency transformers, the most widely used magnetic materi-
als are silicon-steel sheets, nickel-steel sheets, and nanocrystalline ribbons. With
higher excitation frequencies, the skin and proximity effects, hysteresis losses,
and dielectric losses will increase significantly. Therefore, various better magnetic
materials with high saturation flux densities and low specific power losses have
been developed in the last few decades. Among these materials, the amorphous
4.1Introduction 113
Module-2
Generator A
+ B H-bridge H-bridge H-bridge
HF
P A inverter B inverter C inverter
G inverter
Cd with rectifier with rectifier with rectifier
C
HF magnetic-link Phase-A Phase-B Phase-C
Rectifier
Module-N
A
B H-bridge H-bridge H-bridge
HF
P A inverter B inverter C inverter
inverter
with rectifier with rectifier with rectifier
C
HF magnetic-link Phase-A Phase-B Phase-C
and nanocrystalline are the most commonly used core materials in recent high-
frequency applications. This reduced weight and volume medium-frequency
transformer can be integrated in the MMC converter structure to overcome all the
existing limitations, such as the requirement for multiple isolated DC supplies,
balancing of DC-link voltages, grid isolation, and common mode issues [9].
This chapter presents the development and characterization of a high-frequency
magnetic link with multiple secondary windings to couple the renewable energy
source to the MMC converter. The high-frequency magnetic link is used to gener-
ate the isolated balanced multiple DC supplies for all of the H-bridge inverter cells
of the MMC converter from a single low-voltage power source. Compared with
the conventional power frequency transformers, the high-frequency magnetic links
have much smaller and lighter magnetic cores and windings, and thus much lower
costs. The high-frequency magnetic-link-based multilevel converter systems will
have the following advantages: (i) capable of generating multiple isolated sources
from a single or multiple sources, (ii) inherent DC-link voltage balancing, (iii)
inherent grid isolation capability, and (iv) a wide range of MPPT operation.
where N is the number of turns, f the frequency of excitation current, and the
magnetic flux linking to the winding. For a given power capacity, as the operat-
ing frequency increases, the required cross-sectional area of the magnetic core
and the number of turns of the primary and secondary windings can be dramati-
cally reduced. The following sections present the design and analysis of two
high-frequency magnetic links of single primary and six secondary windings.
The magnetic links can be used to generate six isolated balanced DC supplies of a
three-phase 5-level MMC converter. The concept can be used to model other mag-
netic links for other power converter topologies by only changing the number of
primary and secondary windings according to power converter requirements.
Taking into account the operating frequency of commercially available power semi-
conductor devices, one can find a frequency window in the range of 120kHz for
the proposed system. According to the power inverter rating, the magnetic-link
specifications, such as the rated power, frequency, excitation current, and voltage,
can be calculated. From the specifications of magnetic link and the data sheets of
core materials, magnetic-link initial parameters can be calculated. These parameters
can be used as the initial values of optimization process. The volume and weight
of the transformer were optimized by selecting proper parameters. Different fac-
tors are considered during the design process, such as the winding dimensions, hole
reserve for natural cooling, maximum temperature limits, maximum power loss,
availability of core material stripe dimensions (standard available widths in the range
of 2.550mm and thickness of 20m), parasitic parameters, skin and proximity
effects, and possibility to induce identical voltage in multiple secondary windings.
Single-layer windings have low AC/DC resistance ratios, which would increase
significantly the winding and core dimensions. For simplicity of the winding pro-
cess, a toroidal core structure is adopted. Finally, the inner and outer diameters,
and height of the core are chosen as 6.5, 10.5, 25mm, respectively. The flowchart
of the proposed methodology for the multiple secondary windings high-frequency
magnetic-link design is depicted in Fig.4.5. As shown, the design process involves
multiphysics problems with some critical decision making tasks.
Along with the advent of new power semiconductor devices, different soft magnetic
materials are conceived with a high magnetic saturation and low core loss to reduce
the weight and volume of conventional power transformers. The grain-oriented sili-
con-steel sheet, which are commonly used as the core material for power frequency
transformers, are not suitable for medium-frequency applications because of the
4.2 Design of High-Frequency Magnetic Links 115
Calculation of
number of turns
Calculation of
winding dimensions
Calculation of core
dimensions
Calculation of
losses
Considerations of
temperature and
parasitic effect
No
Optimized?
Yes
Optimized
parameters
Stop
heavy eddy current loss [11]. The soft ferrites have been widely used in medium-
and high-frequency inductors and transformers due to their low price and general
availability. Because of the low saturation flux density [11] (only 0.30.5T), which
results in the transformers large size, they are not suitable for large power applica-
tions. The amorphous alloy and nanocrystalline magnetic materials have excellent
magnetic characteristics, such as high permeability, high saturation flux density, and
relatively low core losses at medium-/high-frequency range [1214]. Metglas is a
commercially available amorphous material manufactured by Hitachi Metals, Japan.
Figure 4.6 shows a photograph of Metglas stripe. The Metglas magnetic alloys
2705M and 2714A are cobalt-based materials with maximum flux density of 0.77
and 0.57T, and the specific core losses are about 6W/kg and 3W/kg, respectively,
at 10kHz sinusoidal excitation of 0.3T. The alloy 2,826MB is ironnickel-based
material with maximum flux density of 0.88T and specific core loss of 30W/kg at
116 4 Design and Characterization of High-Frequency
Fig.4.6Metglas amorphous alloy 2605S3A stripe of 20m thickness and 25mm width
10-kHz sinusoidal excitation of 0.3T. The Metglas alloys 2605SA1 and 2605S3A
are iron-based material with maximum flux density of 1.56 and 1.41T, and the spe-
cific core losses are about 20 and 7W/kg, respectively, at 10-kHz sinusoidal excita-
tion of 0.3T. Table4.1 summarizes the properties of five different Metglas alloys,
which are commercially available.
There are a few vendors providing commercially manufactured nanocrys-
talline magnetic materials, such as Hitachi Metals, Vacuumschmelze, MH&W
International, and AMMET, etc. Commercially available nanocrystalline mag-
netic materials are Finemet, Vitroperm, and Nanoperm, which are manufactured
by Hitachi Metals, Vacuumschmelze, and MH&W International, respectively.
Figure 4.7 shows a photograph of Vitroperm nanocrystalline stripe. Table4.2
summarizes the properties of nanocrystalline materials. The precursor material
of Finemet is amorphous metal obtained by rapid quenching the molten metal,
4.2 Design of High-Frequency Magnetic Links 117
Fig.4.7Compound
VITROPERM stripe [16]
consisting of Fe, Si, B, and small amounts of Cu and Nb. By applying heat treat-
ment to the alloy at higher temperature than its crystallization temperature, this
alloy forms nanocrystalline structure (grain size of approximately 10nm).
Although the nanocrystalline material has lower specific core loss than
Metglas, its saturation flux density (about 1T) is much lower than that of Metglas,
which is up to 1.56T. Taking into account the flux density, specific core loss, cost,
and availability, the Metglas alloys 2605S3A and 2605SA1 stripe of 20 and 30m
thickness, respectively, have been chosen as the core materials. In order to develop
test cores, the core material Metglas alloys 2605S3A and 2605SA1 ribbons were
collected from Metglas Inc.
The coefficients, k, m, and n in Steinmetz Eq.(4.2) deduced from the data-
sheet for this material are experimental results under sinusoidal voltage excita-
tion, where f is the frequency in kHz and B the magnitude of flux density in T.
Table 4.3 summarizes the datasheet coefficients of Steinmetz equation. Usually,
the high-frequency magnetic links are operated under non-sinusoidal voltage exci-
tations, i.e., square-wave voltage [17]. Therefore, for this design, new coefficients
118 4 Design and Characterization of High-Frequency
Using these two sets of coefficients, the specific core losses of Metglas alloy
2605SA1 have been compared. About 2030% extra loss is observed due to non-
sinusoidal excitation waveform. Figure4.8 shows the specific core loss of Metglas
alloy 2605SA1 under square-wave voltage excitation. Compared with Metglas
alloy 2605SA1, 2605S3A gives much lower core loss. Figure4.9 plots the specific
core loss of Metglas alloy 2605S3A.
Coils of high-frequency magnetic links are usually wound with Litz wires. High
number of turns may increase the volume, weight, cost, and winding complexity of
the high-frequency magnetic links. On the other hand, sufficient number of turns is
10000
Metglas 2605SA1
11 kHz
16 kHz
1000
21 kHz
Core loss (W/kg)
26 kHz
10
0
10
6 kHz
1 1 kHz
0.1
0.1 0.2 0.3 0.4 0.5 1 2
Flux density (T)
Fig.4.8Specific core loss in terms of flux density and frequency of Metglas alloy 2605SA1
under square-wave excitation
4.2 Design of High-Frequency Magnetic Links 119
10000
Metglas 2605S3A 11 kHz
1000 16 kHz
Core loss (W/kg) 21 kHz
100 26 kHz
10
1
6 kHz
1 kHz
0.1
0.01
0.1 0.2 0.3 0.4 0.5 1 2
Flux density (T)
Fig.4.9Specific core loss in terms of flux density and frequency of Metglas alloy 2605S3A
under square-wave excitation
The expression of the voltage can be deduced by substituting (4.4) into (4.3) as
T
N Tmax
/4 0 t 2
v(t) = . (4.5)
N Tmax T
/4 2 t T
max
T
120 4 Design and Characterization of High-Frequency
Let
max
Vmax = N (4.6)
T /4
and (4.5) can be rewritten as
Vmax 0 t T2
v(t) = . (4.7)
Vmax T2 t T
2 T
Vrms = 2
Vmax = Vmax (4.9)
T 2
The current density within the conductors becomes highly uneven as the excita-
tion frequency increases, due to mainly the skin and proximity effects. With the
increase of excitation frequency, the current density will reduce inside the con-
ductor and increase near the surface. This is called the skin effect. As a result,
although the total amount of current within the conductor is not affected, the cur-
rent density distribution across the conductor becomes non-uniform, and the AC
resistance significantly higher than the DC resistance. The skin effect can be eval-
uated by the skin depth, which is defined as the radial distance from the surface of
the conductor to where the value of current density is 37% smaller than its value
at the surface [18]. The relationship between the skin depth and the operating fre-
quency can be deduced as
= . (4.15)
f
where is the permeability of the material, the resistivity, and f the frequency.
Figure4.11 depicts the skin depth versus frequency of a copper conductor.
If Rdc is the DC resistance of a winding carrying a current of I, the skin effect
loss in a Litz winding can be calculated by [18]
Pskin = Rdc I 2 1 ( ). (4.16)
4
where
d
= (4.17)
2
and
ber( )bei ( ) bei( )ber ( )
1 ( ) = (4.18)
ber ( )2 + bei ( )2
where
ber( ) = Re J( ej3/4 ) , (4.19)
1.5
0.5
0 5 10 15 20
Frequency (kHz)
122 4 Design and Characterization of High-Frequency
bei( ) = Im J( ej3/4 ) , (4.20)
ber( ) + bei( )
ber ( ) = (4.21)
2
and
ber( ) + bei( )
bei( ) = (4.22)
2
Figure4.12 shows the skin effect loss in a round conductor for different penetra-
tion ratios, d/.
On the other hand, the AC current in a wire also generates a magnetic field that
enters the adjacent conductors and induces emfs inside these conductors, resulting
in non-uniform current distribution in the conductors. This is called the proximity
effect, which highly depends on the excitation frequency [18]. Although the total
current of the conductor does not change; the current density in the conductor will
be reduced near the adjacent wire and reinforced on the opposite side through a
redistribution of current density. Proximity effects can be classified into two types,
internal proximity effectsthe effects on each of the strands due to the field gen-
erated by the strands, and external proximity effectsthe effects on an isolated
round conductor within an external field. If ls is the total length of a single strand,
ns the total number of strands, rb the radius of the bundle, and the conductivity,
the power loss due to the internal proximity effects can be calculated by [18]
n s I 2 ls
Pp_int = 2 ( ). (4.23)
4 rb2
where
ber2 ( )ber ( ) + bei2 ( )bei ( )
2 ( ) = . (4.24)
ber ( )2 + bei ( )2
The power losses due to an external magnetic field, He, can be calculated by [18]
1.2
1
0 1 2 3 4 5
Penetration ratio
4.2 Design of High-Frequency Magnetic Links 123
tsc
fe
ef
al
rn
ts
1
te
c
fe
Ex
ef
al
rn
te
In
0
0 0.5 1 1.5 2 2.5
Penetration ratio
2
Pp_ext = ns He2 2 ( ). (4.25)
Figure4.13 shows the power loss in a round conductor due to proximity effects.
The skin and proximity effects will increase the AC losses in high-frequency
windings. A special type of wire has been conceived named the Litz wire, a con-
ductor consisting of insulated strands twisted or braided together. Such a design
equalizes the flux linkages of individual strands causing the current to spread
uniformly throughout the conductor, and the AC to DC resistance ratio tends to
approach unity. In a conductor, the AC/DC resistance ratios, Kr, depends strongly
on the number of layers, U, the conductor diameter, d, and the operating fre-
quency. The AC resistance of the U-th layer for solid round wires can be repre-
sented as [19]
Rac
Kr = = M( ) + (2U 1)2 D( ) . (4.26)
Rdc 2
where
0.886d
= (4.27)
sinh( ) + sin( )
M( ) = (4.28)
cosh( ) cos( )
sinh( ) sin( )
D( ) = (4.29)
cosh( ) + cos( )
and
0.071
= (4.30)
f
For a particular core shape and defined fill factor, there should be an optimal selec-
tion of the Litz wire strand number and diameter to realize the minimum loss.
Figure 4.14 shows the AC/DC resistance ratio of a U-layer winding at a 10-kHz
124 4 Design and Characterization of High-Frequency
19
7
U=
U=
1.8
AC/DC resistance ratios
10
4
U=16
U=
U=
1.6
U=13
U is the number of
1.4
layers
1.2
U=1
1
0.8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Diameter (mm)
Fig.4.14Graphical representation of the AC/DC resistance ratio Kr, at 10kHz, showing the
effect of conductor diameter and number of layers on AC resistance
Finally, for the primary windings, the Litz wires with a diameter of 0.4mm are con-
sidered. Theoretically, the overall area of 13 strand wire is 130.115=1.495mm2.
In practical, when 13 insulated strands are twisted or braided together, the overall
diameter of the Litz wire is 2mm and the cross-sectional area of the primary wind-
ing wire 3.2mm2. Also, the required minimum cross-sectional area of the secondary
winding single strand can be calculated as
4.2 Design of High-Frequency Magnetic Links 125
is
as = 3
= 0.083 mm2 (4.33)
J
and the single-strand diameter can be calculated as
4as
ds = = 0.325 mm. (4.34)
Finally, for the secondary windings, the Litz wires with a diameter of 0.4mm are con-
sidered. Theoretically, the overall area of 3 strand wire is 30.083=0.249mm2. In
practical, when 3 insulated strands are twisted or braided together, the overall diame-
ter of the Litz wire is 1mm and the cross-sectional area of the primary winding wire
0.79mm2. Hence, the design can be considered with the wire cross-sectional areas of 4
and 1.2mm2 for the primary and secondary winding, respectively. The area required by
the primary and secondary windings is calculated as
Aw = Np dp + Ns ds (4.35)
Considering a toroid hole reserve factor of 8 for all the windings, the minimum
required toroid hole area can be calculated by
ATH = 8(Np dp + Ns ds ) (4.36)
4.2.5Parasitic Calculation
The leakage flux and stray capacitance may affect the performance of a high-
frequency transformer as well as the operation of the PWM converter. These two
components, leakage inductances and stray capacitances, are usually called para-
sitic parameters.
4.2.5.1Stray Capacitances
Vp Cpo Cso Vs
Np:Ns
Fig.4.16Equivalent circuit C ps
of a two-winding transformer
with stray capacitances; all L lp L ls
Rp Rs
parameters referred to the
primary side [22] Vp Cp Rm Ep Vs
Cs
-shaped network of three lumped capacitances approach [20, 21] gives a clear
view of the coupling capacitances using the concepts of self- and mutual capaci-
tances. This approach represents the overall effects of all stray capacitances by three
lumped capacitors, such as the self-capacitances of the primary and secondary wind-
ings, and the mutual capacitance between the primary and secondary windings [22].
Figure 4.15 illustrates the circuit of a two-winding transformer with stray capaci-
tance effects, where Rp and Rs are the resistances of the primary and secondary
windings and Cpo, Cso, and Cpso are the self-capacitances of the primary and second-
ary windings, and the mutual capacitance between two windings, respectively.
If Llp is the leakage inductance of the primary winding, Lls the equivalent leak-
age inductance of secondary winding referred to the primary side, Ep the mag-
netization back emf, and Rm and Lm are the equivalent core loss resistance and
magnetization inductance, respectively, the equivalent circuit of a two-winding
transformer referred to the primary side with stray capacitance effects can be rep-
resented by a network as shown in Fig.4.16 [22].
The equivalent capacitances, Cp, Cs, and Cps, can be calculated from
Ns
Cp = Cpo + 1 Cpso (4.37)
Np
2
Ns Ns Ns
Cs = Cso + 1 Cpso (4.38)
Np Np Np
and
Ns
Cps = Cpso . (4.39)
Np
If Rp and Rs can be ignored and the primary and secondary windings are short
circuited, it is possible to measure Cpso approximately as the capacitance between
the primary and secondary. In order to calculate the Cpso, an external inductor with
4.2 Design of High-Frequency Magnetic Links 127
known inductance value, Lex can be used to make a resonance circuit and then
from two resonance frequencies, f1 and f2, the Cpso can be calculated from
1 1
Cpso = . (4.40)
(2f2 )2 Lex (2f1 )2 Lex
Using (4.39) and (4.40), Cps can be calculated.The approximate values of capaci-
tances Cp and Cs can be calculated from the short-circuit test of Fig.4.15 with the
following relations
Cp = Ceqp Cps (4.41)
and
Cs = Ceqs Cps . (4.42)
where the capacitances Ceqp and Ceqs are the approximated equivalent capaci-
tances seen from the primary and secondary sides with the other side short cir-
cuited, which makes the circuit just like a single-coil inductor. The equivalent
capacitances Ceqp and Ceqs can be calculated from the step response of the circuit
under the condition of one-side short circuited. If Vc is the capacitor-charging
voltage and Ic is the average capacitor current over a time period, t, the stray
capacitance of the coil inductor can be calculated from
tIc
Ceq = . (4.43)
Vc
4.2.5.2Leakage Inductances
Usually, the leakage inductance is defined as the ratio of the leakage flux linking a
winding, l, and the current passing through the winding, i, which is appropriate in
the case of linear magnetic cores. In order to develop the dynamic circuit model of
a high-frequency transformer, differential leakage inductance may be used due to
its non-linear magnetic properties, which can be defined as [22]
dl
Ldl = i. (4.44)
d
The differential leakage inductances of the primary and secondary windings can
be defined by
dlp (ip )
Ldlp = . (4.45)
dip
and
dls (is )
Ldls = . (4.46)
dis
If imp and ims are the magnetization currents seen from the primary and second-
ary sides, respectively, the mutual inductances between the primary and secondary
windings can be defined by
128 4 Design and Characterization of High-Frequency
dmp dm
Ldmp = = Np . (4.47)
dimp dimp
and
dms dm
Ldms = = Ns . (4.48)
dims dims
where m is the mutual flux.
An equivalent circuit of a two-winding medium-frequency transformer is
shown in Fig.4.17 [22].
If p (im ) = Np m (im ) + Np lp (ip )is the total flux linkage of the primary wind-
ing and s (im ) = Ns m (im ) Ns ls (is ) the total flux linkage of the secondary
winding, and lp and ls are the leakage flux of the primary and secondary wind-
ings, respectively, the differential self-inductances of the primary and secondary
windings can be calculated as
p
Ldp = . (4.49)
ip
and
s
Lds = . (4.50)
is
For self- and mutual inductances the leakage inductances of the primary and sec-
ondary windings can be calculated as
Ldlp = Ldp Ldmp (4.51)
and
Ldls = Lds Ldms . (4.52)
4.2.6Design Optimization
It has been widely employed for optimization of electromagnetic devices and has
achieved many improvements [24, 25].
The procedure of DEA, very similar to that of the genetic algorithm, consists of
three processes, namely mutation, crossover, and selection. It starts by initializing
the population randomly in the design space. The individuals in the population are
then perturbed with others through mutation and crossover operators, and a new
population consisting of the most promising solution can be generated by applying
a selection criterion [23, 24]. Different factors are considered during the optimi-
zation, such as the winding dimensions, hole reserve for natural cooling, maxi-
mum temperature limits, maximum power loss, availability of core material stripe
dimensions (available sizes of alloys 2605S3A and 2605SA1: widths of 2.550
and 5213mm, respectively, and thickness of 20m), parasitic parameters, skin
and proximity effects, and possibility to induce identical voltage in multiple sec-
ondary windings. Power loss, size, and weight of the high-frequency magnetic link
have been considered the main objective functions of optimization process.
In the implementation, the algorithm parameters of DEA are mutation factor of
0.8, crossover factor of 0.8, the maximum number of iteration of 1,000, and the maxi-
mum stall generation of 100 (as the stop criterion) [25]. The optimal parameters of
2.5-kVA magnetic links are summarized in Table4.5. The designs show that magnetic
alloy 2605S3A has a slightly larger volume and weight but much lower specific core
loss than that of alloy 2605SA1 and is suitable for high-frequency magnetic links.
Ansoft Maxwell 3D solves the electromagnetic field problems for a given
model with appropriate materials, boundaries, and source conditions, applying
Maxwells equations over a finite region of space. There are two types of solutions
available in Maxwell 3D, such as magnetic fields and electric fields. Category
magnetic fields cover three solvers, such as magnetostatic to calculate static mag-
netic fields, forces, torques, and inductances caused by DC currents, eddy current
to calculate sinusoidally varying magnetic fields, forces, torques, and impedances
caused by AC currents and oscillating external magnetic fields, and transient mag-
netic to calculate transient magnetic fields caused by time-varying or moving elec-
trical sources and permanent magnets. Electric fields also cover three solvers, such
as electrostatic to calculate static electric fields, forces, torques, and capacitances
caused by voltage distributions and charges, DC conduction to calculate voltage,
electric field, and the current density calculated from the potential, and transient
electric to calculate transient electric fields caused by time-varying voltages,
charge distributions, or current excitations in inhomogeneous materials.
In the Ansoft Maxwell 3D environment, two magnetic cores are mod-
eled using the parameters obtained from optimization and non-sinusoidal
Based on the optimization results, the optimal core dimensions are chosen as 6.5-
cm inner diameter (ID), 10.5cm outer diameter (OD), and 2.5cm height (HT) for
the design, as shown in Fig.4.25.
The Metglas sheet was glued with Araldite 2011 on the surface of each layer,
providing both the electrical insulation and mechanical bonding. During the wrap-
ping process, equal and opposite forces were applied to make a uniform distribu-
tion of Araldite. Figure4.26 shows a photograph of the wrapping process.
132 4 Design and Characterization of High-Frequency
After wrapping, the frame was quickly removed before the Araldite dried up.
The core volume and mass are 133.52cm3 and 0.96kg, respectively. Figure4.27
shows a photograph of the Metglas core with frame; just after wrapping process.
The dried core is shown in Fig.4.28. The core was covered by transformer
tape. To minimize the proximity effect, Litz wires are used for windings with a
4.2 Design of High-Frequency Magnetic Links 133
m
2c
6.5 c
m
ID OD
HT = 2.5 cm ID = 6.5 cm
OD = 10.5 cm HT
Fig.4.27A photograph of the transformer core with frame; just after wrapping
Fig.4.28Photograph of the transformer core with Metglas alloy 2605SA1 ribbon of 30m
thickness and 25mm of width
136 4 Design and Characterization of High-Frequency
each turn is 0.13m. Since the primary winding has 14 turns and each second-
ary winding has 25 turns, the total winding wire lengths are 1.82 and 3.25m,
respectively. About 0.14 and 0.08m extra wires are required for the end con-
nection of primary and secondary windings, respectively. When the strands are
twisted together, there is an increase in the length of the windings. About 1.14
and 1.09% increases are observed in the length of primary and secondary wind-
ings, respectively. Therefore, the overall length (1.82+0.14)1.14=2.24m
and (3.25+0.08)1.09=3.62m are considered for the primary and second-
ary windings, respectively. The diameters of primary and secondary wind-
ing copper wires are the same (0.4mm), and also the cross-sectional areas
(12.56 108m2). Therefore, the resistance of a single strand at 20C can be
calculated by
2.24
RP = 1.678 108
12.56 108
= 0.30 (for single strand of primary winding) (4.55)
= 0.0230 (for primary winding, 13 strands) and
3.62
RS = 1.678 108
12.56 108
= 0.483 (for single strand of secondary winding) (4.56)
= 0.161 (for each secondary winding, 3 strands)
At the room temperature of 23C (during the test), the resistance can be calcu-
lated by
234.5 + t2
Rt2 = Rt1 (4.57)
234.5 + t1
234.5 + 23
Rt2 = Rt1 = 1.012 Rt1 (4.58)
234.5 + 20
Therefore, 0.0233 and 0.162resistances are considered theoretically for the pri-
mary and secondary windings, respectively.
A digital multimeter (DMM) was used to get an idea about the range of resist-
ances. The DMM readings are tabulated in Table4.6.
The Wheatstone bridge is also suitable for measuring a small unknown electrical
resistance by balancing two legs of a bridge circuit. Figure4.31 shows the Wheatstone
bridge circuit diagram, and Fig.4.32 describes the measurement technique.
138 4 Design and Characterization of High-Frequency
R1 R3
G
5V
R2 RX
E
F
R1 R3
D
G P
5V
R2 RX C
A
B
R2
Therefore, RX = R3 . (4.60)
R1
The Wheatstone bridge is used to measure the resistance of the coils since the coil
resistance is very small. The lead wire resistance is also considered and subtracted
from the measured values, as tabulated in Table4.7. The measured winding resist-
ances are compared with theoretical values and the variation in percentage is also
tabulated in Table4.7.
If the number of turns of primary coil (P) is NP, the numbers of turns of secondary
coils (A, B, C, D, E, and F) are NA, NB, NC, ND, NE and NF, and the corresponding
induced voltages in the primary and secondary coils are vP, vA, vB, vC, vD, vE, and
4.3 Characterization of High-Frequency Magnetic Links 139
vF, respectively, the voltage transformation ratio can be expressed by (the same
number of turns in all secondaries)
NA NB NC ND NE NF
= = = = = (4.61)
NP NP NP NP NP NP
vA vB vC vD vE vF
= = = = = = . (4.62)
vP vP vP vP vP vP
The theoretical turn ratio can then be calculated as
374
= = 1.781.
210
The coil P is excited by a 50-Hz alternating current, iP, and the corresponding second-
ary coil-induced voltages, vP, vA, vB, vC, vD, vE, and vF, obtained from the respec-
tive coils, P, A, B, C, D, E and F, are listed in Tables4.8 and 4.9. The transformation
ratios of all secondary coils, TRA, TRB, TRC, TRD, TRE, and TRF, are calculated with
respect to the primary coil. The measured ratios compared with the calculated values
140 4 Design and Characterization of High-Frequency
are also listed in Tables4.8 and 4.9. The measured ratios fairly coincide with the cal-
culated values, considering the very small change in voltage with the large change
in excitation current since at this frequency, the winding resistances are quite small.
Utility supply with single-phase auto-transformer can be used to calculate the volt-
age transformation ratios at 50-Hz sinusoidal excitation. A Fluke clip-on wattmeter
is used to measure the voltage and current of the coils. Figure4.34 shows the experi-
mental setup to calculate voltage transformation ratios at 50-Hz sinusoidal excitation.
Voltage transformation ratios are also calculated with a 1-kHz excitation cur-
rent. The calculated transformation ratios are compared with the theoretical values
as listed in Tables4.10 and 4.11. The ratios are highly coincident with the theoreti-
cal values and better than power frequency transformation ratios.
The voltage transformation ratios have also been measured at 10kHz and com-
pared to the calculated value (1.781). The ratios and their percentage variation from
the calculated value are summarized in Tables4.12 and 4.13. The high-frequency
transformer generates 6 almost equal and isolated sources (i.e., all secondary wind-
ings show similar voltage transformation characteristics). Such a similarity of char-
acteristics is obligatory to generate balanced multiple sources for the MMC system.
4.3.3Measurement of Losses
V B (374 V)
V p (210 V)
Voltage Current
calculated by using the DC resistances (0.024 for the primary and 0.16 for
copper loss of each winding at a different frequency ranging from 4 to 12kHz was
the secondary), since the AC/DC resistance ratios, Kr, in this design are almost
unity due to the use of the Litz wires. Figure4.38 shows that the total losses of all
secondary windings measured at different excitation frequencies ranging from 4 to
12kHz are almost the same. Measurements were also conducted by exciting the
secondary windings one by one with different excitation currents (0.10.6 A) and
a fixed frequency of 10kHz. Table4.15 summarizes the losses of all six second-
ary windings with different values of excitation current. As shown in Fig.4.39, at
10kHz, all secondary windings also have very similar total losses. Such a similar-
ity of characteristics is also obligatory to generate balanced multiple sources for
the MMC system. The proper balancing of all sources means the elimination of
the extra control circuit with the switching algorithm.
The core loss against flux density was measured within the frequency rang-
ing from 6 to 12kHz. The specific core loss of Metglas alloy 2605SA1 measured
was 157W/kg under 10-kHz square-wave excitation of magnitude 0.8T as shown
in Fig.4.40, while the specific core loss of 125W/kg is reported by the material
144 4 Design and Characterization of High-Frequency
Fig.4.38Measured total
losses of Metglas alloy 80
2605SA1 against excitation 70 A
Loss (W)
frequencies at excitation
current of 0.35A; only one 60 B
coil is energized at a time C
50
while the others are open D
circuited 40 E
F
30
4 5 6 7 8 9 10 11 12
Frequency (kHz)
4.3.4Measurement of BH Characteristics
The magnetic field intensity and magnetic flux density are calculated by measuring
the P-coil excitation voltage and current and the open-circuit terminal voltage of the
secondary side D-coil. As the coils are uniformly wound on the toroidal core, the
4.3 Characterization of High-Frequency Magnetic Links 145
Fig.4.39Measured total
losses of Metglas alloy
2605SA1 against excitation 100
Total loss (W)
magnetic field intensity H and magnetic flux density B within the core can be con-
sidered as uniform. By the Amperes law, the field intensity can be calculated as
N1 i(t)
H= . (4.63)
le
where N1 is the number of turns in the primary coil, i(t) the excitation current, and
le the mean length of the core.
146 4 Design and Characterization of High-Frequency
Fig.4.40Measured core
12 kHz
losses of Metglas alloy
2 10 kHz
2605SA1 at different 10
By the Faradays law, the magnetic flux density in the core can be calculated as
1
B= VL dt. (4.64)
N2 Ae
where N2 is number of turns in the pickup coil (D-coil) and Ae the cross-sectional
area of the core, and VL the pickup coil voltage.
Different magnitude of 10-kHz excitation currents (e.g., 13A) are applied to
the primary windings. The BH loops are plotted in Fig.4.41 based on experimen-
tal data. Up to 0.5T, the flux density rises sharply with a constant field intensity
of about 50A/m. At 3A, the maximum magnetic flux density is about 0.8T with
the field intensity of about 600A/m, which satisfies the design requirement. The
BH loops are also measured at different temperatures ranging from 40 to 100C
as depicted in Fig.4.42. The maximum flux density remains approximately con-
stant for this temperature range, as illustrated in Fig.4.43. The FLUKE infrared
temperature probe 80T-IR and FLIR infrared thermal imaging camera i7 were
used to measure the temperature of the high-frequency magnetic links. Figure4.44
shows the thermal image of the high-frequency magnetic link when the probe
was pointed at the surface of the core. Quite lower temperature is observed at the
center of the toroid hole. Figure4.45 shows the thermal image of the high-fre-
quency magnetic link when the probe was pointed at the center of the toroid hole.
Fig.4.41Measured BH
loops of Metglas alloy
2605SA1 at 40C; maximum
magnetic flux density at 1,
2, and 3A is 0.65, 0.74, and
0.80T, respectively
4.3 Characterization of High-Frequency Magnetic Links 147
Fig.4.42Measured BH
loops of Metglas alloy
2605SA1 at different
temperature ranging from 40
to 100C
Fig.4.43Measured
0.8
maximum magnetic flux
Max. flux density (T)
Fig.4.44Thermal image of
high-frequency magnetic link
when the probe was pointed
at the surface of the core
Fig.4.45Thermal image of
high-frequency magnetic link
when the probe was pointed
at the center of the core
Fig.4.46Measured BH
loops of Metglas alloy
2605S3A at excitation current
of 3 and 5 A. The link is
excited by 12-kHz square-
wave primary voltages
Fig.4.47Measured
BH loops of Metglas
alloy 2605S3A at various
temperatures. The link is
excited by 12-kHz square-
wave primary voltages
Fig.4.48Measured BH
loops of Metglas alloy
2605S3A at different
frequencies
Fig.4.49Measured BH
loops of Metglas alloys
2605SA1 and 2605S3A;
the links are excited by
12-kHz square-wave primary
voltages
of Metglas alloy 2605S3A are compared with that of Metglas alloy 2605SA1, as
shown in Fig.4.49. In comparison with 2605SA1, the 2605S3A shows a slightly
narrower BH loop, i.e., lower core loss.
Vdc (370 V)
VB (376 V)
50 Hz phase voltage
738 V peak value
Fig.4.51Measured phase voltage of the prototype 5-level MMC converter before the LC line
filter circuit
4.4Summary
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152 4 Design and Characterization of High-Frequency
5.1Introduction
Fig.5.1Photograph of an
ASIC by AMI
increases not only the developmental time but also the cost of the controller. In
this chapter, a fully digital switching controller is developed for a 3-phase 5-level
converter. The SK 30 GH 123 IGBTs are used to develop a prototype multilevel
converter, and an XC3S500E FPGA is used to develop the switching controller.
The most common software such as the MATLAB/Simulink- and Xilinx ISE-
based alternative design technique is used, which may reduce the developmental
time and cost of the switching controller. The simulation results serve as a pre-
liminary validation of the proposed design technique, which will be finally verified
by the experimental results. The developed switching scheme can be used for any
multilevel converter configurations with very little change in the software environ-
ment. Moreover, the proposed design and implementation techniques may be use-
ful for designing any other modern power converters switching controller.
5.1.1ASIC Technology
5.1.2DSP Technology
Compared to an ASIC, the DSP and FPGA technologies have much lower NRE
costs. The DSP has a fixed hardware configuration, which is the hardware of the
5.1Introduction 155
Fig.5.2Photograph of a
DSP by TI
5.1.3FPGA Technology
Fig.5.3Photograph of an
FPGA by Xilinx
Fig.5.4Multiplications per 10
6
second of texas instruments
DSP and Altera FPGA 10
5
Multiplications/s
4
10
3
10
DSP
2 FPGA
10
1
10
1990 1995 2000 2005 2010
Year
as implementation time, and high reliability and accuracy. In this regard, recent
studies have shown that FPGA could be an appropriate alternative over DSP for
many applications.
signal. The capability of parallel processing of the FPGA provides the opportu-
nity to the switching controller to update all gate signals simultaneously [8]. In
most cases, the processing time is independent of the number of converter levels.
Therefore, the FPGA technology is a natural choice for the control of multilevel
converters. A comparison between the FPGA and the DSP technology is summa-
rized in Table5.1.
Xilinx and Altera are the current market leaders in the FPGA technology. These
two vendors have developed different series of FPGA boards and kits. FPGA
developmental boards and kits are specially designed and suitable for the design of
prototype test platforms. Before selecting the board, the software environment also
needs to be considered because different vendors may use different programming
software. The selection of FPGA boards depends on many factors, such as clock
158 5 FPGA-Based Digital Switching Controller for Multilevel Converters
speed, number of LEs, number of I/O pins, number of multipliers, area of appli-
cations, market availability, and commercial price. A few commercially available
developmental boards and kits are summarized in Table5.2 [9, 10].
Various design techniques and software environments are available for the mod-
eling of switching control schemes with the FPGA technology. The most com-
monly used design techniques are (i) modeling the switching circuit and target
system in the MATLAB/Simulink environment and generation of the pro-
gramming file with hardware description language (HDL) coder, as shown
in Fig.5.6 and (ii) modeling the switching circuit and target system in the
MATLAB/Simulink environment and generation of the programming file with
the System Generator, as shown in Fig.5.7. In order to verify the performance
of generated VHDL code in the simulation environment, the ModelSim and
PSIM with ModCoupler represent the possible options. These techniques require
special software such as HDL coder, System Generator, PSIM, and ModelSim,
which increases the developmental time and cost. Figure5.8 shows the interfacing
with target system in simulation environment. In this chapter, the most common
5.2 FPGA-Based Switching Controller Design Techniques 159
Design
MATLAB/Simulink
HDL coder
HDL verifier
Implementation/Verification
VHDL/Verilog code
FPGA
Design
MATLAB/Simulink
System generator
Develop system generator
representation
FPGA
Reference signal
generator (3-phases)
SA1
>= 0 SB1
SC1
Comp
0o shifted carrier SA2
signal generator SB2
NOT
SC2
Inv
SA3
>= 0 SB3
Inv SC3
Comp
SA4
SB4
NOT
SC4
Inv
SA5
>= 0 SB5
SC5
Comp
90o shifted carrier SA6
signal generator SB6
NOT
SC6
Inv
SA7
>= 0 SB7
Inv SC7
Comp
SA8
SB8
NOT
SC8
Inv
Gate pulses
the right half-bridge). The carrier for each H-bridge cell on a particular phase leg
is phase-shifted by 360/(m1) [11, 12]. Figure5.9 shows the switching scheme
for a 5-level converter [13].
On each phase leg, in total four half-bridge cells, only two carrier signals are
required and the other two can be generated just by inverting them. In total, three
reference signals are required, one for each phase leg. The frequency of the refer-
ence signal determines the frequency of the converter output voltage. The com-
parator module compares the carrier signal with the respective reference signal and
generates control pulses including reasonable deadtime as required by switching
devices. An onboard crystal (e.g., 50MHz) is used for a clock source, and a clock
divider reduces the clock frequency. A lookup table (LUT) is used to generate the
reference signals, which makes the control circuit totally digital and integrated. The
basic architecture of the FPGA-based switching controller is illustrated in Fig.5.10.
In total, there are eight switching devices in a phase, requiring eight gate pulses
to drive them. Including the inverted carrier signals, a total of four carriers are able
to generate four gate pulses when comparing them with a reference signal. The
other four gate pulses can be generated by just inverting these four gate pulses
with a consideration of deadtime.
The available libraries of the Xilinx FPGA development software Xilinx ISE
Design Suite 13.2 only have basic logic symbols, which are clearly insufficient for
FPGA board
SA1
00 Com SB1
00 SC1
1200 1200
SA2
2400 2400
NOT SB2
SC2
Reference
SA3
signal Counter00 00 Com SB3
generator
Dead band unit
SC3
Inv 1800
Carrier
Gate signals
(3-phases) SA4
signal 900 900 NOT SB4
Look-up generator SC4
Inv 2700
Table SA5
Slow Clk Com SB5
SC5
Clk divider SA6
NOT SB6
SC6
Comparator
SA7
Com SB7
Crystal Clk SC7
SA8
NOT SB8
SC8
RTL generation
Timing simulation
Bitstream
FPGA
5.3 Modeling and Schematic Symbol Creation Using VHDL 163
1
sin asin -K- 1
theta
-K- 1
0
sin asin -K- 2
90 -K- 2
1
Amplitude (V)
0.5
0
-0.5
-1
0 0.5 1 1.5
Time (s) -3
x 10
Fig.5.13Two carrier signals; one for the top H-bridge and 90 shifted carrier for the bottom
H-bridge
3 3 3 3
2 2 2 2
1 1 1 1
0 0 0
Up counter Down counter Up counter Down counter
Fig.5.14Updown counter-based carrier signal generation, where H is the highest count, and
t the step size
164 5 FPGA-Based Digital Switching Controller for Multilevel Converters
counter unit. The frequency of the carrier signal should be many times higher than
the reference signal. In this work, 1.5-kHz and 50-Hz frequencies are considered
for the carrier and reference signals, respectively (i.e., carrier is set 30 times fast
as the reference signal). For the 9-bit updown counter, the total number of steps
in a PWM period is 229=1,024. If switching frequency 1.5kHz is considered,
then the required counter clock frequency is 1,0241.5103Hz.
Therefore, the clock divider value, k1, for a system clock frequency of 50MHz
is given by
50 106 Hz
k1 = = 32.552. (5.1)
1024 1.5 103 Hz
In this work, the value of k1 has been considered to be 32, and with this value,
the switching frequency is calculated as 1.525kHz. The updown counter and
comparator unit combination generates a pulse center aligned within the PWM
period. The center-aligned PWM has advantages over the edge-aligned PWM in
that the outputs that control the inverter are not all switching on at the same time,
at the beginning of every period, as they would do with edge-aligned PWM. This
can help reduce noise on the converter power lines, thus increasing conversion
efficiency.
The VHDL-code-based behavioral model of the updown counter is designed
and synthesized using the Project Navigator tool of the Xilinx ISE Design Suite
13.2 software. The syntax of the behavioral model is verified using the behavioral
check syntax tool. After having analyzed the performance of the behavioral model
using the ISim simulator, a schematic symbol is created as shown in Fig.5.15a.
Similarly, the 90 phase-shifted counter is created as depicted in Fig.5.15b. An
inverter or 180 phase shifter is synthesized to generate the inverted carrier sig-
nals from the output of the T_Cou_V_3 and B_Cou_V_3 counters. The schematic
symbol of the inverter is illustrated in Fig.5.16.
Fig.5.15Schematic symbols of updown counter: a without phase shift and b with 90 phase
shift
Fig.5.16Schematic
symbols of inverter, 180
phase shifter
5.3 Modeling and Schematic Symbol Creation Using VHDL 165
In order to generate the 50-Hz 3-phase voltage output waveform, three ref-
erence signals with 120 phase-shifted from each other are needed. The
MATLAB/Simulink model for the generation of these reference signals is illus-
trated in Fig.5.17, and the generated reference signals are shown in Fig.5.18.
The microcontrollers and DSPs are commonly used to generate reference signals.
This additional external component increases the system size, weight, and cost and
requires proper synchronization. In this instance, logic-based reference signal gen-
eration (programming the FPGA logic cells to generate reference signals) using
direct digital synthesis (DDS) has attracted significant attention recently [1416].
The DDS is an LUT-based technique to generate analog signal using stored digital
samples. An LUT is actually a set of memory locations which contain the sampled
values of a desired analog signal.
2*pi
m
Freq
1
sin Ust
12:34
[0 -2*pi/3 2*pi/3]
Phase -K-
deg. ->rad
1
Phase A Phase B Phase C
Reference signals
0.5
0
50 Hz
-0.5
-1
0 0.005 0.01 0.015 0.02
Time (s)
The frequency of the sine wave can be increased by skipping entries in the sine
lookup table as the angular resolution depends on the number of entries, Ln for
a cycle. The angular resolution can be calculated from
360
= (i + 1) (i) = . (5.2)
Ln
The clock divider may determine the frequency of the reference signals. For exam-
ple, if there are 256 entries in the LUT, to generate a 50-Hz reference signal from
256 entries using the 50-MHz clock, the clock divider value k2 is given by
50 106 Hz
k2 = = 3,906.25. (5.5)
256 50 Hz
The sample values of the reference signals can be calculated from (5.4). The ref-
erence signals for phases A, B, and C can be generated by considering the values
of as 0, 120, and 120, respectively. If the peak value, Aout, is 255, and Ln
128
150
100
50
0
0
1 50 100 150 200 250
Entries
Fig.5.20Schematic symbol
of reference signal block
256, the decimal sample values of three sine reference signals can be presented as
shown in Fig.5.19. In order to store the sample values, the decimal number needs
to be converted to hexadecimal number.
A VHDL-code-based program is used to create the LUT, which contains the
sine reference. Different carrier-based modulation techniques used in the tradi-
tional converters can also be used in the MMC converter system (e.g., SPWM and
THPWM) [17]. Each technique has its unique advantages and disadvantages. In
order to analyze the converter performance against different types of reference sig-
nals, sine and third-harmonic injected sine reference signals are stored in the LUT.
Only one reference signal from each type is stored in the LUT. Based on the stored
reference signal, three sine waves (each 120 out of phase from the others) are cre-
ated by using three separate indexes into the LUT. Only one type reference is used
at a time, which can be controlled by an onboard switch without modifying the
program. After verifying the syntax of the behavioral model and analyzing the per-
formance through the ISim Simulator environment, a schematic symbol is created
as shown in Fig.5.20.
5.3.3Comparator Unit
One comparator unit is used for each of the half-bridge cells. The comparator units
compare the carrier signal with a reference signal. Each comparator unit gener-
ates one switching signal for the top switching device of the half-bridge cell. The
inverted form of this switching signal drives the bottom switching device. For the
left half-bridge cell, one is asserted when the reference signal value is greater than
or equal to the carrier signal value, and the other is asserted when the reference
signal value is less than the carrier signal value. For the right half-bridge cell, one
is asserted when the inverted carrier signal value is greater than or equal to the
reference signal value, and the other is asserted when the inverted carrier signal
value is less than the reference signal value. The MATLAB/Simulink model of the
comparator unit for a 5-level converter is illustrated in Fig.5.21. The four carrier
signals and the three reference signals as required by the 3-phase 5-level converter
are depicted in Fig.5.22.
The overall switching system is implemented in the MATLAB/Simulink envi-
ronment to verify the performance roughly. Each H-bridge cell requires four gate
168 5 FPGA-Based Digital Switching Controller for Multilevel Converters
1
TT1
Ust >=
NOT TT2
Com
0 Inv
TT3
>=
-1
Com1 NOT TT4
1
1 Inv1
2 theta
wt
TT5
2 >=
NOT TT6
Com2
2 Inv2
Carriers
Generator TT7
-1
>=
0.5
Amplitude
-0.5
-1
0 0.002 0.004 0.006 0.008 0.01
Time (s)
Fig.5.22Carrier and reference signals in Simulink environment: thick waves represent sine ref-
erence signals and dotted triangular lines represent the inverted form of carrier signals as pre-
sented by triangular solid lines
(a) 1
0.5
0
0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014
(b) 1
0.5
0
0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014
(c) 1
0.5
0
0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014
(d) 1
0.5
0
0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014
Time (s)
Fig.5.23Gate pulses for the top H-bridge cell in phase A: a left top, b left bottom, c right top
and d right bottom
(a) 1
0.5
0
0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014
(b) 1
0.5
0
0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014
(c) 1
0.5
0
0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014
(d) 1
0.5
0
0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014
Time (s)
Fig.5.24Gate pulses for the bottom H-bridge cell in phase A: a left top, b left bottom, c right
top and d right bottom
(a) 1
0.5
0
0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.02
(b) 1
0.5
0
0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.02
(c) 1
0.5
0
0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.02
(d) 1
0.5
0
0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.02
Time (s)
Fig.5.25Gate pulses for the top H-bridge cell in phase B: a left top, b left bottom, c right top
and d right bottom
170 5 FPGA-Based Digital Switching Controller for Multilevel Converters
(a) 1
0.5
0
0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.02
(b) 1
0.5
0
0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.02
(c) 1
0.5
0
0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.02
(d) 1
0.5
0
0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.02
Time (s)
Fig.5.26Gate pulses for the bottom H-bridge cell in phase B: a left top, b left bottom, c right
top and d right bottom
(a) 1
0.5
0
0.03 0.031 0.032 0.033 0.034 0.035 0.036 0.037
(b) 1
0.5
0
0.03 0.031 0.032 0.033 0.034 0.035 0.036 0.037
(c) 1
0.5
0
0.03 0.031 0.032 0.033 0.034 0.035 0.036 0.037
(d) 1
0.5
0
0.03 0.031 0.032 0.033 0.034 0.035 0.036 0.037
Time (s)
Fig.5.27Gate pulses for the top H-bridge cell in phase C: a left top, b left bottom, c right top
and d right bottom
(a) 1
0.5
0
0.03 0.031 0.032 0.033 0.034 0.035 0.036 0.037
(b) 1
0.5
0
0.03 0.031 0.032 0.033 0.034 0.035 0.036 0.037
(c) 1
0.5
0
0.03 0.031 0.032 0.033 0.034 0.035 0.036 0.037
(d) 1
0.5
0
0.03 0.031 0.032 0.033 0.034 0.035 0.036 0.037
Time (s)
Fig.5.28Gate pulses for the bottom H-bridge cell in phase C: a left top, b left bottom, c right
top and d right bottom
5.3 Modeling and Schematic Symbol Creation Using VHDL 171
Carrier Reference
Time
Time
Fig.5.31Schematic symbol
of the comparator and PWM
pulse generator unit, which
also has an output terminal
called DBA_L to access the
deadband wave against PWM
waves at pwm_L_T and
pwm_L_B
172 5 FPGA-Based Digital Switching Controller for Multilevel Converters
to the reference value plus half of the deadband value and the other PWM output
is asserted when the carrier value is less than the reference value minus half of the
deadband value.
The designed comparator as well as the PWM pulse generator is simulated by
the ISim Simulator, and a schematic symbol is created from the VHDL program-
based behavioral model. The schematic symbol for the comparator and PWM
pulse generator unit is depicted in Fig.5.31. The overall algorithm to synthesize
a single fully digital integrated circuit (IC) to control a 5-level converter is illus-
trated in Fig.5.32 [9].
Reference
signals
Crystal clk
Up-down
Clock 900 shifted
divider up-down
counter
counter
Inverter Inverter
NOT
NOT
Deadband
SC7
SC8
SB7
SA7
SB8
SA8
SC1
SC2
SC3
SC4
SC5
SC6
SB1
SA1
SB2
SA2
SB3
SA3
SB4
SA4
SB5
SA5
SB6
SA6
Gate signals
Fig.5.32Basic block diagram of FPGA-based 5-level converter control algorithm
5.4 Model of Complete Switching Controller 173
A test bench program file is created using VHDL code to verify the control cir-
cuit performance. The behavioral model of the complete switching control-
ler is simulated by the ISim Simulator with the created test bench file. The gate
pulse waveforms, deadtime wave forms, and other timing signals such as clock,
load, enabling and reset are displayed on the waveform viewer. The gate pulses
as well as deadtime waveforms are illustrated in Figs.5.34, 5.35, and 5.36, each
Fig.5.34Gate pulses and deadband signals for switches in phase A, where the narrow pulses
represent the deadband (adjustable in software environment)
Fig.5.35Gate pulses and deadband signals for switches in phase B, where the narrow pulses
represent the deadband (adjustable in software environment)
5.5 Behavioral Simulation of Switching Controller 175
Fig.5.36Gate pulses and deadband signals for switches in phase C, where the narrow pulses
represent the deadband (adjustable in software environment)
corresponding to one phase of the converter circuit. Through the waveform viewer,
it is possible to analyze (by comparing with the MATLAB/Simulink results) the
generated gate pulses. The deadtime is not considered in the MATLAB/Simulink
system, but the pulse pattern verification can be done with this comparison.
5.6Model Implementation
After analyzing the performance of the behavioral model of the complete switching
controller with behavioral simulation, the model is ready for implementation. The
schematic model is first synthesized using the Synthesized-XST tool. All input and
output ports are assigned according to the available pin configuration of the Xilinx
FPGA chip using the User Constraints-Floorplan Area/IO/Logic (PlanAhead) tool.
All output signals (24 gate signals and twelve deadband signals) are assigned
to the first row connectors of the Hirose 100-pin FX2 connector on the Xilinx
Spartan-3E development board used for testing. Most of all the connectors in the
second row are connected to the ground. There are eight small LEDs (LD0LD7)
parallel connected with eight pins of the top row. Therefore, these signals should
be assigned to the pins whose output requires monitoring. The board has four slide
switches labeled as SW0SW3. When a switch is in the UP or ON position, it con-
nects the respective FPGA pin to 3.3V (i.e., a logic high) and when in the DOWN
or OFF position, it connects the FPGA pin to the ground (i.e., a logic low). The
input control signals, such as the load, enabling, and reference type, are assigned
to these switches. The board also has four momentary push button switches.
Pressing a push button connects the associated FPGA pin to 3.3V (i.e., a logic
high). The I/O pin assignment pattern is summarized in Table5.3.
176 5 FPGA-Based Digital Switching Controller for Multilevel Converters
There are two ways to configure the FPGA pins in the Xilinx ISE Design Suite
13.2 software environment. The first method is to enter the pin number in the site
field in the I/O Port Properties tab when the I/O signal is selected. The I/O Port
Properties-based I/O pins assignment is illustrated in Fig.5.37.
Dragging into the Package view is an alternative way for the I/O pins assign-
ment. In this method, a signal needs to be selected, dragged into the Package
view and then dropped on the desired pin location. The Package view is shown
in Fig.5.38. The I/O port viewer displays the ports with their configuration such
as input/output and pin number as depicted in Fig.5.39. Once the PlanAhead is
closed by selecting the Exit tab, a ucf file is added to the project, which contains
the constraints. In order to translate the model to something that can physically
be mapped into the FPGA, i.e., xc3s500e-4fg320, the Implement Design tab is
used.
Actually under the Implement Design tab, there are three main functions such
as Translate, Map, and Place and Route. The Translate process merges all of the
input netlists and design constraint information and creates a Xilinx native generic
database (NGD) file. The Map process creates a native circuit description (NCD)
file, which actually implements the logic functions in a device. The Place and
Route process creates another NCD file to place and route the design by using the
NCD file created during the Map process.
5.7Design Verification
The design Summary viewer reports all the design issues such as overall summary
(as shown in Fig.5.40), timing constraints, pinout report (as shown in Fig.5.41),
errors and warnings and other information.
5.7 Design Verification 179
It is essential to check the pinout report carefully (e.g., whether or not all sig-
nals have been assigned to the correct FPGA pins). The View RTL Schematic
process views the schematic of the behavioral model as depicted in Fig.5.42.
Moreover, the View Technology Schematic process is used to view the physical
architecture of the I/O configuration as illustrated in Fig.5.43.
The timing (post-place and route) simulation uses the block and routing delay
information to give a more accurate assessment of the behavior of the circuit. The
timing simulation is carried out to ensure the actual device operation in the simula-
tion environment.
5.8 FPGA Programming 181
Fig.5.43View technology
schematic
5.8FPGA Programming
After analyzing the design, a configuration bitstream is created. The process tab
Generate Programming File generates a bit file that can be used to program the
FPGA. Before programming the FPGA, the configuration mode jumper settings
must be set for JTAG programming. After connecting the FPGA board with the
PC through a standard USB cable on the USB-based download/debug port of
the test board, the power switch is turned on. Figure5.44 shows a photograph of
FPGA board with PC connection through USB cable. A green light-emitting diode
(LED) lights up after a successful connection. The FPGA is programmed using
the iMPACT tool under the Configure Target Device process. There is no need to
include some configuration files for SPI ports or BPI PROM to this device. The
configuration files assignment options for other ports of xcf04s and xc2c64 should
be bypassed. During this process, the device xc3s500e is selected to program the
FPGA. The iMPACT process viewer is shown in Fig.5.45. There are two indi-
cations of successful programming: a message Program Succeeded shows up in
iMPACT process view and at the same time a yellow LED (underneath the J30
jumper) on the board lights up.
182 5 FPGA-Based Digital Switching Controller for Multilevel Converters
All FPGA I/Os that interface to the Hirose connector on the test board are in Bank
0 of the FPGA. The I/O Bank 0 supply is 3.3V by default. Therefore, the PWM
gate pulses from the FPGA are also 3.3V, which is insufficient for the IGBT drivers
used. Driver ICs TC4427A are used to increase the voltage level to the desired value
5.9 Experimental Testing and Verifications 183
(TC4427A can support up to 18V). Through Hirose 100-pin FX2 connector and rib-
bon cables, the generated 3.3-V gate pulses are applied to the interface circuit. The
experimental setup of the switching controller for the 5-level 3-phase multilevel con-
verter system is illustrated in Fig.5.46. The gate pulses from the driver circuit can be
used to switch the switching devices. The gate pulses for a 3-phase 5-level converter
are illustrated in Figs.5.47, 5.48, 5.49, 5.50, 5.51, and 5.52.
An Agilent Technologies DS06034A oscilloscope was used to observe the
signal waveforms. This oscilloscope has four input channels, and the gate pulses
for each H-bridge cell (i.e., four) are shown in a figure. The measured switching
Left top
Left bottom
Deadband
Right top
1.525 kHz
Right bottom
Fig.5.47Measured gate pulses for the top H-bridge cell in phase A: 1 left top, 2 left bottom, 3
right top, and 4 right bottom
184 5 FPGA-Based Digital Switching Controller for Multilevel Converters
Left top
Left bottom
Deadband
1.525 kHz
Right top
Right bottom
Fig.5.48Measured gate pulses for the bottom H-bridge cell in phase A: 1 left top, 2 left bottom,
3 right top, and 4 right bottom
Left
top
Fig.5.49Measured gate pulses for the top H-bridge cell in phase B: 1 left top, 2 left bottom, 3
right top, and 4 right bottom
frequency of the switching signals is 1.525kHz, which precisely matches the the-
oretical result. Pulse patterns are also verified with theoretical results as well as
MATLAB/Simulink and Xilinx ISE simulation results, and they are found highly
consistent. Gate pulses are applied to the switching devices of the converter, and
5.9 Experimental Testing and Verifications 185
Left
top
Left bottom
Deadband
1.525 kHz Right top
Right bottom
Fig.5.50Measured gate pulses for the bottom H-bridge cell in phase B: 1 left top, 2 left bot-
tom, 3 right top, and 4 right bottom
Left top
Left bottom
Deadband
Right top
Fig.5.51Measured gate pulses for the top H-bridge cell in phase C: 1 left top, 2 left bottom, 3
right top, and 4 right bottom
the output phase voltage is measured using oscilloscope as shown in Fig.5.53, and
it is found satisfactory. The phase voltage waveforms were also found highly con-
sistent with MATLAB simulation results. Figure5.54 shows simulated phase volt-
age waveform of a 5-level converter.
186 5 FPGA-Based Digital Switching Controller for Multilevel Converters
Left top
Left bottom
Deadband
1.525 kHz
Right top
Right bottom
Fig.5.52Measured gate pulses for the bottom H-bridge cell in phase C: 1 left top, 2 left bottom,
3 right top, and 4 right bottom
1000
Phase voltage
500
Voltage (V)
-500 50 Hz
-1000
0 5 10 15 20 25 30 35 40
Time (ms)
5.10Summary
In order to develop switching circuits for multilevel converters, the FPGA may
be the natural choice because of its high-speed operation and capacity to han-
dle multiple PWM signals. An integrated fully digital switching controller has
been developed for a 3-phase 5-level converter system using an FPGA devel-
opment board, which has some user-friendly onboard switches and buttons for
I/O. Through these switches and buttons, it is possible to control the operation
of the switching controllers such as reset, enabling, load, type of reference sig-
nal, and many more. During the behavioral modeling of the switching control-
ler, the MATLAB/Simulink model and its responses have been considered as the
reference. Finally, the switching circuit has been implemented for experimental
verification. The experimental results are found highly consistent with theoreti-
cal and MATLAB/Simulink results. This switching scheme and design technique
can be used for any other converter with minor modification to the software
environment.
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Chapter 6
Experimental Validation of 1-kV
Modular Multilevel Cascaded Converter
with High-Frequency Magnetic Link
6.1Introduction
1 1 1
2 2 2
MV grid
k k k
G G G
MV converter
C1 C2
Converter module
for the MMC converter. All the generators are driven by the same wind turbine,
and each stator winding generates an isolated source for all the H-bridge inverter
cells of the MMC converter. The MMC converter generates medium-voltage AC
output, which can be connected to the medium-voltage network directly. A multi-
ple generator-based wind turbine system is shown in Fig.6.2.
6.1Introduction 191
380690/380690 V
380690 V
Module Module Module
Inverter
G Rectifier (HF) 2 2 2
Fig.6.3Wind turbine generator system for direct medium-voltage grid integration [1]
Phase-A
H-bridge
Cd
A
_
Phase-B
B
Rectifier Inverter (high C
frequency)
High-frequency link
balance due to the common magnetic link, (iv) direct gird connection without
using the step-up transformer, (v) an overall compact and lightweight system, and
(vi) an inherent minimization of the grid isolation problem through the high-fre-
quency magnetic link.
A scaled down 1-kV 3-phase 5-level MMC is developed, where each phase leg
consists of two H-bridge inverter cells. Table6.1 summarizes the converter
specifications. The DC-link voltage of each H-bridge inverter cell is calcu-
lated at 367.70V. Considering the market availability, cost and suitability for
High-frequency
magnetic-link
Module A-1
Vdc
A
+
Cdc
Generator
B
Cd C
Phase-C
Phase-B
_
AC grid
frequency)
Module A-2
Phase-A
Fig.6.6A Photograph of
Semikron IGBT modules
SK30GH123
r
r te
ve
er
ert
n
co
z inv
l
ve
kH
e
10
til
ul
M
Distr
ibuti
tive boar on
r o tec es d
P evic
d
FPG
A bo
ard
Drive
r circ
uit
The Semikron driver SKHI 20op requires 15-V gate pulses. The generated gate
pulses by Xilinx FPGA XC3S500E are 3.3V, and these require stepping-up
before feeding to the driver SKHI 20op. Figure6.8 shows a photograph of Xilinx
Spartan-3E starter kit. An extra driver circuit is required to interface the FPGA
and driver SKHI 20op. The microchip dual high-speed power metal oxide field
effect transistor (MOSFET) driver TC4427A is used to design the extra driver cir-
cuit. The IC has some special features: high output current (e.g., 1.5A), gener-
ated gate pulse voltage of up to 18V, short delay time (e.g., 40ns), low output
impedance (e.g., about 7), and low supply current (e.g., about 4mA for logic 1
input and 400A for logic 0 input). Xilinx Spartan-3E board has 100-pin header
6.2 Development of High-Frequency Magnetic-Link MMC Converter 197
Fig.6.8A photograph of
Spartan-3E starter kit
Fig.6.9A photograph of
ribbon cable and header
socket
to interface with peripherals. Therefore, 100-pin socket with proper ribbon cable
is required for the connection of FPGA board with driver circuit. Figure6.9 shows
the ribbon cable connection with 100-pin socket. Figure6.10 shows the detailed
circuit diagram of the extra driver circuit. A photograph of the extra driver circuit
is shown in Fig.6.11. The 3-phase 5-level MMC converter consists of 24 IGBTs,
and the switching controller evolves 24 gate signals. Each microchip dual high-
speed power MOSFET driver TC4427A can drive two gate signals. Therefore, in
total, 12 drivers are used. Each driver SKHI 20op handles two gate signals: one
for the top IGBT of a half-bridge leg and the other for the bottom IGBT. The
driver also requires DC supply with proper ground connection. A separate header
198 6 Experimental Validation of 1-kV Modular Multilevel
NC NC NC NC
24 30
TC4427A
TC4427A
A1RT A1LT
10 k 10 k
23 29 A1LT
A1RB A1LB
10 k 10 k A1LB
0.047 F 0.047 F A1RT
NC NC NC NC
22 28 A1RB
TC4427A
TC4427A
A2RT A2LT A2LT
10 k 10 k
21 27 A2LB
A2RB A2LB A2RT
10 k 10 k
TC4427A
B1RT B1LT B1LB
10 k 10 k
B1RT
19 25
B1RB B1LB B1RB
10 k 10 k
B2LT
0.047 F 0.047 F
NC NC NC NC B2LB
7 18 12
TC4427A
TC4427A
B2RT
7 6 B2RT B2LT
10 k 10 k
2 B2RB
1 17 11
Header B2RB B2LB
C1LT
10 k 10 k
C1LB
0.047 F 0.047 F
NC NC NC C1RT
NC
16 10
TC4427A
TC4427A
C1RB
C1RT C1LT
10 k 10 k C2LT
15 9
C2LB
C1RB C1LB
10 k 10 k
C2RT
0.047 F 0.047 F
C2RB
NC NC NC NC
14 8
Terminals
TC4427A
TC4427A
C2RT C2LT
10 k 10 k
13 7
C2RB C2LB
10 k 10 k
0.047 F 0.047 F
Ground + 15 V
Fig.6.10Detailed circuit diagram of driver circuit to step-up the gate signal to 15V
and socket set, each set for a half-bridge leg with ribbon cable are used to handle
the gate signals and DC supplies of the driver circuits. A special switching control
signal distribution board is designed for proper management. The gate signals, DC
supply, and ground connection of the distribution board are depicted in Fig.6.12.
A photograph of the switching and control signal distribution board is shown in
Fig.6.13.
6.2 Development of High-Frequency Magnetic-Link MMC Converter 199
Fig.6.11A photograph of extra driver circuit to step-up the gate signal to 15V
and
Vr(pp) Idc Doff
Vr(rms) = = . (6.2)
2 3 4 3Cfs
Hence, the ripple factor can be deduced as [1]
Vr(rms) Idc Doff
r =
Vdc
= (6.3)
4 3Cfs Vdc
6.2 Development of High-Frequency Magnetic-Link MMC Converter 201
C dc C dc C dc
C dc C dc C dc
Fig.6.16Capacitor voltage V
Rectified voltage (without capacitor)
of the fast recovery rectifier
[1] Vm
Tr t
Trc
Ts
Vo
V dc Vr(p-p)
temperature, TJ, case temperature, TC, and ambient (air) temperature, TA, are
related by the device heat-handling capacity and can be presented in terms of ther-
mal-electric analogy as
JA = (JC + CS + SA ) (6.5)
and
TJ = PD JA + TA , (6.6)
where JA is the total thermal resistance (junction to ambient), JC is the transistor
thermal resistance (junction to case), CS is the insulator thermal resistance (case
to heat sink), SA is the heat-sink thermal resistance (heat sink to ambient), and PD
is the power dissipation. Using (6.5) and (6.6), the heat-sink thermal resistance can
be deduced as [1]
TJ TA
JC + CS + SA =
PD
TJ TA
SA = (JC + CS ). (6.7)
PD
From the data sheet of DSEE15-12CC, we obtain JC =1.60C/W,
CS=0.5C/W, TJ=170C, and PD is about 2W. Therefore, the heat-sink ther-
mal resistance can be calculated as
170 40
SA = (1.6 + 0.5) = 62.9 C/W.
2
Fischer Elektronik FK 245 MI 247 O clip-on heat sinks without soldering lug are
considered for this project. The heat sink is made of copper material with a ther-
mal resistance of 20.2C/W. For proper contact with semiconductor devices, the
Electrolube HTC10S non-silicone heat transfer compound is used on the contact
surface area of the heat sinks.
Filtering
capacitors IGBT driver
circuit
Switching
signals
SK 30 GH 123 IGBT based H-
bridge inverter
(mounted on the top of the
heatsink)
Heatsink
Fig.6.18A photograph of
Texas Instruments high-speed
PWM controller UC3825BN
VCC
200
0.1F
15 13
VC
0.1F 16 V VCC
RF
A 11 Out A
2 NI
UC3825BN
B 14
Out B
1 INV
1nF 9
3 E/A
4.3k
Ramp 7
3.3k
NC 4 Clk CT 6
RT CT
R PGnd 12
5 Gnd
T
SS
10 8
0.1F
Fig.6.19Simplified circuit of the switching signal generator using Texas Instruments high-
speed PWM controller UC3825BN [23]
Fig.6.20A photograph of control circuit using Texas Instruments high-speed PWM controller
UC3825BN
206 6 Experimental Validation of 1-kV Modular Multilevel
Fig.6.21Basic internal
circuit of the Texas
Instruments high-speed
PWM controller UC3825BN
(oscillator section only)
Fig.6.22Alternative two
output topology
with high accuracy. The maximum signal high time is determined by the rising
capacitor voltage, whereas dead time is determined by the timing capacitor dis-
charge. Figure6.21 shows the internal circuit diagram of the Texas Instruments
high-speed PWM controller UC3825BN (oscillator section only).
Based on the desired maximum duty cycle, Dmax the timing resistor can be cal-
culated as
3V
RT =
10 mA (1 Dmax )
3V (6.8)
= = 3 103 or 3 k.
10 mA (1 0.90)
6.2 Development of High-Frequency Magnetic-Link MMC Converter 207
A B
Thigh_A
Thigh
Two alternative signals are generated through a T flip-flop, and output signal fre-
quency is half that of oscillator frequency, as shown in Fig.6.22. Therefore, dou-
bled oscillator frequency (compared to the output) is required for designing the
timing capacitor.
Based on the calculated value of the timing resistor and desired maximum duty
cycle, the timing capacitor can be calculated as
1.6 Dmax
CT =
RT f
(6.9)
1.6 0.90
= = 2.4 108 (F)
3 103 20 103
Thigh
D% = 100
Thigh + Tdead
(6.10)
44.8
= 100 = 90.30 %
44.8 + 4.8
The expected time period, T, and frequency, fH, of the medium frequency inverter
can also be calculated as
T = Thigh_A + Tdead_A + Thigh_B + Tdead_B
(6.11)
= 44.8 s + 4.8 s + 44.8 s + 4.8 s = 99.20 s
1 1
fH = = = 10.08 kHz.
T 99.2 106
208 6 Experimental Validation of 1-kV Modular Multilevel
Thigh_B
Tdead
With the advent of new power semiconductor devices, different high magnetic sat-
uration and low power loss soft magnetic materials are conceived to reduce the
weight and volume of conventional power transformers. The grain-oriented silicon
sheet steels, which are commonly used as the core material of power frequency
transformers, are not suitable for high-frequency applications because of the heavy
eddy current loss [24]. The soft ferrites have been widely used in medium- and
high-frequency inductors and transformers due to the low price and general avail-
ability. Because of the low saturation flux density [24] (only 0.30.5T), which
would make the transformer bulky, they are not suitable for large power applica-
tions. On the other hand, the amorphous alloy and nanocrystalline materials have
excellent magnetic characteristics for high-frequency applications, such as high
permeability, high saturation flux density, and relatively low core losses. Two
commercially available amorphous and nanocrystalline materials are Metglas
and Finemet, respectively, both manufactured by Hitachi Metals, Japan. Although
Finemet has lower specific core loss than Metglas, its saturation flux density
(about 1T) is much lower than that of Metglas, which is 1.56T. Until now, many
kinds of soft magnetic alloys with high magnetic flux density combined with low
core loss have been developed [25, 26]. Taking into account the flux density, spe-
cific core loss, cost, and availability, we chose Metglas 2605SA1 stripe of 30m
thickness and 25mm width as the core material. The other parameters of 2605SA1
include mass density of 7.18g/cm3, saturation flux density of 1.56T, and spe-
cific core loss of 180W/kg, at 10kHz sinusoidal excitation of 1T. Figure6.25
shows a photograph of the Metglas alloy 2605SA1 sheet-based multi-output high-
frequency magnetic link. For small skin depth and proximity effect, the number
of layers as well as the conductor diameter should be kept as small as possible.
Moreover, the insulated strands should be twisted or braided together to equalize
the flux linkages throughout the conductors. To achieve this so as to reduce the
winding loss, a Litz wire with small number of layers should be always used in a
high-frequency magnetic link. Figure6.26 shows a photograph of Litz wire.
6.3 Experimental Testing and Performance Analysis 209
of the experimental test platform. The gate pulses for the high-frequency inverter
were measured, as shown in Fig.6.28, and compared with the simulation results.
The measured pulses were found to be highly consistent with the simula-
tion results. The primary and secondary voltages of the high-frequency mag-
netic link were measured and the voltage transformation ratio was calculated, as
listed in Table6.3, and found to be highly consistent with the theoretical values.
Figure 6.29 shows the voltage waveforms of the primary and secondary sides of
the high-frequency magnetic link. Tektronix DPO 2024 digital phosphor oscillo-
scope with the P5200 high-voltage differential probe and Tektronix TCPA300 cur-
rent probe were used to observe the voltage and current waveforms.
6.3 Experimental Testing and Performance Analysis 211
Table6.3Voltage Windings A B C D E F
transformation ratios against
Ratios 1.781 1.780 1.779 1.780 1.780 1.781
primary winding [27]
Variation 0.00 0.05 0.11 0.05 0.05 0.00
(%)
loss. In March 2013, Voltech transferred all its power analyzer technology to Tektronix.
Recently, Tektronix developed power analyzer PA4000, which delivers consistently
accurate measurements, even with challenging power waveforms. Figure6.33 shows a
photograph of Tektronic power analyzer PA4000. The PA4000 supports input voltage
and current up to 1,000V rms and 30 A rms, respectively, with a measurement band-
width up to 1MHz. From the oscilloscope data, the copper loss of each winding at a
different frequency ranging from 6 to 12kHz was calculated by using the DC resist-
ances (0.024 for the primary and 0.16 for the secondary), since the AC/DC resist-
ance ratios, Kr, in this design is almost unity due to the use of Litz wires.
214 6 Experimental Validation of 1-kV Modular Multilevel
Left top
Left bottom
Right bottom
15 V, 1.525 kHz
Fig.6.37Measured phase voltage of the prototype system (phase voltage before LC filter
circuit)
Fig.6.38Zoomed phase voltage of the prototype system (phase voltage before LC filter circuit;
with 1.525-kHz PWM frequency
converter and the output phase voltage and line current are measured, and they are
found to be satisfactory. Figure6.37 depicts the output phase voltage of the proto-
type converter. Each level of the output voltage contains a number of PWM pulses.
Figure6.38 plots the zoomed (zoom factor=8) output phase voltage of the pro-
totype system. The line voltages of the prototype converter were measured; they
were found to be highly consistent with the simulation results.
The SPWM and THPWM schemes were implemented practically and perfor-
mances were verified by observing the line voltage waveforms, and they were
found to be highly consistent with the theoretical and simulation results. The LC
filter circuit is designed with the 3-mH MTE RL 00401 reactor and 6-F RS
6.3 Experimental Testing and Performance Analysis 217
Fig.6.42Measured line voltage with SPWM of the prototype system before filter
Fig.6.43Measured line voltage with SPWM of the prototype system after the filter when the
filter capacitors are connected in Y
Fig.6.44Measured line voltage with SPWM of the prototype system after the filter when the
filter capacitors are connected in
as the THD was reduced from 4.5% to about 3.2%. After filter circuit, the line
voltages are depicted in Fig.6.44, when the filter capacitors are connected in .
The THPWM scheme provides much better results than the SPWM, which was
found to be highly consistent with the simulation results. The line voltage wave-
form before the filter circuit with THPWM is illustrated in Fig.6.45. Figure6.46
plots the zoomed (zoom factor=6) output line voltage with THPWM. The fre-
quency spectrum of the measured line voltage (before the filter circuit) is shown
in Fig.6.47, which contains about 19% THD. The line voltages were also meas-
ured after the filter circuit, and they were found to be consistent with the simulation
220 6 Experimental Validation of 1-kV Modular Multilevel
Fig.6.45Measured line voltage (before filter circuit) of the prototype 1-kV modular multilevel
cascaded converter with THPWM
Fig.6.46Zoomed measured line voltage (before filter circuit) of the prototype 1-kV modular
multilevel cascaded converter with THPWM
results. The measured line voltages after the filter circuit are shown in Fig.6.48.
Figure6.49 plots zoomed 3-phase line voltage after the filter circuit with THPWM.
As measured, after the filter circuit, the output voltage waveform contains about
2.75% THD. The frequency spectrum of the line voltage after the filter circuit is
shown in Fig.6.50. The line currents were measured and compared with theoretical
as well as simulation results, and they were found to be almost the same.
If Pc_inv is the conduction loss and Psw_inv is the switching loss, the losses in the
inverter section of the proposed converter can be described as
Ploss_inv = Pc_inv + Psw_inv (6.12)
6.3 Experimental Testing and Performance Analysis 221
0.06
0.02
0
0 10 20 30 40 50
Frequency (kHz)
Fig.6.48Measured line voltage (after filter circuit) of the prototype 1-kV modular multilevel
cascaded converter with THPWM
Fig.6.49Zoomed measured line voltage (after filter circuit) of the prototype 1-kV modular
multilevel cascaded converter with THPWM
0.015
Normalized amplitude
0.005
0
0 10 20 30 40 50
Frequency (kHz)
and
1 1 ma 3 ma
Pc_D = Ir Vf pf + Ir2 RAK pf . (6.16)
2 4 8 3
where ma is the amplitude modulation index, pf the power factor of the current, Ir
the device current, and Vt and Vf are the voltage drops at zero current condition,
6.3 Experimental Testing and Performance Analysis 223
and RCE and RAK the forward resistances of IGBT and diode, respectively, which
can be collected from the manufacturers data sheets. The total conduction loss in
a 3-phase 2-level inverter can be approximated as
Pc_inv_2 = 6(Pc_sw + Pc_D ). (6.17)
The inverter section of the medium/high-frequency-link MMC converter consists
of a series of H-bridge inverter cells in a cascaded connection. Therefore, the total
conduction losses of an m-level inverter can be approximated as
Pc_inv_M = 6(m 1)(Pc_sw + Pc_D ). (6.18)
The device commutation voltage of m-level inverter is (m1) times lower than
that of a device in the 2-level inverter. The on-state saturation voltage of an IGBT
and forward voltage of a diode are highly dependent on device voltage ratings. For
these reasons, although the multilevel inverter uses a large number of devices, the
total conduction loss is similar to that of a 2-level inverter with the same power
conditions. Due to lower switching losses, the total loss of a multilevel inverter is
much lower than that of a 2-level inverter with the same power conditions.
The efficiency of each section and for the whole system of the high-frequency
magnetic-link MMC converter can be calculated from
Pout
= . (6.19)
Pin
and percentage of efficiency can be calculated from
Pout
% = 100. (6.20)
Pin
As calculated, the multilevel inverter section of the high-frequency magnetic-link
MMC converter gives about 80% efficiency at 20% rated load. The efficiency
reaches 90% at about 50% rated load. Almost 95% efficiency was measured with
the fully rated power condition. The overall efficiency of the whole system was
also calculated. The overall efficiency of the whole system was much lower than
that of the multilevel inverter section due to the significant power losses in the
10-kHz inverter, high-frequency magnetic link, and fast recovery rectifiers. About
58% efficiency was evaluated with the 20% rated power. The overall efficiency
increases to 70% at about 50% rated power. The full load overall efficiency of
the proposed system was measured at 76%. Compared with the traditional 2-level
converter (inverter section only), about 15% lower efficiency was evaluated.
Although the high-frequency magnetic-link MMC system gives 15% lower effi-
ciency than that of a 2-level converter, it is still similar to a 2-level converter-based
traditional system, because the traditional system uses two main additional com-
ponents, i.e., line filter, and the power frequency step-up transformer. The step-
up transformers and harmonic neutralizing filters produce about 50% of the total
losses and occupy up to 40% of the system volume [29]. With the high-frequency
magnetic-link MMC converter, the elimination of the heavy and large step-up
transformer and line filter will enable large cost savings in terms of the installation,
224 6 Experimental Validation of 1-kV Modular Multilevel
6.4Summary
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Chapter 7
Design and Analysis of 11- and 33-kV
Modular Multilevel Cascaded Converters
Abstract The high number of levels of modular multilevel cascaded (MMC) con-
verters enables the direct connection of the renewable generation units to the
medium-voltage grid and improvement of the output power quality. The component
number and control complexity increase linearly with the increase in the number of
levels. On the other hand, the distortion in generated output voltage and semicon-
ductor cost of the converter decrease dramatically with the increase in the converter
number of levels. As the number of levels increase, it is possible to use lower switch-
ing frequencies, even the fundamental switching frequency, which can significantly
reduce the switching losses. Therefore, the optimal selection of the number of con-
verter levels is important for the best performance/cost ratio of the medium-voltage
converter systems and this is the central content of this chapter. In this chapter, an
11-kV system and a 33-kV system are designed and analyzed taking into account the
specified system performance, control complexity, and cost and market availability
of the power semiconductors. It is found that the 19-level and 43-level converters are
the optimal choice for the 11- and 33-kV systems, respectively. Besides the design
and analysis of medium-voltage converters, the traditional low-voltage converters
with power frequency step-up transformers are also discussed.
7.1Introduction
Different power electronic converters have been developed using the conventional
topologies to fulfill the requirements of renewable generation systems. However, it
is hard to connect the traditional converters to the grids directly, as the distortion
in generated output voltages is high and a single switch cannot stand the grid volt-
age level [1, 2]. Therefore, the traditional low-voltage converters/inverters have
typically used step-up transformer to step up the voltage to the grid voltage level.
Many power semiconductor vendors such as Semikron, ASEA brown boveri (ABB),
IXYS, and Mitsubishi Electric produce devices specially designed for the diode rec-
tifier-based converter and back-to-back converter (modular form) for wind turbine
generator systems. All of the devices are in a single pack, which reduces the cost and
complexity of the power conditioning system. Semikron developed modules IGDD6-
4-426-D3816-E1F12-BL-FA and SKS 660F B6U+E1C+B6CI 250 V06 for the
diode rectifier-based power conditioning systems [3, 4]. This type of power converter
is normally used in a wound rotor synchronous generator (WRSG) or a permanent
magnet synchronous generator (PMSG)-based wind power generation system instead
of an induction generator. According to the internal circuit configuration, module
IGDD6-4-426-D3816-E1F12-BL-FA is suitable for WRSG-based wind turbine gen-
erator systems and module SKS 660F B6U+E1C+B6CI 250 V06 is suitable for
PMSG-based wind turbine generator systems. In a WRSG-based system, to achieve
variable-speed operation, the system uses an extra excitation circuit, which feeds the
excitation winding of WRSG. Figure7.1 shows the Semikrons SEMIKUBE con-
verter module IGDD6-4-426-D3816-E1F12-BL-FA. The internal electrical circuit of
the Semikrons SEMIKUBE converter module IGDD6-4-426-D3816-E1F12-BL-FA
is shown in Fig.7.2. The PMSG-based wind turbine generator systems are equipped
with a step-up chopper circuit. The step-up chopper adapts the rectifier voltage to
the DC-link voltage of the inverter. Controlling the inductor current in the step-up
chopper can control the generator torque and speed. The diode rectifier with step-up
chopper-based power conditioning system is illustrated in Fig.7.3. In this converter
system, the grid-side inverter controls the active and reactive power delivered to the
grid. Mitsubishi Electric developed the IGBT module CM100MXA-24S with this
converter topology which can be used for wind turbine generator systems [5]. The
module is recommended for the collector current of100A and the collectoremitter
Fig.7.1A photograph of
Semikrons SEMIKUBE
converter module IGDD6-4-
426-D3816-E1F12-BL-FA
7.1Introduction 229
Rectifier Inverter
Rectifier Inverter
L
Q C
power flows to the grid and keeps the DC-link voltage constant, improving the
output power quality by reducing the total harmonic distortion (THD). The gen-
erator-side converter works as a driver, controlling the magnetization demand and
the desired rotor speed of the generator. The decoupling capacitor between grid-
side converter and generator-side converter provides independent control capabil-
ity of the two converters. Due to some special features, this converter topology
has received great attention recently. Many power semiconductor manufacturers,
such as Semikron, ABB, Hitachi, Siemens, IXYS, and Mitsubishi Electric, pro-
duce components in module forms, suitable for this converter, which makes the
converter compact and lightweight. The back-to-back converter can be used for
PMSG and squirrel cage induction generator (SCIG)-based wind power genera-
tion systems. Siemens employs back-to-back converter for power conditioning of
SCIG-based wind turbine generator systems. Semikrons SEMISTACK RE mod-
ule SKS B2 140 GDD 69/12 U-A11 MA PB is a back-to-back converter typically
used for power conditioning of synchronous and doubly fed generator-based wind
power systems, as well as in central solar PV inverters [6]. Figure7.5 shows a
photograph of SEMISTACK RE. The modules maximum ratings are the input/
Fig.7.5A photograph of
Semikron SEMISTAK RE
converter module SKS B2
140 GDD 69/12 U-A11 MA
PB
7.1Introduction 231
Inverter Inverter
Fig.7.7A photograph of Semikrons SEMIKUBE converter modules designed for 110-, 220-,
400-, and 900-kW (from the left) solar PV power converters
Inverter
Fig.7.11Siemens PV inverter SINVERT PVS; the left two cabinets are the DC cabinets and the
other two the AC cabinets
234 7 Design and Analysis of 11- and 33-kV Modular
of Siemens central PV inverter SINVERT PVS. The cabinet holds touch panel
which consists of indicators and key-operated switch. Figure7.12 shows the func-
tion units of Siemens PV inverter SINVERT PVS, where the markings of 112
indicates the modules for 1,000V option, modules for PV array grounding option,
modules for options, DC connectors, DC terminal compartment of the PV array
and LV HRC fuses, inverter module (power unit), connection to AC cabinet, com-
munication area, AC filter, cooling ventilators, AC contactor, and circuit breaker
for isolating the AC system and overvoltage protection, respectively.
Fig.7.14Housing of ABB
cast coil dry-type transformer
wind farms and solar PV power plants are intermittent power sources, it is of great
importance to minimize transformer no-load losses. A liquid-filled 2-MVA trans-
former is about 5.7m3 in volume and 4,530kg in weight with 870kg of liquid as
the coolant and insulator [1, 13]. The no-load and full-load losses are approximately
3.2 and 21kW, respectively. Figure7.15 shows a photograph of an ABB liquid-filled
transformer. In offshore wind farms, this transformer is usually installed inside the
nacelle of the wind turbine. Ground-mounted liquid-filled transformers are typically
used for solar PV plants and onshore wind farm applications. Figure7.16 shows a
photograph of a ground-mounted liquid-filled transformer for onshore wind farm.
The SLIM transformer developed by Pauwels is compact in size and has low
no-load losses, typically half of those of the dry-type transformers. For example, a
33/0.69-kV, 2.6-MVA SLIM transformer has a no-load loss of 2.6kW and a full-
load loss of 22.5kW [1, 14, 15]. Figure7.17 shows a photograph of a Pauwels
SLIM transformer. This transformer is typically lifted through the tower door.
7.1Introduction 237
Figure 7.18 shows the transformer lifting technique. The conventional liquid-
immersed transformer uses cellulose and mineral oil, whereas SLIM uses a high-
temperature aramid insulation material called NOMEX and a silicone liquid. The
use of about 900kg or more silicone fluid as the coolant and insulator in these
transformers ensures a high degree of fire safety (the flash points of mineral oil
dielectric and silicone fluid are about 150 and 360C, respectively). These insu-
lation materials are usually chosen on the basis of reliability, performance,
safety, and environment concerns. Especially, the liquid degradation has received
a lot of attention. For example, according to European requirements, more than
65% of the liquids must be degraded in 28days. This concern can be overcome
by using fully biodegradable liquids. M&I Materials Ltd. developed the syn-
thetic ester MIDEL 7131, which is the preferred dielectric fluid for transformers
in environmentally sensitive locations and already recognized as readily biode-
gradable. Pauwels developed a new transformer by optimally using the synthetic
ester MIDEL 7131 in combination with the high-temperature NOMEX insulation
system to obtain the compactness and reliability of the SLIM transformer. This
resulted biodegradable liquid-based SLIM transformer is called Bio-SLIM. The
volume and weight of a 20/0.69-kV, 2.3-MVA Bio-SLIM transformer are about
238 7 Design and Analysis of 11- and 33-kV Modular
Fig.7.17Pauwels SLIM
transformer
7.1Introduction 239
Fig.7.18A Pauwels transformer being lifted through the door of a wind turbine tower during
installation
Fig.7.19Pauwels Bio-
SLIM transformer for
offshore applications
4m3 and 5,040kg, respectively [1, 14, 15]. The Bio-SLIM transformer is physi-
cally similar to SLIM, but painted blue to distinguish it from SLIM and to link to
marine and water applications. Figure7.19 shows a photograph of the Bio-SLIM
transformer. Table7.1 summarizes the data of various transformers.
240 7 Design and Analysis of 11- and 33-kV Modular
Table7.1Transformer data
Transformer Rating Size Weight No-load loss Full-load Liquid
type (MVA) (m3) (kg) (kW) loss (kW) (kg)
Cast coil 2.50 8.50 6,200 5.80 25.00
Liquid filled 2.00 5.70 4,530 3.20 21.00 870
SLIM 2.30 4.00 5,040 2.60 22.50 900
Fig.7.20Number of IGBTs/
Number of IGBTs/Complexity
120
control complexity versus Number of IGBTs
converter level numbers 100 Control complexity
80
60
40
20
5 10 15 20
Number of levels
Semiconductor cost
converter level numbers 10 (AUD)
THD (%)
8
8 10 12 14 16 18 20
Number of levels
242 7 Design and Analysis of 11- and 33-kV Modular
The total nominal DC-link voltage for an 11-kV 2-level converter is 16,176V.
Each H-bridge inverter cell commutation voltage of a 5-level converter is about
4,044V. The highest voltage rating of a commercially available IGBT is 6.5kV,
which is recommended for a maximum voltage of 3,600V. Therefore, the 5-level
or lower-level converter cannot be used to design the 11-kV converter. Each
H-bridge inverter cell commutation voltage of a 7-level topology-based 11-kV
converter is 2,696V which may be supported by the 6.5-kV IGBT. Accordingly,
at least 7-level topology is required to design an 11-kV converter. The output
power quality of a 21-level converter is good enough to feed into the 11-kV AC
grid directly. The cheap 1.7-kV IGBT can be used to design the 21-level converter.
Therefore, 7-level to 21-level MMC topologies are considered for an 11-kV con-
verter system. If Vcom is the commutation voltage of respective commutation cells,
the device voltage utilization factor (DVUF) can be calculated from
Vcom
DVUF = . (7.1)
Vcom@100FIT
Table7.2 summarizes the commutation voltage and DVUF of different level MMC
converters. A higher DVUF is essential for cost-effective design, since the semicon-
ductor cost is a significant figure in medium-voltage converter applications. From
Table7.2, it can be seen that only a few converters have high DVUFs. Considering
the availability of the power semiconductor devices, one can find only a few converter
topologies of 9, 11, 15, 19, and 21 levels may give good DVUFs. Although the 7-level
circuit topology can be used to develop an 11-kV converter, the available commercial
IGBTs are not well suited. Therefore, devices of higher ratings are required, which
would yield a very poor DVUF of about 75%. A low DVUF means the use of unnec-
essarily high-cost semiconductors. In general, to use the active switching devices cost-
effectively, a converter must have a DVUF of 90% or above. As listed in the table,
only two converter systems give more than 90% DVUF. In order to ensure a cost-
effective design, the converters of 9, 11, 15, 19, and 21 levels for 11-kV systems were
considered for further analysis. The lowest number of levels of an MMC converter is
3, and such a converter consists of only one H-bridge inverter cell on each phase leg.
Each additional cascaded H-bridge inverter cell contributes two voltage levels to the
output voltage waveform. Therefore, the numbers of levels are only of odd values.
The circuit diagram of a 9-level MMC converter is shown in Fig.7.22. There are
48 active switching devices in the three-phase circuit, and each phase contains
16 devices. Each phase leg consists of 4 H-bridge inverter cells in cascaded con-
nection. The line voltage of a 9-level MMC converter is illustrated in Fig.7.23.
The line voltage THDs of an 11-kV 9-level converter are calculated and found as
a
b
c
SA5 SA7 SB5 SB7 SC5 SC7
9
8
7
10 Vab 2022 V 6
5
4
Voltage (kV) 3
2
1
0
-10
10 15 20 25 30 35 40
Time (ms)
0.05
Normalized amplitude
0.04
9.60% THDs
0.03
0.02
0.01
0
0 0.05 0.1 0.15 0.2 0.25
Frequency (MHz)
-10
10 15 20 25 30 35 40
Time (ms)
9.60%. The frequency spectrum of line voltage is depicted in Figs.7.24 and 7.25
shows the three line voltages of three-phase converter system.
7.2 Design and Analysis of 11-kV Converter Systems 245
1
0 1 2 3 4 5 6
Rated voltage (kV)
forward voltage, which in turn depend on the voltage rating of switching devices.
Figure 7.27 plots the collectoremitter saturation voltages of different voltage
rated Mitsubishi Electric IGBTs [20].
11
10 Vab 1618 V
Voltage (kV)
1
0
-10
10 15 20 25 30 35 40
Time (ms)
0.05
Normalized amplitude
0.04
8.20% THDs
0.03
0.02
0.01
0
0 0.05 0.1 0.15 0.2 0.25
Frequency (MHz)
-10
10 15 20 25 30 35 40
Time (ms)
11-level MMC converter is depicted in Fig.7.29. Figure7.30 shows the three line
voltages of three-phase converter system.
In total, 60 IGBTs are in the 3-phase 11-level MMC converter circuit. Each
IGBT price is about AUD 1,369.31, such that the cost of 60 IGBTs is about
AUD 82,159.00. A few vendors, such as Mitsubishi Electric, ABB, and Infineon,
commercially developed 3.3-kV IGBT modules. Table7.4 summarizes the pos-
sible 3.3-kV IGBT modules to design the 11-level 11-kV converter. Figure7.31
shows the photograph of Infineon 3.3-kV IGBT module FZ800R33KL2C. Since
the switching control circuits consist of 55 ALOs, at least 30 PWM channels are
required to control the 3-phase 11-level converter. The single DSP cannot handle
the PWM pulses as required by the 3-phase 11-level converter. The parallel oper-
ation of several DSPs makes the control circuit hard to implement. The modern
FPGA may be an appropriate option to design the control circuit for multilevel
converters.
248 7 Design and Analysis of 11- and 33-kV Modular
Fig.7.31Infineon
3.3-kV IGBT module
FZ800R33KL2C
The 15-level converter topology is also well suited with the available commer-
cial semiconductors. Each phase leg consists of seven H-bridge inverter cells,
28 IGBTs in a phase, and 84 in total in the 3-phase circuit. The DC supply volt-
age rating of an 11-kV 15-level converter is 1,155V. The commercially avail-
able 2.5-kV IGBT may be used to design the 11-kV 15-level converter, because
this IGBT is recommended for 1,200V maximum applications. Figure7.32 plots
15
Vab 1155 V
10
Voltage (kV)
1
0
-10
10 15 20 25 30 35 40
Time (ms)
0.05
Normalized amplitude
0.04
6.00% THDs
0.03
0.02
0.01
0
0 0.05 0.1 0.15 0.2 0.25
Frequency (MHz)
-10
10 15 20 25 30 35 40
Time (ms)
the line voltage waveform of a 15-level MMC converter. There are 28 steps in
the peak-to-peak line voltage waveform, and each step contributes 1,155V to
the line voltage. The frequency spectrum of the line voltage of a 15-level MMC
converter is depicted in Fig.7.33. Figure7.34 shows the three line voltages of
three-phase 15-level 11-kV converter. Quite a few vendors, such as ABB and
Mitsubishi Electric, commercially developed 2.5-kV IGBT modules. Table7.5
Fig.7.35ABB 2.5-kV
IGBT module 5SNA
1200E250100
summarizes possible 2.5-kV IGBT modules for designing the 15-level 11-kV con-
verter. Figure7.35 shows the photograph of ABB 2.5-kV IGBT module 5SNA
1200E250100, whose rated current is 1,200 A.
Figure7.36 shows the circuit diagram of a 19-level converter. Each phase leg of a
19-level converter consists of 9 H-bridge inverter cells, i.e., 36 IGBTs in a phase
and 108 in total in the 3-phase circuit. The DC-link voltage rating of an 11-kV
19-level converter is about 899V. Figure7.37 shows voltage waveform across an
IGBT in 19-level 11-kV converter.
The available 1.7-kV IGBT may be used to design the 11-kV 19-level con-
verter. This IGBT is cheap and matured in terms of technology and is recom-
mended for 900V maximum applications. With this converter topology, the
highest achievable DVUF is almost 100%. Although a large number of IGBTs
are required for a 19-level converter, the total semiconductor cost is about AUD
36,670.00, which is only about 42% of a 9-level converter with the same power
rating. Each H-bridge inverter cell in cascaded multilevel converter generates
output voltage as 2-level converter. Figure7.38 shows the voltage waveform
of an H-bridge inverter cell in a 19-level 11-kV converter. There are 18 and 36
steps in the peak-to-peak phase and line voltage waveforms, and each step con-
tributes 899V to the phase or line voltage. Figure7.39 shows the phase volt-
age waveform of a 19-level 11-kV converter. Figure7.40 plots the line voltage
waveform of a 19-level MMC converter. Due to the small step size, the output
power quality is suitable for filter-less grid connection. The frequency spec-
trum of the line voltage of a 19-level MMC converter is depicted in Fig.7.41.
Figure 7.42 shows the three line voltages of the three-phase 19-level 11-kV
7.2 Design and Analysis of 11-kV Converter Systems 251
a
b
c
SA5 SA7 SB5 SB7 SC5 SC7
500
400
300
200
100
0
0 5 10 15 20 25 30 35 40
Time (ms)
800
600
Voltage (V) 400
200
0
-200
-400
-600
-800
15 20 25 30 35 40 45 50
Time (ms)
8
6
4
Voltage (kV)
2
0
-2
-4
-6
-8
10 15 20 25 30 35 40 45 50
Time (ms)
19
Vab 899 V
10
Voltage (kV)
1
0
-10
10 15 20 25 30 35 40
Time (ms)
0.05
Normalized amplitude
0.04
4.30% THDs
0.03
0.02
0.01
0
0 0.05 0.1 0.15 0.2 0.25
Frequency (MHz)
-10
10 15 20 25 30 35 40
Time (ms)
300
200
Current (A)
100
-100
-200
-300
0 10 20 30 40 50 60
Time (ms)
The DC-link voltage rating of an 11-kV 21-level converter is about 809V. The
1.2-kV IGBT or lower-rated devices cannot be used and at least 1.7-kV IGBT
is required to design the 11-kV 21-level converter. With this converter topology,
7.2 Design and Analysis of 11-kV Converter Systems 255
21
Vab 809 V
10
Voltage (kV)
1
0
-10
10 15 20 25 30 35 40
Time (ms)
the highest achievable DVUF is 90%, which is much lower than that of the
19-level converter. In total, 120 IGBTs are used in a 21-level converter, where 10
H-bridge inverter cells are cascaded on each phase leg. The total semiconductor
cost is about AUD 40,744.00, which requires about 11% more cost than that of
the 19-level converter. Figure7.45 shows the line voltage waveform of a 21-level
converter, and its frequency spectrum is illustrated in Fig.7.46. The THDs are cal-
culated and found to be 4.25%, which means only 1.1% improvement compared
with the 19-level converter. The control scheme consists of 110 ALOs to drive 120
active switching devices. The control complexity of an 11-kV 21-level converter is
about 11% more than that of a 19-level converter. Figure7.47 shows the three line
voltages of three-phase 21-level 11-kV converter.
0.05
Normalized amplitude
0.04
4.25% THDs
0.03
0.02
0.01
0
0 0.05 0.1 0.15 0.2 0.25
Frequency (MHz)
10
Vab Vbc Vca
Voltage (kV)
-10
10 15 20 25 30 35 40
Time (ms)
The number of ALOs for the switching section and cost of semiconductors
are calculated as tabulated in Table7.7. The number of ALOs is used to com-
pare the complexity of the converters. The THDs are calculated through the
MATLAB/Simulink environment. The price data quoted for the semiconductor
devices were collected from the Galco Industrial Electronics and Farnell catalogs,
and quotations from different vendors where devices were chosen from the same
family so that it was possible to meet the requirements.
Using (3-29), the normalized index values are calculated to obtain the overall
performance/cost of the converters. Table7.8 tabulates the normalized index val-
ues of Table7.7. Based on Table7.8, the performance indicators are plotted as
shown in Fig.7.48. For the 11-kV converter, the total index value is the lowest
1.5
THD Cost Complexity
1
Index value
0.5
0
10 12 14 16 18 19 20
Number of levels
at level 19, because there is no significant output power quality improvement and
semiconductor cost reduction for inverters with more than 19 levels. Moreover,
the component number and control complexity increase linearly with the increase
in the number of levels. Therefore, the 19-level topology is the optimum for the
11-kV converter systems. The output power quality of a 19-level converter is good
enough to feed the converter output directly into the medium-voltage grid directly
(i.e., without using step-up transformer or line filter circuit). Figure7.49 shows the
total indexes of different 11-kV converters. Lower total index value means lower
converter cost and complexity and better quality of output power.
2.00
1.83
Total index
9-level 11 kV converter
11-level 11 kV converter
19-level 11 kV converter
21-level 11 kV converter
1.09
15-level 11 kV converter
1.04
0.84
The total nominal DC-link voltage for a 33-kV 2-level converter is 48,538V. Each
H-bridge inverter cell communication voltage of a 13-level converter is about
4,044V. The highest voltage rating of a commercially available IGBT is 6.5kV,
which is recommended for a maximum voltage of 3,600V. Therefore, the con-
verter should have 13 or more levels for direct connection to a 33-kV grid. Each
H-bridge inverter cell communication voltage of a 15-level topology-based 33-kV
converter is 3,467V which may be supported by the 6.5-kV IGBT. Accordingly, at
least 15-level topology is required to design a 33-kV converter. While the output
power quality of 55-level converter is good enough to feed into the 33-kV AC grid
directly, the cheap 1.7-kV IGBT can be used to construct the 55-level converter.
Therefore, MMC topologies 15 level to 55 level are considered for a 33-kV con-
verter system. The DVUFs are tabulated for converters of different level numbers
in Table7.9.
A high DVUF is essential for a cost-effective design, since the semiconductor
cost is the significant figure in MV inverter applications. From Table7.9, it can
be seen that only some converters have high DVUFs. In order to ensure a cost-
effective design, the converters with level numbers of 15, 23, 29, 43, and 55 for a
33-kV system were considered for further analysis in the following sections. The
converters with DVUFs of more than 95% are assumed to satisfactorily utilize the
active switching devices.
The 15-level converter topology may be considered for designing a 33-kV con-
verter with the available commercial semiconductors. Each phase leg consists
of seven H-bridge inverter cells with 28 IGBTs in a phase and 84 in total in the
3-phase circuit. The DC supply voltage for a 33-kV 15-level converter is 3,467V.
The available 6.5-kV IGBT may be used for constructing the 33-kV 15-level con-
verter, because this IGBT is recommended for application of 3,600V in maxi-
mum. Figure7.50 plots the phase voltage waveform of a 33-kV 15-level MMC
converter. There are 28 steps in the peak-to-peak line voltage waveform, and each
step contributes 3,467V to the line voltage. Figure7.51 shows the line voltage
waveforms of the 15-level 33-kV converter. The frequency spectrum of the line
voltage of a 15-level MMC converter is depicted in Fig.7.52.
ABB, Infineon, and Mitsubishi Electric commercially developed 6.5-kV IGBT
modules with various power ratings. Table7.10 summarizes some possible 6.5-kV
IGBT modules for constructing medium-voltage converters. ABB and Mitsubishi
Electric are the market leaders to supply 6.5-kV IGBT module, who developed
6.5-kV IGBT modules with a current rating of a few hundred amperes. Figure7.53
shows the ABB 6.5-kV IGBT module 5SNA 0400J650100.
15
Phase 14
20 13
voltage 12
11
10 10
Voltage (kV)
3467 V 9
0
8
7
6
-10 5
4
3
-20 2
1
10 15 20 25 30 35 40 45 50
Time (ms)
50
Vab Vbc Vca
Voltage (kV)
0
-50
10 15 20 25 30 35 40
Time (ms)
0.03
Normalized amplitude
0.02
6.40% THDs
0.01
0
0 0.05 0.1 0.15 0.2 0.25
Frequency (MHz)
a
b
c
SA5 SA7 SB5 SB7 SC5 SC7
The H-bridge inverter DC-link voltage for a 33-kV 29-level converter is 1,734V.
The available 3.3-kV IGBT may be used to construct the 33-kV 29-level converter,
because this IGBT is recommended for 1,800V maximum applications. About
96% DVUF can be obtained with the 3.3-kV IGBTs. The devices dv/dt is about
50% lower than that of the devices in the 15-level converter, under the same oper-
ating conditions. About 50% lower dv/dt means significant improvement in the
device reliability. In total, there are 14 H-bridge inverter cells in each phase leg. In
order to drive such a converter, 14 phase-shifted carriers are required and adjacent
carriers are shifted by (180/14) degrees. The phase voltage and line voltage wave-
forms of the 29-level 33-kV converter are depicted in Figs.7.59 and 7.60.
7.3 Design and Analysis of 33-kV Converter Systems 263
Gate pulses
Reference >= 0 PS1
Comp NOT PS2
Inv
0o shifted >= 0 PS3
Inv
Comp NOT PS4
o
180 shifting Inv
>= 0 PS5
o
(180/11)1 Comp NOT PS6
shifted
Inv
Inv
o
>= 0 PS7
180 shifting
Comp NOT PS8
Inv
>= 0 PS41
(180/11)10o Comp NOT PS42
shifted
Inv
Inv
o
>= 0 PS43
180 shifting
Comp NOT PS44
Inv
Phase
20
voltage
10
Voltage (kV)
2206 V
0
-10
-20
10 15 20 25 30 35 40 45 50
Time (ms)
50
Vab Vbc Vca
Voltage (kV)
0
-50
10 15 20 25 30 35 40
Time (ms)
0.03
Normalized amplitude
0.01
0
0 0.05 0.1 0.15 0.2 0.25
Frequency (MHz)
Phase
20 voltage
10
Voltage (kV)
1734 V
0
-10
-20
10 15 20 25 30 35 40 45 50
Time (ms)
50
Vab Vbc Vca
Voltage (kV)
-50
10 15 20 25 30 35 40
Time (ms)
0.03
Normalized amplitude
0.01
0
0 0.05 0.1 0.15 0.2 0.25
Frequency (MHz)
The line peak-to-peak voltage consists of 56 voltage levels, and each level con-
tributes 1,734V to the peak-to-peak line voltage. The line voltage contains 4.12%
THDs, which satisfies the grid requirements and may enable line filter-less grid con-
nection. Figure7.61 plots the frequency spectrum of the 29-level 33-kV converter.
Compared with the 23-level converter, about 9% additional harmonic reduction can
be achieved with the 29-level converter. The switching scheme involves about 154
ALOs, which is 27% more complex than that of a 23-level converter control scheme.
The cost of 168 IGBTs is about AUD 229,992.00, which is about 12% lower than
that of a similar 15-level converter using IGBTs of one level higher voltage rating.
The H-bridge inverter DC-link voltage for a 33-kV 43-level converter is 1,156V.
The available cheap and matured 2.5-kV IGBT can be used for constructing the
33-kV 43-level converter, because this IGBT is recommended for application of
266 7 Design and Analysis of 11- and 33-kV Modular
1,200V in maximum. About 96% DVUF can be obtained with the 2.5-kV IGBTs.
In total, there are 21 H-bridge inverter cells in each phase leg and 252 active
switching devices are required for the 3-phase 43-level converter. Figure7.62
shows the circuit diagram of 43-level converter. In order to drive 252 IGBTs, 21
phase-shifted carriers are required and adjacent carriers are shifted by (180/21)
degrees. Figure7.63 shows the block diagram of the switching control scheme for
the 3-phase 43-level converter.
A total of 231 ALOs are involved with the switching scheme. Although three
times more switching devices are used in the 43-level converter, the semiconduc-
tor cost is about 41% lower than that of the 15-level converter using IGBTs of one
level higher voltage rating, due to the cheap cost of low-voltage-rated devices. The
line peak-to-peak voltage consists of 84 voltage levels, and each level contributes
a
b
c
SA5 SA7 SB5 SB7 SC5 SC7
Gate pulses
Reference >= 0 PS1
Comp NOT PS2
Inv
0o shifted >= 0 PS3
Inv
Comp NOT PS4
o
180 shifting Inv
>= 0 PS5
o
(180/21)1 Comp NOT PS6
shifted
Inv
Inv
o
>= 0 PS7
180 shifting
Comp NOT PS8
Inv
>= 0 PS81
(180/21)20o Comp NOT PS82
shifted
Inv
Inv
o
>= 0 PS83
180 shifting
Comp NOT PS84
Inv
1200
1000
800
Voltage (V)
600
400
200
0
10 15 20 25 30 35 40 45 50
Time (ms)
1000
500
Voltage (V)
-500
-1000
15 20 25 30 35 40 45 50
Time (ms)
Phase
20 voltage
10
Voltage (kV)
1156 V
0
-10
-20
10 15 20 25 30 35 40 45 50
Time (ms)
50
Vab Vbc Vca
Voltage (kV)
0
-50
10 15 20 25 30 35 40
Time (ms)
0.03
Normalized amplitude
0.02
3.61% THDs
0.01
0
0 0.05 0.1 0.15 0.2 0.25
Frequency (MHz)
400
300
200
Current (A)
100
0
-100
-200
-300
-400
0 10 20 30 40 50 60
Time (ms)
Phase
20 voltage
899 V
10
Voltage (kV)
-10
-20
10 15 20 25 30 35 40 45 50
Time (ms)
The H-bridge inverter DC-link voltage for a 33-kV 55-level converter is 899V.
The available cheap and mature 1.7-kV IGBT can be used to design the 33-kV
55-level converter, because this IGBT is recommended for application of 900V
in maximum. An almost 100% DVUF can be obtained with the 1.7-kV IGBTs. In
total, there are 27 H-bridge inverter cells in each phase leg and 324 active switch-
ing devices are required for the 3-phase 55-level converter. The 1.7-kV IGBT is
cheap, and the total semiconductor cost of the 55-level converter is about AUD
110,030.00, which is 22% lower than that of the 43-level converter using IGBTs
of one level higher voltage rating. The IGBTs price of 2.5kV or lower is in linear
50
Vab Vbc Vca
Voltage (kV)
-50
10 15 20 25 30 35 40
Time (ms)
range. Therefore, the reduction to the total price is small. The line peak-to-peak
voltage consists of 108 voltage levels, and each level contributes 899V to the
peak-to-peak line voltage. Due to the small step size, the line voltage waveforms
are found to be very consistent with the reference sine waveforms. Figures7.70
and 7.71 plot the phase and line voltage waveforms, respectively. The line volt-
age frequency spectrum is shown in Fig.7.72. The 55-level 33-kV voltage wave-
form contains about 3.47% THDs, which is only 3.8% lower than that of the
43-level converter. However, the switching scheme of the 55-level converter con-
sists of 297 ALOs. Compared with the 43-level converter, the control scheme of
the 55-level converter requires 66 more ALOs; that is, the control scheme is 28%
more complex.
0.03
Normalized amplitude
0.02
3.47% THDs
0.01
0
0 0.05 0.1 0.15 0.2 0.25
Frequency (MHz)
1.5
1
Index value
0.5
0
20 30 40 43 50
Number of levels
Table7.11Converter No. of 15 23 29 43 55
comparison for a 33-kV levels
system [10, 21]
IGBTs 84 132 168 252 324
THD (%) 6.40 4.54 4.12 3.61 3.47
Cost (AU$) 258,552 237,600 229,992 141,200 110,030
ALOs 77 121 154 231 297
2.00
Total index
23-level 33 kV converter
29-level 33 kV converter
43-level 33 kV converter
55-level 33 kV converter
1.00
0.94
7.4Summary
In this chapter, the designs of 11-kV and 33-kV converter systems have been ana-
lyzed with a focus on selecting the optimal number of levels for a medium-volt-
age converter. All possible MMC converter topologies have been considered for
each converter system. In order to ensure a cost-effective design, the DVUFs were
calculated and only the selected converters with high DVUFs were considered.
During the design process, the availability of semiconductor devices was consid-
ered in the first instance. After checking the availability of devices, the converter
systems were designed taking into account three main factors: the specified con-
verter output power quality, complexity of the switching controller, and cost of the
semiconductors. The investigation has shown that the 19-level MMC converter is
the optimal choice for an 11-kV converter system and the 43-level topology is the
optimal choice for a 33-kV inverter system.
References
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challenges, and research and developmental trends. Renew Sustain Energy Rev 33:161176
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559571
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2011/2012, Semikron International, May 2011, pp 9495
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Chapter 8
Conclusions and Future Works
Abstract This chapter concludes the book. In summary, this book has focused on
the optimal design of medium-voltage power converters for step-up-transformer-
less direct grid integration of renewable power generation systems and develop-
ment of a scaled down 1kV laboratory prototype test platform to describe the
implementation process of medium-voltage converter topologies. The design and
prototype development concept can be used to model the 1133kV system taking
into account some additional safety and reliability issues. Further, a few directions
have been recommended for future research and development.
8.1Introduction
Distribution of wind and solar photovoltaic (PV) energy throughout the world
should be first priority in solving our energy and environment crisis. Scientists
all around the world are now seeking energy solution from different renewable
resources and till today only wind and solar PV energy sources are found to be
suitable for future large-scale generation. By generating electric power from our
abundance renewable, such as wind and solar energy sources, we can solve a big
portion of energy deficiency. Moreover, the energy sector of the world is growing
curiously. It is facing an accelerating compound crisis of the globally established
fossil fuels. Immediate different breakthroughs for wind and solar PV power gen-
eration technologies are necessity to mitigate our fast growing energy demand. It
is expected that more than 80% future wind and solar PV power generation sys-
tems will be connected with the grids by 2030. Therefore, it is essential for scien-
tists and researchers to find the most effective converter technologies for the grid
integration of wind and solar PV power generation systems. Conventional grid
integration technique utilizes the power-frequency step-up-transformer, filter, and
booster. These heavy and large size power-frequency step-up-transformers signifi-
cantly increase the weight and volume of the renewable power generation systems.
Because of the heavy weight and large size of the power-frequency transformer,
the wind turbine generator and PV inverter system can be expensive and complex
8.2Conclusions
In order to select the most suitable power converter topology, an extensive litera-
ture review was carried out on the existing renewable power generation technolo-
gies covering generation, conversion, transmission, and distribution issues. The
recent commercial medium and large-scale renewable power generation systems
were mainly considered. As these require large areas of land, they are usually
installed in offshore or remote areas, far from cities and industrial area where is
electricity is consumed. The available power converter topologies developed in the
recent decades were investigated for their offshore and remote area applications.
The recently introduced smart micro-grid concept for efficient power transmission
and distribution was also considered in the literature review.
Although several types of multilevel converter topologies have been devel-
oped in the last few decades, most of them are not suitable for medium-voltage
high-power offshore and remote applications. In order to find suitable multilevel
converter topology, an extensive analysis was carried out on different multilevel
converter topologies taking into account the specified converter performance, con-
trol complexity, cost, and market availability of the power semiconductors.
Because of some special features (e.g., number of components scale linearly
with the number of levels, and individual modules are identical and completely
modular in construction hence enabling a high-level number attainability), the
MMC converter topology can be viewed as the best possible candidate for medium
voltage applications. However, the MMC converter requires multiple isolated
and balanced DC sources. A high-frequency magnetic link operated at a few kHz
to MHz was therefore developed to generate multiple isolated and balanced DC
sources for all the H-bridge inverter cells of the MMC converter from a single
source and a comprehensive electromagnetic analysis was conducted to verify the
feasibility of this new technology. Compared with the power-frequency transform-
ers, the high-frequency magnetic link has much smaller and lighter magnetic cores
and windings, thus much lower costs.
The multilevel converter requires a number of switching and control PWM
signals, which cannot be generated by the available DSP because the available
DSP can at present only provide about six pairs of PWM channels. Unlike the
DSP which runs a sequential program in its microprocessor, an FPGA may run
all the operations in parallel with the clock signal. In this instance, the FPGA is
the natural choice for medium voltage multilevel converters. Various design tech-
niques and software environments are available for the modeling of switching
control schemes with FPGA technology. Most of the techniques require special
software such as HDL coder, System Generator, PSIM, and ModelSim, which
increase the development time and cost. The most common software, such as the
8.2Conclusions 277
8.3Future Works
Although the high-frequency magnetic link can minimize the voltage imbalance
and common mode issues, it would also be an interesting article to develop a
special modulation scheme with voltage imbalance and common mode minimi-
zation capabilities; and
In order to verify the feasibility and ensure the safety, reliability, and stability of
the real-scale high-frequency magnetic-link MMC medium-voltage converter, a
full voltage (e.g., 1133kV) test platform should be developed.