This document describes a voltage converter circuit that contains: 1) A delayed-signal-generating circuit that delays a reference pulse signal using a selector and generates a delayed pulse signal. 2) A detection-signal-generating circuit that generates a detection pulse signal delayed by one clock cycle from the reference signal using the same delay component. 3) A delay-difference-detecting circuit that detects the phase difference between the delayed and detection pulse signals. 4) A control circuit that adjusts the target circuit's power supply voltage based on the detected phase difference.
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This document describes a voltage converter circuit that contains: 1) A delayed-signal-generating circuit that delays a reference pulse signal using a selector and generates a delayed pulse signal. 2) A detection-signal-generating circuit that generates a detection pulse signal delayed by one clock cycle from the reference signal using the same delay component. 3) A delay-difference-detecting circuit that detects the phase difference between the delayed and detection pulse signals. 4) A control circuit that adjusts the target circuit's power supply voltage based on the detected phase difference.
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VOLTAGE CONVERTER CIRCUIT:
The present invention provides a semiconductor device a comprising: a
delayed-signal-generating circuit for delaying a reference pulse signal by a delay time caused by a delay component on a critical path of a target circuit by a selector included in the delayed signal generating circuit and, thereby, generating a delayed pulse signal; a detection-signal-generating circuit, having the same delay component as the selector, for generating a detection pulse signal delayed in phase by one cycle of a clock signal Ck with respect to the reference pulse signal; a delay-difference-detecting circuit for detecting a phase difference between the delayed pulse signal and the detection pulse signal; and a control circuit for adjusting the magnitude of a power-supply voltage VDD supplied to the target circuit according to the-phase difference detected by the delay- difference-detecting circuit.