RT9955 Richtek

®
RT9955
PMIC for LCD TV / Monitor

General Description Features
The RT9955 generates all the supply rails for thin-film
 8V to 14V Supply Input Voltage Range
transistor (TFT) liquid-crystal display (LCD) panels in TVs
 Current Mode Boost Regulator
and monitors. It includes boost and buck regulators, VGH
 20V 3A 0.1ΩΩ Internal N-MOSFET
and VGL charge pump regulators, gate pulse modulator
 Programmable Over Current Protection
(GPM) , HV LDO, voltage detector (XAO) and VCOM OP.
 Programmable Soft-Start
The RT9955 supports input voltage from 8V to 14V and is
 Current Mode Buck Regulator
optimized for LCD TV panel and LCD monitor applications
 16.5V 3.2A 0.15ΩΩ Internal N-MOSFET
running directly from 12V supply.
 Over Current Protection
The boost and buck regulators feature internal power  Adjustable Output Voltage from 1.8V to 3.3V
MOSFETs and high frequency operation, allowing the use  Adjustable VGH Charge Pump
of small inductors and capacitors, for in a compact solution.  Continuous Output Current 50mA
Both switching regulators use fixed frequency, current  Adjustable VGL Charge Pump
mode control architectures, providing fast load-transient  Continuous Output Current 50mA
response and easy compensation.  Gate Pulse Modulator
The VGH and VGL charge pump regulators provide supply  18V to 35V Positive Supply Input
voltages for the TFT gate driver. Both output voltages can  Power On/Off Sequence Control
be adjusted with external resistive voltage dividers.  On-Chip GPM Controller with Adjustable Falling
Time and Falling Stop Voltage

The GPM is controlled by frame signals from the timing
 Voltage Detector (XAO)
controller to modulate the Gate-On voltage (VGHM), which
±1%)
 Adjustable Detecting Voltage (±
acts as a flicker compensation to reduce the coupling
 N-CH Open-Drain Output
effect between gate lines and pixels. It can also delay
 VCOM OP
VGHM while power on to achieve a correct power on
 5V to 20V Input Supply Voltage
sequence for gate driver ICs. The VGHM power on delay
±300mA Output Short-Circuit Current for 1ms
time, the falling time and falling stop voltage can all be
μs Slew Rate
 45V/μ
programmed by an external capacitor, an external resistor
 20MHz, −3dB Bandwidth
and an resistive voltage divider.
 HV LDO
The voltage detector (XAO) monitors VIN voltage to issue  5V to 20V Input Supply Voltage
a reset signal when the VIN voltage is too low. The ±0.5%)
 Adjustable Output Voltage (±
detecting level is determined by an external resistive  Over Current Protection (60mA)
voltage divider.  Low Dropout Voltage 0.5V (60mA)
The HV LDO can provide a highly accurate voltage (0.5%)  Selectable Frequency (500kHz/750KHz)
for gamma reference voltage. It has fast transient response  External PMOS Isolation Switch Controlled by Gate
and also a wide operation input range. Drive Signal
 Under Voltage Protection
The VCOM OP can drive the LCD VCOM voltage that
 Short Circuit Protection
features high short circuit current (300mA), fast slew rate
 Over Temperature Protection
(45V/μs), wide bandwidth (20MHz) and rail-to-rail inputs
 Power On Sequence Control
and outputs.
 Thin 48-Lead WQFN Package
The RT9955 is available in a small WQFN-48L 7x7 package.  RoHS Compliant and Halogen Free
Copyright © 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS9955-04 July 2018 www.richtek.com

1
RT9955
Applications Pin Configuration
 LCD TV / Monitor (TOP VIEW)
Ordering Information
VREF_FB
VREF_O
VGHM
DRVN
SUPN
DLY1
GND
DRN
VGH
RT9955
REF
FBN
FBP
Package Type 48 47 46 45 44 43 42 41 40 39 38 37
QW : WQFN-48L 7x7 (W-Type) VREF_I 1 36 DRVP
Lead Plating System VOP 2 35 CPGND
OGND 3 34 SUPP
G : Green (Halogen Free and Pb Free) OPP 4 33 THR
Note : OPN 5 32 COMP
OPO 6 31 FB1
Richtek products are : XAO 7
GND 30 GD
GVOFF 8 29 GD_I
 RoHS compliant and compatible with the current require-
EN 9 28 PGND
ments of IPC/JEDEC J-STD-020. FB2 10
49
27 PGND
OUT 11 26 LX1
 Suitable for use in SnPb or Pb-free soldering processes.
GND2 12 25 LX1
13 14 15 16 17 18 19 20 21 22 23 24
LX2
LX2
IN2
IN2
FSEL
BST
GND
VDET
NC
CLIM
SS
INVL
Marking Information
RT9955GQW : Product Number
WQFN-48L 7x7
RT9955 YMDNN : Date Code
GQW
YMDNN
Functional Block Diagram

INVL SS CLIM LX1 FB1 PGDN FSEL GD_I GD
Step-Up Oscillator
Internal Regulator Gate
Regulator Control
COMP
BST VREF_I
IN2 VREF_FB
HVLDO
VREF_O
Sequence EN
Step-Down
LX2 Control DLY1
Regulator
VOP
OPN
GND2 -
OUT OPO
+
FB2 Thermal OGND
Shutdown OPP
GVOFF
THR
REF Fault
Reference Logic and Switch DRN
GND
Timer Control VGHM
Block VGH
FBN Negative Voltage Positive

FBP
DRVN Regulator Detector Regulator
CPGND
SUPN VDET XAO SUPP DRVP
www.richtek.com DS9955-04 July 2018

2
RT9955
Typical Application Circuit
L1
10µH D1
VIN P1
VAVDD
C30 C4 C5
C27 C28 47nF 10nF R1 10µF
10µF 10µF C3 392k
1µF 20 25, 26 29 C6
INVL LX1 GD_I 10µF
GD 30 R2
30k C12
R17 16, 17 FB1 31 10µF
62k IN2 R4
32 30.9k
C1 C29 COMP
10µF 10µF RT9955
R5
R19 100k C7
10k CLIM 23 330pF
19 C8
VDET
42 22nF
24
SUPN SS VREF
C24
1µF 1
VREF_I
15 C2
BST R6
L2 C21 1µF
10µH 10k
0.1µF 13, 14 47
VOUT LX2 VREF_FB
C20
22µF D2 48 R7
12 VREF_O VREF
GND2 820
R21 C11
2k 10µF
11 OUT
2
C25 VOP R3
10nF 10 C21
FB2 6 10 1µF
OPO VCOM
R20 C26
68pF R18 5
1.2k 10k 7 OPN
VOUT XAO 4
OPP OPP
22 C22
High / Low FSEL OGND 3 1µF
Chip Enable R10
9 EN 340k
33
THR
46 37 R11
REF DLY1
C9 9.76k
C18 10nF
1µF
R13
105k 8 FROM
GVOFF
45 FBN TCON
R12
R14 43 41 1.2k
DRVN DRN
604k C16
0.47µF 40
VGHM VGHM
VGL
39
C17 VGH
1µF D5 C10
1µF R8
18, 44, Exposed Pad (49) 475k
GND 38
FBP
28, 27 C15
PGND R9
24k 22pF
CPGND SUPP DRVP
35 34 36
C23 C13
1µF 0.47µF
VAVDD VGH
D3
C14
1µF

3
®
RT9955
Timing Diagram
VIN UVLO
VBUCK
VGL
VEN
GD OK
P1 VSG
VAVDD
VGH

4
®
RT9955
Functional Pin Description
Pin No. Pin Name Pin Function
1 VREF_I Linear regulator input. Bypass VREF_I to GND with a 1F capacitor close to the pin.
Operational amplifier supply input. Connect this pin to the output of boost regulator and
2 VOP
bypass to OGND with a 1F capacitor.
3 OGND Ground for operational amplifiers. Connect this pin to power ground underneath the IC.
4 OPP Operational amplifier non-inverting input.
5 OPN Operational amplifier inverting input.
6 OPO Operational amplifier output.
7 XAO Reset function output.
High voltage switch control input. When GVOFF is high, the high voltage switch between
VGH and VGHM is on and the high voltage switch between VGHM and DRN is off. When
8 GVOFF GVOFF is low, the switch between VGH and VGHM is off and the switch between VGHM
and DRN is on. GVOFF is inhibited by the VIN under voltage lock out when the voltage on
DLY1 is less than 1.25V.
9 EN Enable input. Pulling EN high enables boost regulator and VGH charge pump.
Buck regulator feedback input. Connect FB2 to the center of a resistive voltage divider
10 FB2
between buck regulator output and GND to set buck regulator output voltage.
Buck regulator output sense input. OUT is the inverting input to the internal current sense
11 OUT
amplifier. Connect OUT directly to the step-down regulator output.
12 GND2 Buck regulator power ground.
Buck regulator switching node. LX2 is the source of the internal high side MOSFET.
13, 14 LX2 Connect the inductor and Schottky diode to LX2 and minimum the trace area for low EMI
performance.
Buck regulator bootstrap pin. BST is the supply for the high side MOSFET gate driver.
15 BST
Connect a 0.1F ceramic capacitor from BST to LX2.
16, 17 IN2 Buck regulator supply input.
Voltage detection input. Connect VDET to the center of a resistive voltage divider
19 VDET
between VIN and AGND.
4V internal linear regulator and startup circuitry supply input. The input voltage range of
20 INVL INVL is between 8V and 14V. Connect a 1F ceramic capacitor between INVL and GND.
Place the capacitor close to the IC.
21 NC No internal connection.
Frequency select pin. Connect FSEL to VIN or leaving FSEL unconnected for 750kHz
22 FSEL
operation. Connect this pin to GND for 500kHz operation.
23 CLIM Boost regulator OCP level setting by an external resistor to GND.
Soft-start control pin. Connect a soft-start capacitor (C8) to this pin. Soft-start capacitor is
charged with 5A. The soft start capacitor is discharged to ground when EN is low. If C8
24 SS
is less than 220pF, soft-start is controlled internally and soft-start time is 10ms. Otherwise,
the soft-start time is controlled by C8 and 5A charging current.
Boost regulator switching node. Connect the inductor and the Schottky diode to LX1 and
25, 26 LX1
minimum the trace area for low EMI.
27, 28 PGND Boost regulator power ground.

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RT9955
Pin No. Pin Name Pin Function
Output sense pin. The GD_I pin is connected to the internal tracking circuit and
29 GD_I over voltage protection comparator. This pin needs to be connected to the
output of the boost converter.
Gate drive pin. Used to control an external PMOSFET switch to provide input to
30 GD output isolation of AVDD. GD pin will be pulled low when EN pulls high. The GD
pin pulls high when UVP/SCP occurs.
Boost regulator feedback input. Connect FB1 to the center of a resistive voltage
31 FB1 divider between boost regulator output and GND to set boost regulator output
voltage. Place the resistive voltage divider close to FB1.
32 COMP Boost regulator error amplifier compensation pin.
VGHM falling regulation adjustment input. Connect THR to the center of a
resistive voltage divider between a reference supply and GND to adjust the
33 THR VGHM falling regulation set point. GVOFF low allow VGHM to disconnect from
VGH and be discharged through RE; discharge stops when VGHM reaches 10 x
VTHR.
VGH charge-pump regulator supply input. Bypass SUPP to CPGND with a
34 SUPP
minimum 1F ceramic capacitor.
35 CPGND Power ground for charge pump.
36 DRVP VGH charge pump regulator driver output.
VGH charge pump regulator and GPM delay input. Connect a capacitor, C9,
37 DLY1 between DLY1 and GND to set the delay time. A 5A current source charges
C9.
VGH charge pump regulator feedback input. Connect FBP to the center of a
resistive voltage divider between the positive output and GND to set the positive
38 FBP
charge pump regulator output voltage. Place the resistive voltage divider close
to FBP.
39 VGH GPM input.
40 VGHM GPM output.
41 DRN GPM discharge pin.
VGL charge pump regulator supply input. Bypass SUPN to GND with a minimum
42 SUPN
1F ceramic capacitor.
43 DRVN VGL charge pump regulator driver output.
18, 44 GND VGL charge pump power ground and analog ground.
VGL charge pump regulator feedback input. Connect FBN to the center of a
resistive voltage divider between the negative output and REF to set the
45 FBN
negative charge pump regulator output voltage. Place the resistive voltage
divider close to FBN.
46 REF Reference output. Connect a 1F ceramic capacitor between REF and GND.
Linear regulator feedback input. Connect VREF_FB to the center of a resistive
47 VREF_FB voltage divider between to VREF_O and GND to set the needed regulator output
voltage.
Linear regulator output. Bypass VREF_O to GND with a minimum 1F capacitor
48 VREF_O close to the pin.
Ground pin. The Exposed Pad must be soldered to a large PCB and connected
49 (Exposed Pad) GND
to GND for maximum power dissipation.

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RT9955
Absolute Maximum Ratings (Note 1)
 IN2, INVL, SUPN, FSEL to GND -------------------------------------------------------------------------- −0.3V to 16.5V
 SUPP, GD_I, VOP, VREF_I to GND ---------------------------------------------------------------------- −0.3V to 20V
 DRVP to CPGND --------------------------------------------------------------------------------------------- −0.3V to (VSUPP + 0.3V)
 DRVN to GND ------------------------------------------------------------------------------------------------- −0.3V to (VSUPN + 0.3V)
 OPO, OPP, OPN to OGND -------------------------------------------------------------------------------- −0.3V to (VVOP + 0.3V)
 VREF_O to GND --------------------------------------------------------------------------------------------- −0.3V to (VVREF_I + 0.3V)
 FB1, FB2, FBP, FBN, GVOFF, DLY1, VREF_FB, THR, EN to GND ----------------------------- −0.3V to 6.5V
 OUT, REF, COMP, SS, XAO, VDET, CLIM to GND --------------------------------------------------- −0.3V to 6.5V
 GND2, OGND, CPGND to GND --------------------------------------------------------------------------- ±0.3V
 BST to GND2 -------------------------------------------------------------------------------------------------- −0.3V to 20V
 LX1 to PGND -------------------------------------------------------------------------------------------------- −0.3V to 20V
 LX2 to GND2 --------------------------------------------------------------------------------------------------- −0.3V to (IN2+0.3V)
 VGHM, VGH, DRN to GND --------------------------------------------------------------------------------- −0.3V to 40V
 VGH to VGHM ------------------------------------------------------------------------------------------------- −0.3V to 40V
 VGH, VGHM to DRN ----------------------------------------------------------------------------------------- −0.3V to 40V
 Power Dissipation, PD @ TA = 25°C
WQFN-48L 7x7 ----------------------------------------------------------------------------------------------- 3.226W
 Package Thermal Resistance (Note 2)
WQFN-48L 7x7, θJA ------------------------------------------------------------------------------------------ 31°C/W
WQFN-48L 7x7, θJC ----------------------------------------------------------------------------------------- 6°C/W
 Junction Temperature ---------------------------------------------------------------------------------------- 150°C
 Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------ 260°C
 Storage Temperature Range ------------------------------------------------------------------------------- −65°C to 150°C
Recommended Operating Conditions (Note 3)

 Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C
 Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
General
IN2, INVL Input Voltage Range 8 12 14 V
Quiescent Current into INVL IQIN LX not switching -- 0.02 2 mA
VUVLO VIN falling 5.4 6 6.6
Under-Voltage Lockout Threshold V
Rising hystersis 0.1 -- 0.5
FSEL = GND -- 500 --
Switching Frequency kHz
FSEL = VIN -- 750 --
Maximum Duty-Cycle -- 80 -- %
Boost Regulator
Output Voltage Range VAVDD VIN -- 18 V
FB1 Reference Voltage VFB1 1.2375 1.25 1.2625 V

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RT9955
FB Line Regulation VIN = 10.8V to 13.2V -- 0.15 0.2 %/V
Transconductance Gm I = ±2.5A at COMP = 1V -- 100 -- A/V
Voltage Gain AV FB to COMP -- 700 -- V/V
Current Limit ILIM1 3 4 -- A
On-Resistance RDS(ON) -- 100 250 m
Current-Sense Transresistance RCS -- 0.25 -- V/A
Soft-start Charge Current ISS -- 5 -- A
Internal Soft-Start C8 < 220pF -- 10 -- ms
Reference
REF Output Voltage No external load, -- 1.25 -- V
REF Load Regulation 0 < IREF < 50A -- 10 -- mV
REF Sink Current REF in regulation -- 10 -- A
Buck Regulator
FB2 Reference Voltage VFB2 1.2375 1.25 1.2625 V
DC Line Regulation 10.8V < VIN < 13.2V -- 0.1 -- %/V
LX2-to-IN2 Switch On-Resistance -- 150 300 m
LX2-to-GND2 Switch
-- 20 -- 
On-Resistance
Current Limit 2.5 3.2 -- A
Error Amplifier Transconductance Gm2 -- 100 -- A/V
Error Amplifier Voltage Gain AV -- 700 -- V/V
Current-Sense Transresistance RCS -- 0.3 -- V/A
Soft-Start Ramp Time -- 3 -- ms
FB2 UVP Trip Level Falling edge -- 1 -- V
Duration to Trigger UVP Condition -- 50 -- ms
FB2 SCP Trip Level Falling edge -- 0.5 -- V
Positive Charge-Pump Regulator
FBP Reference Voltage VFBP 1.225 1.25 1.275 V
FBP Line Regulation Error VIN = 10.8V to 13.2V -- -- 6 mV/V
DRVP P-MOSFET On-Resistance -- 2 -- 
DRVP N-MOSFET On-Resistance -- 1 -- 
FBP UVP Trip Level Falling edge -- 1 -- V
Duration to Trigger Fault Condition -- 50 -- ms
FBP Short Circuit Level Falling edge -- 0.5 -- V
Negative Charge-Pump Regulator
FBN Regulation Voltage 0.21 0.25 0.29 V

8
RT9955
Final FBN Regulation Voltage VREF VFBN 0.98 1 1.02 V
FBN Line Regulation Error VIN = 10.8V to 13.2V -- -- 6 mV/V
DRVN P-MOSFET On-Resistance -- 6 -- 
DRVN N-MOSFET On-Resistance -- 2 -- 
FBN UVP Trip Level VREF VFBN -- 0.8 -- V
Duration to Trigger Fault Condition -- 50 -- ms
FBN Short Circuit Protection Level VREF VFBN -- 0.4 -- V
Sequence Control
EN Input Low Voltage -- -- 0.6 V
EN Input High Voltage 1.5 -- 5.5 V
DLY1 Capacitor Charge Current -- 5 -- A
VDLY1 Turn-On Threshold -- 1.25 -- V
GD Output Sink Current EN = high, VGD_I = VIN -- 10 -- A
GD On-Voltage EN = high, VGD_I = VIN -- VIN 5 -- V
Gate Pulse Modulator (GPM)
GVOFF Input Low Voltage -- -- 0.6 V
GVOFF Input High Voltage 1.5 -- 5.5 V
GVOFF Input Leakage Current 1 -- 1 A
GVOFF-to-VGHM Rising 1k from DRN to GND,
-- 100 -- ns
Propagation Delay 1.5nF from VGHM to GND
GVOFF-to-VGHM Falling 1k from DRN to GND,
-- 250 -- ns
Propagation Delay 1.5nF from VGHM to GND
VDLY1 = GVOFF = 3V -- 1.5 2
VGH Input Current mA
VDLY1 = 3V, GVOFF = 0 -- 0.14 0.2
DRN = 8V, VDLY1 = 3V,
DRN Input Current -- 0 1 A
VGHM > DRN, GVOFF = 0
VGH Switch On-Resistance VDLY1 = GVOFF = 3V -- 5 10 
VDLY1 = 3V, GVOFF = 0,
DRN Switch On-Resistance -- 20 50 
VGHM= 28V, THR = 1.4V
VGHM Stop Level VTHR < 1.5V -- 10 x VTHR -- V
Voltage Detector (XAO)
Detecting Voltage Adjustment VDET Falling edge -- 1.25 -- V
Detecting Voltage Accuracy 1 -- 1 %
VCOMP OP
Supply Voltage Range VOP 4.5 -- 18 V
Supply Current IOP -- 3 -- mA
Input Offset Voltage VOS VCOM = AVDD/2 -- -- 20 mV
Input Bias Current IBIAS -- 1 100 nA

9
RT9955
VSUP
Output Voltage Swing High VOH ILOAD = 10mA -- -- mV
100
Output Voltage Swing Low VOL ILOAD = 10mA -- 100 -- mV
Short Circuit Current To AVDD/2 source or sink for 1ms -- 300 -- mA
-3dB Bandwidth F3dB RL = 10k, CL = 10pF -- 20 -- MHz
Gain Bandwidth Product GBW RL = 10k, CL = 10pF -- 8 -- MHz
Slew Rate -- 45 -- V/s
HVLDO
Quiescent Current IQ -- 40 -- A
LDO Feedback Reference Voltage VREF_FB -- 1.25 -- V
Feedback Voltage Tolerance 0.5 -- 0.5 %
VREF_I = 15V, VREF_O = 14V,
Output Current Limit 60 -- -- mA
ROUT = 50
Dropout Voltage ILOAD = 60mA -- 0.5 -- V
VREF_I = VREF_O + 1V,
Power Supply Rejection Rate -- 60 -- dB
IOUT = 10mA
Protection
Thermal Shutdown Threshold TSD -- 160 -- C
Switching Frequency Selection
FSEL = high 1.5 -- --
FSEL Input Levels V
FSEL = low -- -- 0.6
FSEL Pull High Current -- 5 -- A
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. The device is not guaranteed to function outside its operating conditions.

10
RT9955
Typical Operating Characteristics
Boost Efficiency vs. Load Current Buck Efficiency vs. Load Current
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
50 50
40 40
30 30
20 20
10 10
VIN = 12V, VAVDD = 17.5V, FSEL = VIN VIN = 12V, VOUT = 3.3V, FSEL = VIN
0 0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Load Current (A) Load Current (A)
Boost Output Voltage vs. Load Current Buck Output Voltage vs. Load Current
17.5 3.30
17.4 3.26
Output Voltage (V)
Output Voltage (V)
17.3 3.22
17.2 3.18
17.1 3.14
VIN = 12V, FSEL = VIN VIN = 12V, FSEL = VIN

17.0 3.10
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Load Current (A) Load Current (A)
VGH Output Voltage vs. Load Current VGL Output Voltage vs. Load Current
25.0
-5.4
24.5
-5.6
Output Voltage (V)
Output Voltage (V)
24.0
-5.8
23.5
-6.0
23.0
-6.2
22.5
-6.4
VIN = 12V, FSEL = VIN
22.0
VIN = 12V, FSEL = VIN
-6.6
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Load Current (A)
Load Current (A)

11
RT9955
Boost Reference Voltage vs. Temperature Buck Reference Voltage vs. Temperature
1.28 1.28
1.27 1.27
Reference Voltage (V)

1.26 1.26
1.25 1.25
1.24 1.24
1.23 1.23
VIN = 12V VIN = 12V

1.22 1.22
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)
VGH Reference Voltage vs. Temperature REF-FBN Voltage vs. Temperature

1.28 1.04
1.27 1.03
REF-FBN Voltage (V)
1.26 1.02
1.25 1.01
1.24 1.00
1.23 0.99
VIN = 12V VIN = 12V

1.22 0.98
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)
Frequency vs. Temperature Power On

800
780
760 VIN
(10V/Div)
Frequency (kHz)1
740
720
VOUT
700 (5V/Div)
680
660 VGL
(10V/Div)
640
VAVDD
620 (10V/Div)
VIN = 12V, FSEL = VIN VIN = 12V, FSEL = VIN
600
-50 -25 0 25 50 75 100 125 Time (50ms/Div)
Temperature (°C)

12
RT9955
Boost Load Transient Response Buck Load Transient Response

L1 = 10μH, R4 = 30.9kΩ, C7 = 330pF L2 = 10μH, C25 = 10nF, C26 = 68pF
VAVDD_ac V BUCK_ac
(1V/Div) (100mV/Div)
IAVDD
(500mA/Div)
IOUT
VIN = 12V, VAVDD = 17.5V, FSEL = VIN
(500mA/Div)
VIN = 12V, VOUT = 3.3V, FSEL = VIN
Time (500μs/Div) Time (500μs/Div)
GPM with GVOFF OPA Rail-to-Rail Input vs. Output

CLOAD = 1.5nF, R12 = 1.2k
GVOFF
(5V/Div)
OPP
(5V/Div)
VGHM
(10V/Div)
OPO
(5V/Div)
VGH Ripple
(500mV/Div)
VGH = 24V, FLK = 50kHz, VTHR = 0.5V VOP = 10V
Time (5μs/Div) Time (2μs/Div)
OPA Slew Rate
OPO
(2V/Div)
OPP
(2V/Div)
VOP = 10V
Time (100ns/Div)

13
RT9955
Application Information
The RT9955 contains a high performance boost regulator Boost Loop Compensation
to generate voltage for the panel source driver ICs and a The voltage feedback loop can be compensated with an
buck converter to provide the logic voltage for the timing external compensation network consisting of R4 and C7 .
controller. It also includes a voltage detector, a high voltage Choose R4 to set high frequency integrator gain for fast
LDO regulator, and a fast response operational amplifier transient response and C7 to set the integrator zero to
for common voltage. Moreover, a positive and a negative maintain loop stability.
charge pump regulator are included to generate gate high
and gate low voltages respectively. The following content Boost Over Current Protection
contains detailed description of the part, as well as The RT9955 boost converter has over-current protection
information for component selection. to limit the peak inductor current. It prevents large current
from damaging the inductor and diode. If the inductor
Boost Regulator
current exceeds the current limit, while the switch is ON
The boost regulator is a high efficiency current-mode PWM the internal LX switch will turn off immediately to shorten
architecture with 500kHz / 750kHz operation frequency. the duty cycle. Therefore, the output voltage drops
It provides the regulated supply voltage for the panel source whenever the over current condition occurs. The peak
driver ICs. The converter is a high switching frequency inductor current is also affected by the input voltage, duty
current-mode regulator with an integrated 20V N-Channel cycle, and inductor value. Therefore, the boost OCP level
0.1Ω MOSFET that allows the use of ultra-small inductors is setting by an external resistor to GND. The regulated
and ceramic capacitors. It provides fast transient response OCP level is shown as following equation :
to generate source driver supplies for TFT LCD display.
60.5k
Boost Current Limit Setting Level = ILIM1 
R5
Gate Function
where ILIM1 is the current-limit level and typical value is 4A
The gate function is used to control an external P-MOSFET
to provide input to output isolation of AVDD. The GD pin is Boost Inductor Selection
pulled low when EN pulls high. The GD pin pulls high when The inductance depends on the maximum input current.
UVP or SCP occurs. As a general rule, the inductor current ripple is 20% to
40% of the maximum input current. Assuming 40% as
Boost Soft-Start the criterion, then
The RT9955 boost converter provides a soft-start function VOUT x IOUT(MAX)
IIN(MAX) =
to minimize the inrush current. If the capacitor,C8, is less  x VIN
than 220pF, soft-start will be controlled internally with a IRIPPLE = 0.4 x IIN(MAX)
default soft-start time of 10ms. Otherwise, the soft-start
where η is the efficiency, IIN(MAX) is the maximum input
time is controlled by C8 with a 5μA charging current. A
current and IRIPPLE is the inductor current ripple. The input
typical value for the soft-start capacitor is 22nF.
peak current is then calculated to be the maximum input
Boost Output Voltage Setting current plus half of the inductor current ripple.
The regulated output voltage is shown in the following IPEAK = 1.2 x IIN(MAX)
equation :
Note that the saturated current of the inductor must be
 R1  greater than IPEAK. The inductance can then be determined
AVDD = VFB1 x  1 +  , where VFB1 = 1.25V (typ.)
 R2 
by the following equation :
The recommended value for R2 is up to 10kΩ without any
 x  VIN  x  VOUT  VIN 
2
side-effects. Moreover, place the resistor divider as close L=
0.4 x  VOUT  x IOUT(MAX) x fOSC
2
as possible to the chip to reduce noise sensitivity.

14
RT9955
Where fOSC is the switching frequency. To consider the
system performance, a shielded inductor is preferred to
avoid EMI issue. ΔIL
Input Current Inductor Current

Boost Diode Selection
Schottky diode is a good choice for any asynchronous
boost converter due to its small forward voltage.
However,important parameters such as power dissipation, Output Current
reverse voltage rating and pulsating peak current should Time
be considered when selecting the Schottky diode. It is

(1-D)TS Output Ripple
recommended to choose a suitable diode with reverse Voltage (ac)
voltage rating greater than the maximum output voltage.
Time
Boost Output Capacitor Selection ΔVOUT1
Output ripple voltage is an important index for estimating

the performance. This portion consists of two parts, one Figure 1. The Output Ripple Voltage without the Contribution
is the product of the inductor current ripple with ESR of of ESR
output capacitor, while the other part is formed by charging
and discharging process of the output capacitor. As shown Boost Input Capacitor Selection
in Figure 3, ΔVOUT1 can be evaluated base on the ideal
Low ESR ceramic capacitors are recommended for input
energy equalization. According to the definition of Q, the
capacitor applications. Low ESR will effectively reduce
Q value can be calculated as the following equation :
the input voltage ripple caused by the switching operation.
1  1   1 
Q= x  IIN + IL  IOUT  +  IIN  IL  IOUT   A 20μF low ESR ceramic capacitor is sufficient for most
2  2   2  applications. Nevertheless, this value can be decreased
VIN 1
x x = COUT x VOUT1 for applications with lower output current requirement.
VOUT fOSC
Another consideration is the voltage rating of the input
where fOSC is the switching frequency and ΔIL is the capacitor, which must be greater than the maximum input
inductor ripple current. Bring COUT to the left side to voltage.
estimate the value of ΔVOUT1 according to the following
equation : Buck Regulator
D x IOUT
VOUT1 = The buck converter is a high efficiency PWM architecture
 x COUT x fOSC
with 500kHz / 750kHz operation frequency, fast transient
when D is the duty cucle and η and the boost converter
response and simple internal compensation. The converter
efficiency.
drives an internal N-channel MOSFET connected between
Finally, taking ESR into account, the overall output ripple the IN2 pin and LX2 pin. Connect a 100nF low ESR ceramic
voltage can be determined by the following equation : capacitor between the BST pin and LX2 pin to provide gate
D x IOUT
VOUT = IIN x ESR + driver voltage for the high side MOSFET.
 x COUT x fOSC
The output capacitor, COUT, sholud be selected accordingly. Buck Output Voltage Setting
The regulated output voltage is shown as following the
equation :
 R21 
VOUT = VFB2 x  1 +  , where VFB2 = 1.25V (typ.)
 R20 

15
RT9955
Buck Inductor Selection This formula has a maximum at VIN = 2VOUT, where
The inductor value and operating frequency determine the I RMS = I OUT/2. This simple worst-case condition is
ripple current according to a specific input and output commonly used for design because even significant
voltage. The ripple current, IL, will increase with higher VIN deviations do not offer much relief. Choose a capacitor
and decrease with higher inductance. rated at a higher temperature than required. Several
 V   V  capacitors may also be paralleled to meet size or height
IL =  OUT  x  1  OUT 
 fOSC x L   VIN  requirements in the design. For the input capacitor, a
Having a lower ripple current reduces not only the ESR 10μF x 2 low ESR ceramic capacitor is recommended.
losses in the output capacitors but also the output voltage
ripple. High frequency with small ripple current can achieve Buck Output Capacitor Selection
the highest operation efficiency . However, it requires a The selection of COUT is determined by the required ESR
large inductor to achieve this goal. For the inductor to minimize voltage ripple. Moreover, the amount of bulk
selection, setting the value of ΔII(MAX) = 0.4 is a reasonable capacitance is also a key for COUT selection to ensure
starting point. The largest ripple current occurs at the that the control loop is stable. Loop stability can be
highest VIN. To guarantee that the ripple current stays checked by viewing the load transient response as
below the specified maximum, the inductor value should described in a later section.
be chosen according to the following equation : The output ripple, VOUT, is determined by :
 VOUT   VOUT   1 
L=   x 1   VOUT = IL x  ESR + 
 fOSC x I   VIN(MAX)   8 x fOSC x COUT 
 L(MAX) 
The output ripple will be highest at the maximum input
The inductor's current rating (causes a 40°C temperature voltage since IL increases with input voltage. Multiple
rise from 25°C ambient) should be greater than the capacitors placed in parallel may be needed to meet the
maximum load current, and its saturation current should ESR and RMS current handling requirement. Suitable
be greater than the short-circuit peak current limit. candidates such as dry tantalum, special polymer,
aluminum electrolytic and ceramic capacitors are all
Buck Diode Selection
available in surface mount packages. Special polymer
When the power switch turns off, the path of the current
capacitors offer very low ESR value. However, it provides
is through the diode connected between the switch output
lower capacitance density than other types. Although
and ground. This forward biased diode must have a
Tantalum capacitors have the highest capacitance density,
minimum voltage drop and quick recovery time. Schottky
it is important to only use types that pass the surge test
diodes are recommended and should be able to handle
for use in switching power supplies. Aluminum electrolytic
typical operation currents. Care should be given, however,
capacitors have significantly higher ESR. However, it can
to make sure that the reverse voltage rating of the diode
be used in cost-sensitive applications requiring high ripple
is greater than the maximum input voltage, and the current
current rating and long term reliability. Ceramic capacitors
rating is greater than the maximum load current.
have excellent low ESR characteristics but can have a
Buck Input Capacitor Selection high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
The input capacitance, C IN, is needed to filter the
can also lead to significant ringing.
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor Nevertheless higher value, lower cost ceramic capacitors
sized for the maximum RMS current should be used. The are now becoming available in smaller case sizes. Their
RMS current is given by : high ripple current, high voltage rating and low ESR make
VOUT VIN them ideal for switching regulator applications. However,
IRMS = IOUT(MAX) x 1
VIN VOUT care must be taken when these capacitors are used at

16
RT9955
the input and output. When a ceramic capacitor is used VGHM Stop Level vs. THR Voltage
35
at the input and VIN the power is supplied by a wall adapter
through long wires, a load step at the output can induce
28
VGHM Stop Level (V)

ringing at the input. At best, this ringing can couple to the
output and be mistaken as loop instability. At worst, a
21
sudden inrush of current through the long wires can
potentially cause a voltage spike at VIN large enough to
14
damage the part.
LDO Current Limit 7
The HVLDO contains an independent current-limit

mechanism, which monitors and controls the pass 0
0 0.4 0.8 1.2 1.6 2
transistor's gate voltage to limit the output current. It can
THR Voltage (V)
protect the IC even when directly shorting the output to
GND. Figure 2
Operational Amplifier
LDO Output Voltage Setting
The function of the operational amplifier is to supply the
The regulated output voltage can be calculated as the
LCD backplane, VCOM. The operational amplifier features
following equation :
±300mA output short-circuit current, 45V/μs slew rate,
 R6  and 20MHz bandwidth. An internal short-circuit protection
VREF = VREF_FB x  1 +  , where VREF_FB
 R7 
circuit is implemented to protect the device from output
= 1.25V (typ.)
short-circuit.
The recommended value for R6 is up to 10kΩ without any
side-effects. Place the resistor divider as close as possible Voltage Detector
to the chip to reduce noise sensitivity. The voltage detector monitors the VDET pin voltage to
generate a reset signal when VDET is lower than the
GPM detecting level and the detecting level is determined by
The GPM is controlled by frame signals from the timing an external resistor divider.
controller to modulate the Gate-On voltage and acts as a  R17   R17 
Reset Voltage = VDET x 1 +  = 1.25V x 1 + 
flicker compensation circuit to reduce the coupling effect  R19   R19 
between gate lines and pixels. It can also delay the Gate-  R17 
VHYS = 50mV x 1 + , where VHYS is the Hysteresis
On voltage while in power on for achieving a correct power  R19 
on sequence for gate driver ICs. Both, the power on delay
time and the falling time of the Gate-On voltage, are Positive Charge-Pump Regulator
programmable by an external capacitor and resistor. The The positive charge pump provides high level voltage for
delay time is programmable by an external capacitor (C9). the TFT gate driver. The charge pump can provide a
Moreover, when GVOFF is low, VGHM falling stop level is programmable output voltage by setting the resistive
10 times the voltage on the THR pin. However, this gain voltage-divider sensing at the FBP pin. The error amplifier
ratio will be increase if VTHR higher than 1.5V. The following varies the differential voltage by sensing FBP pin to
figure illustrates the corresponding VGHM stop level within regulate the output voltage as the following equation :
the THR voltage.  R8 
VGH = VFBP x  1 + 
 R9 
Where VFBP is the reference voltage and the typical value
is 1.25V.

17
RT9955
Negative Charge Pump Regulator Layout Consideration
The operation of the negative charge pump is similar to For high frequency switching power supplies, a correct
the positive charge pump. The negative charge pump PCB layout is important to get good regulation, high
provides low level voltage for the TFT gate driver. The charge efficiency and stability. The following descriptions are the
pump can provide a programmable output voltage by setting guidelines for better PCB layout.
the resistive voltage divider sensing at the FBN pin. The  For good regulation, place the power components as
error amplifier varies the differential voltage by sensing close as possible. The traces should be wide and short
FBN pin to regulate the output voltage as the following enough especially for the high-current loop.
equation :
R14  The feedback voltage-divider resistors must be near the
VGL = VFBN   VREF  VFBN  x
R13 feedback pin. The divider center trace must be short
Where VREF is the reference voltage on pin and the typical and the trace must be kept away from any switching
value is 1.25V. VFBN is the reference voltage and the typical nodes.
value is 0.25V  The compensation circuit should be kept away from the
power loops and be shielded with a ground trace to
Over-Temperature Protection
prevent any noise coupling.
The RT9955 boost converter has a thermal protection
 Minimize the size of the LX node and keep it wide and
function to prevent overheating from excessive power
short. Keep the LX node away from the FB.
dissipation. When the junction temperature exceeds
160°C, it will shut down the all switching signals and the  The Exposed Pad of the chip should be connected to a
GD pin will pull high. strong ground plane for maximum thermal consideration.
VREF_FB
VREF_O
VGHM
The compensation circuit

DRVN
SUPN
DLY1
GND
DRN
VGH
FBN
REF
FBP
should be kept away from

the power loops and
should be shielded with a
48 47 46 45 44 43 42 41 40 39 38 37 ground trace to prevent
The feedback voltage-
divider resistors must VREF_I 1 36 DRVP any noise coupling.
be near the feedback VOP 2 35 CPGND
pin. The divider center R4 C7
trace must be short OGND 3 34 SUPP
and avoid the trace OPP 4 33 THR R2 GND
near any switching GND
nodes. OPN 5 32 COMP
R1
OPO 6 31 FB1 The feedback voltage-
R20 C26 XAO GND GD C12
7 30 divider resistors must be
GVOFF 8 29 GD_I near the feedback pin. The
C6 divider center trace must be
R21 EN 9 28 PGND short and avoid the trace
C25
FB2 10 27 PGND near any switching nodes.
49
OUT 11 26 LX1 C5
GND2 12 25 LX1
D1 AVDD
13 14 15 16 17 18 19 20 21 22 23 24
C20 L1 Minimize the size of the LX
LX2
LX2
IN2
IN2
FSEL
BST
VDET
SS
GND
NC
CLIM
INVL
C1 node and keep it wide and

VOUT D2 short. Keep the LX node away
GND from the FB and analog
ground.
+
C20 C21
L2
VIN
Minimize the size of the LX
node and keep it wide and
short. Keep the LX node away
from the FB and analog
ground.
Figure 3. PCB Layout Guide

18
RT9955
Outline Dimension
1 1
2 2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.
Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.200 0.300 0.008 0.012
D 6.950 7.050 0.274 0.278
D2 5.050 5.250 0.199 0.207
E 6.950 7.050 0.274 0.278
E2 5.050 5.250 0.199 0.207
e 0.500 0.020
L 0.350 0.450 0.014 0.018
W-Type 48L QFN 7x7 Package
Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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®

PMIC for LCD TV / Monitor

Time and Falling Stop Voltage

DS9955-04 July 2018 www.richtek.com

Functional Block Diagram

FBN Negative Voltage Positive

SUPN VDET XAO SUPP DRVP

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DS9955-04 July 2018 www.richtek.com

DS9955-04 July 2018 www.richtek.com

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Recommended Operating Conditions (Note 3)

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Load Current (A) Load Current (A)

VIN = 12V, FSEL = VIN VIN = 12V, FSEL = VIN

Load Current (A) Load Current (A)

Output Voltage (V)

DS9955-04 July 2018 www.richtek.com

Reference Voltage (V)

VIN = 12V VIN = 12V

Temperature (°C) Temperature (°C)

VGH Reference Voltage vs. Temperature REF-FBN Voltage vs. Temperature

VIN = 12V VIN = 12V

Frequency vs. Temperature Power On

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Boost Load Transient Response Buck Load Transient Response

Time (500μs/Div) Time (500μs/Div)

GPM with GVOFF OPA Rail-to-Rail Input vs. Output

Time (5μs/Div) Time (2μs/Div)

OPA Slew Rate

DS9955-04 July 2018 www.richtek.com

www.richtek.com DS9955-04 July 2018

Input Current Inductor Current

reverse voltage rating and pulsating peak current should Time

be considered when selecting the Schottky diode. It is

Output ripple voltage is an important index for estimating

DS9955-04 July 2018 www.richtek.com

www.richtek.com DS9955-04 July 2018

VGHM Stop Level (V)

LDO Current Limit 7

The HVLDO contains an independent current-limit

DS9955-04 July 2018 www.richtek.com

The compensation circuit

should be kept away from

C1 node and keep it wide and

Figure 3. PCB Layout Guide

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Note : The configuration of the Pin #1 identifier is optional,

Dimensions In Millimeters Dimensions In Inches

W-Type 48L QFN 7x7 Package

Richtek Technology Corporation

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