® ESDAxxL

Application Specific Discretes

DUAL TRANSIL ARRAY
A.S.D. FOR ESD PROTECTION
APPLICATIONS
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
- COMPUTERS
- PRINTERS
- COMMUNICATION SYSTEMS
It is particulary recommended for the RS232 I/O
port protection where the line interface withstands
only with 2kV ESD surges.
FEATURES
SOT23
n 2 UNIDIRECTIONAL TRANSIL FUNCTIONS.
n LOW LEAKAGE CURRENT : IR max. < 20µA at
VBR.
n 300 W PEAK PULSE POWER (8/20µs)

DESCRIPTION
The ESDAxxL is a dual monolithic voltage FUNCTIONAL DIAGRAM
suppressor designed to protect components which
are connected to data and transmission lines
against ESD.
It clamps the voltage just above the logic level
supply for positive transients, and to a diode drop
below ground for negative transients.
It can also work as bidirectionnal suppressor by
connecting only pin1 and 2.

BENEFITS
High ESD protection level : up to 25 kV.
High integration.
Suitable for high density boards.

COMPLIES WITH THE FOLLOWING STANDARDS :

IEC61000-4-2 level 4

MIL STD 883C-Method 3015-6 : class 3.

(human body model)

Marchr 2000 - Ed: 4A 1/6

ESDAxxL
ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C)

Symbol Parameter Value Unit

VPP Electrostatic discharge kV
MIL STD 883C - Method 3015-6 25
IEC61000-4-2 air discharge 16
IEC61000-4-2 contact discharge 9

PPP Peak pulse power (8/20 µs) 300 W

Tstg Storage temperature range - 55 to + 150 °C

Tj Maximum junction temperature 150 °C

TL Maximum lead temperature for soldering during 10s 260 °C

Top Operating temperature range - 40 to + 125 °C

note 1: Evolution of functional parameters is given by curves.

ELECTRICAL CHARACTERISTICS (Tamb = 25°C)

Symbol Parameter I
IF
VRM Stand-off voltage
VBR Breakdown voltage
VCL Clamping voltage VBR

IRM Leakage current V RM VF

V
IPP Peak pulse current I RM

αT Voltage temperature coefficient

C Capacitance
Rd Dynamic resistance Slope: 1
Rd I PP
VF Forward voltage drop

Types VBR @ IR IRM @ VRM Rd αT C VF @ IF

min. max. max. typ. max. typ. max.
note 1 note 2 0V bias
µA mΩ
-4
V V mA V 10 /⊃C pF V mA

ESDA5V3L 5.3 5.9 1 2 3 280 5 220 1.25 200

ESDA6V1L 6.1 7.2 1 20 5.25 350 6 140 1.25 200

ESDA14V2L 14.2 15.8 1 5 12 650 10 90 1.25 200

ESDA25L 25 30 1 1 24 1000 10 50 1.2 10

note 1 : Square pulse Ipp = 15A, tp=2.5µs.
note 2 : ∆ VBR = αT* (Tamb -25°C) * VBR (25°C)

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 ESDAxxL
CALCULATION OF THE CLAMPING VOLTAGE
USE OF THE DYNAMIC RESISTANCE
The ESDA family has been designed to clamp fast As the value of the dynamic resistance remains
spikes like ESD. Generally the PCB designers stable for a surge duration lower than 20µs, the
need to calculate easily the clamping voltage VCL. 2.5µs rectangular surge is well adapted. In
This is why we give the dynamic resistance in addition both rise and fall times are optimized to
addition to the classical parameters. The voltage avoid any parasitic phenomenon during the
across the protection cell can be calculated with measurement of Rd.
the following formula:
VCL = VBR + Rd IPP

Where Ipp is the peak current through the ESDA cell.

DYNAMIC RESISTANCE MEASUREMENT

The short duration of the ESD has led us to prefer
a more adapted test wave, as below defined, to the
classical 8/20µs and 10/1000µs surges.

I
Ipp

t
2µs

tp = 2.5µs

2.5µs duration measurement wave.

3/6
ESDAxxL

Fig. 1: Peak power dissipation versus initial junc- Fig. 2: Peak pulse power versus exponential
tion temperature. pulse duration (Tj initial = 25 °C).

Ppp[Tj initial]/Ppp[Tj initial=25°C] Ppp(W)

1.1 3000
1.0
0.9 1000
0.8
0.7
0.6
0.5
100
0.4
0.3
0.2
0.1 Tj initial(°C) tp(µs)
0.0 10
0 25 50 75 100 125 150 1 10 100

Fig. 3: Clamping voltage versus peak pulse cur- Fig. 4: Capacitance versus reverse applied volt-
rent (Tj initial = 25 °C). age (typical values).
Rectangular waveform tp = 2.5 µs.

Ipp(A) C(pF)
50.0 200
ESDA5V3L
ESDA6V1L ESDA14V2L F=1MHz
ESDA25L ESDA5V3L
Vosc=30mV

10.0 100
ESDA6V1L

50
ESDA14V2L
1.0

tp=2.5µs
20
ESDA25L
Vcl(V) VR(V)
0.1 10
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 1 2 5 10 20 50

Fig. 5: Relative variation of leakage current versus Fig. 6: Peak forward voltage drop versus peak for-
junction temperature (typical values). ward current (typical values).

IR[Tj] / IR[Tj=25°C] IFM(A)

200 5.00 ESDA5V3L
ESDA6V1L Tj=25°C
100 & ESDA14V2L
ESDA14V2L
1.00 ESDA6V1L

ESDA25L ESDA25L

10
0.10

Tj(°C) ESDA5V3L

VFM(V)
1 0.01
25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

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 ESDAxxL
1. ESD protection by the ESDAxxL the transient rises above the operating voltage of
Electrostatic discharge (ESD) is a major cause of the device, the TVS array becomes a low
failure in electronic systems. impedance path diverting the transient current to
ground.
Transient Voltage Suppressors (TVS) are an ideal
choice for ESD protection. They are capable of The ESDAxxL array is the ideal board level
clamping the incoming transient to a low enough protection of ESD sensitive semiconductor
level such that damage to the protected components.
semiconductor is prevented. The tiny SOT23 package allows design flexibility in
Surface mount TVS arrays offer the best choice for the design of high density boards where the space
minimal lead inductance. saving is at a premium. This enables to shorten the
routing and contributes to hardening againt ESD.
They serve as parallel protection elements,
connected between the signal line to ground. As

I/O
I/O
I/O

I/O

ESD
sensitive
device

GND
2 * ESDAXXL

2. Circuit Board Layout

Circuit board layout is a critical design step in the
suppression of ESD induced transients. The n All conductive loops, including power and
following guidelines are recommended : ground loops should be minimized
n The ESDAxxL should be placed as close as pos- n The ESD transient return path to ground should
sible to the input terminals or connectors. be kept as short as possible.
n The path length between the ESD suppressor n Ground planes should be used whenever possi-
and the protected line should be minimized ble.

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ESDAxxL
ORDER CODE

ESDA 6V1 L

ESD ARRAY PACKAGE : SOT23 PLASTIC

VBR min

PACKAGE MECHANICAL DATA

SOT23 (Plastic)
A
E DIMENSIONS
REF. Millimeters Inches
Min. Max. Min. Max.
e
e1 D
A 0.89 1.4 0.035 0.055
B
A1 0 0.1 0 0.004
B 0.3 0.51 0.012 0.02
S
c 0.085 0.18 0.003 0.007
A1
D 2.75 3.04 0.108 0.12
e 0.85 1.05 0.033 0.041
L
e1 1.7 2.1 0.067 0.083
H E 1.2 1.6 0.047 0.063
H 2.1 2.75 0.083 0.108
L 0.6 typ. 0.024 typ.
c
S 0.35 0.65 0.014 0.026

FOOT PRINT (in millimeters) MARKING

0.9 0.9
0.035 0.035
TYPE MARKING
0.043
1.1

ESDA5V3L EL53
1.9
0.075 ESDA6V1L EL61
2.35
0.92

mm
1.45
0.037
inch
ESDA14V2L EL15
ESDA25L EL25
0.043
1.1

0.9
0.035
Packaging: Standard packaging is tape and reel.

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use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied.
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proval of STMicroelectronics.
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