Scan Insertion Lab Observations

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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS


Test Case 9: -

Problem Definition: - Design has 1 clock domain, insert 2 scan chains for design containing

2 memories but no memory Bist or collar around the memory Inputs: -

  Synthesis Netlist
  Library Model
 Dofile commands
Outputs: -

  Scan inserted Netlist


  ATPG Dofile
  ATPG Testproc
 Scan Def
What is issue?
Design has S7 violations , design has undefined modules
How resolved?
Set test logic –set on –reset on –clock on =>dofile command adds required mux and
inverter gates to clear DRC violations
Add black boxes –modules sp_256x128_4we 0
Add black boxes –modules dp_256x21_2we_m4 0
Observations: -
1) Write block diagram with all DFT inputs?

Clk
Input Scan Channel
Top Design: icache
Output Scan channel
Scan_En

2) How many clock domains?

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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Clk

3) How many resets? Ans.


There is no reset pin

4) Number of scan
chains
2 scan chain

5) Clock mixing or not clock mixing?


Not clock mixing

6) How many Lockup-latches are added during scan insertion?


No lockup latches are added during scan insertion.

7) Is it top-down or bottom up approach?


Top-down approach

8) How many terminal lockup latches are


added? Zero

9) Number of scan flops and non-scan flops in the


design?. 77 scannable flops.

10) Chain length?


chain length 1 39.
chain length 2 38

11) Number of DRC violations?


7 S1, 694 FN1, 5 FP13 violations

12) Write diagram with issues?

13) Write diagram with solution?

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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

14) Log file: - please note your observations from the log file
Top module is icache
Number of shift registers =0
Number of new Pins inserted= 5 ( scan_in1, scan_in2, scan_en, scan_out1, scan_out2)

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