Tetramax Lab 1: Automatic Test Pattern Generation (ATPG) : Computer-Aided VLSI System Design

NTUEE GIEE
Computer-Aided VLSI System Design

Tetramax Lab 1: Automatic Test Pattern Generation (ATPG)
Objectives:
In this lab, you will learn:
1. How to generate single stuck-at fault !!"# test $atterns for our si%$le &'U
Copy Files from CSDA Directory
1. co$y all the files into your work (irectory,
cp R ~cvsd/06F/Tetramax/Lab1 .
). check if you ha*e these files
Filename Description
Lab1_alu_dft.v gate le*el netlist with scan inserte(# for the si%$le &'U
Lab1_alu_dft.spf !TI' test $rotocol file generate( by +ft ,o%$iler#
TmaxLab1.script scri$ts to run Tetra%a-
.. ,heck the contents of these files.
Invo!e etr"m"#
To in*oke Tetra%a-, first inclu(e the following , shell scri$t
source /usr/cad/synopsys/CIC/tmax.csh
&n( then, you can (o either one
tmax no!u" co%%an( %o(e#
tmax # GUI %o(e#
In this 'ab, we will use the co%%an( %o(e. /ou are welco%e to try the GUI
%o(e. In the GUI %o(e, you can ty$e in your co%%an(s in the co%%an( line,
locate( at the botto% of the win(ow.
$e"d Input Files
0ea( in your (esign an( ,I, 1..2 library both in 3erilog for%at#
read net$"st
/home/ra"d1%1/c"c/C&'(01)%*+C%,rt"san/CIC/-er"$o!/umc1).v
read net$"st Lab1%a$u%d.t.v
NOTE: Unlike the (esign co%$iler, Tetra%a- (oes not take the library in .(b
for%at. Instea(, Tetra%a- rea(s library in 3erilog for%at.
S%& ' (uild )odel
1. This ste$ buil(s a %o(el of your (esign for &T4G.
NTU GIEE ,o%$uter &i(e( !yste% +esign 156
NTUEE GIEE
run bu"$d%mode$ ,L*
Question: How %any *iolations (o you see7 8888
). To $robe further for the *iolations, ty$e
report v"o$at"ons a$$
E-a%ine these *iolations,
Question: 9hat causes these *iolations7 8888888888888888888888888888
:ne *iolation ;< un(ri*en %o(ule out$ut $in# was cause( by an un(ers$ecifie( U+4
$roble% in the library. !ince we (o not use this U+4, this $roble% we can ignore.
The other two *iolations
Un(ri*en %o(ule out$ut $in &'U8+9118a((sub8=815,: #. ;<-1#
9arning: Unconnecte( %o(ule in$ut $in &'U8+9118a((sub8=815,I #. ;=-1#
are cause( by the (esignware. The carry out$ut $in of the a((er (oes not connect to
any out$ut $in. This is because we (o not use the carry out of that a((er. The carry
in$ut is tie( to logic >ero.
:ther errors are internal errors:
Unconnecte( %o(ule internal net !+""0?15(!N #. ;11-1#
Unconnecte( %o(ule internal net !+""0?15!an(0an(!E #. ;11-)#
Unconnecte( %o(ule internal net !+""0?15!an(0an(!Eb #. ;11-.#
Unconnecte( %o(ule internal net !+""0?15flag #. ;11-6#
9e assu%e that we alrea(y fin( out those *iolations will not har% us. 'et@s %o*e on
to ne-t ste$s.
). To tell Tetra%a- so%e infor%ation about our scan chain, ty$e
add c$oc/ 0 c$/
add scan enab$e 1 test%se
S%& * $un D$C
This ste$ run (esign rule checking. 4lease ty$e,
run drc Lab1%a$u%d.t.sp.
The s$f file is fro% our (ft co%$iler. It tells the &T4G how to o$erate the circuit
in test %o(e.
Question: +oes our (esign $ass all rules7 888888888
NTU GIEE ,o%$uter &i(e( !yste% +esign )56
NTUEE GIEE
S%& + $un A&,
1. In this ste$, you can s$ecify your reAuire%ents for &T4G, such as run ti%e,
co*erage, an( so on. ;ecause our (esign is *ery si%$le, we (o not nee( to s$ecify
%any things here. Bust ty$e.
set atp! mer!e med"um
). !$ecify fault %o(el
set .au$ts mode$ stuc/
.. InCect all faults an( start &T4G. &n( start running.
add .au$ts a$$
run%atp! auto
Question: How %any total faults (o we ha*e7 8888888888888
S%& - $evie. $esults
To get a su%%ary of your &T4G results, ty$e
report%summar"es
To get a list of faults, ty$e
report .au$ts a$$
Question: How %any faults are (etecte(7 9hat is the fault co*erage7 88888
How %any test $atterns ha*e we got7 8888888888
Question: 9hich faults# are not (etecte( 7 88888888 (o you know why7
88888888888
+I (etection i%$lie(# an( +! (etecte( by si%ulation# are (etecte( faults. N:
are un(etecte( faults because the fault is not obser*able.
to know the co%%an( usage, you can ty$e
he$p report%.au$t in the co%%an( %o(e#
to get %ore (etaile( infor%ation, ty$e
man report%.au$t in GUI %o(e#
S%& / St"tic Compression
To further co%$ress the $atterns, ty$e
run pattern%compress"on 00
report%summar"es
NTU GIEE ,o%$uter &i(e( !yste% +esign .56
NTUEE GIEE
Question: How %any $atterns (o you ha*e now7 88888888 Is it shorter7
S%& 0 S"ve &"tterns
1. To see your $atterns, ty$e
report patterns a$$
). !a*e your $atterns into files. There are %any for%ats su$$orte( by tetra%a-.
9G' 9a*efor% Generation 'anguage# an( !TI' !tan(ar( Test Interface 'anguage#
are two of the $o$ular for%ats. +e$en(s on the test eAui$%ent you use, you can
choose other (ifferent for%ats.
1r"te pattern Lab1%a$u%,T23.1!$ .ormat 43L
1r"te pattern Lab1%a$u%,T23.st"$ .ormat 5TIL
.. &lthough &T4G shoul( gi*e us DcorrectE $atterns, it is always goo( to *erify
the $atterns. !a*e $atterns in 3erilog for%at so that you can *erify your $atterns
using 3erilog si%ulator.
1r"te pattern Lab1%a$u%,T23%tb.v .ormat ver"$o!
Question: How %any files (o you get by ty$ing the last co%%an(7 8888888
Try to run 3erilog si%ulations an( see if you get correct results.
Congr"tul"tions1 2ou "re done3
9hat we ha*e (one is in the file Tmax.script.
%4D of LA(
,reator:
1
st
E(ition: ,hien-Fo 'i, )111
)
n(
E(ition: /u-'in ,hang, )116
NTU GIEE ,o%$uter &i(e( !yste% +esign 656

Tetramax Lab 1: Automatic Test Pattern Generation (ATPG) : Computer-Aided VLSI System Design

Uploaded by

Copyright:

Available Formats

Tetramax Lab 1: Automatic Test Pattern Generation (ATPG) : Computer-Aided VLSI System Design

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Tetramax Lab 1: Automatic Test Pattern Generation (ATPG) : Computer-Aided VLSI System Design

Uploaded by

Copyright:

Available Formats

NTUEE GIEE

Computer-Aided VLSI System Design

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.