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    Kilaru Jayasri: Career Objective

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    Jaya Sri
    Kilaru Jayasri is seeking a career opportunity to utilize her technical skills and experience in electronics and communication engineering. She has experience designing IP blocks using Verilog, including designing I2C and APB protocols. She is proficient in Verilog, System Verilog, and C programming. She completed her BTech in ECE from KKR and KSR Institute of Technology and Sciences in 2018.

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    Kilaru Jayasri: Career Objective

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    Jaya Sri
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    Kilaru Jayasri is seeking a career opportunity to utilize her technical skills and experience in electronics and communication engineering. She has experience designing IP blocks using Verilog, including designing I2C and APB protocols. She is proficient in Verilog, System Verilog, and C programming. She completed her BTech in ECE from KKR and KSR Institute of Technology and Sciences in 2018.

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    Jaya Software Resume

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    Kilaru Jayasri is seeking a career opportunity to utilize her technical skills and experience in electronics and communication engineering. She has experience designing IP blocks using Verilog, including designing I2C and APB protocols. She is proficient in Verilog, System Verilog, and C programming. She completed her BTech in ECE from KKR and KSR Institute of Technology and Sciences in 2018.

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    43 views2 pages

    Kilaru Jayasri: Career Objective

    Uploaded by

    Jaya Sri
    Kilaru Jayasri is seeking a career opportunity to utilize her technical skills and experience in electronics and communication engineering. She has experience designing IP blocks using Verilog, including designing I2C and APB protocols. She is proficient in Verilog, System Verilog, and C programming. She completed her BTech in ECE from KKR and KSR Institute of Technology and Sciences in 2018.

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    jayasri.2154@gmail.

    com
    +918143347744

    KILARU JAYASRI

    CAREER Strive for excellence and to be a part of an organization in which I


    OBJECTIVE can utilize my technical skills, experience and enhance my
    knowledge that will help the company to meet its goals and
    objectives.
    PROFESSIONAL  Design Intern in the field of VLSI with 3months of experience.
    SUMMARY  Hands on Experience in Verilog.
     Good understanding of IP level Test bench Architecture
     Fair understanding of protocols like I2C, APB, AHB Lite.
     Familiar with concept of C.
     Specialties: Basics of System Verilog, Verilog, Xilinx 14.7 ISE.

    EDUCATION KKR AND KSR INSTUTE OF TECHNOLOGY AND


    SCIENCES, GUNTUR—B.TECH
    Completed Bachelors of Technology in Electronics And
    Communication Engineering with 72.3%in 2018.
    NARAYANA JR.COLLEGE COURSE (MPC)
    Completed (MPC) education with 89.2% in 2014.
    Z.P.H.S —SANGAMJAGARLAMUDI—SSC
    Completed Board of Secondary education with 87% in 2012.
    PROJECTS DESIGN OF I2C PROTOCOL USING VERILOG
    Organization : Nano NSRC, Hyderabad.
    Profile : Design Intern
    Project description: I2C is serial communication protocol for two –
    wire interface to connect low-speed devices like microcontrollers,
    EEPROMs, A/D and D/A converters, I/O interfaces and other
    similar peripherals in embedded systems.I2C (Inter Integrated
    Circuit) is an interface that facilitates the transfer of synchronous
    serial data. I2C (Inter Integrated Circuit) is a synchronous serial data
    link that operates in half duplex mode. It communicates in
    master/slave mode where the master device initiates the data frame.
    Multiple slave devices are allowed with individual slave select line
    (SS).
    Role Description: Individually performed designing by applying
    different stimuli from test bench and observed output
    Tools used : Xilinx 14.7 ISE.
    Languages used: Verilog.
    DESIGN OF APB PROTOCOL AT IP LEVEL
    Organization : Nano NSRC, Hyderabad.
    Project description: APB (Advanced Peripheral Bus) is a part of
    AMBA3 family. It provides a low cost interface that is optimized for
    minimal power consumption and reduced interface complexity. It
    interfaces any peripherals that are low-bandwidth and do not require
    high performance of a pipelined bus interface. APB has unpipelined
    protocol. All signal transitions are only related to the rising edge of
    the clock to enable the integration of APB peripherals easily into any
    design flow. Every transfer takes at least two clock cycles.
    Role Description: Individually performed designing by applying
    different stimuli from test bench and observed output.
    Tools used : Xilinx 14.7 ISE.
    Languages used: Verilog
    ACADEMIC 1. Fingerprint based vehicle starter system Using GSM.
    PROJECTS 2. Implementation of full adder, full subtractor by using
    reversible gates.
    SKILLS &  EDA TOOLS: Xilinx 14.7 ISE, MATLAB.
    ABILITIES  HVLS, HDLS & METHODOLOGIES: Verilog, Basics of
    System Verilog.
     PROGRAMMING & SCRIPTING LANGUAGES: C,
    Basics of MATLAB.
     PLATFORMS: Windows7, 8, 8.1, 10, Fedora, Zorin ,
    Ubuntu.

    CO CURRICULAR  Attended 3-day workshop on "PCB DESIGNING" conducted


    ACTIVITIES at KITS GUNTUR by "SKY LABS".
     Attended INSPIRE CAMP held at RVR&JC College Guntur.
     Worked as volunteer at KITS GUNTUR.
     I got a prize for paper presentation-2018
    DECLARATION I hereby declare that the information given here with is correct to
    best of my Knowledge and I will responsible for any
    discrepancy.

    DATE: K.JAYASRI

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