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    Chandan Kumar Challagundla: Contact Details Objective

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    Chandan Kumar Challagundla is seeking a career where he can utilize his skills in organizations and learn new skills. He has an M.Tech from NIT Durgapur and a B.Tech from JNTUA College of Engineering. He has work experience as an intern at NXP Semiconductors and Amararaja Electronics. His areas of interest include RTL design, static timing analysis, digital ASIC flow, FPGA design, and analog design. He is proficient in Verilog, Python, Unix, C and has exposure to tools like Vivado, VCS, Xcelium, QuestaSim, and Virtuoso.

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    Chandan Kumar Challagundla: Contact Details Objective

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    Chandan Kumar Challagundla is seeking a career where he can utilize his skills in organizations and learn new skills. He has an M.Tech from NIT Durgapur and a B.Tech from JNTUA College of Engineering. He has work experience as an intern at NXP Semiconductors and Amararaja Electronics. His areas of interest include RTL design, static timing analysis, digital ASIC flow, FPGA design, and analog design. He is proficient in Verilog, Python, Unix, C and has exposure to tools like Vivado, VCS, Xcelium, QuestaSim, and Virtuoso.

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    Chandan Kumar Challagundla is seeking a career where he can utilize his skills in organizations and learn new skills. He has an M.Tech from NIT Durgapur and a B.Tech from JNTUA College of Engineering. He has work experience as an intern at NXP Semiconductors and Amararaja Electronics. His areas of interest include RTL design, static timing analysis, digital ASIC flow, FPGA design, and analog design. He is proficient in Verilog, Python, Unix, C and has exposure to tools like Vivado, VCS, Xcelium, QuestaSim, and Virtuoso.

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    Download as pdf or txt
    53 views2 pages

    Chandan Kumar Challagundla: Contact Details Objective

    Uploaded by

    chimp
    Chandan Kumar Challagundla is seeking a career where he can utilize his skills in organizations and learn new skills. He has an M.Tech from NIT Durgapur and a B.Tech from JNTUA College of Engineering. He has work experience as an intern at NXP Semiconductors and Amararaja Electronics. His areas of interest include RTL design, static timing analysis, digital ASIC flow, FPGA design, and analog design. He is proficient in Verilog, Python, Unix, C and has exposure to tools like Vivado, VCS, Xcelium, QuestaSim, and Virtuoso.

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    of 2

    CHANDAN KUMAR CHALLAGUNDLA

    CONTACT DETAILS OBJECTIVE


    To pursue my career in an organization where I can utilize my
    5-63, Near New SBI Bank,
    acquired skills and learn new skills for mutual growth and success.
    Puthalapattu, Chittoor-517124

    +91 9642332729 ACADEMICS


    M.Tech - NIT Durgapur , WB (2019-21)
    chandan.challa4@gmail.com VLSI and Microelectronics with CGPA of 8.79

    https://www.linkedin.com/in/chandan406/ B.Tech – JNTUA College of Engineering Plvd, AP (2015-19)


    Electronics and Communication with CGPA of 8.45
    WORK EXPERIENCES
    INTERMEDIATE –Sri Chaitanya Boys Jr College, AP (2013-15)
    Class 12th (BIEAP) with percentage of 95
    NXP Semiconductors
    Role - Student Intern Technical School – Mangal Vidyalayam (2013)
    Duration -11 months (Aug 2020 – June 2021) Class 10th (SSC) with GPA of 9.7
    Location - Bangalore, Karnataka
    PROJECTS
    Reference - Manikandan Panchapakesan
    Amararaja Electronics Pvt Ltd 1.Project Title : IP-XACT Based Design Automation for
    AMS IP’s [M.Tech Thesis]
    Role - Intern in PCB design
    Duration -3 months (May 2017 – July 2017) Organisation/Institute : NXP Semiconductors / NIT Durgapur
    Location - Chittoor, A.P Description : To Integrate the Analog and Digital IP’s in an AMS IP
    we have created the architecture view and IP package for digital and
    AREA OF INTEREST analog IP’s respectively. We designed the IP package using verilog
    and automated the generation of package using Python Automation
    RTL Design and Integration language.
    Static Timing Analysis Tools & Programming : Magillem, Cadence Xcelium, Python
    Digital ASIC Flow Automation
    FPGA Design Flow Challenges : During generation of IP, as Registers and their
    Analog design and Layout properties are very huge. It is very hard to check all the properties
    RTL Formal Verification manually. So we created a python script to verify the properties of
    Registers before generation of IP.
    VLSI EDA EXPOSURE
    Xilinx Vivado (RTL Design) Fast_to_Slow CDC analysis on
    2. Project title :
    Synopsys VCS (RTL Simulation) complex HDL Designs
    Cadence Xcelium (RTL Simulation) Organisation / Institute : NXP Semiconductors / NIT Durgapur
    MG QuestaSim (RTL Formal Verification)
    Description : In this project, found the fast to slow Clock Domain
    Magillem (RTL Integration)
    Crossing Bugs in the Design. checked the probability of Data loss in
    Cadence Virtuoso (Schematic & Layout)
    the design and made the data stable till 1.5T so that data gets
    captured in the destination Domain.
    Tools : MG QuestaSim
    3.Project Title : Design of Traffic light controller Using
    PROGRAMMING / OS
    FSM and Implemented over FPGA
    Verilog HDL
    Python Automation. Institute : NIT Durgapur
    Tool Command Language (TCL) Description : The traffic light control system for 4-way intersection
    Unix of 2-lane roads using Moore Machine with minimum number of
    C Programming states which provides less traffic congestion. It consists of 8 FSM
    CERTIFICATIONS states.
    NPTEL : Tools & Programming : Xilinx Vivado, Basys-3 FPGA board and
    Verilog HDL
    Hardware modelling using Verilog
    Digital IC design 4.Project Title : Design of Telescopic Op-Amp
    Verilog HDL
    Institute : . NIT Durgapur
    CADENCE :
    Description : Designed Cascode differential amplifier with Cascode
    Basic static timing analysis
    pmos load to increase the gain in UMC 180 nm Technology. Observed
    RTL to GDS II
    high gain compared to single stage operational amplifier. Veified
    UDEMY : Phase Margin , Gain Margin, CMRR, slew rate.
    Tools & Technology : Cadence Virtuoso,UMC 180 nm
    VSD - TCL programming
    Challenges : By using this we got some small loss of vt in gain, we
    ACHIEVEMENTS used wide swing current mirror circuit to rectify the loss caused by
    normal two stage operational amplifier.
    Secured 4893 rank and 507 score in GATE
    2019. 5.Project Title : Implementation and analysis of

    Got Merit scholarship during B.Tech.


    reference voltage generator in highly efficient
    power amplifiers [B.Tech Thesis]
    ECHIP-Student Coordinator (2018-19). Institute : JNTUA college of Engineering Pulivendula
    Conducted various technical related activities.
    Description : In this project we designed a reference voltage
    .
    Stood First position in Innovative Quiz and generator block using basic opamp and found the rise time , fall
    Group Talk at college level. time , delay, power

    STRENGTHS Tools & Technology : Cadence virtuoso , gpdk 180

    Quick learner
    6.Project Title : Design of 32-bit Floating Point
    Team Player
    Problem Solving Arithmetic unit Using Verilog HDL
    Self-Motivated
    Institute : JNTUA college of Engineering Pulivendula
    Description : A 32-bit floating point arithmetic unit is designed
    PERSONAL PROFILE using VHDL and later modified using Verilog HDL.
    Tools & Programming : Xilinx Vivado , Verilog HDL
    Date of Birth: 01/06/1998
    Father’s Name: C . Bhaskar
    Marital Status: Single DECLARATION
    Languages Known: English, Hindi, Telugu
    I hereby declare that the above-mentioned particulars are true
    to the best of my knowledge.
    [ C . CHANDAN KUMAR ]

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