Dual Synchronous Buck Pseudo Fixed Frequency Power Supply Controller
Dual Synchronous Buck Pseudo Fixed Frequency Power Supply Controller
Dual Synchronous Buck Pseudo Fixed Frequency Power Supply Controller
D1
R1 R2 U1 SC1485 C1 0.1uF
22 7
RTON1 10R EN/PSV1 BST1 Q1 C2
23 6 10uF
TON1 DH1
VOUT1 24 5
VOUT1 LX1 L1
R3 R4
VOUT1
25 4
VCCA1 ILIM1 C3
R5 +
26 3
FB1 VDDP1 Q2 R6 0R
27 2
PGOOD PGD1 DL1 VSSA1
C4
R7 28 1
C5 C6 VSSA1 PGND1 1uF
1nF 1uF
VSSA1
VBAT 5VSUS VBAT
5VSUS
D2
R8 R9 C7 0.1uF
8 21
RTON2 10R EN/PSV2 BST2 Q3 C8
9 20 10uF
TON2 DH2
VOUT2 10 19
VOUT2 LX2 L2
R10 R11
VOUT2
11 18
VCCA2 ILIM2 C9
R12 +
12 17
FB2 VDDP2 Q4 R13 0R
13 16
PGOOD PGD2 DL2 VSSA2
C10
R14 14 15
C11 C12 VSSA2 PGND2 1uF
1nF 1uF
VSSA2
POWER MANAGEMENT
Absolute Maximum Ratings(1)
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may
affect device reliability.
Notes:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(2) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.
Electrical Characteristics
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2 = VDDP2 = 5V, VOUT1 = VOUT2 =1.25V, RTON1 = RTON2 = 1MΩ
Input Supplies
VCCA1, VCCA2 Operating Current FB > regulation point, ILOAD = 0A 700 1100 µA
V C C A 1, V C C A 2 5 10 µA
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Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2 = VDDP2 = 5V, VOUT1 = VOUT2 =1.25V, RTON1 = RTON2 = 1MΩ
Controller
Over-Current Sensing
PSAVE
Fault Protection
Output Under-Voltage Fault With respect to internal ref. -30 -40 -25 %
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Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2 = VDDP2 = 5V, VOUT1 = VOUT2 =1.25V, RTON1 = RTON2 = 1MΩ
Inputs/Outputs
Soft Start
Gate Drivers
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Pin Configuration Ordering Information
Device Package(1)
SC1485ITSTR TSSOP-28
SC1485ITSTRT(2) TSSOP-28
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE, RoHS
and J-STD-020B compliant.
TSSOP-28
Pin Descriptions
Pin # Pin Name Pin Function
3 VD D P1 +5V supply voltage input for the gate drivers. Decouple this pin with a 1uF ceramic capacitor to
PGND1.
4 ILIM1 Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for
resistor sensing through a threshold sensing resistor.
5 LX 1 Phase node (junction of top and bottom MOSFETs and the output inductor) connection.
6 DH1 Gate drive output for the high side MOSFET switch.
7 BST1 Boost capacitor connection for the high side gate drive.
8 EN/PSV2 Enable/Power Save input. Pull down to VSSA2 to shut down OUT2. Pull up to enable OUT2 and
activate PSAVE mode. Float to enable OUT2 and activate continuous conduction mode (CCM). If
floated, bypass to VSSA2 with a 10nF ceramic capacitor.
9 TON2 This pin is used to sense VBAT through a pullup resistor, RTON2, and to set the top MOSFET on-
time. Bypass this pin with a 1nF ceramic capacitor to VSSA2.
10 VOUT2 Output voltage sense input for output 2. Connect to the output at the load.
11 VC C A2 Supply voltage input for the analog supply. Use a 10 Ohm / 1µF RC filter from 5VSUS to VSSA2.
12 FB 2 Feedback input. Connect to a resistor divider located at the IC from VOUT2 to VSSA2 to set the
output voltage from 0.5V to VCCA2.
13 PGD2 Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles)
following power up.
14 VSSA2 Ground reference for analog circuitry. Connect to PGND2 at the bottom of the output capacitor.
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Pin Descriptions (Cont.)
Pin# Pin Name Pin Function
17 VD D P2 +5V supply voltage input for the gate drivers. Decouple this pin with a 1uF ceramic capacitor to
PGND2.
18 ILIM2 Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for
resistor sensing through a threshold sensing resistor.
19 LX 2 Phase node (junction of top and bottom MOSFETs and the output inductor) connection.
20 DH2 Gate drive output for the high side MOSFET switch.
21 BST2 Boost capacitor connection for the high side gate drive.
22 EN/PSV1 Enable/Power Save input. Pull down to VSSA1 to shut down OUT1. Pull up to enable OUT1 and
activate PSAVE mode. Float to enable OUT1 and activate continuous conduction mode (CCM). If
floated, bypass to VSSA1 with a 10nF ceramic capacitor.
23 TON1 This pin is used to sense VBAT through a pullup resistor, RTON1, and to set the top MOSFET on-
time. Bypass this pin with a 1nF ceramic capacitor to VSSA1.
24 VOUT1 Output voltage sense input for output 1. Connect to the output at the load.
25 VC C A1 Supply voltage input for the analog supply. Use a 10 Ohm / 1µF RC filter from 5VSUS to VSSA1.
26 FB 1 Feedback input. Connect to a resistor divider located at the IC from VOUT1 to VSSA1 to set the
output voltage from 0.5V to VCCA1.
27 PGD1 Power Good open drain NMOS output. Goes high after a fixed clock cycle delay (440 cycles)
following power up.
28 VSSA1 Ground reference for analog circuitry. Connect to PGND1 at the bottom of the output capacitor.
LX
DH
DL
DL
tplhDL tplhDH
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Block Diagram
VCCA1 (25)
POR / SS OT
EN/SPV1 (22)
BST1 (7)
TON1 (23)
TON ON
VOUT1 (24) DH1 (6)
OFF HI
CONTROL
LOGIC
PWM LX1 (5)
TOFF
OC
1.5V REF ISENSE
ZERO I ILIM1 (4)
+
-
VDDP1 (3)
FB1 (26)
X3
DL1 (2)
LO
OV
FAULT
VSSA1 (28) MONITOR UV
REF + 10%
REF - 10%
REF - 30%
VCCA2 (11)
POR / SS OT
EN/SPV2 (8)
BST2 (21)
TON2 (9)
TON ON
VOUT2 (10) DH2 (20)
OFF HI
CONTROL
LOGIC
PWM LX2 (19)
TOFF
OC
1.5V REF ISENSE
ZERO I ILIM2 (18)
+
-
VDDP2 (17)
FB2 (12)
X3
DL2 (16)
LO
OV
FAULT
VSSA2 (14) MONITOR UV
REF + 10%
REF - 10%
REF - 30%
FIGURE 1.
2005 Semtech Corp. 7 www.semtech.com
SC1485
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Applications Information
+5V Bias Supplies This input voltage-proportional current is used to charge
an internal on-time capacitor. The on-time is the time
The SC1485 requires an external +5V bias supply in required for the voltage on this capacitor to charge from
addition to the battery. If stand-alone capability is zero volts to VOUT, thereby making the on-time of the
required, the +5V supply can be generated with an high-side switch directly proportional to output voltage
external linear regulator such as the Semtech LP2951. and inversely proportional to input voltage. This
To avoid interference between outputs, each controller implementation results in a nearly constant switching
has its own ground reference, VSSA, which should be frequency without the need for a clock generator.
tied by a single trace to PGND at the negative terminal of For VOUT < 3.3V:
that controller’s output capacitor (see Layout Guidelines).
V
All external components referenced to VSSA in the t ON = 3.3 x10 −12 • (R TON + 37 x10 3 ) • OUT + 50ns
schematic should be connected to the appropriate VSSA VBAT
trace. The supply decoupling capacitor for controller 1 For 3.3V ≤ VOUT ≤ 5V:
should be tied between VCCA1 and VSSA1. Likewise, the
supply decoupling capacitor for controller 2 should be V
t ON = 0.85 • 3.3 x10 −12 • (R TON + 37 x10 3 ) • OUT + 50ns
tied between VCCA2 and VSSA2. A 10Ω resistor should VBAT
be used to decouple each VCCA supply from the main RTON is a resistor connected from the input supply (VBAT)
VDDP supplies. PGND can then be a separate plane which to the TON pin. Due to the high impedance of this
is not used for routing traces. All PGND connections are resistor, the TON pin should always be bypassed to VSSA
connected directly to the ground plane with special using a 1nF ceramic capacitor.
attention given to avoiding indirect connections which
may create ground loops. As mentioned above, VSSA1 Enable and Powersave
and VSSA2 must be connected to the PGND plane at
the negative terminal of their respective output The EN/PSV pin enables the supply. When EN/PSV is
capacitors only. The VDDP1 and VDDP2 inputs provide tied to VCCA the controller is enabled and power save
power to the upper and lower gate drivers. A decoupling will also be enabled. If PSAVE is enabled, the SC1485
capacitor for each supply is required. No series resistor PSAVE comparator will look for the inductor current to
between VDDP and 5V is required. See layout guidelines cross zero on eight consecutive switching cycles by
for more details. comparing the phase node (LX) to PGND. Once observed,
the controller will enter power save and turn off the low
Pseudo-fixed Frequency Constant On-Time PWM side MOSFET when the current crosses zero. To improve
Controller light-load efficiency and add hysteresis, the on-time is
increased by 50% in power save. The efficiency
The PWM control architecture consists of a constant on- improvement at light-loads more than offsets the
time, pseudo fixed frequency PWM controller (see Figure disadvantage of slightly higher output ripple. If the
1, SC1485 Block Diagram). The output ripple voltage inductor current does not cross zero on any switching
developed across the output filter capacitor’s ESR cycle, the controller will immediately exit power save. Since
provides the PWM ramp signal eliminating the need for a the controller counts zero crossings, the converter can
current sense resistor. The high-side switch on-time is sink current as long as the current does not cross zero
determined by a one-shot whose period is directly on eight consecutive cycles. This allows the output
proportional to output voltage and inversely proportional voltage to recover quickly in response to negative load
to input voltage. A second one-shot sets the minimum steps even when psave is enabled.
off-time which is typically 400ns.
When the EN/PSV pin is tri-stated, an internal pull-up
On-Time One-Shot (tON) will activate the controller and power save will be dis-
abled.
The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input If the EN/PSV pin is pulled low, the related output will be
samples the input voltage and converts it to a current. shut down and tri-stated.
2005 Semtech Corp. 8 www.semtech.com
SC1485
POWER MANAGEMENT
Output Voltage Selection In an extreme over-current situation, the top MOSFET
will never turn back on and eventually the part will latch
The output voltage (OUT2 shown) is set by the feedback off due to output undervoltage (see Output Undervoltage
resistors R9 & R13 of Figure 2 below. The internal Protection).
reference is 1.5V, so the voltage at the feedback pin is
multiplied by three to match the 1.5V reference. The current sensing circuit actually regulates the
Therefore the output can be set to a minimum of 0.5V. inductor valley current (see Figure 3). This means that if
The equation for setting the output voltage is: the current limit is set to 10A, the peak current through
the inductor would be 10A plus the peak-to-peak ripple
R9
VOUT = 1 + • 0.5 current, and the average current through the inductor
R13 would be 10A plus 1/2 the peak-to-peak ripple current.
The equations for setting the valley current and
8 21 calculating the average current through the inductor are
EN/PSV2 BST2
shown below:
9 20
TON2 DH2
VOUT2
VOUT 10 19
VOUT2 LX2
C15 R9
20k0 11
VCCA2 ILIM2
18 IPEAK
INDUCTOR CURRENT
56p 0402
0402
12 17
FB2 VDDP2
ILOAD
13 16
PGD2 DL2
R13 14 15
20k0 VSSA2 PGND2 ILIMIT
0402 U1 SC1485 OUT2
VSSA2
TIME
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The current limit circuitry also protects against negative Switching always starts with DL to charge up the BST
over-current (i.e. when the current is flowing from the capacitor. With the softstart circuit (automatically)
load to PGND through the inductor and bottom MOSFET). enabled, it will progressively limit the output current (by
In this case, when the bottom MOSFET is turned on, the limiting the current out of the ILIM pin) over a
phase node, LX, will be higher than PGND initially. The predetermined time period of 440 switching cycles.
SC1485 monitors the voltage at LX, and if it is greater
than a set threshold voltage of 125mV (nom.) the The ramp occurs in four steps:
bottom MOSFET is turned off. The device then waits for 1) 110 cycles at 25% ILIM with double minimum off-time
approximately 2.5µs and then DL goes high for 300ns (for purposes of the on-time one-shot, there is an
(typ.) once more to sense the current. This repeats until internal positive offset of 120mV to VOUT during this
either the over-current condition goes away or the part period to aid in startup)
latches off due to output overvoltage (see Output 2) 110 cycles at 50% ILIM with normal minimum off-time
Overvoltage Protection). 3) 110 cycles at 75% ILIM with normal minimum off-time
4) 110 cycles at 100% ILIM with normal minimum
Power Good Output off-time.
At this point the output undervoltage and power good
The power good output is an open-drain output and circuitry is enabled. There is 100mV of hysteresis built
requires a pull-up resistor. When the output voltage is into the UVLO circuit and when VCCA falls to 4.1V (nom.)
10% above or below its set voltage, PGD gets pulled low. the output drivers are shut down and tristated.
It is held low until the output voltage returns to within
these tolerances once more. PGD is also held low during MOSFET Gate Drivers
start-up and will not be allowed to transition high until
soft start is over (440 switching cycles) and the output The DH and DL drivers are optimized for driving
reaches 90% of its set voltage. There is a 5µs delay built moderate-sized high-side, and larger low-side power
into the PGD circuitry to prevent false transitions. MOSFETs. An adaptive dead-time circuit monitors the DL
output and prevents the high-side MOSFET from turning
Output Overvoltage Protection on until DL is fully off (below ~1V). Semtech’s
SmartDriver™ FET drive first pulls DH high with a pull-up
When the output exceeds 10% of its set voltage the resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this
low-side MOSFET is latched on. It stays latched on and point, an additional pull-up device is activated, reducing
the controller is latched off until reset (see below). There the resistance to 2Ω (typ.). This negates the need for an
is a 5µs delay built into the OV protection circuit to external gate or boost resistor. The adaptive dead-time
prevent false transitions. circuit also monitors the phase node, LX, to determine
the state of the high side MOSFET, and prevents the low-
Output Undervoltage Protection side MOSFET from turning on until DH is fully off (LX
below ~1V). Be sure to have low resistance and low
When the output is 30% below its set voltage the output inductance between the DH and DL outputs to the gate
is latched in a tri-stated condition. It stays latched and of each MOSFET.
the controller is latched off until reset (see below). There
is a 5µs delay built into the UV protection circuit to Dropout Performance
prevent false transitions. Note: to reset from any fault,
VCCA or EN/PSV must be toggled. The output voltage adjust range for continuous-
conduction operation is limited by the fixed 550ns
POR, UVLO and Softstart (maximum) minimum off-time one-shot. For best dropout
performance, use the slowest on-time setting of 200kHz.
An internal power-on reset (POR) occurs when VCCA When working with low input voltages, the duty-factor
exceeds 3V, starting up the internal biasing. VCCA limit must be calculated using worst-case values for on
undervoltage lockout (UVLO) circuitry inhibits the and off times. The IC duty-factor limitation is given by:
controller until VCCA rises above 4.2V. At this time the t ON( MIN )
UVLO circuitry resets the fault latch and soft start counter, DUTY =
and allows switching to occur if the device is enabled. t ON( MIN ) + t OFF(MAX )
2005 Semtech Corp. 10 www.semtech.com
SC1485
POWER MANAGEMENT
Be sure to include inductor resistance and MOSFET on- The maximum input voltage (VBAT(MAX)) is determined by
state voltage drops when performing worst-case dropout the highest AC adaptor voltage. The minimum input
duty-factor calculations. voltage (V BAT(MIN)) is determined by the lowest battery
voltage after accounting for voltage drops due to
SC1485 System DC Accuracy connectors, fuses and battery selector switches. For the
purposes of this design example we will use a VBAT range
Two IC parameters affect system DC accuracy, the error of 8V to 20V and design OUT2. The design for OUT1
comparator threshold voltage variation and the employs the same technique.
switching frequency variation with line and load. The
error comparator threshold does not drift significantly Four parameters are needed for the output:
with supply and temperature. Thus, the error 1) nominal output voltage, VOUT (we will use 1.2V)
comparator contributes 1% or less to DC system 2) static (or DC) tolerance, TOLST (we will use +/-4%)
inaccuracy. 3) transient tolerance, TOLTR and size of transient (we will
use +/-8% and 6A for purposes of this demonstration).
Board components and layout also influence DC 4) maximum output current, IOUT (we will design for 6A)
accuracy. The use of 1% feedback resistors contribute
1%. If tighter DC accuracy is required use 0.1% Switching frequency determines the trade-off between
feedback resistors. size and efficiency. Increased frequency increases the
switching losses in the MOSFETs, since losses are a
The on pulse in the SC1485 is calculated to give a function of VIN2. Knowing the maximum input voltage and
pseudo fixed frequency. Nevertheless, some frequency budget for MOSFET switches usually dictates where the
variation with line and load can be expected. This design ends up. It is recommended that the two outputs
variation changes the output ripple voltage. Because are designed to operate at frequencies approximately
constant-on regulators regulate to the valley of the 25% apart to avoid any possible interaction. It is also
output ripple, ½ of the output ripple appears as a DC recommended that the higher frequency output is the
regulation error. For example, if the feedback resistors lower output voltage output, since this will tend to have
are chosen to divide down the output by a factor of five, lower output ripple and tighter specifications. The
the valley of the output ripple will be VOUT. For example: default RtON values of 1MΩ and 715kΩ are suggested
if VOUT is 2.5V and the ripple is 50mV with VBAT = 6V, as a starting point, but these are not set in stone. The
then the measured DC output will be 2.525V. If the ripple first thing to do is to calculate the on-time, tON, at VBAT(MIN)
increases to 80mV with VBAT = 25V, then the measured and VBAT(MAX), since this depends only upon VBAT, VOUT and
DC output will be 2.540V. R tON.
The output inductor value may change with current. This For VOUT < 3.3V:
will change the output ripple and thus the DC output
VOUT
voltage. It will not change the frequency. t ON _ VBAT(MIN) = 3.3 • 10 −12 • (R tON + 37 • 103 ) • + 50 • 10 s
−9
V
BAT ( MIN)
Design Procedure From these values of tON we can calculate the nominal
switching frequency as follows:
Prior to designing an output and making component
selections, it is necessary to determine the input voltage VOUT
fSW _ VBAT (MIN ) = Hz
range and the output voltage specifications. For purposes
of demonstrating the procedure the output for the
(VBAT ( MIN ) • t ON _ VBAT ( MIN ) )
POWER MANAGEMENT
From this we can calculate the minimum inductor
VOUT current rating for normal operation:
fSW _ VBAT (MAX ) =
(VBAT(MAX ) • t ON _ VBAT(MAX ) )Hz
IRIPPLE _ VBAT (MAX )
IINDUCTOR (MIN) = IOUT (MAX ) + A (MIN)
tON is generated by a one-shot comparator that samples 2
VBAT via RtON, converting this to a current. This current is
used to charge an internal 3.3pF capacitor to VOUT. The For our example:
equations above reflect this along with any internal
components or delays that influence tON. For our example IINDUCTOR(MIN) = 7.1A(MIN)
we select RtON = 1MΩ:
Next we will calculate the maximum output capacitor
tON_VBAT(MIN) = 563ns and tON_VBAT(MAX) = 255ns equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
fSW_VBAT(MIN) = 266kHz and fSW_VBAT(MAX) = 235kHz allowances. Then the maximum ESR is the smaller of the
calculated static ESR (R ESR_ST(MAX)) and transient ESR
Now that we know tON we can calculate suitable values (R ESR_TR(MAX)):
for the inductor. To do this we select an acceptable
inductor ripple current. The calculations below assume
RESR _ ST (MAX ) =
(ERR ST − ERRDC ) • 2
Ohms
50% of IOUT which will give us a starting place. IRIPPLE _ VBAT (MAX )
t ON _ VBAT (MIN)
L VBAT (MIN) = (VBAT (MIN) − VOUT ) • H Where ERRST is the static output tolerance and ERRDC is
(0.5 • I )OUT
the DC error. The DC error will be 1% plus the tolerance
of the feedback resistors, thus 2% total for 1%
and feedback resistors.
t ON _ VBAT (MAX )
L VBAT (MAX ) = (VBAT (MAX ) − VOUT ) •
For our example:
H
(0.5 • I )OUT
ERRST = 48mV and ERRDC = 24mV, therefore
For our example:
RESR_ST(MAX) = 22mΩ
LVBAT(MIN) = 1.3µH and LVBAT(MAX) = 1.6µH
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We will select a value of 12.5mΩ maximum for our For our example we will use R TOP = 20.0kΩ and
design, which would be achieved by using two 25mΩ RBOT = 14.3kΩ, therefore:
output capacitors in parallel. Note that for constant-on
converters there is a minimum ESR requirement for ZTOP = 6.67kΩ and CTOP = 60pF
stability which can be calculated as follows:
We will select a value of CTOP = 56pF. Calculating the
3 value of VFB based upon the selected CTOP:
RESR (MIN ) =
2 • π • COUT • fSW
This criteria should be checked once the output R BOT
VFB _ VBAT(MIN) = VRIPPLE _ VBAT(MIN) • VP −P
capacitance has been determined. RBOT + 1
1
+ 2 • π • fSW _ VBAT(MIN) • C TOP
R TOp
Now that we know the output ESR we can calculate the
output ripple voltage:
For our example:
VRIPPLE _ VBAT(MAX) = RESR • IRIPPLE _ VBAT(MAX) VP −P
VFB_VBAT(MIN) = 14.8mVP-P - good
and
Next we need to calculate the minimum output
VRIPPLE _ VBAT(MIN) = RESR • IRIPPLE _ VBAT(MIN) VP −P capacitance required to ensure that the output voltage
does not exceed the transient maximum limit, POSLIMTR,
For our example: starting from the actual static maximum, VOUT_ST_POS, when
a load release occurs:
VRIPPLE_VBAT(MAX) = 27mVP-P and VRIPPLE_VBAT(MIN) = 22mVP-P
VOUT _ ST _ POS = VOUT + ERRDC V
Note that in order for the device to regulate in a
controlled manner, the ripple content at the feedback For our example:
pin, VFB, should be approximately 15mVP-P at minimum
V BAT , and worst case no smaller than 10mV P-P . If VOUT_ST_POS = 1.224V
VRIPPLE_VBAT(MIN) is less than 15mVP-P the above component
values should be revisited in order to improve this. Quite
often a small capacitor, CTOP, is required in parallel with POSLIM TR = VOUT • TOL TR V
the top feedback resistor, RTOP, in order to ensure that
V FB is large enough. C TOP should not be greater than Where TOLTR is the transient tolerance. For our example:
100pF. The value of CTOP can be calculated as follows,
where R BOT is the bottom feedback resistor. Firstly POSLIMTR = 1.296V
calculating the value of ZTOP required:
The minimum output capacitance is calculated as
follows:
= BOT • (VRIPPLE _ VBAT (MIN) − 0.015 ) Ohms
R
Z TOP
0.015 2
I
IOUT + RIPPLE _ VBAT (MAX )
Secondly calculating the value of CTOP required to achieve 2
=L•
this:
C OUT (MIN)
( 2
POSLIM TR − VOUT _ ST _ POS
2
F
)
1 1 This calculation assumes the absolute worst case
−
Z TOP R TOP condition of a full-load to no load step transient occurring
C TOP = F
2 • π • fSW _ VBAT (MIN) when the inductor current is at its highest. The
capacitance required for smaller transient steps my be
calculated by substituting the desired current for the IOUT
term.
2005 Semtech Corp. 13 www.semtech.com
SC1485
POWER MANAGEMENT
For our example: Thermal Considerations
The junction temperature of the device may be
COUT(MIN) = 610µF. calculated as follows:
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gives us:
PD = 2 • (5 • 1100 • 10 −6 + 5 • 150 • 10 −6 )
+ 5 • 60 • 10 −9 • 250 • 10 3 + 13 • 1 • 10 −3 • 0.1875
+ 5 • 60 • 10 −9 • 300 • 103 + 13 • 1 • 10 −3 • 0.15
= 0.182 W
and:
TJ = 85 + 0.182 • 84 = 100 °C
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Layout Guidelines
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground references, VSSA1 and VSSA2, should be kept separate from power
ground. All components that are referenced to them should connect to them locally at the chip. VSSA1 and VSSA2
should connect to power ground at their respective output capacitors only.
Feedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives.
Route feedback traces with their respective VSSAs as a differential pair from the output capacitor back to the chip.
Run them in a “quiet layer” if possible.
Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins and connected directly to them on the
same side.
Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling
(including the chip power ground connections). Power components should be placed to minimize loops and reduce
losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use
“minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of
the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical.
Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling
requirement (and to reduce parasitics) if routed on more than one layer
Current sense connections must always be made using Kelvin connections to ensure an accurate signal.
We will examine the SC1485 OUT2 reference design used in the Design Procedure section while explaining the
layout guidelines in more detail, using the same generic components for OUT1.
5VSUS VBAT
VBAT 5VSUS
D1
SOD323
R1 R2 U1 SC1485 C5 0.1uF
10R 22 7 Q2
0402 0402 EN/PSV1 BST1 C6 C1 C2
0603
23 6 2n2/50V 0u1/25V 10u/25V
TON1 DH1 0402 0603 1210
VOUT
VOUT1 24 5
VOUT1 LX1 L1
C7 R4 R5
VOUT1
25 4
0402 VCCA1 ILIM1 C8 C3
0402 0402 + +
26 3 Q1
FB1 VDDP1 R6 0R (1)
7343 7343
27 2
PGOOD PGD1 DL1 0402
C10 VSSA1
R3 28 1
C4 C9 VSSA1 PGND1 1uF
0402 0603
1nF 1uF
0402 0603
VBAT 5VSUS
D2
SOD323
R7 R8 C11 0.1uF
1M 10R 8 21 Q3
0402 0402 EN/PSV2 BST2 IRF7811AV C12 C13 C14
0603
9 20 2n2/50V 0u1/25V 10u/25V
TON2 DH2 0402 0603 1210
VOUT2
VOUT 10 19
VOUT2 LX2 L2 2u2
C15 R9 R10 7k87
VOUT2
20k0 11 18
56p 0402 VCCA2 ILIM2 C16 C17
0402 0402 + +
12 17 Q4
FB2 VDDP2 FDS6676S R12 0R (1) 220u/25m 220u/25m
7343 7343
13 16
PGOOD PGD2 DL2 0402
C20 VSSA2
R13 14 15
C18 20k0 C19 VSSA2 PGND2 1uF
0402 0603
1nF 1uF
0402 0603
N OTES
(1) R 6 and R 12 aid in k eeping VSSA1 and VSSA2 s eparate f rom PGN D ex c ept where des ired in lay out.
VSSA2
POWER MANAGEMENT
The layout can be considered in two parts, the control section referenced to VSSA1/2 and the power section.
Looking at the control section first, locate all components referenced to VSSA1/2 on the schematic and place
these components at the chip. Connect VSSA1 and VSSA2 using either a wide (>0.020”) trace. Very little current
flows in the chip ground therefore large areas of copper are not needed.
5VSUS
VBAT 5VSUS
R1 R2 U1 SC1485
10R 22 7
0402 0402 EN/PSV1 BST1
23 6
TON1 DH1
VOUT
VOUT1 24 5
VOUT1 LX1
C7 R4
25 4
0402 VCCA1 ILIM1
0402
26 3
FB1 VDDP1
27 2
PGOOD PGD1 DL1
C10
R3 28 1
C4 C9 VSSA1 PGND1 1uF
0402 0603
1nF 1uF
0402 0603
VSSA1 5VSUS
VBAT 5VSUS
R7 R8
1M 10R 8 21
0402 0402 EN/PSV2 BST2
9 20
TON2 DH2
VOUT2
VOUT 10 19
VOUT2 LX2
C15 R9
20k0 11 18
56p 0402 VCCA2 ILIM2
0402
12 17
FB2 VDDP2
13 16
PGOOD PGD2 DL2
C20
R13 14 15
C18 20k0 C19 VSSA2 PGND2 1uF
0402 0603
1nF 1uF
0402 0603
VSSA2
POWER MANAGEMENT
In Figure 10, all components referenced to VSSA1 and VSSA2 have been placed and have been connected using
0.020” traces. Note that there are two separate traces, one for VSSA1 and one for VSSA2. Decoupling capacitors
C9 and C19 are as close as possible to their pins, as are VDDP decoupling capacitors C10 and C20. C10 and C20
should connect to the ground plane using two vias each.
POWER MANAGEMENT
VOUT1
VSSA1
U1 SC1485
22 7
EN/PSV1 BST1
23 6
TON1 DH1
VOUT
VOUT1 24 5
VOUT1 LX1
C7 R4
VOUT1
25 4
0402 VCCA1 ILIM1 C8 C3
0402 + +
26 3
FB1 VDDP1 R6 0R (2)
7343 7343
27 2
PGD1 DL1 0402
VSSA1
R3 28 1
VSSA1 PGND1
0402
VSSA1
8 21
EN/PSV2 BST2
9 20
TON2 DH2
VOUT
VOUT2 10 19
VOUT2 LX2
C15 R9
VOUT2
20k0 11 18
56p 0402 VCCA2 ILIM2 C16 C17
0402 + +
12 17
FB2 VDDP2 R12 0R (2) 220u/25m 220u/25m
7343 7343
13 16
PGD2 DL2 0402
VSSA2
R13 14 15
20k0 VSSA2 PGND2
0402
VSSA2
VOUT2
VSSA2
In Figure 11, VOUT1 and VSSA1 are routed as a differential pair from the output capacitors back to the feedback
components and device. Similarly, VOUT2 and VSSA2 are routed as a differential pair from the output capacitors
back to the feedback components and device.
POWER MANAGEMENT
Next, looking at the power section, the schematic in Figure 12 below shows the power section and input loop for
OUT2:
Q3 IRF7811AV
VBAT 8 1
7 D S 2
6 D S 3
5 D S 4
D G L2 2u2
C14 C13 C12
VOUT2
10u/25V 0u1/25V 2n2/50V Q4 FDS6676S C16 C17
1210 0603 0402 4 5 + +
3 G D 6
2 S D 7 R12 0R (2) 220u/25m 220u/25m
1 S D 8 7343 7343
S D
0402
The schematic has been redrawn to emphasize the input loop. The highest di/dts occur in the input loops and thus
these should be kept as small as possible. The input capacitors should be placed with the highest frequency
capacitors closest to the loop to reduce EMI. Use large copper pours to minimize losses and parasitics. Exactly the
same philosophy applies to the OUT1 power section and input loop. Figure 13 below shows an example of the layout
for the power section using these guidelines.
POWER MANAGEMENT
Key points for the power section:
1) there should be a very small input loop, well decoupled.
2) the phase node should be a large copper pour, but compact since this is the noisiest node.
3) input power ground and output power ground should not connect directly, but through the ground planes instead.
4) The two outputs should not share their input capacitors, and these should have separate PWR_SRC and PGND
(component-side) copper pours.
5) The two output inductors should not be placed adjacent to each other to avoid crosstalk.
6) Notice in Figure 13 placement of 0Ω resistor at the bottom of the output capacitor to connect to VSSA1/2 for
each output.
Connecting the control and power sections should be accomplished as follows (see Figure 14 below):
1) Route VSSA1/2 and their related feedback traces as differential pairs routed in a “quiet” layer away from noise
sources.
2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces
with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization,
with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power
ground as its return path. LX is the noisiest node in the circuit, switching between PWR_SRC and ground at high
frequencies, thus should be kept as short as practical. DH has LX as its return path.
3) BST is also a noisy node and should be kept as short as possible.
4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the
ground plane.
5) Locate the current limit sense resistors between the LX and ILIM pins at the device.
U1 SC1485
22 7 Q2
EN/PSV1 BST1
23 6
TON1 DH1
24 5
VOUT1 LX1 L1
R5
25 4
VCCA1 ILIM1
0402
26 3 Q1
FB1 VDDP1
27 2
PGD1 DL1
28 1
VSSA1 PGND1
8 21 Q3
EN/PSV2 BST2 IRF7811AV
9 20
TON2 DH2
10 19
VOUT2 LX2 L2 2u2
R10 7k87
11 18
VCCA2 ILIM2
0402
12 17 Q4
FB2 VDDP2 FDS6676S
13 16
PGD2 DL2
14 15
VSSA2 PGND2
Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node
traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical.
2005 Semtech Corp. 21 www.semtech.com
SC1485
POWER MANAGEMENT
Typical Characteristics
1.2V Efficiency (Power Save Mode) 1.2V Efficiency (Continuous Conduction Mode)
vs. Output Current vs. Input Voltage vs. Output Current vs. Input Voltage
100 100
95 95
VBAT = 8V VBAT = 8V
90 90
85 85
Efficiency (%)
Efficiency (%)
80 80
VBAT = 20V VBAT = 20V
75 75
70 70
65 65
60 60
55 55
50 50
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOUT (A) IOUT (A)
1.2V Output Voltage (Power Save Mode) 1.2V Output Voltage (Continuous Conduction Mode)
vs. Output Current vs. Input Voltage vs. Output Current vs. Input Voltage
1.220 1.220
1.216 1.216
1.212 1.212
1.208 1.208
VBAT = 20V VBAT = 20V
1.204 1.204
VOUT (V)
VOUT (V)
1.200 1.200
1.196 1.196
VBAT = 8V VBAT = 8V
1.192 1.192
1.188 1.188
1.184 1.184
1.180 1.180
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOUT (A) IOUT (A)
1.2V Switching Frequency (Power Save Mode) 1.2V Switching Frequency (Continuous Conduction
vs. Output Current vs. Input Voltage Mode) vs. Output Current vs. Input Voltage
400 400
VBAT = 8V VBAT = 8V
350 350
300 300
Frequency (kHz)
Frequency (kHz)
250 250
VBAT = 20V VBAT = 20V
200 200
150 150
100 100
50 50
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOUT (A) IOUT (A)
POWER MANAGEMENT
Typical Characteristics (Cont.)
Load Transient Response,
Continuous Conduction Mode, 0A to 6A to 0A
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 20V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 40µs/div.
POWER MANAGEMENT
Typical Characteristics (Cont.)
Load Transient Response,
Power Save Mode, 0A to 6A to 0A
Trace 1: 1.2V, 50mV/div., AC coupled
Trace 2: LX, 20V/div
Trace 3: not connected
Trace 4: load current, 5A/div
Timebase: 40µs/div.
POWER MANAGEMENT
Typical Characteristics (Cont.)
Startup (PSV), EN/PSV Going High
POWER MANAGEMENT
Outline Drawing - TSSOP-28
DIMENSIONS
A INCHES MILLIMETERS
e D DIM
MIN NOM MAX MIN NOM MAX
N A - - .047 - - 1.20
A1 .002 - .006 0.05 - 0.15
A2 .031 - .042 0.80 - 1.05
2X E/2 b .007 - .012 0.19 - 0.30
c .003 - .007 0.09 - 0.20
E1 E D .378 .382 .386 9.60 9.70 9.80
PIN 1 E1 .169 .173 .177 4.30 4.40 4.50
INDICATOR E .252 BSC 6.40 BSC
e .026 BSC 0.65 BSC
L .018 .024 .030 0.45 0.60 0.75
ccc C 1 2 3 L1 (.039) (1.0)
2X N/2 TIPS e/2 N 28 28
01 0° - 8° 0° - 8°
B aaa .004 0.10
bbb .004 0.10
ccc .008 0.20
D
aaa C
A2 A
SEATING
PLANE
C A1 H
bxN
bbb C A-B D c
GAGE
PLANE
0.25 L
01
(L1)
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
POWER MANAGEMENT
Land Pattern - TSSOP-28
DIMENSIONS
DIM INCHES MILLIMETERS
C (.222) (5.65)
(C) G Z G .161 4.10
P .026 0.65
X .016 0.40
Y .061 1.55
Y Z .283 7.20
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
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