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SIMULATION AND ANALYSIS OF MASTER SLAVE D FLIP

FLOP

PROJECT REPORT

For The Course

DIGITAL VLSI DESIGN


(EE 619 A)

Under the guidance of


PROF. SHAFI QURESHI
ELECTRICAL ENGINEERING DEPARTMENT
INDIAN INSTITUTE OF TECHNOLOGY (KANPUR)

Made by:
SHWETA KUMARI (18104108)
SHREYA MISHRA (18104106)
Contents
1 Acknowledgment 2

2 Introduction 3

3 Master Slave D Flip Flop 4


3.1 Basic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Gate Level Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Timing and Delay 7

5 Schematic Simulation 8

6 Layout Simulation 11

7 Post Layout Simulation 15

8 Applications 16

9 References 19

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1 Acknowledgment
We are using this opportunity to express our gratitude to everyone who supported us throughout
the course of this Digital VLSI project. We are thankful for their aspiring guidance, invaluably
constructive criticism and friendly advice during the project work.

We are sincerely grateful to them for sharing their truthful and illuminating views on a number
of issues related to the project. I express my warm thanks to, “Dr. S. Qureshi” for his support
and guidance in EE619A Course.

We would also like to thank professor’s TA, “Mr. Dinesh”, without his help we wouldn’t have
been able to complete our project.

Shweta Kumari Shreya Mishra


18104108 18104106
M. Tech EE (MVLSI) M. Tech EE(SPCOMM)
IIT Kanpur IIT Kanpur

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2 Introduction
There can be two different types of memory elements:Latches and Flip-Flops.The basic difference
between them can be described from the following figure:

Figure 1: Block Diagram Of D Flip Flop

A D flip-flop holds the value of a single bit, as the latch, but is not transparent. For standard
D flip-flops, the stored value is updated when a rising edge event occurs at the Clock input.
In this paper we have studied and simulated Master Slave D flipflop. A basic Master Slave D
flipflop is designed by using two gated D-latches with opposite clock signals. The first is called
the master latch, and the second is called slave latch. .The purpose of master-slave flip-flops
is to protect the output of flip flop from inadvertent changes caused by glitches on the input.
Master-slave flip-flops are used in applications where glitches may be prevalent on inputs. The
master-slave configuration has the advantage of being pulse-triggered, making it easier to use in
larger circuits, since the inputs to a flip-flop often depend on the state of its output. We have
implemented our circuit using Mentor Graphics Tool.

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3 Master Slave D Flip Flop
3.1 Basic Block Diagram
This section contains information about the basic functionality of a D flip-flop which will help us
in analyzing Master Slave D Flip-Flop. A D flip-flop holds the value of a single bit, as the latch,
but is not transparent. For standard D flip-flops, the stored value is updated when a rising edge
event occurs at the Clock input. The standard symbol for a D flip-flop is shown in Figure 2.

Figure 2: Block Diagram Of D Flip Flop

A basic Master Slave D flip-flop is designed by using two gated D-latches with opposite clock
signals. The first is called the master latch, and the second is called slave latch. Figure 3 shows
this design. The master latch detects changes in the Data signal at the low clock level, and
propagates the signal to the input of the slave latch. As the clock signal switches to high, the
slave latch propagates this input value to the D flip-flop output Q. If the clock is non-overlapping,
the D flip-flop will be non-transparent, which is required for normal functionality. Master-slave
flip-flops can be constructed to behave as a J-K, R-S, T or D flip-flop.

Figure 3: Master-slave D flip-flop, Master latch to the left, and Slave latch to the right

3.2 Gate Level Implementation


In this section, we will present gate-level implementation of master slave D- Fip Flop. Basically,
we have a cross- coupled NAND structure fed with a clock and D as inputs. In Master-slave

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Figure 4: Master Slave D Flip Flop with NAND Gates

topology, slave structure is fed with inverted clock as shown in the fig.4.
Fig.4 shows negative pulse-triggered master-slave D flipflop. It responds on the negative edge of
the enable input (usually a clock). The circuit consists of two D flip-flops connected together.
When the clock is high, the D input is stored in the first latch, but the second latch cannot
change state. When the clock is low, the first latch’s output is stored in the second latch, but
the first latch cannot change state. The result is that output can only change state when the
clock makes a transition from high to low. Following table explains working of the circuit in the
form a truth table.

Figure 5: Truth Table

Master changes its state when clock is high while the slave changes its state when clock is
low. When the clock is high the master tracks the value of D but since the slave is in inactive
state, Qs also remains unchanged. When the clock signal goes low, the master goes to inactive
state and the slave which is now in active state tracks the value of Qm. While clock is low, Qm
does not change its value. Thus only once during the clock cycle the slave can undergo change
in its value. It can also be observed that only during the transition from high to low, the output
gets change. This transition is referred to as ”negative edge-triggered”
Fig.6 shows the implementation of master-slave D flip-flop with clear input. The circuit is
designed using the truth table given in table.2. When the clr (clear) input goes high, irrespective

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Figure 6: Circuit Diagram with Clear Input

of the inputs D and clock, the output goes low. We have extra control on the value stored in
flip flop using Clear input. Here is the truth table for better understanding how the circuit will
behave with clear as an additional input.

Figure 7: Truth Table with CLR

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4 Timing and Delay
Both master and slave latches have propagation delays which must be considered before im-
plementing them in designs. These delays limit the maximum switching frequency of the clock
signal and input data signal. Different delays for these D flip-flops are described below:

Figure 8: Set-up time, hold time, and propagation delay

• The Setup Time( tsu ) Time that the data inputs (D input) must be valid before the
clock transition (this is, the 0 to 1 transition for a positive edge-triggered register). For
a master-slave D flip-flop, the input signal needs to be available at the slave latche input
before the rising edge of the clock .A violation of the setup time can give incorrect data at
the output, or set the D flip-flop to a metastable state.

• The hold time (thold ) is the time the data input must remain valid after the clock edge.

• Clock to Q delay: Assuming that the set-up and hold-times are met, the data at the
D input is copied to the Q output after a worst-case propagation delay (with reference to
the clock edge) denoted by tc−q .

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5 Schematic Simulation
Schematic of the circuit is made using Mentor Graphics Tool for tsmc 0.18nm libraries. The
schematic diagram of all the components are built using PMOS and NMOS transistors.

• Drain voltage VDD =1.8V

• Total number of transistor is 42,with equal number of NMOS and PMOS

• Length of both type of transistors,L=180nm


W
• L
= 12

• Width of both type of transistors,W=2.16µ m

Figure 9: Schematic Design

Simulation Results:

Figure 10: simulation without CLR

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Figure 11: simulation with CLR input

• We varied our VDD from 1.8V and below, and measured the corresponding power and
delay for each voltage and obtained the following graph.

(a) Delay vs VDD (b) Power vs VDD

Figure 12: Plots of VDD vs Power and Delay

• With the help of above two data set of power and delay,we calculated our average power
delay product PDP=1.067 fJ which varied from 1.096.83 fJ to 1505.5327 fJ on varying
supply voltage.

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SETUP and HOLD TIME

Figure 13: Setup Time:Our calculated setup time is 18.53ns

Figure 14: Hold Time:Our calculated hold time is 1.17166ns

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6 Layout Simulation
The layout of the circuit is shown below. Area occupied by the circuit on chip is about 519.655
µm2

Figure 15: Layout of Master Slave D Flip Flop

After designing the layout we run the DRC check i.e. Design Rule Check. The results are shown
in fig.16. DRC run ensures that the designed layout doesn’t violate any rules set by fabrication
industry. After this, we performed LVS run i.e. Layout versus Schematic. As the name suggests
this step ensure that there are no discrepancies in our schematic and layout. In addition to these
Calibre tool of Mentor Graphics also generate a PEX file i.e. parameter Extraction. This step
keeps an account of parasitic resistances and capacitances of the circuit. PEX file is shown in
fig.18 and fig.19.

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Figure 16: DRC of the design

Figure 17: LVS check of layout

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Figure 18: PEX results.

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Figure 19: PEX results.

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7 Post Layout Simulation
After making the layout circuit has got some additional resistances and capacitances which in-
troduces more delays in our circuit. We can see this effect by doing post layout simulations. For
doing this, first we make symbol of the circuit which is as follows.

Figure 20: Symbol

Now, we will perform similar simulations which we have done while doing schematic analysis.
Timing waveform is as follows.

Figure 21: Timing Diagram without Clear Input

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8 Applications
Data Storage In digital circuits the data is normally stored as a group of bits, represented in
numbers and codes. So it is easy to take data on parallel lines and store the data simultaneously
in a group of flip flops, arranged in a particular order.. Registers are the basic multi – bit data
devices. They are formed by connecting number of D flip – flops such that multiple bits of data
can be stored.

Figure 22: Register

Each D flip – flop is connected with a respective data input. Clock input applied is same to
all the flip – flops so that all of them will store the data simultaneously from their respective D
inputs when a positive edge triggered clock signal is applied.
Data Transfer D flip – flops are also widely used in data transfer. For transferring the data,
D flip – flops are connected to form a shift register. A cascade connection of D flip – flops with
same clock signal will form a shift register. A shift register can shift the data without changing
the sequence of bits. When a clock pulse is applied, the one bit data is shifted or transferred.
Shift registers can store the data temporarily. The 4 bit storage shift register using D flip flop
is shown fig.23.

Shift registers are used in serial to parallel and parallel to serial data conversion. They are
also used as pulse extenders and delay circuits.
Frequency Division Using D Flip Flop Frequency Division circuits are developed by using
D flip flops. This is the most important application of D Flip Flop. In Frequency Division
circuits the state output of the D flip flop (Q’) is connected to the Data input (D) as a closed
feedback loop. Two successive cock pulses will make the flip flop to Toggle, for every two clock

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Figure 23: Shift registers

cycles.
As the name implies, the frequency divider circuits are used to produce the digital signal
output exactly half the input frequency. The frequency divider circuits are generally used in
design of asynchronous counters.

Figure 24: Frequency Divider

Figure 25: Timing diagram of frequency divider

The operation of the circuit is very simple. The incoming data signal is clocked by the clock
input signal. The circuit will perform the division of the input frequency by using the feedback

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loop i.e. connected to the Data input from Q’. The frequency divider circuit divides the input
frequency by 2 for every two clock pulses. Other applications of D flip flop includes Event
detectors and Data synchronizers.

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9 References
• ’DESIGN AND IMPLEMENTATION OF SYNCHRONOUS 4-BIT UP COUNTER US-
ING 180NM CMOS PROCESS TECHNOLOGY’ by Yogita Hiremath,Akalpita L. Kulka-
rni, J. S. Baligar published in IJRET: International Journal of Research in Engineering
and Technology.

• Lecture6: Clocked Elements Computer Systems Laboratory Stanford University;

• ’Digital Integrated Circuits: A design perspective’ by Jan M. Rabaey

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