7.

4 Data Generation and Checking

TBD: Document the 20 PRBS generators and 20 PRBS checkers per channel. This allows
independent control of the 20 data signals in each channel.

7.5 AVMM Master

There is an independent AVMM slave interface present in each of the up to 24 data channels. There is
one AVMM master interface in the MAC. The master takes input from two TDRs in the JTAG TAP
controller:
1. The first is named AIB_AVMM_CTRL. It has fields for controlling functions that are common
to all AVMM accesses including reset, byte enables and a timeout value.
2. The second is named AIB_AVMM_ACCESS. It has fields for controlling individual AVMM
write and read operations.
Control is broken into two TDRs so the bits which do not change frequently do not have to be shifted in
on every, single operation. The JTAG serial interface allows write and read operations to be performed
to any AVMM CSR in the AIB PHY by whatever entity is currently controlling the JTAG test access
port.
There is no support for writing or reading any AVMM CSR register except through the JTAG port.
The AVMM clock is generated in the clock and reset module (see section 7.1, Clock and Reset
Generation).

7.5.1 AIB_AVMM_CTRL TDR

The AVMM reset comes directly out of the AIB_AVMM_CTRL TDR.
The AVMM data bus is 32 bits wide. It is broken into four, 8-bit bytes. Each byte has an associated
byte enable which controls which bytes are written during a given write operation. In all operations
we have observed (for both writes and reads), all four byte enables are always asserted. However, the
AIB_AVMM_CTRL TDR provides the ability to de-assert any byte enables should this need ever arise.
There is a programmable timeout mechanism that will terminate any outstanding AVMM operation to
prevent hanging the AVMM bus if the AVMM slaves do not respond in time (for example, due to them
being in reset or if an unimplemented register is addressed).
These control bits all reside in the AIB_AVMM_CTRL TDR.
First, the instruction AIB_AVMM_CTRL must be loaded into the TAP controller’s instruction register.
Subsequent Shift-DR states will scan data into the following 13-bit TDR. Bit [0] is scanned in first
and, when scanning is complete, is closest to TDO. Bit [12] is scanned in last and is closest to TDI.
There is a latched parallel output register associated with this TDR which prevents changes in the
contents of the shift register from propagating to functional logic while shift operations are in progress.
The contents of the shift register are transferred to the parallel register during the transition through the
Update-DR state of the JTAG TAP controller.
The values in the Rst column represent the values loaded into the parallel register when the
BC_POWER_ON_RESET input is asserted.

# Bits Name Rst Description

1 [0] avmm_rst_n 0 Reset AVMM interface. Active low.
4 [4:1] avmm_byte_en 0xF AVMM byte enables. Active high. Bit[n] of avmm_byte_en corresponds to
byte[n] of avmm_wdata and avmm_rdata. Bytes are addressed in little-
endian format, ie byte[0] = bits[7:0]
8 [12:5] avmm_max_time 0 Maximum number of AVMM clock cycles any valid AVMM operation may
out take before being declared invalid and terminated. A value of 0 disables the
timeout mechanism.

Table 3: AIB_AVMM_CTRL

7.5.2 AIB_AVMM_ACCESS TDR

AIB_AVMM_ACCESS is the single JTAG TDR used to perform all common write and read operations
through the AVMM master. First, the instruction AIB_AVMM_ACCESS is loaded into the TAP
controller’s instruction register. Subsequent Shift-DR states will scan data into the following 54 bit
TDR. Bit [0] is scanned in first and, when scanning is complete, is closest to TDO. Bit [53] is scanned
in last and is closest to TDI.
There is a latched parallel output register associated with this TDR which prevents changes in the
contents of the shift register from propagating to functional logic while shift operations are in progress.
The contents of the shift register are transferred to the parallel register during the transition through the
Update-DR state of the JTAG TAP controller.
The FSM which controls the actual AVMM bus operations only examines the data in this TDR when
the JTAG TAP is transitioning through the Update-DR state and thus the TDR does not need to be
initialized during reset. However, some of the bits (write data and address) are directly driven onto the
AVMM bus. Although not required, we consider driving deterministic data onto the AVMM bus prior
to the first bus transaction to be preferable to driving Xs. Thus, this TDR is cleared during reset.

# Bits Name Rst Description

32 [31:0] avmm_data 0 AVMM data. In the Capture-DR state, will be loaded with read response
data from the AVMM master corresponding to the most recent, valid read
operation. This will be scanned out during the following Shift-DR states at
 the same time write data for the next write operation is scanned in. In the
Update-DR state, this write data will be presented to AVMM master.
17 [48:32] avmm_addr 0 AVMM address. A 17-bit byte address (in little-endian format, see
avmm_byte_en in Table 3: AIB_AVMM_CTRL above) broken up as:
avmm_addr[16:11] = 6-bit channel address,
avmm_addr[10:2] = 9-bit word (32-bit) address within the given channel,
avmm_addr[1:0] = 2-bit byte address within word.
The byte address must always be 0. See the same table listed above for an
explanation of how to access individual bytes within a word.
1 [49] avmm_rd 0 Perform an AVMM read operation. Each transition through the JTAG
Update-DR state (when AIB_AVMM_ACCESS is in the IR) will initiate one
and only one read operation. Read data will be available during the next
Capture-DR/Shift-DR/Update-DR sequence, not the current one.
1 [50] avmm_wr 0 Perform an AVMM write operation. Each transition through the JTAG
Update-DR state (when AIB_AVMM_ACCESS is in the IR) will initiate one
and only one write operation. Writes have priority over reads.
1 [51] avmm_rdvalid 0 AVMM readdatavalid status corresponding to the previous bus operation. If
the previous operation was a write, this will be de-asserted.
1 [52] avmm_waitreq 0 AVMM waitrequest status corresponding to the previous bus operation.
1 [53] avmm_timeout 0 Bus operation timeout status corresponding to the previous bus operation. If
asserted, the previous operation timed out and was terminated.

Table 4: AIB_AVMM_ACCESS

The TAP controller FSM cycles through a Capture-DR/Shift-DR/Update-DR sequence. During the
Capture-DR phase, the current outputs of the AVMM master are sampled and loaded into the
AIB_AVMM_ACCESS TDR. These outputs are scanned out on BC_JTAG_TDO during the Shift-DR
phase while new data is scanned in on BC_JTAG_TDI. This new data is presented as inputs to the
AVMM master during the Update-DR phase. This implies that an AVMM write operation requires one
Capture/Shift/Update sequence (provided the waitrequest response is not needed) to shift in the write
operation, address and data. And that an AVMM read operation requires two Capture/Shift/Update
sequences – one to shift in the read operation and address and, after the AVMM master has completed
the read operation, a second one to shift out the read response.

7.6 JTAG TAP Controller

The only non-AIB interface into the entire BC design is through an IEEE 1149.1 compliant JTAG test
access port (TAP). This simple, serial interface is used to handle normal, JTAG boundary-scan
operations on the AIB interface (as expected), but is also used to configure all of CSRs in the MAC and
PHY and to control and observe the data generation and checking operations in the MAC.