ICCII P-2019.03 Platform Library Training PDF
ICCII P-2019.03 Platform Library Training PDF
03 Release
Library Manager Update Training
CONFIDENTIAL INFORMATION
The information contained in this presentation is the confidential and proprietary
information of Synopsys. You are not permitted to disseminate or use any of
the information provided to you in this presentation outside of Synopsys
without prior written authorization.
IMPORTANT NOTICE
In the event information in this presentation reflects Synopsys’ future plans, such plans
are as of the date of this presentation and are subject to change. Synopsys is not
obligated to update this presentation or develop the products with the features and
functionality discussed in this presentation. Additionally, Synopsys’ services and products
may only be offered and purchased pursuant to an authorized quote and purchase order
or a mutually agreed upon written contract with Synopsys.
• The exploration flow is recommended for library assembly and is the flow used for library
configuration
– Currently, by default, all logic libraries must have consistent library cells and arc data
– The -allow_missing option is widely used because it is common to have missing arcs
– Stream-in instructions
– type, exclude_layers, pin_name_delimiter, port_type_map, text_layer_map,
trace_copy_overlap_shape_from_sub_cell, trace_terminal_length, trace_terminal_type,
trace_unmapped_text, use_only_mapped_text
Library Manager
(Library Assembly) Cell Library
(Updated PRF)
Cell Library
attributes
• The type statement specifies whether the instructions apply to GDSII, OASIS, or both
• The other statements in the stream_in_instruction group set the file.gds.* and
file.oasis.* application options with the same name
© 2019 Synopsys, Inc. 20
Physical Rules File Enhancement
Full Example of stream_in_instructions Group
library ( * ) {
distance_unit : 1um;
length_precision : 1000 ;
stream_in_instructions() {
type : both ;
use_only_mapped_text : false;
trace_copy_overlap_shape_from_sub_cell : false;
trace_unmapped_text: true ;
exclude_layers("M1 EM1:mask_one", "M2 EM2");
port_type_map("VDD power", "VSS ground", "VDDN nwell");
text_layer_map("M1 M1PIN", "M2 M2PIN:1");
trace_terminal_length : 0.1;
trace_terminal_type : signal;
}
}