Part-A

B TECH : 2019-20 VLSI Design
Experiment No.: Date:
PART- A
_________________________________________________________
Objectives: To design and simulate the layout of CMOS Inverter.
Software: MicroWind
Design Description: -
In CMOS (Complementary Metal-Oxide Semiconductor) technology, both N-type and P type

transistors are used to realize logic functions. Today, CMOS technology is the dominant
semiconductor technology for microprocessors, memories and application specific integrated
circuits (ASICs).
The main advantage of CMOS over NMOS and bipolar technology is the much smaller power
dissipation. Unlike NMOS or bipolar circuits, a CMOS circuit has almost no static power
dissipation. Power is only dissipated in case the circuit actually switches. This allows to integrate
many more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better
performance.
The most important CMOS gate is the CMOS inverter. It consists of only two transistors, a pair
of one N-type and one P-type transistor. Fig.1 shows the circuit diagram of a CMOS inverter. Its
operation is readily understood with the help of the simple switch model shown in fig. 2
If the input voltage is '1' (H) the P-type transistor on top is nonconducting, but the Ntype
transistor is conducting and provides a path from GND to the output Y. The output level
therefore is '0'. On the other hand, if the input level is '0'(L), the P-type transistor is conducting
and provides a path from VCC to the output Y, so that the output level is '1', while the N-type
transistor is blocked. If the input is floating, both transistors may be conducting and a short-
circuit condition is possible:
Procedure:
Step 1: Start the Microwind by using the desktop shortcut or by using the Start ➔Programs ➔
Microwind.
Step 2: In the Navigator window go to FILE ➔Select New Layout
Step 3: In the Navigator window go to FILE ➔Select Foundry ➔Select the Technology ➔Click
on Ok.
Step 4: Use palette to add components– say NMOS and PMOS. Pass proper parametric values to
the components.
Step 5: Connect the Vdd and Vss and Add input waveform generators and variable names
associated with nets which you want to monitor in simulation.
Step 6:Give input stimulus. Note the default is a clock whose parameters are tl, tr, th and tf. You
can choose some other forms of inputs also e.g. the pulse, etc.
Step 7: Do Analysis ➔Design Rule Checker and make the layout DRC clean.
Step 8: Go to Simulate➔ Run Simulation, which pops up a waveform window.
Step 9:Play with the Time Scale in the menu on the left of the waveform window to zoom in.
Conclusion:
___________________________________________________________________
___________________________________________________________________
__________________________________________________________________
Rubrics for Evaluation:
Very good Good Average Satisfactory

(9 to 10 Marks) (7 to 8 Marks) (5 to 6 Marks) ( 1 to 4 Marks)
Criteria-1 : Functionality/Specifications
The microwind circuit is The microwind circuit is The microwind circuit is The microwind circuit is
designed with designed with designed without minimally functional;
considering all the DRC considering all the DRC considering the DRC design was untidy with
rules. Design was neat, rules. Design was neat, rules. Design was untidy problems in considering
clear with considering clear with considering with major problems in parameter and labeling.
all parameter and all parameter and minor considering parameter Or copied.
proper labeling. problems in labeling. and labeling.
Criteria-2 : Design Demonstration
designed & Simulated designed & Simulated designed & Simulated designed & Simulated
as well as explained the as well as explained the with some errors. with some errors.
circuit and output circuit and output explained the circuit Unable to explain the
fluently partially and output partially . circuit and output.
Criteria-3 : Documentation
The microwind circuit The microwind circuit The microwind circuit Documents like
and Simulation and Simulation and Simulation microwind circuit and
waveforms file is waveforms file is waveforms file is poorly Simulation waveforms
extremely well reasonably well documented. There are are missing. There are
documented. documented. There are no proper comments no proper comments
minor formatting /titles given. /titles given. Or copied.
omissions that would
have improved user
understanding of code
purpose.
Experiment No. Date:
PART- A
_________________________________________________________
Objectives: To design and simulate the layout of NAND/NOR/OR Gate.
Software: MicroWind
Design Description
A logic gate is an elementary building block of a digital circuit. Most logic gates have two inputs
and one output. At any given moment, every terminal is in one of the two binary
conditions low (0) or high (1), represented by different voltage levels. The logic state of a
terminal can, and generally does, change often, as the circuit processes data. In most logic gates,
the low state is approximately zero volts (0 V), while the high state is approximately five volts
positive (+5 V).There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and
XNOR.
1. NAND Gate using CMOS
NAND gate is one of the logic gates to perform the digital operation on the input signals. It is the
combination of AND Gate followed by NOT gate i.e. it is the opposite operation of AND gate
where the Logic NAND gate is complementary of AND gate. The logic output of NAND gate is
low (FALSE) only when the inputs are high (TRUE).
Figure: Truth Table for CMOS NAND Gate
1. OR/NOR Gate using CMOS
NOR gate is one of the logic gates to perform the digital operation on the input signals. It is the
combination of OR Gate followed by NOT gate i.e. it is the opposite operation of OR gate where
the Logic NOR gate is complementary of OR gate. The logic output of NOR gate is high
(TRUE) only when the inputs are low (FALSE).
Figure 1: Truth table for NOR Gate
Procedure:
Microwind.
on Ok.
the components.
Conclusion:
___________________________________________________________________
___________________________________________________________________
___________________________________________________________________
___________________________________________________________________
___________________________________________________________________

have improved user
purpose.
Experiment No. 2 Date:
PART- A
_________________________________________________________
Ojectives: To design and simulate the layout of Half Adder Circuit.
Software: MicroWind
An adder is a digital logic circuit in electronics that implements addition of numbers. In many
computers and other types of processors, adders are used to calculate addresses, similar
operations and table indices in the ALU and also in other parts of the processors. These can be
built for many numerical representations like excess-3 or binary coded decimal. Adders are
classified into two types: half adder and full adder.
Adder :
The Half-Adder is the basic building block of all arithmetic circuits. Every microchip or
machine that can perform addition, subtraction, multiplication, or division has Half-Adder
blocks inside. Because the Half-Adder is so material to our ability to do math on computers.
 Half adder is a combinational circuit that performs simple addition of two binary
numbers.
 A and B as the two bits whose addition is to be performed, a truth table for half adder
with A, B as inputs and Sum, Carry as outputs
Figure: Half Adder using NAND equation
Procedure:
Microwind.
on Ok.
the components.
Conclusion:
___________________________________________________________________
___________________________________________________________________
___________________________________________________________________
___________________________________________________________________
__________________________________________________________________

have improved user
purpose.
Experiment No. Date:
PART- A
_________________________________________________________
Objectives: Implement 2:1 Mux by conventional method and by using

transmission gates. Comparison of them.
Software: MicroWind
The most widely used solution to deal with the voltage drops induced by pass transistors is the
use of transmission gates. The primary limitation of NMOS or PMOS only pass gate is the
threshold drop (NMOS pass device pass a strong 0 while passing a weak 1and PMOS pass
devices pass a strong 1 while passing a weak 0). The ideal approach is to use the NMOS device
to pull-down and the PMOS device to pull-up. The transmission gate combines the best of both
device by placing a NMOS device in parallel with a PMOS device. The control signals to the
transmission gate (C and C)are complementary. The transmission gate acts as a bidirectional
switch controlled by the gate signal C. When C = 1, both MOSFETs are on, allowing the signal
to pass through the gate. In short, A=B if C=1
On the other hand, C = 0 places both transistors in cutoff, creating an open circuit between nodes
A and B
Diagrams:
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
Figure :2:1 mux using Transmission gate with truth table
D1
S Y
D0
D1 4 2
S 4 2 Y
D0 4 2
2
Figure :2:1 mux using conventional method
Procedure:
Microwind.

on Ok.
the components.

Observations:
If we design 2:1mux using basic gates then 20 transistors are required and if we design
with transmission gate then only 4 gates are required.
Conclusion:
___________________________________________________________________
___________________________________________________________________
___________________________________________________________________
___________________________________________________________________

have improved user
purpose.

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B TECH : 2019-20 VLSI Design

Experiment No.: Date:

In CMOS (Complementary Metal-Oxide Semiconductor) technology, both N-type and P type

Rubrics for Evaluation:

Very good Good Average Satisfactory

Experiment No. Date:

Objectives: To design and simulate the layout of NAND/NOR/OR Gate.

1. NAND Gate using CMOS

Figure: Truth Table for CMOS NAND Gate

1. OR/NOR Gate using CMOS

Figure 1: Truth table for NOR Gate

Rubrics for Evaluation:

Very good Good Average Satisfactory

Experiment No. 2 Date:

Figure: Half Adder using NAND equation

Rubrics for Evaluation:

Very good Good Average Satisfactory

Experiment No. Date:

Objectives: Implement 2:1 Mux by conventional method and by using

Figure :2:1 mux using conventional method

Step 2: In the Navigator window go to FILE ➔Select New Layout

Step 8: Go to Simulate➔ Run Simulation, which pops up a waveform window.

Rubrics for Evaluation:

Very good Good Average Satisfactory

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