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Computer Organization PDF

This document contains 3 questions about cache memory analysis and handling cache misses. Question 1 involves calculating cache sizes, tag sizes, and determining hit rates and average service times for 3 different cache designs. Question 2 involves calculating the tag size and speedup from a unified instruction/data cache and the effects of cache misses. Question 3 involves calculating the percentage of memory bandwidth used for a given cache configuration under write-through and write-back protocols.

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108 views

Computer Organization PDF

This document contains 3 questions about cache memory analysis and handling cache misses. Question 1 involves calculating cache sizes, tag sizes, and determining hit rates and average service times for 3 different cache designs. Question 2 involves calculating the tag size and speedup from a unified instruction/data cache and the effects of cache misses. Question 3 involves calculating the percentage of memory bandwidth used for a given cache configuration under write-through and write-back protocols.

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Part 1.

Memory analysis
Question 1 (40 pt). You are given designs of 3 caches for a 16-bit address machine:
D1:
Direct-mapped cache.
Each cache line is 1 byte.
10-bit index, 6-bit tag.
1 cycle hit time.
D2:
2-way set associative cache.
Each cache line is 1 word (4 bytes).
7-bit index, 7-bit tag.
2 cycle hit time.
D3:
fully associative cache with 256 cache lines.
Each cache line is 1 word.
14-bit tag.
5 cycle hit time.
Answer the following set of questions:
a) What is the size of each cache?
b) How much space does each cache need to store tags?
c) Which cache design has the most conflict misses? Which has the least?
d) The following information is given to you: hit rate for the 3 caches is 50%, 70% and 90%
but did not tell you which hit rate corresponds to which cache, which cache would you guess
corresponded to which hit rate? Why?
e) Assuming the miss time for each is 20 cycles, what is the average service time for each?
(Service Time = (hit rate)*(hit time) + (miss rate)*(miss time)).

Question 2 (30 pt). Assume we have a computer where the CPI is 1.0 when all
memory accesses (including data and instruction accesses) hit in the cache. The cache is a
unified (data + instruction) cache of size 256 KB, 4-way set associative, with a block size of
64 bytes. The data accesses (loads and stores) constitute 50% of the instructions. The
unified cache has a miss penalty of 25 clock cycles and a miss rate of 2%. Assume 32-bit
instruction and data addresses. Now, answer the following questions:

a) What is the tag size for the cache?


b. How much faster would the computer be if all memory accesses were cache hits?

Part2: Handling Cache Miss


Question 3 (30 pt). You purchased a computer with the following features:
• 95% of all memory accesses are found in the cache.
• Each cache block is two words, and the whole block is read on any miss.
• The processor sends references to its cache at the rate of 109 words per second.
• 25% of those references are writes.
• Assume that the memory system can support 10 9 words per second, reads or writes.
• The bus reads or writes a single word at a time (the memory system cannot read or
write two words at once).
• Assume at any one time, 30% of the blocks in the cache have been modified.
• The cache uses write allocate on a write miss.
• You are considering adding a peripheral to the system, and you want to know how
much of the memory system bandwidth is already used.
Calculate the percentage of memory system bandwidth used on the average in the two cases
below. Be sure to state your assumptions.
a. Case 1: The cache is write through.
b. Case 2: The cache is write back.

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