®

ISD2500 Series
Single-Chip Voice Record/Playback Devices
32-*, 40-*, 48-*, 64-*, 60-, 75-,
90-, and 120-Second Durations

FEATURES
• Easy-to-use single-chip voice Record/ • Fully addressable to handle multiple
Playback solution messages
• High-quality, natural voice/audio • 100-year message retention (typical)
reproduction • 100,000 record cycles (typical)
• Manual switch or microcontroller compati-
ble Playback can be edge- or level-
•
•
On-chip clock source
No algorithm development required
1
activated
• Single +5 volt power supply
• Single-chip durations of 32*, 40*, 48*, 64*,
60, 75, 90, and 120 seconds • Available in die form, DIP, SOIC, and
TSOP packaging
• Directly cascadable for longer durations
• Industrial temperature (-40°C to +85°C)
• Automatic Power-Down (Push-Button versions available
Mode)
– Standby current 1 µA (typical)
• Zero-power message storage
– Eliminates battery backup circuits

ISD2500 SERIES SUMMARY

Part Duration Input Sample Typical Filter
Number (Seconds) Rate (KHz) Pass Band (KHz)

ISD2560 60 8.0 3.4

ISD2575 75 6.4 2.7

ISD2590 90 5.3 2.3

ISD25120 120 4.0 1.7

ISD2532* 32 8.0 3.4
ISD2540* 40 6.4 2.7
ISD2548* 48 5.3 2.3
ISD2564* 64 4.0 1.7

Information Storage Devices, Inc. * Advance information: ISD2532/40/48/64 devices. 1–79

 ISD2500 Series Product Data Sheets

GENERAL DESCRIPTION DETAILED DESCRIPTION

Information Storage Devices' ISD2500 Chip-
Speech/Sound Quality
Corder® Series provides high-quality, single-chip
Record/Playback solutions for 32- to 120-second The ISD2500 Series includes devices offered at
messaging applications. The CMOS devices 4.0, 5.3, 6.4, and 8.0 KHz sampling frequencies,
include an on-chip oscillator, microphone pream- allowing the user a choice of speech quality
plifier, automatic gain control, antialiasing filter, options. Increasing the duration within a product
smoothing filter, speaker amplifier, and high den- series decreases the sampling frequency and
sity multi-level storage array. In addition, the bandwidth, which affects sound quality. Please
ISD2500 is microcontroller compatible, allowing refer to the ISD2500 Series Summary table on
complex messaging and addressing to be page 1-79 to compare filter pass band and product
achieved. durations.

Recordings are stored in on-chip nonvolatile mem- The speech samples are stored directly into on-
ory cells, providing zero-power message storage. chip nonvolatile memory without the digitization
This unique, single-chip solution is made possible and compression associated with other solutions.
Direct analog storage provides a very true, natural
-1 through ISD's patented multilevel storage technol-
ogy. Voice and audio signals are stored directly sounding reproduction of voice, music, tones, and
into memory in their natural form, providing high- sound effects not available with most solid-state
quality, solid-state voice reproduction. digital solutions.

Duration
To meet end system requirements, the ISD2500
Series offers single-chip solutions at 32*, 40*, 48*,
64*, 60, 75, 90, and 120 seconds. Parts may also
be cascaded together for longer durations.

ISD2560/75/90/120 DEVICE BLOCK DIAGRAM

Internal Clock Timing

XCLK
Sampling Clock

R
ANA IN Amp 5-Pole Active Analog Transceivers
Antialiasing Filter
480 K Cell
Decoders

ANA OUT
Nonvolatile 5-Pole Active
MIC Multilevel Storage Smoothing Filter
Pre-
Amp Array SP+
MIC REF
Automatic Mux Amp
AGC Gain Control SP–
(AGC)

Power Conditioning Address Buffers Device Control

VCCA VSSA VSSD VCCD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 PD OVF P/R CE EOM AUX IN

1–80 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

ISD2532/40/48/64* DEVICE BLOCK DIAGRAM

Internal Clock Timing

XCLK
Sampling Clock

R
ANA IN Amp 5-Pole Active Analog Transceivers
Antialiasing Filter
256 K Cell

Decoders
ANA OUT
Nonvolatile 5-Pole Active
MIC Multilevel Storage Smoothing Filter
Pre-
Amp Array SP+
MIC REF
Automatic Mux Amp
AGC Gain Control SP–
(AGC)

Power Conditioning Address Buffers Device Control

VCCA VSSA VSSD VCCD A0 A1 A2 A3 A4 A5 A6 A7 A8 PD OVF P/R CE EOM AUX IN

1
EEPROM Storage PIN DESCRIPTIONS
One of the benefits of ISD’s ChipCorder technol-
Voltage Inputs (VCCA, VCCD)
ogy is the use of on-chip nonvolatile memory,
providing zero-power message storage. The mes- To minimize noise, the analog and digital circuits in
sage is retained for up to 100 years typically the ISD2500 Series devices use separate power
without power. In addition, the device can be re- busses. These voltage busses are brought out to
recorded typically over 100,000 times. separate pins and should be tied together as close
to the supply as possible. In addition, these sup-
Microcontroller Interface plies should be decoupled as close to the package
In addition to its simplicity and ease of use, the as possible.
ISD2500 Series includes all the interfaces neces-
sary for microcontroller-driven applications. The Ground Inputs (VSSA, VSSD)
address and control lines can be interfaced to a The ISD2500 Series of devices utilizes separate
microcontroller and manipulated to perform a vari- analog and digital ground busses. These pins
ety of tasks, including message assembly, should be connected separately through a low-
message concatenation, predefined fixed mes- impedance path to power supply ground.
sage segmentation, and message management.
Power Down Input (PD)
Programming
When not recording or playing back, the PD pin
The ISD2500 Series is also ideal for playback-only should be pulled HIGH to place the part in a very
applications, where single or multiple messages low power mode (see ISB specification). When
are referenced through buttons, switches, or a OVF pulses LOW for an overflow condition, PD
microcontroller. Once the desired message config- should be brought HIGH to reset the address
uration is created, duplicates can easily be pointer back to the beginning of the Record/Play-
generated via an ISD programmer. back space. The PD pin has additional
functionality in the M6 (Push-Button) Operational

* Advance information: ISD2532/40/48/64 devices. 1–81

 ISD2500 Series Product Data Sheets

ISD2560/75/90/120 DEVICE PINOUTS

A0/M0 1 28 VCCD
A1/M1 2 27 P/R
OVF 1 32 ANA OUT A2/M2 3 26 XCLK
CE 2 31 ANA IN A3/M3 4 25 EOM
PD 3 30 AGC
EOM 4 29 MIC REF A4/M4 5 24 PD
XCLK 5 28 MIC A5/M5 6 23 CE
P/R 6 27 VCCA ISD2560
VCCD 7 26 SP– A6/M6 7 ISD2575 22 OVF
NC 8
9
ISD2560/75/90/120 25 NC A7 8 ISD2590 21 ANA OUT
NC 24 NC A8 9 ISD25120 20 ANA IN
A0/M0 10 23 SP+
A1/M1 11 22 VSSA A9 10 19 AGC
A2/M2 12 21 VSSD
13 AUX IN 11 18 MIC REF
A3/M3 20 AUX IN
A4/M4 14 19 A9 VSSD 12 17 MIC
A5/M5 15 18 A8
16 VSSA 13 16 VCCA
A6/M6 17 A7
SP+ 14 15 SP–
TSOP DIP/SOIC

Mode described later in the Operational Mode End-Of-Message / RUN Output (EOM)
section. A nonvolatile marker is automatically inserted at
-1 Chip Enable Input (CE) the end of each recorded message. It remains
there until the message is recorded over. The
The CE pin is taken LOW to enable all Playback EOM output pulses LOW for a period of TEOM at
and Record operations. The address inputs and the end of each message.
Playback/Record input (P/R) are latched by the
falling edge of CE. CE has additional functionality In addition, the ISD2500 Series has an internal
in the M6 (Push-Button) Operational Mode VCC detect circuit to maintain message integrity
described later in the Operational Mode section. should VCC fall below 3.5V. In this case, EOM
goes LOW and the device is fixed in Playback-only
Playback/Record Input (P/R) mode.
The P/R input is latched by the falling edge of the When the device is configured in Operational
CE pin. A HIGH level selects a Playback cycle Mode M6 (Push-Button Mode), this pin provides an
while a LOW level selects a Record cycle. For a active-HIGH RUN signal, indicating the device is
Record cycle, the address inputs provide the start- currently recording or playing. This signal can con-
ing address and recording continues until PD or veniently drive an LED for a visual indicator of a
CE is pulled HIGH or an overflow is detected (i.e. Record or Playback operation in process.
the chip is full). When a Record cycle is terminated
by pulling PD or CE HIGH, an End-Of-Message Overflow Output (OVF)
(EOM) marker is stored at the current address in This signal pulses LOW at the end of memory
memory. For a Playback cycle, the address inputs space, indicating the device has been filled and the
provide the starting address and the device will message has overflowed. The OVF output then fol-
play until an EOM marker is encountered. The lows the CE input until a PD pulse has reset the
device can continue past an EOM marker in an device. This pin can be used to cascade several
operational mode, or if CE is held LOW in address ISD2500 devices together to increase Record/
mode. (See page 1-85 for more Operational Playback durations.
Modes).

1–82 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

ISD2532/40/48/64* DEVICE PINOUTS

A0/M0 1 28 VCCD
A1/M1 2 27 P/R
A2/M2 3 26 XCLK
OVF 1 32 ANA OUT
CE 2 31 ANA IN A3/M3 4 25 EOM
PD 3 30 AGC A4/M4 5 24 PD
EOM 4 29 MIC REF
XCLK 5 28 MIC A5/M5 6
ISD2532 23 CE
P/R 6 27 VCCA A6/M6 7 22 OVF
VCCD 7 26 SP– ISD2540
NC 8 ISD2532/40/48/64 25 NC NC 8 ISD2548 21 ANA OUT
NC 9 24 NC
10
A7 9 ISD2564 20 ANA IN
A0/M0 23 SP+
A1/M1 11 22 VSSA A8 10 19 AGC
A2/M2 12 21 VSSD
13
AUX IN 11 18 MIC REF
A3/M3 20 AUX IN
A4/M4 14 19 A8 VSSD 12 17 MIC
A5/M5 15 18 A7
16
VSSA 13 16 VCCA
A6/M6 17 NC
SP+ 14 15 SP–
TSOP DIP/SOIC

Microphone Input (MIC) AGC pin to VSSA analog ground. The “release”
The microphone input transfers its signal to the on- time is determined by the time constant of an
chip preamplifier. An on-chip Automatic Gain Con- external resistor (R2) and an external capacitor
(C2) connected in parallel between the AGC Pin
1
trol (AGC) circuit controls the gain of this
preamplifier from -15 to 24 dB. An external micro- and VSSA analog ground. Nominal values of
phone should be AC coupled to this pin via a series 470 KΩ and 4.7 µF give satisfactory results in
capacitor. The capacitor value, together with the most cases.
internal 10 K ohm resistance on this pin, deter-
Analog Output (ANA OUT)
mines the low-frequency cutoff for the ISD2500
Series passband. See ISD's Application Notes and This pin provides the preamplifier output to the
Design Manual in this book for additional informa- user. The voltage gain of the preamplifier is deter-
tion on low-frequency cutoff calculation. mined by the voltage level at the AGC pin.

Microphone Reference Input (MIC REF) Analog Input (ANA IN)

The MIC REF input is the inverting input to the The analog input pin transfers its signal to the chip
microphone preamplifier. This provides a noise- for recording. For microphone inputs, the ANA
canceling or common-mode rejection input to the OUT pin should be connected via an external
device when connected to a differential capacitor to the ANA IN pin. This capacitor value,
microphone. together with the 3.0 KΩ input impedance of ANA
IN, is selected to give additional cutoff at the low-
Automatic Gain Control Input (AGC) frequency end of the voice passband. If the
The AGC dynamically adjusts the gain of the desired input is derived from a source other than a
preamplifier to compensate for the wide range of microphone, the signal can be fed, capacitively
microphone input levels. The AGC allows the full coupled, into the ANA IN pin directly.
range of whispers to loud sounds to be recorded
External Clock Input (XCLK)
with minimal distortion. The “attack” time is deter-
mined by the time constant of a 5 KΩ internal The external clock input for the ISD2500 devices
resistance and an external capacitor (C2 on the has an internal pull-down device. These devices
schematic on page 1-100) connected from the are configured at the factory with an internal sam-
pling clock frequency centered to ± 1% of

* Advance information: ISD2532/40/48/64 devices. 1–83

 ISD2500 Series Product Data Sheets

specification. The frequency is then maintained to NOTE

a variation of ± 2.25% over the entire commercial Connection of speaker outputs in parallel
temperature and operating voltage ranges. The may cause damage to the device.
internal clock has a ± 5% tolerance over the indus-
trial temperature and voltage range. A regulated A single output may be used alone (including a
power supply is recommended for industrial tem- coupling capacitor between the SP pin and the
perature range parts. If greater precision is speaker). These outputs may be used individually
required, the device can be clocked through the with the output signal taken from either pin. Using
XCLK pin as follows: the differential outputs results in a 4:1 improve-
ment in output power.

Part NOTE
Sample Rate Required Clock
Number Never ground or drive an unused speaker
output.
ISD2560 8.0 KHz 1024 KHz

ISD2575 6.4 KHz 819.2 KHz

Auxiliary Input (AUX IN)
ISD2590 5.3 KHz 682.7 KHz
The Auxiliary Input is multiplexed through to the
-1 ISD25120

ISD2532*
4.0 KHz

8.0 KHz
512 KHz

1024 KHz
output amplifier and speaker output pins when CE
is HIGH, P/R is HIGH, and Playback is currently
ISD2540* 6.4 KHz 819.2 KHz
not active or if the device is in Playback overflow.
When cascading multiple ISD2500 devices, the
ISD2548* 5.3 KHz 682.7 KHz AUX IN pin is used to connect a Playback signal
ISD2564* 4.0 KHz 512 KHz from a following device to the previous output
speaker drivers. For noise considerations, it is sug-
These recommended clock rates should not be gested that the auxiliary input not be driven when
varied because the antialiasing and smoothing fil- the storage array is active.
ters are fixed, and aliasing problems can occur if Address/Mode Inputs (Ax/Mx)
the sample rate differs from the one recom-
mended. The duty cycle on the input clock is not The Address/Mode Inputs have two functions
critical, as the clock is immediately divided by two. depending on the level of the two Most Significant
Bits (MSB) of the address (A8 and A9 for the
IF THE XCLK IS NOT USED, THIS INPUT MUST BE CON-
ISD256075/90/120 devices, and A7 and A8 for the
NECTED TO GROUND.
ISD2532/40/48/64* devices).
Speaker Outputs (SP+/SP-) If either or both of the two MSBs are LOW, the
All devices in the ISD2500 Series include an on- inputs are ALL interpreted as address bits and are
chip differential speaker driver, capable of driving used as the start address for the current Record or
50 milliwatts into 16 Ω from AUX IN (12.2 mW from Playback cycle. The address pins are inputs only
memory). and do not output internal address information as
the operation progresses. Address inputs are
The speaker outputs are held at VSSA levels during
latched by the falling edge of CE.
record and power down. It is therefore not possible
to parallel speaker outputs of multiple ISD2500 If both MSBs are HIGH, the Address/Mode Inputs
devices or the outputs of other speaker drivers. are interpreted as Mode bits according to the
Operational Mode table on page 1-85. There are
six operational modes (M0..M6) available as indi-

1–84 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

OPERATIONAL MODES TABLE

Mode
Function Typical Use Jointly Compatible*
Control

M0 Message cueing Fast-forward through messages M4, M5, M6

M1 Delete EOM markers Position EOM marker at the end of the last M3, M4, M5, M6
message

M2 Not applicable Reserved N/A

M3 Looping Continuous playback from Address 0 M1, M5, M6

M4 Consecutive address- Record/Play multiple consecutive M0, M1, M5

ing messages

M5 CE level-activated Allows message pausing M0, M1, M3, M4

M6 Push-button control Simplified device interface M0, M1, M3

NOTE: An asterisk (*) indicates additional operational modes which can be used simultaneously with the given mode.
1
cated in the table. It is possible to use multiple ISD2500 address space. Later operations can
operational modes simultaneously. Operational begin at other address locations, depending on the
Modes are sampled on each falling edge of CE, operational mode(s) chosen. In addition, the
and thus Operational Modes and direct addressing address pointer is reset to 0 when the device is
are mutually exclusive. changed from Record to Playback, Playback to
Record (except M6 mode), or when a Power-Down
OPERATIONAL MODES cycle is executed.
The ISD2500 Series is designed with several built- Second, Operational Modes are executed when
in operational modes that provide maximum func- CE goes LOW and the two MSBs are HIGH. This
tionality with minimum additional components. Operational Mode remains in effect until the next
These are described in detail below. The opera- LOW-going CE signal, at which point the current
tional modes use the address pins on the ISD2500 address/mode levels are sampled and executed.
devices, but are mapped outside the valid address
range. When the two Most Significant Bits (MSBs) OPERATIONAL MODES DESCRIPTION
are HIGH (A8 and A9 for the ISD2560/75/90/120
The Operational Modes can be used in conjunction
devices, and A7 and A8 for the ISD2532/40/48/64*
with a microcontroller, or they can be hard-wired to
devices), the remaining address signals are inter-
provide the desired system operation.
preted as mode bits and not as address bits.
Therefore, operational modes and direct address- M0 — Message Cueing
ing are not compatible and cannot be used
Message Cueing allows the user to skip through
simultaneously.
messages, without knowing the actual physical
There are two important considerations for using addresses of each message. Each CE LOW pulse
operational modes. First, all operations begin ini- causes the internal address pointer to skip to the
tially at address 0, which is the beginning of the next message. This mode should be used for

* Advance information: ISD2532/40/48/64 devices. 1–85

 ISD2500 Series Product Data Sheets

Playback only, and is typically used with the M4 M6 — Push-Button Mode

Operational Mode. The ISD2500 Series of devices contain a Push-
Button operational mode. The Push-Button mode
M1 — Delete EOM Markers
is used primarily in very low-cost applications and
The M1 Operational Mode allows sequentially is designed to minimize external circuitry and com-
recorded messages to be combined into a single ponents, thereby reducing system cost. In order to
message with only one EOM marker set at the end configure the device in Push-Button operational
of the final message. When this operational mode mode, the two most significant address bits must
is configured, messages recorded sequentially are be HIGH, and the M6 mode pin must also be
played back as one continuous message. HIGH. A device in this mode always powers down
at the end of each Playback or Record
M2 — Unused
cycle after CE goes HIGH.
When operational modes are selected, the M2 pin
should be LOW. When this operational mode is implemented, sev-
eral of the pins on the device have alternate
M3 — Message Looping functionality:
The M3 Operational Mode allows for the auto-
-1 matic, continuously repeated playback of the
message located at the beginning of the address Pin Name
Alternate Functionality in
Push-Button Mode
space. A message CAN completely fill the ISD2500
device and will loop from beginning to end without CE Start/Pause Push-Button
OVF going LOW. (LOW pulse-activated)

PD Stop/Reset Push-Button
M4 — Consecutive Addressing (HIGH pulse activated)
During normal operations, the address pointer will EOM Active-HIGH Run Indicator
reset when a message is played through to an
EOM marker. The M4 Operational Mode inhibits
the address pointer reset on EOM, allowing mes- CE Pin (START/PAUSE)
sages to be played back consecutively. In Push-Button Operational Mode, CE acts as a
LOW-going pulse-activated START/PAUSE sig-
M5 — CE-Level Activated nal. If no operation is currently in progress, a LOW-
The default mode for ISD2500 devices is for CE to going pulse on this signal will initiate a Playback or
be edge-activated on Playback and level-activated a Record cycle according to the level on the P/R
on Record. The M5 Operational Mode causes the pin. A subsequent pulse on the CE pin, before an
CE pin to be interpreted as level-activated as End-Of-Message is reached in Playback or an
opposed to edge-activated during Playback. This overflow condition occurs, will cause the device to
is specifically useful for terminating Playback oper- pause. The address counter is not reset, and
ations using the CE signal. another CE pulse will cause the device to continue
the operation from the place where it was paused.
In this mode, CE LOW begins a Playback cycle, at
the beginning of the device memory. The Playback PD Pin (STOP/RESET)
cycle continues as long as CE is held LOW. When
In push-button Operational Mode, PD acts as a
CE goes HIGH, Playback will immediately end. A
HIGH-going pulse-activated STOP/RESET signal.
new CE LOW will restart the message from the
When a Playback or Record cycle is in progress
beginning unless M4 is also HIGH.
and a HIGH-going pulse is observed on PD, the

1–86 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

current cycle is terminated and the address pointer Playback in Push-Button Mode
is reset to address 0, the beginning of the message 1. The PD pin should be LOW.
space.
2. The P/R pin is taken HIGH.
EOM Pin (RUN)
3. The CE pin is pulsed LOW. Playback starts,
In Push-Button Operational Mode, EOM becomes EOM goes HIGH to indicate an operation in
an active-HIGH RUN signal which can be used to progress.
drive an LED or other external device. It is HIGH
whenever a Record or Playback operation is in 4. If the CE pin is pulsed LOW or an EOM
progress. marker is encountered during an operation,
the part will pause. The internal address
Recording in Push-Button Mode pointers are not cleared, and EOM goes
1. The PD pin should be LOW, usually using a back LOW. The P/R pin may be changed at
pulldown resistor. this time. A subsequent Record operation
would not reset the address pointers and
2. The P/R pin is taken LOW.
the recording would begin where Playback
3. The CE pin is pulsed LOW. Recording ended.
starts, EOM goes HIGH to indicate an oper-
ation in progress.
5. CE is again pulsed LOW. Playback starts
where it left off, with EOM going HIGH to
1
4. The CE pin is pulsed LOW. Recording indicate an operation in progress.
pauses, EOM goes back LOW. The internal
6. Playback continues as in steps 4 and 5 until
address pointers are not cleared, but an
PD is pulsed HIGH or overflow occurs.
EOM marker is stored in memory to point to
the message end. The P/R pin may be 7. If in overflow, pulling CE LOW will reset the
taken HIGH at this time. Any subsequent address pointer and start Playback from the
CE would start a playback at address 0. beginning. After a PD pulse, the part is reset
to address 0.
5. The CE pin is pulsed LOW. Recording
starts at the next address after the previous NOTE
set EOM marker. EOM goes back HIGH. Push-button mode can be used in con-
junction with modes M0, M1, and M3.
NOTE
If the M1 operational mode pin is also
HIGH, the just previously written EOM bit Good Audio Design Practices
is erased, and recording starts at that ISD products are very high-quality single-chip
address.) voice Recording and Playback systems. To ensure
the highest quality voice reproduction, it is impor-
6. When the recording sequences are fin- tant that good audio design practices on layout and
ished, the final CE pulse LOW will end the power supply decoupling be followed. See the ISD
last Record cycle, leaving a set EOM Application Notes and Design Manual in this book
marker at the message end. Recording may for details.
also be terminated by a HIGH level on PD,
which will leave a set EOM marker.

* Advance information: ISD2532/40/48/64 devices. 1–87

 ISD2500 Series Product Data Sheets

ISD1000A COMPATIBILITY Push-Button Mode

The ISD2500 Series of devices is designed to pro- The ISD2500 Series includes an additional Opera-
vide upward compatibility with the ISD1000A tional Mode called Push-Button mode. This
family. When designing with the ISD2500 Series, provides an alternative interface to the Record and
the following differences should be noted. Playback functions of the part. The CE and PD
pins become redefined as edge-activated “push-
Addressing buttons.” A pulse on CE initiates a cycle, and if
The ISD2560/75/90/120 devices have 480K stor- triggered again, pauses the current cycle without
age cells designed to provide 60 seconds of resetting the address pointer (i.e., a Start or Pause
storage at a sampling rate of 8.0 KHz. This is function). PD stops any current cycle and resets
approximately four times the storage of the the address pointer to the beginning of the mes-
ISD1000A family. To enable the same addressing sage space (i.e., a Stop and Reset function).
resolution, two additional address pins have been Additionally, the EOM pin functions as an active-
added. The address space of each device is divis- HIGH run indicator, and can be used to drive an
ible into 300 increments with valid addressing from LED indicating a Record or Playback operation is
00 to 13F Hex. Some higher addresses are in progress. Devices in the Push-Button mode can-
mapped into the Operational Modes. All other not be cascaded.
-1 addresses are invalid.
Looping Mode
The ISD2532/40/48/64 devices have 256K storage The ISD2500 Series can loop with a message that
cells designed to provide 32 seconds of storage at completely fills the memory space.
a sampling rate of 8.0 KHz. This is twice the
amount of storage of the ISD1000A family. To NOTE
enable the same addressing resolution, one addi- Additional descriptions of ISD2500 device
tional address pin has been added. The address functionality and application examples are
space of each device is divisable into 320 incre- provided in the ISD Application Notes and
ments with valid addressing from 00 to 13F Hex. Design Manual in this book.

Overflow
The ISD1000A Series combined two functions on
the EOM pin: end-of-message indication and over-
flow. The ISD2500 separates these two functions.
Pin 25 (PDIP package) remains as EOM, but out-
puts only the EOM signal indication. Pin 22 (PDIP
package) becomes OVF and pulses LOW only
when the device reaches its end of memory, or is
“full.” This change allows easy message cueing
and addressability across device boundaries. This
also means that the M2 operational mode found in
the ISD1000A family is not implemented in the
ISD2500 Series.

1–88 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

TIMING DIAGRAMS
Record

CE TCE

TSET
P/R Don't Care

T PDH TPDS TPDR

THOLD
PD Don't Care

A0-A9 Don't Care Don't Care

TSET
MIC
ANA IN
TPUD TOVF
OVF

1
Playback

CE TCE

TSET

P/R Don't Care

T PDH TPDS TPDP

THOLD
PD Don't Care

A0-A9 Don't Care Don't Care

TSET
SP+/–
TOVF

OVF

EOM

TPUD TEOM

* Advance information: ISD2532/40/48/64 devices. 1–89

 ISD2500 Series Product Data Sheets

ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS

(PACKAGED PARTS) (PACKAGED PARTS)

Condition Value Condition Value

Junction temperature 150° C Commercial operating 0° C to +70° C

temperature range(1)
Storage temperature range –65° C to +150° C
Industrial operating –40° C to +85° C
Voltage applied to any pin (VSS – 0.3 V) to
(VCC + 0.3 V) temperature range(1)

Supply voltage (VCC)(2) +4.5 V to +5.5 V

Voltage applied to any pin (VSS – 1.0 V) to
(Input current limited to ±20 mA) (VCC + 1.0 V)
Ground voltage (VSS)(3) 0V
Lead temperature (soldering – 300° C
10 seconds) NOTES: 1. Case temperature.
2. VCC = VCCA = VCCD.
VCC - VSS – 0.3 V to + 7.0 V 3. VSS = VSSA = VSSD.

NOTE: Stresses above those listed may cause permanent

-1 damage to the device. Exposure to the absolute

maximum ratings may affect device reliability.
Functional operation is not implied at these
conditions.

DC PARAMETERS (PACKAGED PARTS)

Symbol Parameters Min(2) Typ (1) Max(2) Units Conditions

VIL Input Low Voltage 0.8 V

VIH Input High Voltage 2.0 V

VOL Output Low Voltage 0.4 V IOL = 4.0 mA

VOH Output High Voltage VCC–0.4 V IOH = – 10 µA

VOH1 OVF Output High Voltage 2.4 V IOH = – 1.6 mA

VOH2 EOM Output High Voltage VCC–1.0 VCC–0.8 V IOH = – 3.2 mA

ICC VCC Current (Operating) 25 30 mA REXT = ∞ (3)

ISB VCC Current (Standby) 1 10 µA (3)

IIL Input Leakage Current +1 µA

IILPD Input Current HIGH w/Pull 130 µA Force VCC (4)

Down
REXT Output Load Impedance 16 Ω Speaker Load

RMIC Preamp In Input Resistance 4 9 15 KΩ MIC and MIC REF Pins

RAUX AUX INPUT Resistance 5 11 20 KΩ

1–90 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

DC PARAMETERS (PACKAGED PARTS) – CONTINUED

Symbol Parameters Min(2) Typ (1) Max(2) Units Conditions

RANA IN ANA IN Input Resistance 2.3 3 5 KΩ

APRE1 Preamp Gain 1 21 24 26 dB AGC = 0.0 V

APRE2 Preamp Gain 2 –15 5 dB AGC = 2.5 V

AAUX AUX IN/SP+ Gain 0.98 1.0 V/V

AARP ANA IN to SP+/- Gain 21 23 26 dB

RAGC AGC Output Resistance 2.5 5 9.5 KΩ

NOTES: 1. Typical values @ TA = 25° C and 5.0 V.

2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.
Not all specifications are 100% tested.
3. VCCA and VCCD connected together.
4. XCLK pin only.
1
AC PARAMETERS (PACKAGED PARTS)

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

FS Sampling — ISD2532* 8.0 KHz (7)

Frequency — ISD2540* 6.4 KHz (7)
— ISD2548* 5.3 KHz (7)
— ISD2564* 4.0 KHz (7)
— ISD2560 8.0 KHz (7)
— ISD2575 6.4 KHz (7)
— ISD2590 5.3 KHz (7)
— ISD25120 4.0 KHz (7)

FCF Filter Pass Band — ISD2532* 3.4 KHz 3 dB Roll-Off Point (3) (8)
— ISD2540* 2.7 KHz 3 dB Roll-Off Point (3) (8)
— ISD2548* 2.3 KHz 3 dB Roll-Off Point (3) (8)
— ISD2564* 1.7 KHz 3 dB Roll-Off Point (3) (8)
— ISD2560 3.4 KHz 3 dB Roll-Off Point (3) (8)
— ISD2575 2.7 KHz 3 dB Roll-Off Point (3) (8)
— ISD2590 2.3 KHz 3 dB Roll-Off Point (3) (8)
— ISD25120 1.7 KHz 3 dB Roll-Off Point (3) (8)

* Advance information: ISD2532/40/48/64 devices. 1–91

 ISD2500 Series Product Data Sheets

AC PARAMETERS (PACKAGED PARTS) – CONTINUED

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

TREC Record — ISD2532* 32.0 sec

Duration — ISD2540* 40.0 sec
— ISD2548* 48.0 sec
— ISD2564* 64.0 sec
— ISD2560 58.1 60.0 62.0 sec Commercial Operation
— ISD2560 56.5 60.0 63.8 sec Industrial Operation
— ISD2575 72.6 75.0 77.5 sec Commercial Operation
— ISD2575 70.7 75.0 79.7 sec Industrial Operation
— ISD2590 87.1 90.0 93.0 sec Commercial Operation
— ISD25120 116.1 120.0 123.9 sec Commercial Operation

TPLAY Playback — ISD2532* 32.0 sec (7)

Duration — ISD2540* 40.0 sec (7)
— ISD2548* 48.0 sec (7)
— ISD2564* 64.0 sec (7)
— ISD2560 58.1 60.0 62.0 sec Commercial Operation(7)
Industrial Operation(7)
-1 — ISD2560
— ISD2575
56.5
72.6
60.0
75.0
63.8
77.5
sec
sec Commercial Operation(7)
— ISD2575 70.7 75.0 79.7 sec Industrial Operation(7)
— ISD2590 87.1 90.0 93.0 sec Commercial Operation(7)
— ISD25120 116.1 120.0 123.9 sec Commercial Operation(7)

TCE CE Pulse Width 100 nsec

TSET Control/Address Setup Time 300 nsec

THOLD Control/Address Hold Time 0 nsec

TPUD Power-Up Delay — ISD2532* 25.0 msec

— ISD2540* 31.3 msec
— ISD2548* 37.5 msec
— ISD2564* 50.0 msec
— ISD2560 24.1 25.0 27.8 msec Commercial Operation
— ISD2560 23.5 25.0 28.5 msec Industrial Operation
— ISD2575 30.2 31.3 34.3 msec Commercial Operation
— ISD2575 29.3 31.3 35.2 msec Industrial Operation
— ISD2590 36.2 37.5 40.8 msec Commercial Operation
— ISD25120 48.2 50.0 53.6 msec Commercial Operation

TPDR PD Pulse — ISD2532* 25 msec

Width Record — ISD2540* 31.25 msec
— ISD2548* 37.5 msec
— ISD2564* 50.0 msec
— ISD2560 25 msec
— ISD2575 31.25 msec
— ISD2590 37.5 msec
— ISD25120 50.0 msec

1–92 * Advance information: ISD2532/40/48/64 devices.

 Product Data Sheets ISD2500 Series

AC PARAMETERS (PACKAGED PARTS) – CONTINUED

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

TPDP PD Pulse — ISD2532* 12.5 msec

Width Play — ISD2540* 15.625 msec
— ISD2548* 18.75 msec
— ISD2564* 25.0 msec
— ISD2560 12.5 msec
— ISD2575 15.625 msec
— ISD2590 18.75 msec
— ISD25120 25.0 msec

TPDS PD Pulse Width Static 100 nsec (6)

TPDH Power Down Hold 0 nsec

TEOM EOM Pulse Width — ISD2532* 12.5 msec

— ISD2540* 15.625 msec
— ISD2548* 18.75 msec
— ISD2564* 25.0 msec
— ISD2560 12.5 msec 1
— ISD2575 15.625 msec
— ISD2590 18.75 msec
— ISD25120 25.0 msec

TOVF Overflow Pulse Width 6.5 µsec

THD Total Harmonic Distortion 1 2 % @ 1 KHz

POUT Speaker Output Power 12.2 50 mW REXT = 16 Ω (4)

VOUT Voltage Across Speaker Pins 2.5 V p–p REXT = 600 Ω

VIN1 MIC Input Voltage 20 mV Peak-to-Peak (5)

VIN2 ANA IN Input Voltage 50 mV Peak-to-Peak

VIN3 Aux Input Voltage 1.25 V Peak-to-Peak;

REXT = 16 Ω

NOTES: 1. Typical values @ TA = 25° C and 5.0 V.

2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.
Not all specifications are 100% tested.
3. Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions).
4. From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT=12.2 mW, typical.
5. With 5.1 KΩ series resistor at ANA IN.
6. TPDS is required during a static condition, typically overflow.
7. Sampling Frequency and Playback Duration can vary as much as ± 2.25% over the commercial
temperature range and voltage range and ± 5% over the industrial temperature and voltage range.
For greater stability, an external clock can be utilized (see Pin Descriptions).
8. Filter specification applies to the antialiasing filter and the smoothing filter.

* Advance information: ISD2532/40/48/64 devices. 1–93

 ISD2500 Series Product Data Sheets

TYPICAL PARAMETER VARIATION WITH VOLTAGE AND TEMPERATURE

(PACKAGED PARTS)

RECORD MODE OPERATING CURRENT (ICC) STANDBY CURRENT (ISB)

25 1.2
Operating Current (mA)

1.0
20

Standby Current (µA)

0.8
15
0.6
10
0.4

5
0.2
-1
0 0
-40 25 70 85 -40 25 70 85
Temperature (C) Temperature (C)

TOTAL HARMONIC DISTORTION OSCILLATOR STABILITY

0.7 0.4

0.6 0.2
Percent Distortion (%)

Percent Change (%)

0.5 0

0.4 -0.2

0.3 -0.4

0.2 -0.6

0.1 -0.8

0 -1.0
-40 25 70 85 -40 25 70 85
Temperature (C) Temperature (C)

5.5 Volts 4.5 Volts

1–94 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

ABSOLUTE MAXIMUM RATINGS (DIE) OPERATING CONDITIONS (DIE)

Condition Value Condition Value

Junction temperature 150° C Commercial operating 0° C to +50° C

temperature range
Storage temperature range –65° C to +150° C
Supply voltage (VCC)(1) +4.5 V to +6.5 V
Voltage applied to any pad (VSS – 0.3 V) to
(VCC + 0.3 V) 0V
Ground voltage (VSS)(2)
Voltage applied to any pad (VSS – 1.0 V) to
(Input current limited to (VCC + 1.0 V) NOTES: 1. VCC = VCCA = VCCD.
+ 20 mA)
2. VSS = VSSA = VSSD.
VCC - VSS – 0.3 V to + 7.0 V

NOTE: Stresses above those listed may cause permanent

damage to the device. Exposure to the absolute
maximum ratings may affect device reliability.
Functional operation is not implied at these
conditions. 1
DC PARAMETERS (DIE)

Symbol Parameters Min(2) Typ (1) Max(2) Units Conditions

VIL Input Low Voltage 0.8 V

VIH Input High Voltage 2.0 V

VOL Output Low Voltage 0.4 V IOL = 4.0 mA

VOH Output High Voltage VCC–0.4 V IOH = – 10 µA

VOH1 OVF Output High Voltage 2.4 V IOH = – 1.6 mA

VOH2 EOM Output High Voltage VCC–1.0 VCC–0.8 V IOH = – 3.2 mA

ICC VCC Current (Operating) 25 30 mA REXT = ∞ (3)

ISB VCC Current (Standby) 1 10 µA (2)

IIL Input Leakage Current +1 µA

IILPD Input Current HIGH w/Pull 130 µA Force VCC (4)

Down
REXT Output Load Impedance 16 Ω Speaker Load

RMIC Preamp In Input Resistance 4 9 15 KΩ MIC and MIC REF Pads

RAUX AUX INput Resistance 5 11 20 KΩ

RANA IN ANA IN Input Resistance 2.3 3 5 KΩ

* Advance information: ISD2532/40/48/64 devices. 1–95

 ISD2500 Series Product Data Sheets

DC PARAMETERS (DIE) – CONTINUED

Symbol Parameters Min(2) Typ (1) Max(2) Units Conditions

APRE1 Preamp Gain 1 21 24 26 dB AGC = 0.0 V

APRE2 Preamp Gain 2 – 15 5 dB AGC = 2.5 V

AAUX AUX IN/SP+ Gain 0.98 1.0 V/V

AARP ANA IN to SP+/- Gain 21 23 26 dB

RAGC AGC Output Resistance 2.5 5 9.5 KΩ

NOTES: 1. Typical values @ TA = 25° C and 5.0 V.

2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.
Not all specifications are 100% tested.
3. VCCA and VCCD connected together.
4. XCLK pad only.

-1 AC PARAMETERS (DIE)

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

FS Sampling — ISD2532* 8.0 KHz (7)

Frequency — ISD2540* 6.4 KHz (7)
— ISD2548* 5.3 KHz (7)
— ISD2564* 4.0 KHz (7)
— ISD2560 8.0 KHz (7)
— ISD2575 6.4 KHz (7)
— ISD2590 5.3 KHz (7)
— ISD25120 4.0 KHz (7)

FCF Filter Pass Band — ISD2532* 3.4 KHz 3 dB Roll-Off Point (3) (8)
— ISD2540* 2.7 KHz 3 dB Roll-Off Point (3) (8)
— ISD2548* 2.3 KHz 3 dB Roll-Off Point (3) (8)
— ISD2564* 1.7 KHz 3 dB Roll-Off Point (3) (8)
— ISD2560 3.4 KHz 3 dB Roll-Off Point (3) (8)
— ISD2575 2.7 KHz 3 dB Roll-Off Point (3) (8)
— ISD2590 2.3 KHz 3 dB Roll-Off Point (3) (8)
— ISD25120 1.7 KHz 3 dB Roll-Off Point (3) (8)

TREC Record — ISD2532* 32.0 sec

Duration — ISD2540* 40.0 sec
— ISD2548* 48.0 sec
— ISD2564* 64.0 sec
— ISD2560 58.1 60.0 62.0 sec Commercial Operation
— ISD2575 72.6 75.0 77.5 sec Commercial Operation
— ISD2590 87.1 90.0 93.0 sec Commercial Operation
— ISD25120 116.1 120.0 123.9 sec Commercial Operation

1–96 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

AC PARAMETERS (DIE) – CONTINUED

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

TPLAY Playback — ISD2532* 32.0 sec (7)

Duration — ISD2540* 40.0 sec (7)
— ISD2548* 48.0 sec (7)
— ISD2564* 64.0 sec (7)
— ISD2560 58.1 60.0 62.0 sec Commercial Operation(7)
— ISD2575 72.6 75.0 77.5 sec Commercial Operation(7)
— ISD2590 87.1 90.0 93.0 sec Commercial Operation(7)
— ISD25120 116.1 120.0 123.9 sec Commercial Operation(7)

TCE CE Pulse Width 100 nsec

TSET Control/Address Setup Time 300 nsec

THOLD Control/Address Hold Time 0 nsec

TPUD Power-Up Delay — ISD2532* 25.0 msec

— ISD2540* 31.3 msec
— ISD2548*
— ISD2564*
37.5
50.0
msec
msec
1
— ISD2560 24.1 25.0 27.8 msec Commercial Operation
— ISD2575 30.2 31.3 34.3 msec Commercial Operation
— ISD2590 36.2 37.5 40.8 msec Commercial Operation
— ISD25120 48.2 50.0 53.6 msec Commercial Operation

TPDR PD Pulse — ISD2532* 25 msec

Width Record — ISD2540* 31.25 msec
— ISD2548* 37.5 msec
— ISD2564* 50.0 msec
— ISD2560 25 msec
— ISD2575 31.25 msec
— ISD2590 37.5 msec
— ISD25120 50.0 msec

TPDP PD Pulse — ISD2532* 12.5 msec

Width Play — ISD2540* 15.625 msec
— ISD2548* 18.75 msec
— ISD2564* 25.0 msec
— ISD2560 12.5 msec
— ISD2575 15.625 msec
— ISD2590 18.75 msec
— ISD25120 25.0 msec

TPDS PD Pulse Width Static 100 nsec (6)

TPDH Power Down Hold 0 nsec

* Advance information: ISD2532/40/48/64 devices. 1–97

 ISD2500 Series Product Data Sheets

AC PARAMETERS (DIE) – CONTINUED

Symbol Characteristic Min(2) Typ (1) Max(2) Units Conditions

TEOM EOM Pulse Width — ISD2532* 12.5 msec

— ISD2540* 15.625 msec
— ISD2548* 18.75 msec
— ISD2564* 25.0 msec
— ISD2560 12.5 msec
— ISD2575 15.625 msec
— ISD2590 18.75 msec
— ISD25120 25.0 msec

TOVF Overflow Pulse Width 6.5 µsec

THD Total Harmonic Distortion 1 3 % @ 1 KHz

POUT Speaker Output Power 12.2 50 mW REXT = 16 Ω (4)

VOUT Voltage Across Speaker Pins 2.5 V p–p REXT = 600 Ω

-1 VIN1 MIC Input Voltage 20 mV Peak-to-Peak (5)

VIN2 ANA IN Input Voltage 50 mV Peak-to-Peak

VIN3 Aux Input Voltage 1.25 V Peak-to-Peak;

REXT = 16 Ω

NOTES: 1. Typical values @ TA = 25° C and 5.0 V.

2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization.
Not all specifications are 100% tested.
3. Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions).
4. From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT=12.2 mW, typical.
5. With 5.1 KΩ series resistor at ANA IN.
6. TPDS is required during a static condition, typically overflow.
7. Sampling Frequency and Playback Duration can vary as much as ± 2.25% over the commercial temperature range
and voltage range. For greater stability, an external clock can be utilized (see Pin Descriptions).
8. Filter specification applies to the antialiasing filter and the smoothing filter.

1–98 * Advance information: ISD2532/40/48/64 devices.

 Product Data Sheets ISD2500 Series

TYPICAL PARAMETER VARIATION WITH VOLTAGE AND TEMPERATURE (DIE)

RECORD MODE OPERATING CURRENT (ICC) STANDBY CURRENT (ISB)

30 1.0
Operating Current (mA)

25
0.8

Standby Current (µA)

20
0.6
15
0.4
10

0.2
5
1
0 0
0 25 50 0 25 50

Temperature (C) Temperature (C)

TOTAL HARMONIC DISTORTION OSCILLATOR STABILITY

0.7 0.2

0.6 0
Percent Distortion (%)

Percent Change (%)

0.5
-0.2
0.4
-0.4
0.3
-0.6
0.2

0.1 -0.8

0 -1.0
0 25 50 0 25 50

Temperature (C) Temperature (C)

6.5 Volts 5.5 Volts 4.5 Volts

* Advance information: ISD2532/40/48/64 devices. 1–99

 ISD2500 Series Product Data Sheets

ISD2500 APPLICATION EXAMPLE – DESIGN SCHEMATIC

ISD2500 (PDIP/SOIC) V CC
1
A0 VCCD 28
V CC VSS
2
A1 VCCA 16 C8
3 C6
A2 0.1 µF C7
12 22 µF
4
A3 VSSD 0.1 µF
5 13
R4 A4 VSSA
100 KΩ 6
A5
7 14
A6 SP+
8 15
A7 (NC*) SP–
CHIP ENABLE 9 11
A8 (A7*) AUX IN
10 20 16 Ω
A9 (A8*) ANA IN SPEAKER
C3
23 ANA OUT 21 0.1 µF
POWER DOWN CE
24
PD R 6 5.1 KΩ
27 18
P/R MIC REF**
25 17
EOM MIC
PLAYBACK/RECORD 22 C1
OVF V CC
26 19 0.1 µF
-1 XCLK AGC
C5
0.1 µF
R1 R3
1 KΩ 10 KΩ
R2 C2
470 KΩ 4.7 µF ELECTRET R5
C4 MICROPHONE
10 KΩ
220 µF

NOTES: * Pin identifications for the ISD2532/40/48/64 devices which differ from those of the ISD2560/75/90/120 devices are
indicated.
** If desired, pin 18 (PDIP package) may be left unconnected (microphone preamplifier noise will be higher). In this case,
pin 18 must not be tied to any other signal or voltage. Additional design example schematics are provided in the
Application Notes and Design Manual in this book.

APPLICATION EXAMPLE – BASIC DEVICE CONTROL

Control Step Function Action

1 Power up chip and select Record/Playback mode 1. PD = LOW, 2. P/R = As desired

2 Set message address for Record/Playback Set addresses A0–A9

3A Begin Playback P/R = HIGH, CE = Pulsed LOW

3B Begin Record P/R = LOW, CE = LOW

4A End Playback Automatic

4B End Record PD or CE = HIGH

1–100 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

APPLICATION EXAMPLE – PASSIVE COMPONENT FUNCTIONS

Part Function Comments

R1 Microphone power supply Reduces power supply noise

decoupling

R2 Release time constant Sets release time for AGC

R3, R5 Microphone biasing resistors Provides biasing for microphone operation

R4 Series limiting resistor Reduces level to prevent distortion at higher supply

voltages.

R6 Series limiting resistor Reduces level to high supply voltages

C1, C5 Microphone DC–blocking capacitor Decouples microphone bias from chip. Provides single-
Low-frequency cutoff pole low-frequency cutoff and common mode noise
rejection.

C2 Attack/Release time constant Sets attack/release time for AGC

C3

C4
Low-frequency cutoff capacitor

Microphone power supply

Provides additional pole for low-frequency cutoff

Reduces power supply noise

1
decoupling

C6, C7, C8 Power supply capacitors Filter and bypass of power supply

EXPLANATION
In this simplified block diagram of a microcontroller NOTE
application, the Push-Button mode and message ISD does not recomend connecting
cueing are used. The microcontroller is a 16-pin address lines directly to a microprocessor
version with enough port pins for buttons, an LED, bus. Address lines should be externally
and the ISD2500 Series device. The software can latched.
be written to use three buttons: one each for play
and record, and one for message selection.
Because the microcontroller is interpreting the but-
tons and commanding the ISD2500 device,
software can be written for any functions desired in
a particular application.

* Advance information: ISD2532/40/48/64 devices. 1–101

 ISD2500 Series Product Data Sheets

ISD2500 APPLICATION EXAMPLE – MICROCONTROLLER/ISD2500 INTERFACE

V CC

D1
S1 S2 S3
RUN
RECORD PLAY MSG#
MC68HC705K1A
ISD2500 (PDIP/SOIC)
OSC1 PB0
1 28
OSC2 PB1 A0 CCD
2 16
A1 CCA
R1 3
RESET PA0 A2
TBD 4 12
IRQ PA1 A3 SSD
5 13
U1 PA2 A4 SSA
6 U2
PA3 A5
7 14
VDD PA4 A6
8 15
PA5 A7 (NC*)
9 11
V SS PA6 A8 (A7*)
10 20
PA7 A9 (A8*)
-1 23
CE
21
24
PD
27 18
P/R
25 17
EOM
22
OVF
26 19
XCLK

NOTES: * Pin identifications for the ISD2532/40/48/64 devices which differ from those of the
ISD2560/75/90/120 devices are indicated.

1–102 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

ISD2500 APPLICATION EXAMPLE – PUSH-BUTTON

ISD2500 (PDIP/SOIC) V CC
1
A0 VCCD 28
V CC
VSS
2
A1 VCCA 16
3 C4 C5
A2
0.1 µF C1 22 µF
4
A3 VSSD 12 0.1 µF
R6 R7 5 13
V CC A4 VSSA
100 KΩ 100 KΩ 6
A5
V CC LS1
7 14
S1 A6 SP+
8 15
A7 (NC*) SP–
9 11
START/PAUSE A8 (A7*) AUX IN 16 Ω
10 20 SPEAKER
A9 (A8*) ANA IN
S2 C3
23 21 0.1 µF
STOP/RESET CE ANA OUT
24
PD R 4 5.1 KΩ
27 18
P/R MIC REF
25 17
EOM MIC
PLAYBACK/RECORD 22
OVF V CC C1
19
26 0.1 µF
XCLK AGC
C5
0.1 µF
1
R3
10 KΩ
R2 C2
470 KΩ 4.7 µF ELECTRET R5
C4 MICROPHONE
10 KΩ
220 µF

NOTES: * Pin identifications for the ISD2532/40/48/64 devices which differ from those of the
ISD2560/75/90/120 devices are indicated.
** For more details, please refer to the ISD Application Notes and Design Manual.

APPLICATION EXAMPLE – PUSH-BUTTON CONTROL

Control Step Function Action

1 Select Record/Playback mode P/R = As desired

2A Begin Playback P/R = HIGH

CE = Pulsed LOW
2B Begin Record P/R = LOW
CE = Pulsed LOW

3 Pause Record or Playback CE = Pulsed LOW

4A End Payback Automatic at EOM marker or

PD = Pulsed HIGH
4B End Record PD = Pulsed HIGH

* Advance information: ISD2532/40/48/64 devices. 1–103

 ISD2500 Series Product Data Sheets

APPLICATION EXAMPLE – PASSIVE COMPONENT FUNCTIONS

Part Function Comments

R2 Release time constant Sets release time for AGC

R4 Series limiting resistor Reduces level to prevent distortion at

higher supply voltages

R6, R7 Pull-up and pull-down resistors Defines static state of inputs

C1, C4, C5 Power supply capacitors Filters and bypass of power supply

C2 Attack/Release time constant Sets attack/release time for AGC

C3 Low-frequency cutoff capacitor Provides additional pole for low-

frequency cutoff

PUSH-BUTTON PARAMETERS
-1
Symbol Characteristic Min Typ (1) Max Units Conditions

TCE CE Pulse Width [Start/Pause] 300 nsec

TSET Control/Address Setup Time 300 nsec

TPUD Power-Up Delay — ISD2532* 25 msec

— ISD2540* 31.25 msec
— ISD2548* 37.25 msec
— ISD2564* 50.0 msec
— ISD2560 25 msec
— ISD2575 31.25 msec
— ISD2590 37.25 msec
— ISD25120 50.0 msec

TPD PD Pulse Width [Stop/Reset] 300 nsec

TRUN CE to EOM HIGH 25 400 nsec

TPAUSE CE to EOM LOW 50 400 nsec

TDB CE HIGH — ISD2532* 70 105 msec

Debounce — ISD2540* 85 135 msec
— ISD2548* 105 160 msec
— ISD2564* 135 215 msec
— ISD2560 70 105 msec
— ISD2575 85 135 msec
— ISD2590 105 160 msec
— ISD25120 135 215 msec

1–104 * Advance information: ISD2532/40/48/64 devices.

Product Data Sheets ISD2500 Series

TIMING DIAGRAMS
Push-Button Mode Record

"Start" "Pause" "Start" "Stop"

TCE TCE TCE
CE
(Start/Pause) TSET TSET TSET
P/R

TSET TPD TSET

PD
(Stop/Reset)
TSET
A0-A9

MIC ANA IN

OVF
TRUN TPAUSE
EOM
(Run)
TDB TDB
TDB
TPUD
Notes: (1) (2) (3) (4, 5)
TPUD
(6, 7) (8) 1
Push-Button Mode Playback

"Start" "Pause" "Start" "Stop"

TCE TCE TCE

CE
(Start/Pause) TSET TSET TSET
P/R

TSET TPD TSET

PD
(Stop/Reset)
TSET
A0-A9

SP+/–

OVF
TRUN TPAUSE
EOM
(Run) TDB TDB TDB
TPUD TPUD
Notes: (1) (2) (3) (4, 5) (6, 7) (8)

NOTES: 1. A9, A8, and A6 = 1 for push-button operation.

2. The first CE LOW pulse performs a Start function.
3. The part will begin to play or record after a power-up delay TPUD.
4. The part must have CE HIGH for a debounce period TDB before it will recognize another falling edge of
CE and pause.
5. The second CE LOW pulse, and every even pulse thereafter, performs a Pause function.
6. Again, the part must have CE HIGH for a debounce period TDB before it will recognize another falling
edge of CE, which would restart an operation. In addition, the part will not do an internal power down until
CE is HIGH for the TDB time.
7. The third CE LOW pulse, and every odd pulse thereafter, performs a Resume function.
8. At any time, a HIGH level on PD will stop the current function, reset the address counter, and power down
the device.

* Advance information: ISD2532/40/48/64 devices. 1–105

 ISD2500 Series Product Data Sheets

ORDERING INFORMATION

Product Number Descriptor Key

ISD25 _ _ _ _

2 = 2nd Generation Special Temperature Field:

Blank = Commercial Packaged (0˚C to +70˚C)
5 = 5 Volts
or Commercial Die (0˚C to +50˚C)
Duration: I = Industrial (-40˚C to +85˚C)
32 = 32 Seconds*
40 = 40 Seconds* Package Type:
48 = 48 Seconds* E = 28-Lead 8x13.4-mm Thin Small Outline Package
(TSOP)
64 = 64 Seconds*
P = 28-Lead 0.600-Inch Plastic Dual In-Line Package
60 = 60 Seconds (PDIP)
-1 75 = 75 Seconds
90 = 90 Seconds
S = 28-Lead 0.300-Inch Small Outline Integrated Circuit
(SOIC)
120 = 120 Seconds T = 32-Lead 8x20-mm Thin Small Outline Package
(TSOP)
X = Die

When ordering ISD2500 Series devices, please refer to the following valid part numbers.

Part Number Part Number Part Number Part Number

ISD2560E ISD2575E ISD2590E ISD25120P

ISD2560EI ISD2575EI ISD2590P ISD25120X

ISD2560P ISD2575P ISD2590S

ISD2560PI ISD2575PI ISD2590T

ISD2560S ISD2575S ISD2590X

ISD2560SI ISD2575SI

ISD2560T ISD2575T

ISD2560TI ISD2575TI

ISD2560X ISD2575X

For the latest product information, access ISD’s worldwide website at http://www.isd.com.

1–106 * Advance information: ISD2532/40/48/64 devices.