IPC-7093

Design and Assembly

Process Implementation
for Bottom Termination
SMT Components

Developed by the IPC Bottom Termination Components (BTC) Task

Group (5-21h) of the Assembly & Joining Processes Committee (5-20)
of IPC

Users of this publication are encouraged to participate in the

development of future revisions.

Contact:

IPC
3000 Lakeside Drive, Suite 309S
Bannockburn, Illinois
60015-1249
Tel 847 615.7100
Fax 847 615.7105
March 2011 IPC-7093

Table of Contents
1 SCOPE ......................................................................1 4.5.3 Marking Alternatives ...........................................24
1.1 Purpose ................................................................1 4.5.4 Materials Used ....................................................24
1.2 Intent ....................................................................1 4.6 Description of Commercial Variations ..................24
4.6.1 Detailed Description of MLF®, MLP, and
2 APPLICABLE DOCUMENTS ....................................1
MLFP™ Components ..........................................25
2.1 IPC ......................................................................1
4.6.2 Detailed Description of LLC™ and LFCSP™
2.2 JEDEC .................................................................2 Components ........................................................27
4.7 Packaging and Handling ......................................30
3 SELECTION CRITERIA AND MANAGING BTC
IMPLEMENTATION ...................................................2
5 MOUNTING STRUCTURES ....................................31
3.1 Terms and Definitions ...........................................2
5.1 Types of Mounting Structures ..............................31
3.1.1 Bottom Termination Components (BTC) ................2
5.1.1 Organic Resin Systems ........................................31
3.1.2 Component Mounting Site .....................................2
5.1.2 Inorganic Structures ............................................31
3.1.3 Conductive Pattern* ..............................................2
5.1.3 Layering (Multilayer, Sequential or Build-Up
3.1.4 Land Pattern* .......................................................2 and HDI) ............................................................31
3.1.5 Mixed Component-Mounting Technology* .............2 5.2 Properties of Mounting Structures ........................31
3.1.6 Printed Board Assembly ........................................2 5.2.1 Resin Systems .....................................................32
3.1.7 Surface Mounting Technology (SMT)* ...................2 5.2.2 Reinforcements ...................................................32
3.2 BTC Executive Summary ......................................2 5.2.3 Reliability Concerns with High Temperature
3.3 Description of Different Component Lead-Free Soldering ............................................32
Structures ...........................................................3 5.2.4 Thermal Expansion .............................................33
3.4 Total Cost of Ownership ........................................6 5.2.5 Moisture Absorption ............................................33
3.5 Design and Assembly Process Considerations 5.2.6 Flatness (Bow and Twist) ....................................34
for QFN Type BTC Packages ................................6
5.3 Surface Finishes ..................................................34
3.6 Future Needs and Expectations ..............................8
5.3.1 Hot Air Solder Leveling (HASL) .........................35
4 COMPONENT CONSIDERATIONS ..........................8 5.3.2 Organic Surface Protection (Organic Solder-
4.1 General Description of Different BTC ability Preservative) Coatings ...............................36
Packages ...............................................................8 5.3.3 Noble Metal Platings/Coatings .............................36
4.2 Detailed Description and Standards for 5.4 Solder Mask .......................................................38
BTCs ...................................................................9
5.4.1 Wet and Dry Film Solder Masks ..........................38
4.2.1 Single Row Molded Lead-Frame Based
Packaging ............................................................9 5.4.2 Photoimageable Solder Masks ..............................40
4.2.2 Multiple Row Molded Lead-Frame Based 5.4.3 Registration ........................................................41
Packaging .............................................................9 5.4.4 Via Protection .....................................................41
4.2.3 JEDEC Publication 95 Design Guide 4.8 ..............10 5.5 Thermal Spreader Structure Incorporation (e.g.,
4.2.4 JEDEC Publication 95 Design Guide 4.23 ............12 Metal Core Boards) .............................................44

4.2.5 JEDEC Publication 95 Design Guide 4.19 ............15 5.5.1 Lamination Sequences .........................................44
4.3 Detailed Description of QFN and SON 5.5.2 Heat Transfer Pathway ........................................44
(DFN) Packages ..................................................17 5.5.3 Thermal Pad Attachment .....................................44
4.3.1 Manufacturing Methods .......................................17 5.5.4 Thermal Vias ......................................................45
4.3.2 Types of Defects .................................................21 5.6 Solderless Interconnections Systems .....................45
4.3.3 Marking Alternatives ...........................................21
6 PRINTED CIRCUIT ASSEMBLY DESIGN
4.3.4 Materials Used ....................................................21 CONSIDERATIONS .................................................46
4.3.5 Solderability Testing ............................................21 6.1 BTC Part Description ..........................................46
4.4 Custom QFN and SON (DFN) .............................21 6.1.1 BTC Package Variations ......................................46
4.5 Detailed Description of LGA, QFN and
6.1.2 Termination Formats ...........................................48
SON (DFN) Substrate-Based Packages .................23
6.1.3 Mounting Conditions ...........................................48
4.5.1 Manufacturing Methods for Substrate-
Based Packages ...................................................23 6.1.4 Package Tolerances .............................................54
4.5.2 Types of Defects .................................................24 6.1.5 Attachment Techniques ........................................57

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IPC-7093 March 2011

7 ASSEMBLY OF BTCs ON PRINTED 8.2.3 Mold Compound Material ....................................85

BOARDS ..................................................................60 8.2.4 Die Size .............................................................85
7.1 PCB Surface Finish Requirements ........................60 8.2.5 Full vs. Half Etched Leadframe ...........................85
7.2 PCB Design ........................................................61 8.2.6 Gold/Silver/Palladium Embrittlement ....................85
7.2.1 Consideration for Soldering Process .....................61 8.2.7 Stand-Off Height .................................................85
7.2.2 Component Preconditioning Bake ........................62 8.3 PCB Design Considerations .................................85
7.2.3 Component Preparation for Assembly ...................62 8.3.1 Land Size ...........................................................85
7.2.4 Solder Paste and its Application ...........................62 8.3.2 Fillet Formation ..................................................86
7.2.5 Component Placement Impact ..............................65 8.3.3 Board Thickness .................................................87
7.2.6 Reflow Soldering and Profiling ............................66 8.4 Voids in Thermal Pad ..........................................87
7.2.7 Reflow Process Impact on Material ......................68 8.5 Design for Reliability (DfR) Process ....................87
7.2.8 Vapor Phase ........................................................69 8.5.1 Wear-Out Mechanisms ........................................88
7.2.9 Cleaning vs. No-Clean ........................................70 8.5.2 Creep-Fatigue Interaction .....................................88
7.2.10 Package Standoff .................................................70 8.5.3 Solder Thickness Mechanical Reliability ..............89
7.3 Post-SMT Processes ............................................71 8.6 Wear-Out Mechanisms Review ............................90
7.3.1 Conformal Coatings ............................................71 8.6.1 Reliability Factors ...............................................90
7.3.2 Use of Underfills and Adhesives ..........................71 8.6.2 Benefits of Reinforcement ...................................90
7.3.3 Depaneling of Boards and Modules ......................71 8.6.3 Event Related Failures .........................................91
7.4 Inspection Techniques .........................................71 8.7 Design for Reliability Issues and Concerns ...........91
7.4.1 X-Ray Usage ......................................................72 8.7.1 Damage Mechanisms and Failure of Solder
7.4.2 Scanning Acoustic Microscopy ............................72 Attachments ........................................................91
7.4.3 BTC Standoff Measurement .................................72 8.7.2 Solder Joints and Attachment Types .....................91
7.4.4 Optical Inspection ...............................................73 8.7.3 Solder Interface Grain Structure Effects ................92
7.4.5 Destructive Analysis Methods ..............................73 8.7.4 Global Expansion Mismatch ................................92
7.5 Testing and Product Verification ...........................74 8.7.5 Local Expansion Mismatch ..................................92
7.5.1 Electrical Testing ................................................74 8.7.6 Internal Expansion Mismatch ...............................93
7.5.2 Test Coverage .....................................................75 8.8 Solder Attachment Failure ...................................93
7.5.3 Burn-In Testing ...................................................75 8.9 Validation and Qualification Tests ........................93
7.5.4 Product Screening Tests .......................................75 8.10 Screening Procedures ..........................................93
7.6 Assembly Process Control Criteria for 8.10.1 Solder Joint Defects ............................................93
Plastic BTCs ......................................................75 8.10.2 Screening Recommendations ................................93
7.6.1 Voids in BTC Solder Joints .................................75
7.6.2 Solder Bridging ...................................................76 9 DEFECT AND FAILURE ANALYSIS
CASE STUDIES ......................................................94
7.6.3 Opens .................................................................77
9.1 Solder Attachment Failures ..................................94
7.6.4 Cold Solder ........................................................78
9.1.1 Solder Attachment Failure Conditions ..................94
7.6.5 Defect Correlation/Process Improvement ..............78
9.1.2 Insufficient Solder Failures ..................................94
7.6.6 Effect of Insufficient and/or Uneven Heating ........78
9.1.3 Land, Nonsolderable ...........................................95
7.6.7 BTC Component Solderability Testing .................78
9.1.4 Termination, Nonsolderable .................................95
7.6.8 Solder Ball Defects .............................................78
9.2 Package Failures .................................................95
7.7 Repair Processes .................................................78
7.7.1 Rework/Repair Philosophy ...................................78 9.2.1 Package Warpage ................................................95

7.7.2 Removal of BTC .................................................79 9.3 Dewetting Failures ..............................................96

7.7.3 BTC Assembly Defect Repair ..............................79 9.3.1 Dewetting on QFN ..............................................96
9.4 Cracked Solder Joint Failure ................................96
8 RELIABILITY ...........................................................83 9.4.1 Cracks in Solder Joints ........................................96
8.1 Accelerated Reliability Testing .............................83 9.5 Component Failures ............................................97
8.2 Damage Mechanisms and Failure of 9.5.1 Tilted Component ...............................................97
Solder Attachments .............................................83
9.5.2 Lead Configuration Conditions .............................97
8.2.1 Differences in Accelerated Testing of
SAC vs. Tin/Lead ...............................................84 9.5.3 Joint Configuration Condition ..............................98
8.2.2 Mixed Alloy Soldering ........................................85 9.5.4 Solder Joint Volume ............................................98

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March 2011 IPC-7093

9.6 Voids ..................................................................99 Figure 4–16 Two and Three Row QFN Package Examples ..16
9.6.1 Voids in Solder Joint Through Xray .....................99 Figure 4–17 Basic Two Row Terminal Layout Variations .....16
9.6.2 Voids in Solder Joints Microsection Figure 4–18 Basic Three Row Terminal Layout Variations ...17
and X-Ray ..........................................................99 Figure 4–19 Contact Geometry Variations ...........................17
9.6.3 Voids in Thermal Pad ........................................100 Figure 4–20 Basic QFN Package Outline Drawing ..............17
10 GLOSSARY AND ACRONYMS ............................101 Figure 4–21 Pin 1 Location Option .....................................18
Figure 4–22 BTC Multiple Package Configurations .............18
11 BIBLIOGRAPHY AND REFERENCES .................101
Figure 4–23 Typical Die Attach Side Leadframe with Ni-
APPENDIX A ................................................................102 PdAu Finish for QFNs ....................................18
Figure 4–24 Typical Solder Pad Side of QFN Panel for
APPENDIX B ................................................................105 with Tape over the Leadframe .........................18
Figure 4–25 QFN Fabrication with Saw Singulation ............19
Figures Figure 4–26 Overmolded Leadframe Configuration ..............19
Figure 3-1 Discrete General Types of Bottom-Only Figure 4–27 QFN Fabrication with Punch Singulation .........20
Terminations .....................................................3
Figure 4–28 Comparing Punch-Press and Saw-Cut
Figure 3-2 Quad Flat No Lead Type Bottom-Only Singulation and Illustrating Wire Bond
Terminations .....................................................4 Options ..........................................................20
Figure 3-3 Small Outline No Lead Type Bottom-Only Figure 4–29 Example of Half Etch Pullback Contact
Terminations .....................................................4 and Full Etch No-Pullback Perimeter
Figure 3-4 Land Grid Array Type Bottom-Only Contact Configurations ....................................21
Terminations .....................................................4 Figure 4–30 Plating Layer Construction Comparison ...........23
Figure 3-5 Typical QFN Cross-Section ...............................5 Figure 4–31 Detailed View of a Custom Site for a QFN ......23
Figure 3-6 Saw Singulated (a, b) BTC Package ..................6 Figure 4–32 Bottom View of Land Grid Array
Figure 3-7 MLF Package Thickness When Compared to Printed Board .................................................24
Other Types of Packages ...................................6 Figure 4–33 Top View of Land Grid Array Printed Board ....24
Figure 3-8 Solder Mask Clearance Guideline for BTCs .......7 Figure 4–34 BTC Fabrication on a Substrate with Saw
Figure 3-9 Example of Segmented Stencil Pattern Design Singulation .....................................................25
on Thermal Land ..............................................7 Figure 4–35 Amkor’s 28 I/O MicroLeadFrame® Package .....27
Figure 3-10 Recommended Stencil Design to Provide Figure 4-36 Fairchild’s MLP is a Thermally Enhanced
50–60% Paste Coverage to Ground Lands SON Developed for Power Switch
(but 100% on I/O lands) ...................................8 Technology .....................................................27
Figure 4-1 Various Forms of BTC Parts .............................9 Figure 4–37 Intersil’s Quad No-lead Micro Leadframe
Figure 4-2 Singulated LGA Showing Bottom of Part .........10 Plastic Package (MLFP) ..................................27
Figure 4-3 Basic Single Row Lead-Frame Based SON- Figure 4–38 JEDEC MO-220 Package Outline ....................28
QFN Package Assembly Model .......................10 Figure 4–39 QFN Contact Design .......................................28
Figure 4-4 Basic Multiple Row QFN Package Assembly Figure 4–40 Analog Devices LFCSP™ (Leadframe
Model ............................................................10 Chip-Scale Package) .......................................29
Figure 4-5 Terminal Configuration for Single Row SON Figure 4–41 National Semiconductor LLP™ (Leadless
and QFN Packaging ........................................10 Package) ........................................................29
Figure 4-6 JEDEC Defined Package Outlines for Single Figure 4–42 Typical LLC and LFCSP Outline Detail ...........30
Row SON and QFN Packaging .......................11
Figure 4–43 JEDEC Tray Carrier Format ............................30
Figure 4-7 Terminal Design Variations for Single Row
SON and QFN Packaging ...............................12 Figure 5-1 Typical Build-Up HDI Platform, 2[4]2
Layer Configuration ........................................31
Figure 4-8 Odd and Even Terminal Contact Layout ..........12
Figure 5-2 Material Thermal Expansion Comparison .........34
Figure 4-9 Depopulation Schemes for Single Row
QFN Packaging ..............................................13 Figure 5–3 SSD Application Basic Fabrication Steps .........39
Figure 4–10 Corner Terminals and Exposed Heat Spreader ..13 Figure 5-4 SSD Process Steps ..........................................40
Figure 4–11 Fine-Pitch Two Row QFN (No lead) Figure 5-5 Comparing Solder Mask off Via Land with
Packaging .......................................................13 a Solder Mask Encroached Via Land ...............41
Figure 4–12 QFN Dual Row Package (top and side views) ..14 Figure 5-6 Planarized and Capped Via Protection
Example .........................................................42
Figure 4–13 Outer and Inner Terminal Layout Variations .....15
Figure 5-7 Via Protection Methods ...................................43
Figure 4–14 Two Row Terminal Layout ..............................15
Figure 4–15 The Notch Feature on the Exposed Die Figure 5-8 Metal Core Board Construction Examples ........44
Attach Pad Confirms Package Orientation Figure 5–9 Examples of Type VII Filled
with Reference to the A1 and B1 Terminals .....15 and Capped Vias .............................................. 45
...

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IPC-7093 March 2011

Figure 5-10 Example of Circuit Development of Solderless Figure 7-9 Metal Defined Land Solder Joint .....................66
Connection Technology .............................. 45
. Figure 7-10 Profile for Tin/Lead Solder Reflow ..................68
Figure 6-1 Family of Bottom Termination Components Figure 7-11 Profile for SAC Alloy Solder Reflow ...............68
(BTC) ............................................................47
Figure 7-12 SAC Alloy Flow Characteristics ......................71
Figure 6-2 QFN Bottom Termination Component
Lead-Frame Array ...........................................47 Figure 7-13 Post Assembly Contact and DAP Solder
Joint Profile ....................................................71
Figure 6-3 Comparing Pullback and No-Pullback
Configurations ................................................48 Figure 7-14 X-Ray Images Using Various Techniques to
Detect Missing Solder .....................................72
Figure 6-4 Land Pattern and DAP Land Layout Guide ......49
Figure 7-15 Typical X-Ray After Process ...........................73
Figure 6-5 Basic Outline Drawing for the 6 I/O SON .......49
Figure 7-16 Wire-bond X-Ray to Leadframe Illustration .....73
Figure 6-6 Recommended Land Pattern for JEDEC 6
I/O SON Package ...........................................50 Figure 7–17 Scanning Acoustic Microscopy ........................74
Figure 6-7 QFN Component and Land Pattern Figure 7-18 Typical Thermal Plane Voiding ........................75
Composite ......................................................50 Figure 7-19 Solder Paste Segments vs. Solder Paste Dots
Figure 6-8 Definition of Toe, Heel and Side Fillets ...........50 Printed over Plugged Thermal Vias ..................76
Figure 6-9 Comparing Pull Back to no-Pull Back Figure 7-20 X-Ray Images Showing Solder Segment and
Package Outline and Land Pattern Thermal Solder Dot Voiding Results .............................77
Land Layout ...................................................53 Figure 7-21 Solder Paste Printing Strategy: Segments
Figure 6–10 SON 0.5 mm Pitch, 6 Pin with Thermal Tab ....54 (left) vs. Solder Dots (right) ............................77
Figure 6-11 DAP to PCB Interface Example ......................54 Figure 7-22 Solder Segments vs. Solder Dots – Void
Potential .........................................................77
Figure 6–12 The Affect of θJA vs. Number, Distribution and
Diameter of Thermal Vias and Die Sizes for Figure 7-23 Dip and Look Test ..........................................78
a 36 I/O QFN with a 9 x 9 mm Body and Figure 7-24 Process Simulation Test ..................................78
7x7 mm Thermal Land ...................................55
Figure 7–25 Solder is Heated to Liquidus State and
Figure 6–13 Comparing Optional Solder Mask Variations ....55
the BTC is Withdrawn Before Solder
Figure 6–14 Solder Mask for (A) Perimeter Lands for Re-Solidification .............................................80
0.5 mm and Higher Pitch Parts, and (B)
for 0.4 mm Pitch Parts ....................................55 Figure 7–26 Desoldering of the BTC Mounting Site ............80

Figure 6–15 Representative BTC Outline Detail ..................56 Figure 7-27 Typical Laser Ablated Stencil Aperture
Geometry .......................................................81
Figure 6–16 Effect of Number of Thermal Via on Package
Thermal Performance ......................................56 Figure 7-28 Example of Window Pane Pattern on Stencil ....81
Figure 6–17 PCB Thermal Pad and Via Array for 7x7 mm, Figure 7-29 Typical Metal Stencil for Printing onto
48 lead and 10x10 mm, 68 Lead Packages .......57 Component .....................................................81
Figure 6–18 Comparison of the 80% Rule with Standard Figure 7-30 BTC Device is Clamped into Stencil Fixture ....82
Grid Systems for Routing Improvement ..........57 Figure 7-31 Solder Paste is Transferred Through Stencil
Figure 6–19 Effect of Voids on Thermal Performance ..........58 Apertures onto the Undersurface Features
of the BTC .....................................................82
Figure 6–20 X-Ray Example Showing Voids in the
Thermal Pad ...................................................59 Figure 7-32 Typical Dispensing System ..............................82
Figure 6–21 Solder Protrusion from the Bottom Side of Figure 7-33 Solder Bumping Method Using a Stencil .........82
PCB for Encroached Vias ................................60 Figure 7–34 Alignment Stencil on PCB ..............................83
Figure 7-1 Example of Good Land Patterns for Bottom Figure 7–35 “Bumped” Part Placed and Reflowed ...............83
Termination Components .................................61
Figure 8-1 Plate-Up Bumped Option ................................85
Figure 7-2 Example of Poor Land Patterns for Bottom
Termination Components .................................61 Figure 8-2 Cracks in QFN Solder Joints after
Temperature Shock .........................................86
Figure 7-3 Comparison of Solder Dipped and a Non
Solder-Dipped BTC and Resultant No Solder Figure 8-3 Land Size Impact on Fatigue Life of 7 mm
Condition .......................................................62 BTC Package .................................................86
Figure 7-4 Undersized PCB Pads Resulting in Potential Figure 8-4 QFN with Wettable Flanks ..............................86
Areas Where Pure Tin Finish Has Not Mixed
Figure 8-5 Weibull Plot Showing Thinner Board Results
with SnPb Solder Paste ...................................63
in Higher Fatigue Life ....................................87
Figure 7-5 Recommended Aperture Dimensions for Figure 8-6 The Crack Formation is the Result of the
Commonly Used Stencil Thicknesses ...............64 CTE Mismatch ...............................................89
Figure 7-6 Thermal Pad Stencil Designs for 7x7 mm and Figure 8-7 Depiction of the Effects of Accumulating
10x10 mm BTC Devices .................................65 Fatigue Damage in the Solder Joint
Figure 7-7 Solder Stencil Aperture Wall Area ...................65 Structure ........................................................92
Figure 7-8 Assessing Maximum Pre-Reflow Off-Land Figure 8-8 Solder Crack Due to Cte Mismatch after
Acceptance .....................................................65 1000 Cycles ...................................................92

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March 2011 IPC-7093

Figure 9–1 Optical image of acceptable QFN edge Figure 9–26 16-pin QFN with voids in the joint and the
terminations. Solder fillets should exist if thermal pad but well within action level. .........99
the design incorporates pads that extend Figure 9–27 QFN component with increase level of
beyond the package width. ..............................94 voiding to above 30%. Could be a reliability
Figure 9–2 Optical image of acceptable QFN edge concern. .......................................................100
terminations. Solder fillets should be Figure 9–28 Acceptable Condition of QFN edge joints
visible to a minimum of 75% of the showing an increased level of voiding within
width of the termination. .................................94 the joints but well within any action level. .....100
Figure 9–3 Cross section of BTC open joint due to Figure B1-1 BTC Component (left) and PCB (right)
insufficient solder paste volume during after Part Removal ........................................106
printing. .........................................................94
Figure 9–4 Cross section of BTC reliability failure after
Tables
1000 cycles due to insufficient solder paste
volume during printing. ...................................94 Table 3-1 Total Cost of Ownership of Bottom
Figure 9–5 Nonsolderable land on LGA package. ..............95 Terminated Components (BTC) ..........................7
Figure 9–6 3-D X-ray shows non-wet joints on a QFN. .....95 Table 4-1 QFN and DFN Configurations ............................9
Figure 9–7 Optical image of unacceptable QFN edge Table 4-2 Terminal width variations for SON and QFN ....13
terminations. The solder rise is limited and Table 4-3 Body Outline and Maximum Terminal Count ....14
an open joint can be seen. The package is
Table 4-4 Leadframe Package Defects and Failure
also ‘floating’ above the surface of the pads. ....95
Modes .............................................................22
Figure 9–8 Cross section image of QFN with an open Table 4-5 Plating Systems Used on Metal Leadframes ......23
joint caused by nonwetting of the solder to
the bottom land of the QFN. ...........................95 Table 4-6 Substrate Based Package Defects and Failure
Modes .............................................................26
Figure 9–9 Cross section of LGA with a corner joint
failure. The paste wicked to the package. .........95 Table 4-7 Typical Package Outline and I/O for QFN ........29
Figure 9–10 Concave warpage on 15x15 mm BTC. .............95 Table 4-8 Contact Pitch and Width Variations ..................30
Figure 9–11 Good wetting on QFN thermal pad after Table 4-9 Basic Material Elements for the LLC and
printing and reflow. .........................................96 LFCSP Devices ...............................................30
Figure 9–12 Dewetting on QFN thermal pad after printing Table 5-1 Environmental Properties of Common
and reflow. .....................................................96 Dielectric Materials .........................................33

Figure 9–13 Defect Condition of QFN edge joints Table 5-2 Key Attributes for Various Board Surface
showing insufficient solder in a joint. ...............96 Finishes ..........................................................35
Table 5-3 Via filling/encroachment to surface finish
Figure 9–14 Cracks in QFN solder joints after process evaluation ...........................................42
temperature shock. ..........................................96
Table 6-1 Quad Flat No Lead Tolerance Goals for
Figure 9–15 Tilted BTC causing high joint height Solder Joint Formation .....................................51
open on the left. .............................................97
Table 6-2 Package and Land Pattern (Pullback and No-
Figure 9–16 Tilted BTC causing good height on the right. ...97 Pullback) Dimensions ......................................52
Figure 9–17 Full lead option on BTS component. ...............97 Table 6-3 Legend for Basic Mechanical Attributes ............54
Figure 9–18 Half etched option on BTS component. ...........97 Table 6-4 Contact Pitch and Width Variations ..................56
Figure 9–19 Small fillet due to nonwetting of the side Table 7-1 Particle Size Comparisons ................................63
copper. ...........................................................98 Table 7-2 Typical Reflow Profile for Eutectic
Figure 9–20 Side fillet on bottom termination component (63Sn/37Pb) Solder Paste .................................67
good wetting to copper lead. ...........................98 Table 7-3 Profile Comparison Between SnPb and
Figure 9–21 Large fillet due to increase of solder volume. ...98 SAC Alloys .....................................................67
Figure 9–22 No Side fillet on bottom termination Table 7-4 Typical Reflow Profile for Lead-Free
component. .....................................................98 (SAC305 or SAC405) Solder Paste ..................69

Figure 9–23 Target Condition of QFN edge joints where Table 7-5 Guidelines for Void Criteria in Thermal/
showing a moderate level of voiding within Ground Planes of BTCs ...................................76
joints is acceptable. All joints have reflowed. ...99 Table 8-1 Accelerated Testing for End Use
Environments ..................................................84
Figure 9–24 Acceptable Condition of QFN edge joints
showing an increased level of voiding within Table 8-2 Coefficients of Thermal Expansion for
the joints but well within any action level. .......99 Typical Materials .............................................89
Figure 9–25 BTC component with a large edge joint. Table 8-3 Typical Heights (Joined) ..................................89
The joint did not have any cracking after Table A1-1 Etchants used to highlight Intermetallic
shock test. ......................................................99 compounds .....................................................104

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March 2011 IPC-7093

Design and Assembly Process Implementation

for Bottom Termination Components

1 SCOPE IPC-A-610 Acceptability of Electronic Assemblies

This document describes the design and assembly chal-
IPC-SM-785 Guidelines for Accelerated Reliability Test-
lenges for implementing Bottom Termination surface mount
ing of Surface Mount Solder Attachments
Components (BTCs) whose external connections consist of
metallized terminations that are an integral part of the
component body. Throughout this document the word IPC-1756 Manufacturing Process Data Management
“BTC” can mean all types and forms of bottom only
termination components intended for surface-mounting. IPC-2226 Sectional Design Standard for High Density
This includes such industry descriptive nomenclature as Interconnect (HDI) Printed Boards
QFN, DFN, SON, LGA, MLP, and MLF, which utilize
surface to surface interconnections. The focus of the infor- IPC-4101 Specification for Base Materials for Rigid and
mation contained herein is on critical design, assembly, Multilayer Printed Boards
inspection, repair, and reliability issues associated with
BTCs. IPC-4761 Design Guide for Protection of Printed Board
Via Structures
1.1 Purpose The target audiences for this document are
managers, design and process engineers, and operators and IPC-6012 Qualification and Performance Specification
technicians who deal with the electronic design, assembly, for Rigid Printed Boards
inspection, and repair processes. The intent is to provide
useful and practical information to those companies who are IPC-7351 Generic Requirements for Surface Mount De-
using or considering tin/lead, lead-free, adhesives or other sign and Land Pattern Standard
forms of interconnection processes for assembly of BTC
type components. IPC-7525 Stencil Design Guidelines
1.2 Intent This document, although not a complete
recipe, identifies many of the characteristics that influence IPC-7526 Stencil and Misprinted Board Cleaning Hand-
the successful implementation of robust and reliable assem- book
bly processes and provides guidance information to compo-
nent suppliers regarding the issues being faced in the IPC-9201 Surface Insulation Resistance Handbook
assembly process. The exchange of information between the
component supplier, product designer, and assembly per- IPC-9701 Performance Test Methods and Qualification
sonnel about those parameters that influence good assembly Requirements for Surface Mount Solder Attachments
practices are more critical with BTC implementation than
with many other surface mount parts. J-STD-001 Requirements for Soldered Electrical and
Electronic Assemblies
2 APPLICABLE DOCUMENTS
J-STD-002 Solderability Tests for Component Leads, Ter-
2.1 IPC1 minations, Lugs, Terminals and Wires
IPC-T-50 Terms and Definitions for Interconnecting and
Packaging Electronic Circuits J-STD-005 Requirements for Soldering Pastes

IPC-CH-65 Guidelines for Cleaning of Printed Boards J-STD-020 Moisture/Reflow Sensitivity Classification for
and Assemblies Nonhermetic Solid State Surface Mount Devices

IPC-D-279 Design Guidelines for Reliable Surface J-STD-033 Handling, Packing, Shipping and Use of
Mount Technology Printed Board Assemblies Moisture/Reflow Sensitive Surface Mount Devices

1. www.ipc.org