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CO Expt No. 4

The document describes designing and testing a 4-bit ripple carry adder using VHDL. It explains the theory of ripple carry adders, how they work by cascading full adders. A 4-bit ripple carry adder is implemented in VHDL, including the entity, architecture, testbench and sample outputs. The summary concludes the experiment.

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153 views

CO Expt No. 4

The document describes designing and testing a 4-bit ripple carry adder using VHDL. It explains the theory of ripple carry adders, how they work by cascading full adders. A 4-bit ripple carry adder is implemented in VHDL, including the entity, architecture, testbench and sample outputs. The summary concludes the experiment.

Uploaded by

amol mali
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 6

EXPERIMENT NO 4

AIM: To study and execute VHDL code for 4 bit Ripple Carry Adder.

THEORY:
In digital electronics adding of two-bit binary numbers can be possible by using half
adder. And if the input sequence has a three-bit sequence, then the addition process can be
completed by using a full adder. But if the numbers of bits are more in the input sequence
then the process can be completed by using half adder. Because full adder cannot be able to
complete the addition operation. So these drawbacks can be overcome by using “Ripple
Carry Adder”. It’s a unique type of logic circuit used for adding the N-bit numbers in digital
operations. This article describes an overview of what is ripple-carry-adder and its operation.

Ripple Carry Adder:


A structure of multiple full adders is cascaded in a manner to gives the results of the
addition of an n bit binary sequence. This adder includes cascaded full adders in its structure
so, the carry will be generated at every full adder stage in a ripple-carry adder circuit. These
carry output at each full adder stage is forwarded to its next full adder and there applied as a
carry input to it. This process continues up to its last full adder stage. So, each carry output
bit is rippled to the next stage of a full adder. By this reason, it is named as “RIPPLE
CARRY ADDER”. The most important feature of it is to add the input bit sequences whether
the sequence is 4 bit or 5 bit or any.
One of the most important point to be considered in this carry adder is the final output
is known only after the carry outputs are generated by each full adder stage and forwarded to
its next stage. So there will be a delay to get the result with using of this carry adder.

4-bit Ripple Carry Adder:


The below diagram represents the 4-bit ripple-carry adder. In this adder, four full
adders are connected in cascade. Co is the carry input bit and it is zero always. When this
input carry ‘Co’ is applied to the two input sequences A1 A2 A3 A4 and B1 B2 B3 B4 then
output represented with S1 S2 S3 S4 and output carry C4.

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Working of 4-bit Ripple Carry Adder:
1. Let’s take an example of two input sequences 0101 and 1010. These are representing
the A4 A3 A2 A1 and B4 B3 B2 B1.
2. As per this adder concept, input carry is 0.
3. When Ao & Bo are applied at 1st full adder along with input carry 0.
4. Here A1 =1 ; B1=0 ; Cin=0
5. Sum (S1) and carry (C1) will be generated as per the Sum and Carry equations of this
adder. As per its theory, the output equation for the Sum = A1⊕B1⊕Cin and Carry =
A1B1⊕B1Cin⊕CinA1
6. As per this equation, for 1st full adder S1 =1 and Carry output i.e., C1=0.
7. Same like for next input bits A2 and B2, output S2 = 1 and C2 = 0. Here the important
point is the second stage full adder gets input carry i.e., C1 which is the output carry
of initial stage full adder.
8. Like this will get the final output sequence (S4 S3 S2 S1) = (1 1 1 1) and Output carry
C4 = 0
9. This is the addition process for 4-bit input sequences when it’s applied to this carry
adder.

Ripple Carry Adder Applications:


 The ripple-carry-adder applications include the following.
 These carry adders are used mostly in addition to n-bit input sequences.
 These carry adders are applicable in the digital signal processing and microprocessors.

Ripple Carry Adder Advantages:


 The ripple-carry-adder advantages include the following.
 This carry adder has an advantage like we can perform addition process for n-bit
sequences to get accurate results.
 The designing of this adder is not a complex process.

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Disadvantages of Ripple Carry Adder:
 Ripple Carry Adder does not allow to use all the full adders simultaneously.
 Each full adder has to necessarily wait until the carry bit becomes available from its
adjacent full adder.
 This increases the propagation time.
 Due to this reason, ripple carry adder becomes extremely slow.
 This is considered to be the biggest disadvantage of using ripple carry adder.

PROGRAM:
DESIGN:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--entity declaration with port definitions
entity rc_adder is
port( num1 : in std_logic_vector(3 downto 0); --4 bit input 1
num2 : in std_logic_vector(3 downto 0); -- 4 bit input 2
sum : out std_logic_vector(3 downto 0); -- 4 bit sum
carry : out std_logic -- carry out.
);
end rc_adder;
--architecture of entity
architecture Behavioral of rc_adder is
--temporary signal declarations(for intermediate carry's).
signal c0,c1,c2,c3 : std_logic := '0';
begin
--first full adder
sum(0) <= num1(0) xor num2(0); --sum calculation
c0 <= num1(0) and num2(0); --carry calculation
--second full adder
sum(1) <= num1(1) xor num2(1) xor c0;
c1 <= (num1(1) and num2(1)) or (num1(1) and c0) or (num2(1) and c0);

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--third full adder
sum(2) <= num1(2) xor num2(2) xor c1;
c2 <= (num1(2) and num2(2)) or (num1(2) and c1) or (num2(2) and c1);
--fourth(final) full adder
sum(3) <= num1(3) xor num2(3) xor c2;
c3 <= (num1(3) and num2(3)) or (num1(3) and c2) or (num2(3) and c2);
--final carry assignment
carry <= c3;
end Behavioral;

TESTBENCH:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--this is how entity for your test bench code has to be declared.
entity testbench is
end testbench;

architecture behavior of testbench is


--signal declarations.
signal num1,num2,sum : std_logic_vector(3 downto 0) :=(others => '0');
signal carry : std_logic:='0';
begin
--entity instantiation
UUT : entity work.rc_adder port map(num1,num2,sum,carry);
--definition of simulation process
tb : process
begin
num1<="0001"; --num1=1
num2<="1000"; --num2 =8

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wait for 2 ns;
num1<="1010"; --num1 =10
num2<="0011"; --num2 =3
wait for 2 ns;
num1<="1010"; --num1=10
num2<="0101"; --num2 =5
wait for 2 ns;
num1<="1001";--num1 =9
num2<="0111"; --num2 =7
--more input combinations can be given here.
wait for 2 ns;
wait;
end process tb;
end;

OUTPUT:

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CONCLUSION:

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