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DEPARTMENT OF AVIONICS ENGINEERING

SUBJECT : FPGA BASED EMBEDDED SYSTEM

DESIGN
SUBJECT CODE : 408448
LAB NO : 04

TITLE : Instantiation: 4-Bit Ripple Carry Full

Adder Design by instantiating 1-Bit Full
Adders

SUBMITTED TO : Engr. Lal Said Khan

SEMESTER :
SECTION :

Marks Obtain
Group Member 1 Group Member 2
NAME M.Diyan Zahid
REGISTRATION NUMBER 220701027
LAB REPORT 04
PERFORMANCE
TOTAL MARKS

DEADLINE FOR SUBMISSION:

DATE OF SUBMISSION:

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Objectives:

 The primary objective of this lab is to designing a 4-Bit Ripple Carry Full Adder
through instantiating individual 1-Bit Full Adders within the 4-Bit module.
 The students will gain a deep understanding of how to structure and interconnect
modules using instantiation techniques.

Introduction:

In Verilog, Instantiation is a fundamental concept in digital design that involves the

creation and utilization of modular components within larger circuits. It enables the
encapsulation and reuse of specific functionalities by allowing designers to define
modules, which represent individual building blocks of a digital system. When a module
is instantiated, an instance of that module is created within another module or at the top
level of a design. The instantiation process involves specifying the connections between
the instantiated module and other signals or ports in the surrounding module.

4-bit Carry Ripple Adder

A N-bit full adder can be designed by cascading N number of 1-bit full adders. Each full
adder takes a carry-in Cin, which is the carry-out Cout of the previous adder. This kind of
chain of adders forms a ripple-carry adder, since each carry-bit "ripples" to the next full
adder. The layout of a ripple-carry adder is simple, which allows for fast design time;
however, the ripple-carry adder is relatively slow, since each full adder must wait for the
carry-bit to be calculated from the previous full adder. A 4-bit ripple carry adder formed
by cascading four 1-bit full adders is shown in Figure 1.

Figure 1. 4-bit Carry Ripple Adder formed by cascading four full adders

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Verilog Module

Figure 2 shows the Verilog module of a 4-bit carry ripple adder. A and B are the two 4-
bit input ports which is used to read in the two 4-bit numbers that are to be summed up.
The 1-bit carry-in input port Cin is used to read in a carry bit, if another instance of the
ripple carry adder is cascaded towards lesser significant stage. The 4-bit sum generated
by the adder is presented in the 4-bit output port Sum and 1-bit carry-out in the Cout
output port. The carry out, Cout provides a carry-bit, if another instance of the ripple
carry adder is cascaded towards more significant stage.

Figure 2. Verilog module of a 4-bit Ripple Carry Adder

Verilog Code for 4-bit Carry Ripple Adder

`timescale 1ns / 1ps

module ripple_carry_4bit_full_adder(
input [3:0] A, B, // 4-bit inputs
input Cin, // Carry input
output [3:0] Sum, // 4-bit sum output
output Cout // Carry output
);
wire [3:0] c; // Internal carry signals

// Instantiating four 1-bit full adders

full_adder u1 (.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(c[0]));
full_adder u2 (.A(A[1]), .B(B[1]), .Cin(c[0]), .Sum(Sum[1]), .Cout(c[1]));
full_adder u3 (.A(A[2]), .B(B[2]), .Cin(c[1]), .Sum(Sum[2]), .Cout(c[2]));
full_adder u4 (.A(A[3]), .B(B[3]), .Cin(c[2]), .Sum(Sum[3]), .Cout(Cout));

endmodule
// 1-bit full adder module
module full_adder (
input A, B, Cin,
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output Sum, Cout

);
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (B & Cin) | (A & Cin);
endmodule

Test Bench

`timescale 1ns / 1ps

module tb_ripple_carry_4bit_full_adder;
// Testbench inputs and outputs
reg [3:0] A, B; // 4-bit inputs
reg Cin; // Carry input
wire [3:0] Sum; // 4-bit sum output
wire Cout; // Carry output

// Instantiate the ripple_carry_4bit_full_adder module

ripple_carry_4bit_full_adder uut (
.A(A),
.B(B),
.Cin(Cin),
.Sum(Sum),
.Cout(Cout)
);

// Initial block for testbench stimulus

initial
begin
// Test case 1
A = 4'b1000; //
B = 4'b1011; //
Cin = 0;
#10; // Allow some time for the signals to stabilize
$display("Test Case 1: A = %b, B = %b, Cin = %b, Sum = %b, Cout = %b", A, B, Cin,
Sum, Cout);

// Test case 2
A = 4'b1101; // Binary 13
B = 4'b0010; // Binary 2
Cin = 1;
#10;

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$display("Test Case 2: A = %b, B = %b, Cin = %b, Sum = %b, Cout = %b", A, B, Cin,
Sum, Cout);

// Add more test cases as needed

// End simulation
$finish;
end

endmodule

Time diagram

Task:
Design 4-Bit Full subtractor by instantiating 1-Bit subtractor

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A 4-bit ripple carry subtractor performs bitwise subtraction of two 4-bit numbers using
full subtractors.Each 1-bit full subtractor computes the difference and propagates the
borrow to the next stage.The borrow output (Bout) of one stage acts as the borrow input
(Bin) for the next stage.The difference is computed as A + B + Bin, and borrow is
determined using (~A & (B | Bin)) | (B & Bin).This design ensures sequential borrow
propagation, similar to a ripple carry adder but for subtraction.

Verilog:

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Testbench:

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Timing Diagram:

Conclusion:

In the first case, a borrow is generated since A is smaller than B.In the second case, no
borrow is needed because A is larger than B.The ripple carry subtractor correctly
computes the difference and propagates borrow if required.

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