LB# 820-2849 Schematic Diagram PDF

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCHEMATIC,"ANGEL ISLAND",MLB 2009-05-19
Rev.A 02/23/10
D (.csa) Date (.csa) Date (.csa) Date
D
Page 1
Contents Sync 04/01/2008
Page 49
Page 100
1 46 91
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
Table of Contents K20_MLB SMC K17_WFERRY CPU Constraints K17_WFERRY

2 03/26/2009 50 06/17/2009 101 06/09/2009
2 47 92
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
Revision History K20A_MLB SMC Support K17_REF Memory Constraints K17_WFERRY

3 03/26/2009 51 03/30/2009 102 06/09/2009
3 48 93
Revision History K20A_MLB LPC+SPI Debug Connector T22_MLB PCH Constraints 1 K17_WFERRY
4 03/26/2009 52 05/20/2009 103 06/17/2009
4 49 94
Revision History K20A_MLB K17 SMBus Connections K17_WFERRY PCH Constraints 2 K17_REF
5 06/09/2009 53 06/17/2009 104 06/09/2009
5 50 95
BOM Configuration K17_WFERRY Current & Voltage Sensing K17_REF Ethernet Constraints K17_WFERRY
7 06/17/2009 54 06/04/2009 105 06/09/2009
6 51 96
Functional / ICT Test K17_REF Current Sensing K17_CHENGD FireWire Constraints K17_WFERRY
8 (MASTER) 55 07/08/2009 106 06/09/2009
7 52 97
Power Aliases (MASTER) Thermal Sensors K17_CHENGD SMC Constraints K17_WFERRY

TABLE_TABLEOFCONTENTS_ITEM
9 06/17/2009 TABLE_TABLEOFCONTENTS_ITEM
107 06/09/2009
8 10
Signal Aliases K17_REF
06/09/2009 TABLE_TABLEOFCONTENTS_ITEM
53 57
Fan Connectors K20A_MLB
98 108
GPU (GT216) CONSTRAINTS K17_WFERRY
06/17/2009
9 11
CPU DMI/PEG/FDI/RSVD K17_WFERRY
54 58
WELLSPRING 1 K17_WFERRY
99 109
Project Specific Constraints K17_REF
06/09/2009
10 12
CPU Clock/Misc/JTAG K18_MLB
55 59
WELLSPRING 2 K17_WFERRY
100 121
PCB Rule Definitions K17_WFERRY
06/17/2009
11 13
CPU DDR3 Interfaces K17_REF
56 60
Sudden Motion Sensor (SMS) K20A_MLB
101 122
Ibex Peak-M Power Aliases K17_REF
06/17/2009
12 14
CPU Power (1 of 2) K17_WFERRY
57 61
DEBUG SENSORS AND ADC K17_CHENGD
102 132
Current Sensing K17_REF
05/20/2009
13 15
CPU Power (2 of 2) K17_WFERRY
58 62
SPI ROM K17_WFERRY
103 T57 Card Connector K17_WFERRY
14 16
CPU Grounds K17_REF
59 63
AUDIO:CODEC K17_REF
05/30/2009
15 17
CPU Non-GFX Decoupling (1 of 2) K17_WFERRY
60 65
AUDIO: LINE IN K17_REF
05/30/2009
16 CPU Non-GFX Decoupling (2 of 2) K17_REF 61 AUDIO: HEADPHONE OUT K17_REF
C
17 18
19
PCH SATA/PCIE/CLK/LPC/SPI K17_REF
08/24/2009
06/09/2009
62 66
67
AUDIO:SPEAKER AMP K17_REF
05/30/2009
11/24/2009
C
18 20
PCH DMI/FDI/Graphics K17_WFERRY
63 68
AUDIO: JACKS K17_LENGO
05/30/2009
19 21
PCH PCI/FlashCache/USB K18_MLB
64 69
AUDIO: JACK TRANSLATORS K17_REF
04/29/2009
20 22
PCH MISC K18_MLB
65 70
DC-In & Battery Connectors K17_REF
04/29/2009
21 23
PCH Power K18_MLB
03/26/2009
66 72
PBus Supply & Battery Charger K17_REF
03/26/2009
22 67
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
PCH Grounds T22_MLB 5V / 3.3V Power Supply K20A_MLB

24 06/09/2009 73 06/24/2009
23 68
PCH Non-GFX Decoupling K17_WFERRY 1.5V DDR3 Supply K17_REF

25 06/09/2009 74 06/29/2009
24 69
CPU/PCH GFX Decoupling K17_WFERRY CPU IMVP VCore Regulator K18_POWER

26 06/22/2009 75 03/26/2009
25 70
eXtended Debug Port (XDP) K18_MLB GFX IMVP VCore Regulator T22_MLB
27 05/19/2009 76 03/26/2009
26 71
Clock (CK505) K17_REF CPUVTT (1.05V) Power Supply T22_MLB

28 06/17/2009 77 06/09/2009
27 72
Chipset Support K17_REF Misc Power Supplies K17_WFERRY

29 05/13/2009 78 06/09/2009
28 73
DDR3 SO-DIMM Connector A K17_REF Power FETs K17_WFERRY

30 06/19/2009 79 06/09/2009
29 74
DDR3 Byte/Bit Swaps K18_MLB Power Control K17_WFERRY

80 06/29/2009
30 32
DDR3 SO-DIMM Connector B K17_WFERRY
75 81
NV GT216 PCI-E K18_MLB
03/26/2009
31 33
CPU Memory S3 Support K18_MLB
76 82
NV GT216 CORE/FB POWER GT216
06/29/2009
32 34
FSB/DDR3/FRAMEBUF Vref Margining K17_WFERRY
77 84
NV GT216 FRAME BUFFER I/F K18_MLB
03/26/2009
33 35
X16/ALS/CAMERA CONNECTOR K18_MLB
78 85
GDDR3 Frame Buffer A (Top) GT216
03/26/2009
B TABLE_TABLEOFCONTENTS_ITEM
34 36
ExpressCard Connector K17_WFERRY
79 86
GDDR3 Frame Buffer B (Top) GT216
06/29/2009 B
35 37
USB HUB 1 K18_MLB
80 87
NV GT216 GPIO/MIO/MISC K18_MLB
07/01/2009
36 39
USB HUB 2 K18_MLB
81 88
GT216 GPIOS & STRAPS K18_MLB
06/29/2009
37 40
Ethernet PHY (Caesar II/IV) K18_MLB
82 89
NV GT216 VIDEO INTERFACES K18_MLB
06/09/2009
38 41
Ethernet Connector K17_WFERRY
83 90
GPU (GT216) CORE SUPPLY K17_WFERRY
03/26/2009
39 42
FireWire LLC/PHY (FW643) K20A_MLB
84 93
LVDS Display Connector K20A_MLB
06/17/2009
40 43
FireWire Port Power K20A_MLB
85 94
Muxed Graphics Support K17_REF
03/26/2009
41 45
FireWire Ports K18_MLB
86 95
DisplayPort Connector K20A_MLB
06/17/2009
42 46
SATA Connectors K20A_MLB
87 96
1.05V GPU / 1V8 FB Power Supply K17_REF
06/24/2009
43 47
External USB Connectors K17_WFERRY
03/26/2009
88 97
Graphics MUX (GMUX) K17_REF
12/16/2009
44 89
PROJECT SPECIFIC CONNS K20A_MLB LCD Backlight Driver (MC34845) K17_VEMURI

48 03/26/2009 98 03/26/2009
45 90
Front Flex Support K20A_MLB
LCD Backlight Support K20A_MLB
A A
DRAWING TITLE
Schematic / PCB #’s Apple Inc.

DRAWING NUMBER
REVISION
SIZE
D
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION R
051-8503 1 SCHEM,ANGEL_ISLAND,MLB,K17 SCH CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE
820-2849 1 PCBF,ANGEL_ISLAND,MLB,K17 PCB CRITICAL PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING
TITLE=MLB
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 132
ABBREV=DRAWING III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
LAST_MODIFIED=Tue Feb 23 21:52:40 2010 IV ALL RIGHTS RESERVED 1 OF 103
8 7 6 5 4 3 2 1
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U2600
U8000 INTEL CPU
PRAPHICS 2.X GHZ XDP CONN
PG 25
NV GT216 ARRANDALE
PG 9
PG 73 J2900
2 UDIMMs
DDR3-1067/1333MHZ
DIMM
D PG 28,30
J6950
D
DC/BATT POWER SUPPLY
PG 63
GPIO FDI DMI RTC

PG 20 PG 18 PG 18 PG 17 U4900
TEMP SENSOR
U2700 CLOCK
CK505 Misc PG 44
CLK
PG 20
U6100
P8 26 BUFFER POWER PGSENSE
44
SPI
PG 17 Boot ROM J5650,5660
J4500
SPI FAN CONN AND CONTROL
SATA PG 56 PG 51
PG 17
Conn
HD 1.05V/3GHZ.
P8 40 INTEL U4900
B,0 BSB ADC Fan Ser
J5100
SATA IBEX PEAK-MPCH SMC Prt LPC Conn
J4501
SATA PG 17 LPC Port80,serial
C Conn
1.05V/3GHZ.
PG 17
PG 44
PG 46 C
ODD U1800
P8 40
J9000
PWR
DISPLAY PORT
DP OUT CTRL
CONN
PG 84 RGB OUT
J3401 J5713 J3401 J3401 J4600,J4610,4720
0 1 2 3 4 5 6 7 8 9 10 11 12 13
HDMI OUT
Bluetooth TRACKPAD/ IR CAMERA EXTERNAL
U9600 KEYBOARD USB
DVI OUT Connectors
GMUX PG 33 PG 52 PG 33 PG 33
PG 41
(UP TO 14 DEVICES)
XP25-5 LVDS OUT
PG 85 TMDS OUT
USB
PG 19
PG 18
PCI
PG 19
J9400
LVDS PCI-E
B CONN PG 19 B
SMB
PG 71 JTAG SMB
PG 17
PG 17
CONN
PCI-E HDA PG 47
PEG DIMM’s
(UP TO 16 LINES)
PG 17
PG 17 PG 17
U6200
Audio
Codec
PG 57
U6500 U6610,6620,6630,6640,6650
U4100 U3900 J3500
A FW643 GB
E-NET
EXPRESSCARD Line In HEADPHONE Line Out Speaker
SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009 A
CONN Amp Amp Amp Amps PAGE TITLE
BCM5764M
PG 37
PG 35 PG 34
PG 59 PG 60 Revision History
DRAWING NUMBER SIZE
Apple Inc. D
J3400 J4310 J4000 REVISION
R
Mini PCI-E E-NET E-NET J6780,6781,6782,6700,6750

NOTICE OF PROPRIETARY PROPERTY: BRANCH
AirPort Conn Conn Audio
Conns PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
PG 28 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PG 39 PG 36
PG 61 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
2 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 103
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POWER SYSTEM ARCHITECTURE SMC PWRGD

NCP303LSN SMC_RESET_L
PPDCIN_G3H_OR_PBUS_R U5000
R6905
(PAGE 45)
ENABLE SMC AVREF SUPPLY
3.425V G3HOT
SMC_PBUS_VSENSE LT3470A PP3V42_G3H PP3V3_S5_AVREF_SMC
VIN
U6990 VR5020 VOUT
D J6900 F7040
PPBUS_G3H
V Q5315
(PAGE 63) (PAGE 45)
SMC_TPAD_RST_L D
F6905 SMC_ONOFF_L
6A FUSE R7020
AC U5001
ADAPTER
DCIN(16.5V)
A U7000 PPVBAT_G3H_CHGR_REG V SMC_GPU_VSENSE R7640
IN
SMC_DCIN_ISENSE
VIN
ISL6259HRTZ
VOUT
F7041
8A FUSE
PP5V_S3_GPUVCORE
VDD
VIN
GPU VCORE
VOUT A PPVCORE_GPU PP5V_S0_CPUVTTS0
VIN
1.05V
VOUT
A PPCPUVTT_S0
SMC_CPU_FSB_ISENSE
PBUS SUPPLY/ U5410 TPS51513
ISL6263C U7600
BATTERY CHARGER R7050 A VR_ON
U8900
PGOOD
SMC_GPU_ISENSE
CPUVTTS0_EN
EN
PGOOD
CPUVTTS0_PGOOD
SMC_BATT_ISENSE GPUVCORE_EN GPUVCORE_PGOOD (PAGE 69)

(PAGE 64) (PAGE 81)
SMC_CPU_VSENSE
J6950
Q7055 R5388 V
PPVBATT_G3H_CONN PPVBAT_G3H_CHGR_R SMC_CPU_HI_ISENSE CPU VCORE
A PPVCORE_S0_CPU
(6 TO 8.4V)
A VIN
VOUT IBEX PEAK MPM_PWRBTN_L
PWRBTN#
2S4P
ISL9522
SMC_CPU_ISENSE SYS_RERST#
CPUIMVP_VR_ON U7400
CHGR_BGATE VR_ON RSMRST#
PGOOD CPUIMVP_GOOD
ACPRESENT
(PAGE 67)
PM_PCH_PWRGD
PS_PWRGD PLT_RERST_L
PLTRST#
C U1800 PROCPWRGD
CPU_PWRGD C
GMUX PB16B EG_RAIL1_EN P1V1GPU_EN PM_MEM_PWRGD
DRAMPWROK
U5440
EG_RAIL2_EN P3V3GPU_EN U2850 (PAGE 17~22)
PB17A PP5V_S3_DDRREG SMC_CPU_DDR_VSENSE
U9600
PB17B EG_RAIL3_EN GPUVCORE_EN
R7350
XP25-5 PB18A EG_RAIL4_EN P1V8_S0GPU_EN
DDRREG_EN 1.5V
VIN VLDOIN
SMC_DDR_ISENSE
V
(PAGE 86)
PL32A
PM_ALL_GPU_PGOOD
P1V1GPU_EN
EN1 VIN
VOUT1
PP1V1_S0GPU
DDRVTT_EN
S5
S3 0.75V
VOUT1
PPDDR_S3_REG
A PP1V5_S3
1.103V(L/H) R5413 VOUT2 PPVTT_S0_DDR_LDO SM_DRAMPWROK

CPU
SMC P1V8FB_EN
EN2
1.8V(R/H)
VOUT2
A PP1V8_S0GPU
SMC_GPU_1V8_ISENSE
TPS51116
U7300 PGOOD
DDRREG_PGOOD U1000 VCCCPUPWRGD
(PAGE 66)
U4900 ISL6236 POK1 P1V1GPU_PGOOD RESET*
(PAGE 9~14)
RC P3V3S5_EN U9500 P1V8FB_PGOOD Q7860 Q7850
P60 POK2 SLG5AP020 PP1V5_S0
DELAY (PAGE 85) PP5V_S0_FET P1V5DDR_EN VOUT
SMC_PM_G2_EN ON PP1V2_GMUX_FET
(PAGE 44) U7801
VIN P5VS0_EN P1V2GMUX_EN

P5VS3_EN VOUT1
PP5V_S3
IBEX_PEAK_M EN1 5V
(L/H) PM_ALL_GPU_PGOOD
PP3V3_S5 PP3V3_S5
PM_SLP_S5_L P3V3S5_EN VOUT2 VIN U7980
B SLP_S5#(E4) EN2 3.3V P1V2ENET_EN
EN
ISL8009B PP1V2_ENET SMC B
Q9806 (R/H) U7760 VOUT ALL_SYS_PWRGD
Q7870 (PAGE 70) SMC_ADAPTER_EN
RC P5VS3_EN TPS51980 PWRGD(P12)
(P64)
DELAY
U7201 PP3V3_S0_GPU
(PAGE 65) RSMRST_PWRGD RSMRST_IN(P13) PM_RSMRST_L
RSMRST_OUT(P15)
PGOOD1 PGOOD2
RC DDRREG_EN BKLT_PLT_RST_L P1V5_EXP_S0_EN VIN PP1V5_EXP_S0 SMC_ONOFF_L 99ms DLY
P3V3S5_PGOOD EN ISL8009B PWR_BUTTON(P90) IMVP_VR_ON
DELAY && VIN P3V3GPU_EN
U7710 OUT IMVP_VR_ON(P16)
U1800 LCD_BKLT_EN APP001 (PAGE 70)

P5VS3_PGOOD Q7810 PM_SYSRST_L
P3V3S3_EN SYSRST(PA2)
BKLT_EN U9700 PPVOUT_S0_LCDBKLT PP3V3_S3
ENA VOUT Q7922 PP3V3_ENET
PP3V3_S0_PWRCTL
PM_PWRBTN_L
P17(BTN_OUT)
PM_SLP_S4_L (PAGE 87) P1V8S0_PGOOD
SLP_S4#(H7) PM_SLP_S5_L
P3V3S3_EN SLP_S5_L(P95)
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN P5VS3_PGOOD SMC_RESET_L
Q4260 Q7830 PM_SLP_S4_L RES*
SLP_S4_L(P94)
PM_SLP_S3_L PFWBOOST S0PGOOD_PWROK PM_SLP_S3_L
SLP_S3#(P12) LTC1872 PP3V3_S0_FET SLP_S3_L(P93)
VIN VOUT VIN PP1V8_S0
U7790 P1V8_S0_EN ISL8014 VOUT
(PAGE 17~22) (PAGE 70) EN U4900
U7720 P1V8S0_PGOOD PP3V3_S0 (PAGE 44)
P3V3S0_EN
(PAGE 70) PGOOD
SMC_ADAPTER_EN&&PM_SLP_S3_L Q3810
SMC_GFX_VSENSE VCC
R7978 Q4291 PP1V5_S0 U7971
PM_SLP_S3_L_R
R7540
GFXIMVP_ISENSE
V PP3V3_FW_FET
ADJ1
ISL88042IRTEZ
RST*
VIN PP1V05_S0
A
RC P1V8S0_EN GFX_VR_ENVR_ON
1.05V AUX
TPS51981
VOUT A PPVCORE_S0_GFX FW_PWR_EN
ADJ2
(PAGE 72) SYNC_MASTER=K20A_MLB
PAGE TITLE
SYNC_DATE=03/26/2009 A
DELAY P5VS0_EN
U7500
TRST = 200mS
Revision History
P1V2GMUX_EN DRAWING NUMBER SIZE
RC
DELAY
(PAGE 68)
Apple Inc. D
P3V3S0_EN REVISION
GFX_DPRSLPVR
DPRSLPVR
R
CPUVTTS0_EN GFXIMVP_PGOOD
RC PGOOD
DELAY
PBUSVSENS_EN THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
RC P1V5DDR_EN
DELAY
3 OF 132
8 7 6 5 4 3 2 1
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(For changes prior to Rev. A, refer to earlier schematics)
Rev. A:
02/23/10
MLB_TI_IMVP65
csa. 5 Added K17_PVT BOM group
csa. 74 Updated Symbol for U7400; new VPN is TPS51983
csa. 121 Changed ARB_ONLY sense Rs to XWs
D D
C C
B B
A SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009 A
PAGE TITLE
Revision History
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

4 OF 132
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BOM Variants Alternate Parts TABLE_ALT_HEAD
TABLE_BOMGROUP_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

BOM NUMBER BOM NAME BOM OPTIONS PART NUMBER
TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM
639-0973 PCBA,2.53GHZ,512SAM_VRAM,K17 K17_COMMON,CPU_2_53GHZ,FB_512_SAMSUNG,EEEE_DCMV,K17_PVT 138S0603 138S0602 ALL Murata alt to Samsung

639-0971 PCBA,2.53GHZ,512HYN_VRAM,K17 K17_COMMON,CPU_2_53GHZ,FB_512_HYNIX,EEEE_DCMR,K17_PVT 157S0058 157S0055 ALL Delta alt to TDK Magnetics
639-0972 PCBA,2.66GHZ,512SAM_VRAM,K17 K17_COMMON,CPU_2_66GHZ,FB_512_SAMSUNG,EEEE_DCMT,K17_PVT 152S0896 152S0518 ALL MAG LAYERS ALT TO CYNTEC
639-0970 PCBA,2.66GHZ,512HYN_VRAM,K17 K17_COMMON,CPU_2_66GHZ,FB_512_HYNIX,EEEE_DCMQ,K17_PVT 152S0915 152S0796 ALL MAG LAYERS ALT TO CYNTEC
085-1425 K17 MLB DEVELOPMENT K17_DEVEL_ENG 155S0457 155S0329 ALL MAG LAYERS ALT TO MURATA
TABLE_ALT_ITEM
D 516S0806 516S0805 ALL FOXCONN ALT TO MOLEX

TABLE_ALT_ITEM
D
138S0612 138S0602 ALL Taiyo Yuden alt to Samsung
TABLE_ALT_ITEM
353S2805 353S2603 ALL Fairchild 8 in alt to 6 in wafer
TABLE_ALT_ITEM
127S0111 127S0060 ALL Rohm alt to Kemet

TABLE_ALT_ITEM
128S0299 128S0218 ALL NEC/TOKIN alt to Sanyo

TABLE_ALT_ITEM
337S3808 337S3839 ALL GT216 A02 alt to A03 part

TABLE_ALT_ITEM
376S0887 376S0749 ALL Fairchild alt to Vishay
K17 BOM GROUPS TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM
K17_COMMON ALTERNATE,COMMON,K17_COMMON1,K17_COMMON2,K17_PROGPARTS
TABLE_BOMGROUP_ITEM
K17_COMMON1 BCM5764M,DCI,GMUX_VSYNC,CPUPOC_IMAX_40_50,PCH_NAND_3V3,CPUMEM_S0,EXT_HP_AMP,VFRQ_SLPS3,SMC_DEBUG_YES,DPMUX_EN_PLD,FB1V35,USBHUB_2061
TABLE_BOMGROUP_ITEM
K17_COMMON2 GPUVID_0P90V,BKLT_PWR_PBUS,DP_ESD,DP_CA_DET_EG_PLD,SMC_EXCARD_NOT,GPU_SS_INT,RDRV_8515_A2,GMUXPLL_3V3,HUB1_2NONREM,HUB2_2NONREM,RAIL_MON
TABLE_BOMGROUP_ITEM
K17_DEVEL_ENG ARB_ONLY,CALPELLA_XDP,DEBUG_ADC,LPCPLUS,VREFMRGN,GMUX_JTAG_CONN,EFI_DEBUG,BMON_ENG,SMC_OSC_YES
TABLE_BOMGROUP_ITEM
K17_PROGPARTS GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG
TABLE_BOMGROUP_ITEM
K17_PVT BMON_PROD,VREFMRGN_NOT,XDP,XDP_NORMAL,XDP_CPU_BPM
C BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_HEAD
C
TABLE_BOMGROUP_ITEM
FB_512_SAMSUNG VRAM4,VRAM_512_SAMSUNG
TABLE_BOMGROUP_ITEM
FB_512_HYNIX VRAM4,VRAM_512_HYNIX
TABLE_BOMGROUP_ITEM
CALPELLA_XDP XDP,XDP_CONN,XDP_CPU_BPM,XDP_NORMAL,XDP_PCH
Bar Code Labels / EEEE #’s

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_DCMQ] CRITICAL EEEE_DCMQ
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_DCMR] CRITICAL EEEE_DCMR
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_DCMT] CRITICAL EEEE_DCMT
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE_DCMV] CRITICAL EEEE_DCMV
B B
Module Parts
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
337S3847 1 ARD,SLBPF,PRQ,2.53,35W,C2,3M,BGA U1000 CRITICAL CPU_2_53GHZ
337S3848 1 ARD,SLBPE,PRQ,2.66,35W,C2,4M,BGA U1000 CRITICAL CPU_2_66GHZ
337S3846 1 ARD,SLBNA,PRQ,2.40,35W,C2,3M,BGA U1000 CRITICAL CPU_2_4GHZ
337S3849 1 IBEX (HM55),SLGZS,PRQ,B3 U1800 CRITICAL
337S3839 1 IC,GPU,NV GT216 LP++,969BGA,40NM,A03 U8000 CRITICAL
343S0493 1 IC,ASIC,BCM5764M,ENET CONTROLLER,8x8,64 QFN U3900 CRITICAL BCM5764M
338S0753 1 IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12 U4100 CRITICAL
338S0563 1 IC,SMC,HS8/2117,9MMX9MM,TLP U4900 CRITICAL SMC_BLANK
341T0229 1 IC,SMC,K17 U4900 CRITICAL SMC_PROG
335S0610 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_BLANK
341T0244 1 IC,EFI ROM,K17 U6100 CRITICAL BOOTROM_PROG
341S2384 1 IR,ENCORE II, CY7C63833-LFXC U4800 CRITICAL

341S2616 1 IC,TP PSOC,K17,K18 U5701 CRITICAL TPAD_PROG
336S0025 1 IC,XP2-5,HF,CPLD,BLANK U9600 CRITICAL GMUX_5K_BLANK
A 341S2568 1 IC,CPLD,LATTICE,132CSBGA,K17MLB U9600 CRITICAL GMUX_PROG

SYNC_MASTER=K17_WFERRY SYNC_DATE=06/09/2009 A
333S0533 4 IC,SGRAM,GDDR3,32MX32,1GHZ,D-DIE,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_SAMSUNG PAGE TITLE
333S0535 4 IC,SDRAM,GDDR3,32MX32,900MHZ,TIVA,HF U8400,U8450,U8500,U8550 CRITICAL VRAM_512_HYNIX

BOM Configuration
DRAWING NUMBER SIZE
341S2731 1 IC,1MBIT,SPI FLASH K17/K18 U3990 CRITICAL
Apple Inc. D
REVISION
516S0805 1 CONN,204P,SODIMM,SOCKET,DDR3,RAM,NON/SC J3100 CRITICAL R
197S0350 1 OSC,XTAL,32.768KHZ,9-3.6V,12P SOIC,HF U5010 CRITICAL SMC_OSC_YES NOTICE OF PROPRIETARY PROPERTY: BRANCH
5 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J5713 (KEY BOARD CONN) 74 88 102 103 FUNC_TEST
TRUE PP3V3_S3 I720 TRUE SYS_LED_ANODE_R 45
ICT Test Points NC NO_TESTs
Functional Test Points USB PORTS I1103
TRUE PP3V42_G3H
36 49 50 51
6 7 17 20 31
32 33 34 35
54 55 56 72
I722 TRUE LPC_CLK33M_LPCPLUS 27 48 94
NO_TEST
TRUE NC_SMC_FAN_3_TACH 46 47
I1038 TRUE PP5V_S3_RTUSB_A_F 43
I1102
TRUE WS_KBD1
6
7 17 21 23
43 45 46 47
5448 49 50 51 I724 TRUE LPC_AD<0..3> 17 46 48 88 94
CPU NO_TESTs I1297
TRUE NC_SMC_FAN_3_CTL 46 47
USB2_LT1_N I1104 I761
J5650 (LEFT FAN CONN) I1039 TRUE 43 99 54 65 66 74
I1105 TRUE WS_KBD2 54 I723 TRUE SPI_ALT_MOSI 48 NO_TEST I762 TRUE NC_SMC_FAN_2_TACH 46 47
FUNC_TEST I1040 TRUE USB2_LT1_P 43 99
3 TPs I1107 TRUE WS_KBD3 54 I725 TRUE SPI_ALT_MISO 48 I763 TRUE NC_SMC_FAN_2_CTL 46 47
TRUE PP5V_S0 70 71
6 7 8
73 87
23 42 per Fan TRUE GND 9 TP_CPU_RSVD<65..62> TRUE NC_TP_CPU_RSVD<65..62>
48 53 55 69
102 I1106 TRUE WS_KBD4 54 I726 TRUE LPC_FRAME_L 17 46 48 88 94 MAKE_BASE=TRUE I764 TRUE NC_FW2_TPBP 39 41
TRUE FAN_LT_PWM 53 I1108 TRUE WS_KBD5 54 I727 TRUE PM_CLKRUN_L 18 46 48 9 TP_CPU_RSVD<58..45> TRUE NC_TP_CPU_RSVD<58..45> I765 TRUE NC_FW2_TPBN 39 41
SMC_TMS MAKE_BASE=TRUE
TRUE FAN_LT_TACH 53 I1042 TRUE PP5V_S3_RTUSB_B_F 43 I1109 TRUE WS_KBD6 54 I729 TRUE 46 47 48 I767 TRUE NC_FW2_TPBIAS 39 41
LPCPLUS_RESET_L 27 48 88 94 TP_CPU_RSVD<43..32> TRUE NC_TP_CPU_RSVD<43..32> 9
I1043 TRUE USB_LT2_N 43 99 I1110 TRUE WS_KBD7 54 I728 TRUE MAKE_BASE=TRUE I766 TRUE NC_FW2_TPAP 39 41
J5660 (RIGHT FAN CONN) USB_LT2_P
I1044 TRUE 43 99 I1111 TRUE WS_KBD8 54 I730 TRUE SMC_TDO 46 47 48 9 TP_CPU_RSVD<27..26> TRUE NC_TP_CPU_RSVD<27..26> I769 TRUE NC_FW2_TPAN 39 41
MAKE_BASE=TRUE
TRUE FAN_RT_PWM 53 TRUE GND I1112 TRUE WS_KBD9 54 I732 TRUE SMC_TRST_L 46 48 I768 TRUE NC_FW0_TPBP 39 41 96
9 TP_CPU_RSVD<24..15> TRUE NC_TP_CPU_RSVD<24..15>
D TRUE
TRUE
FAN_RT_TACH
GND
53
4 TPs
I1113
I1114
TRUE WS_KBD10
TRUE WS_KBD11
54
54
I731 TRUE SMC_MD1
I734 TRUE SMC_TX_L
46 48
43 46 47 48 9 TP_CPU_RSVD<2..1>
MAKE_BASE=TRUE
TRUE NC_TP_CPU_RSVD<2..1>
I770
I772
TRUE
TRUE
NC_FW0_TPBN
NC_FW0_TPAP
39 41 96
39 41 96
D
per Fan I1046 TRUE PP5V_S3_RTUSB_C_F 44 MAKE_BASE=TRUE
I1115 TRUE WS_KBD12 54 I733 TRUE SPIROM_USE_MLB 20 48 58 I771 TRUE NC_ESTARLDO_EN 46 47
I1047 TRUE USB_LT3_N 44 99 TP_CPU_RSVD_NCTF<8..5> TRUE NC_TP_CPU_RSVD_NCTF<8..5> 9
I1117 TRUE WS_KBD13 54 I735 TRUE SPI_ALT_CLK 48 MAKE_BASE=TRUE I774 TRUE NC_ALS_GAIN 46 47
I1048 TRUE USB_LT3_P 44 99
J6780 (MIC CONN) TRUE WS_KBD14 I736 TRUE SPI_ALT_CS_L
TRUE GND I1116
TRUE WS_KBD15_CAP
54 48
NC NO_TESTs 39 6 NC_FW643_AVREG TRUE NC_FW643_AVREG 6 39
I1118 54 I737 TRUE LPC_SERIRQ 17 46 48
NC_FW643_TDI MAKE_BASE=TRUE
NC_FW643_TDI
NO_TEST 39 6 6 39
I557 TRUE INT_MIC_N 63 99 I1119 TRUE WS_KBD16_NUM 54 I739 TRUE LPC_PWRDWN_L 18 46 48 MAKE_BASE=TRUE
SMC_TDI 18 6 NC_CRT_IG_BLUE TRUE NC_CRT_IG_BLUE 6 18
TRUE INT_MIC_SHIELD 63 J3401, J3402 (AIRPORT/BT/CAMERA CONN) I1120 TRUE WS_KBD17 54 I738 TRUE 46 47 48 MAKE_BASE=TRUE 18 6 NC_DP_IG_C_HPD TRUE NC_DP_IG_C_HPD 6 18
I558
SMC_TCK 18 6 NC_CRT_IG_GREEN TRUE NC_CRT_IG_GREEN 6 18 MAKE_BASE=TRUE
TRUE INT_MIC_P 63 99 I1051 TRUE PCIE_AP_R2D_P 33 94 I1122 TRUE WS_KBD18 54 I740 TRUE 46 47 48 MAKE_BASE=TRUE 18 6 NC_DP_IG_C_CTRL_CLK TRUE NC_DP_IG_C_CTRL_CLK 6 18
I559
18 6 NC_CRT_IG_RED TRUE NC_CRT_IG_RED 6 18 MAKE_BASE=TRUE
I1050 TRUE PCIE_AP_R2D_N 33 94 I1121 TRUE WS_KBD19 54 I741 TRUE SMC_RESET_L 46 47 48 66 MAKE_BASE=TRUE 18 6 NC_DP_IG_C_CTRL_DATA TRUE NC_DP_IG_C_CTRL_DATA 6 18
MAKE_BASE=TRUE
I1053 TRUE PCIE_AP_D2R_P 17 33 94 I1123 TRUE WS_KBD20 54 I742 TRUE SMC_NMI 46 48 TP_DP_IG_C_MLP<3..0> TRUE NC_DP_IG_C_MLP<3..0> 18
18 6 NC_CRT_IG_DDC_CLK TRUE NC_CRT_IG_DDC_CLK 6 18 MAKE_BASE=TRUE
I1052 TRUE PCIE_AP_D2R_N 17 33 94 I1124 TRUE WS_KBD21 54 I743 TRUE SMC_RX_L 43 46 47 48
NC_CRT_IG_DDC_DATA MAKE_BASE=TRUE
NC_CRT_IG_DDC_DATA
TP_DP_IG_C_MLN<3..0> TRUE NC_DP_IG_C_MLN<3..0> 18
18 6 TRUE 6 18 MAKE_BASE=TRUE
J6781 (LEFT SPEAKER) I1054 TRUE PCIE_CLK100M_AP_CONN_P 33 99 I1125 TRUE WS_KBD22 54 I744 TRUE LPCPLUS_GPIO 20 48 MAKE_BASE=TRUE 18 6 NC_DP_IG_C_AUXP TRUE NC_DP_IG_C_AUXP 6 18
MAKE_BASE=TRUE
I1056 TRUE PCIE_CLK100M_AP_CONN_N 33
I1127 TRUE WS_KBD23 54 I751 TRUE ISSP_SCLK_P1_1 54 18 6 NC_DP_IG_C_AUXN TRUE NC_DP_IG_C_AUXN 6 18
I985 TRUE SPKRAMP_FL_OUT_P 62 63 99 99
18 6 NC_CRT_IG_HSYNC TRUE NC_CRT_IG_HSYNC 6 18 MAKE_BASE=TRUE
I1055 TRUE AP_CLKREQ_Q_L 33 I1126 TRUE WS_KBD_ONOFF_L 54 I752 TRUE ISSP_SDATA_P1_0 54 MAKE_BASE=TRUE
I987 TRUE SPKRAMP_FL_OUT_N 62 63 99 18 6 NC_CRT_IG_VSYNC TRUE NC_CRT_IG_VSYNC 6 18 18 6 NC_DP_IG_D_HPD TRUE NC_DP_IG_D_HPD 6 18
SPKRAMP_BL_OUT_P I1058 TRUE PCIE_WAKE_L 6 18 27 33 34 I1128 TRUE WS_LEFT_SHIFT_KBD 54 TRUE SMC_ONOFF_L 46 47 54 MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK
I986 TRUE 62 63 99 18 6 TRUE 6 18
SPKRAMP_BL_OUT_N I1057 TRUE AP_RESET_CONN_L 33 I1129 TRUE WS_LEFT_OPTION_KBD 54 I756 TRUE PM_SYSRST_L 18 27 46
NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_CLK NC_DP_IG_D_CTRL_DATA MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_DATA
I988 TRUE 62 63 99 18 6 TRUE 6 18 18 6 TRUE 6 18
I1059 TRUE PP3V3_WLAN 33 I1130 TRUE WS_CONTROL_KBD 54
NC_LVDS_IG_CTRL_DATA MAKE_BASE=TRUE MAKE_BASE=TRUE
18 6 TRUE NC_LVDS_IG_CTRL_DATA 6 18 TP_DP_IG_D_MLP<3..0> TRUE NC_DP_IG_D_MLP<3..0> 18
I1061 TRUE PP3V3_S3_BT_F 33
LCD_BKLT_PWM NC_PCH_LVDS_VBG MAKE_BASE=TRUE
NC_PCH_LVDS_VBG TP_DP_IG_D_MLN<3..0> MAKE_BASE=TRUE
NC_DP_IG_D_MLN<3..0>
I1288 TRUE 88 89 18 6 TRUE 6 18 TRUE 18
J6782 (RIGHT & SUB SPEAKER) I1060 TRUE SMBUS_SMC_A_S3_SDA 6 33 46 49 55 97 J4800 (FRONT CABLE CONN) MAKE_BASE=TRUE
NC_DP_IG_D_AUXP MAKE_BASE=TRUE
NC_DP_IG_D_AUXP
18 6 TRUE 6 18
SPKRAMP_LFE_OUT_P 62 63 99 I1063 TRUE SMBUS_SMC_A_S3_SCL 6 33 46 49 55 97 MAKE_BASE=TRUE

I989 TRUE
USB_CAMERA_CONN_P I1148 TRUE PP3V42_G3H_LIDSWITCH_R 45
NC_HDA_SDIN1 NC_HDA_SDIN1 18 6 NC_DP_IG_D_AUXN TRUE NC_DP_IG_D_AUXN 6 18
I1062 TRUE 33 99 17 6 TRUE 6 17 MAKE_BASE=TRUE
I990 TRUE SPKRAMP_LFE_OUT_N 62 63 99 I1150 TRUE PP5V_S3_IR_R 45 MAKE_BASE=TRUE
SPKRAMP_FR_OUT_P 62 63 99 I1064 TRUE USB_CAMERA_CONN_N 33 99 17 6 NC_HDA_SDIN2 TRUE NC_HDA_SDIN2 6 17
I992 TRUE I1149 TRUE SMC_LID_R 45 MAKE_BASE=TRUE 18 6 NC_SDVO_TVCLKINN TRUE NC_SDVO_TVCLKINN 6 18
SPKRAMP_FR_OUT_N 62 63 99 I1066 TRUE CONN_USB2_BT_P 33 99

IR_RX_OUT 17 6 NC_HDA_SDIN3 TRUE NC_HDA_SDIN3 6 17
NC_SDVO_TVCLKINP MAKE_BASE=TRUE
NC_SDVO_TVCLKINP
I991 TRUE I1151 TRUE 45 MAKE_BASE=TRUE 18 6 TRUE 6 18
SPKRAMP_BR_OUT_P 62 63 99 I1065 TRUE CONN_USB2_BT_N 33 99 MAKE_BASE=TRUE

I994 TRUE I1152 TRUE SYS_LED_ANODE 45 47
TRUE PP5V_S3_ALSCAMERA_F 33 18 6 NC_SDVO_STALLN TRUE NC_SDVO_STALLN
I993 TRUE SPKRAMP_BR_OUT_N 62 63 99 I1451
TRUE GND NCNO_TEST
NO_TESTs 18 6 NC_SDVO_STALLP MAKE_BASE=TRUE
TRUE NC_SDVO_STALLP
6 18
6 18
C J9000 (LVDS CONN) J3500 (EXPRESS CARD CONN)

TP_PCI_AD<31..0>
TP_PCI_C_BE_L<3..0>
TRUE
MAKE_BASE=TRUE
TRUE
NC_PCI_AD<31..0> 19
NC_PCI_C_BE_L<3..0> 19
18 6 NC_SDVO_INTN
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_INTN 6 18
C
MAKE_BASE=TRUE 18 6 NC_SDVO_INTP TRUE NC_SDVO_INTP 6 18
I1296 TRUE LVDS_CONN_BKL_SYNC 8 84 I1067 TRUE PP1V5_S0_EXCARD_SWITCH 34 19 6 NC_PCI_GNT3_L TRUE NC_PCI_GNT3_L 6 19 MAKE_BASE=TRUE
MAKE_BASE=TRUE
I995 TRUE PP3V3_SW_LCD 84 I1068 TRUE PCIE_WAKE_L 6 18 27 33 34 19 6 NC_PCI_GNT2_L TRUE NC_PCI_GNT2_L 6 19
NC_GPU_BUFRST_L NC_GPU_BUFRST_L 6 75
MAKE_BASE=TRUE 75 6 TRUE
TRUE PP3V3_S0 73 74 81 84 85 86 88 99 101
TRUE SMBUS_PCH_CLK NC_PCI_GNT1_L TRUE NC_PCI_GNT1_L MAKE_BASE=TRUE
I996 6 7 8 25 26 27 28 30 34 37 40 42 47
48 49 52 53 55 59 63 64 69 70 71 72 I1069
17 25 26 28 30 32 34 42 48 49
64 94 POWER RAILS 19 6
MAKE_BASE=TRUE
6 19
81 80 TP_GPU_GSTATE<0> TRUE NC_GPU_GSTATE<0>
I997 TRUE PPVOUT_S0_LCDBKLT 57 84 89 2 TP neededI1071 TRUE SMBUS_PCH_DATA 17 25 26 28 30 32 34 42 48 49 19 6 NC_PCI_GNT0_L TRUE NC_PCI_GNT0_L 6 19
TP_GPU_GSTATE<1> MAKE_BASE=TRUE
NC_GPU_GSTATE<1>
64 94 FUNC_TEST MAKE_BASE=TRUE 81 TRUE
I998 TRUE LVDS_DDC_CLK 84 85 I1070 TRUE PP3V3_S0_EXCARD_SWITCH 34 PM_SLP_S3_L 19 6 NC_PCI_PAR TRUE NC_PCI_PAR 6 19
TP_GPU_MIOA_D<9..0> MAKE_BASE=TRUE
NC_GPU_MIOA_D<9..0>
I640 TRUE 18 31 46 74 86 MAKE_BASE=TRUE 81 80 TRUE
I1000 TRUE LVDS_DDC_DATA 84 85 I1072 TRUE PP3V3_S3_EXCARD_SWITCH 34 19 6 NC_PCI_RESET_L TRUE NC_PCI_RESET_L 6 19 MAKE_BASE=TRUE
TRUE PPBUS_G3H 7 8 40 50 66 67 68 70 71 83 87 MAKE_BASE=TRUE 81 80 TP_GPU_MIOA_DE TRUE NC_GPU_MIOA_DE
I1001 TRUE LVDS_CONN_A_DATA_P<0> 84 85 98
I1074 TRUE USB2_EXCARD_CONN_N 34 99
I602
19 6 NC_PCI_PME_L TRUE NC_PCI_PME_L 6 19 MAKE_BASE=TRUE
TRUE PPBUS_CPU_IMVP_ISNS 7 50 69 MAKE_BASE=TRUE
I1002 TRUE LVDS_CONN_A_DATA_N<0> 84 85 98 I1073 TRUE USB2_EXCARD_CONN_P 34 99 NC_PCI_CLK33M_OUT3 NC_PCI_CLK33M_OUT3 6 TP_LVDS_EG_B_CLK_N NC_LVDS_EG_B_CLKN
I603
19 6 TRUE 19 82 81 TRUE
TRUE PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1004 TRUE LVDS_CONN_A_DATA_P<1> 84 85 98 I1075 TRUE EXCARD_CPUSB_L TP_LVDS_EG_B_CLK_P NC_LVDS_EG_B_CLKP
I604
34 50 51 54 65 66 74 82 81 TRUE
TRUE PP5V_S3 7 31 33 43 44 45 47 51 55 68 73 83 103 MAKE_BASE=TRUE
I1003 TRUE LVDS_CONN_A_DATA_N<1> 84 85 98 I1076 TRUE EXCARD_CLKREQ_CONN_L 34 NC_LVDS_EG_BKL_PWM NC_LVDS_EG_BKL_PWM 6
I605
6 TRUE
TRUE PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 TP_NV_DQ<15..0> TRUE NC_NV_DQ<15..0> 19 MAKE_BASE=TRUE
I1005 TRUE LVDS_CONN_A_DATA_P<2> 84 85 98 I1077 TRUE EXCARD_CPPE_L TP_LVDS_IG_B_CLKN NC_LVDS_IG_B_CLKN
I607
34 MAKE_BASE=TRUE 93 18 8 TRUE
TRUE PPVCORE_S0_CPU 7 12 15 50 69 TP_NV_DQS<1..0> TRUE NC_NV_DQS<1..0> 19 MAKE_BASE=TRUE
I1007 TRUE LVDS_CONN_A_DATA_N<2> 84 85 98 I1079 TRUE PLT_RESET_SWITCH_L 34 TP_LVDS_IG_B_CLKP NC_LVDS_IG_B_CLKP
I606
101 MAKE_BASE=TRUE 93 18 8 TRUE
86 99
MAKE_BASE=TRUE
I1006 TRUE LVDS_CONN_A_CLK_F_P 84 98 I1078 TRUE PCIE_EXCARD_D2R_P 17 34 94 TP_NV_CE_L<3..0> NC_NV_CE_L<3..0> TP_LVDS_IG_BKL_PWM NC_LVDS_IG_BKL_PWM
74 84
2 TPs TRUE 19 18 8 TRUE
TRUE PP3V3_S5
58 72 73
7 31 35 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1009 TRUE LVDS_CONN_A_CLK_F_N 84 98 I1081 TRUE PCIE_EXCARD_D2R_N 17 34 94
I610 49 50 51
TRUE PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54 19 6 NC_NV_ALE TRUE NC_NV_ALE 6 19
I1008 TRUE LVDS_CONN_B_DATA_P<0> 84 85 98 I1080 TRUE PCIE_EXCARD_R2D_P 34 94
I612 55 56 72 74 88 102 103 MAKE_BASE=TRUE
TRUE PP3V3_S0 84 85 86 88 99 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 19 6 NC_NV_CLE TRUE NC_NV_CLE 6 19
I1010 TRUE LVDS_CONN_B_DATA_N<0> 84 85 98 I1082 TRUE PCIE_EXCARD_R2D_N 34 94
I611 52 53 55 59 63 64 69 70 71 72 73 74 81 MAKE_BASE=TRUE
19 6 NC_NV_RB_L TRUE NC_NV_RB_L 6 19 20 6 NC_PCH_SST TRUE NC_PCH_SST 6 20
TRUE LVDS_CONN_B_DATA_P<1> 84 85 98 TRUE PCIE_CLK100M_EXCARD_CONN_P 34 99 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1011 I1083
TRUE PP1V2_S0 7 73 88 TP_NV_WR_RE_L<1..0> TRUE NC_NV_WR_RE_L<1..0> 19 20 6 NC_PCH_NC1 TRUE NC_PCH_NC1 6 20
I1012 TRUE LVDS_CONN_B_DATA_N<1> 84 85 98 I1084 TRUE PCIE_CLK100M_EXCARD_CONN_N 34 99
I600 MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE PP1V8_S0 7 12 16 72 73 88 101 TP_NV_WE_CK_L<1..0> TRUE NC_NV_WE_CK_L<1..0> 19 20 6 NC_PCH_NC2 TRUE NC_PCH_NC2 6 20
I1014 TRUE LVDS_CONN_B_DATA_P<2> 84 85 98
I625 MAKE_BASE=TRUE
J5800 (IPD FLEX CONN) MAKE_BASE=TRUE
NC_PCH_NC3 NC_PCH_NC3
TRUE
I1013 TRUE LVDS_CONN_B_DATA_N<2> 84 85 98 I1085 TRUE PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54 17 6 NC_PCIE_CLK100M_PE4N TRUE NC_PCIE_CLK100M_PE4N 6 1720 6
MAKE_BASE=TRUE 6 20
55 56 72 74 88 102 103 MAKE_BASE=TRUE NC_PCH_NC4 TRUE NC_PCH_NC4
I1015 TRUE LVDS_CONN_B_CLK_F_P 84 98 I1086 TRUE PP18V5_S3 6 55 17 6 NC_PCIE_CLK100M_PE4P TRUE NC_PCIE_CLK100M_PE4P 6 1720 6
MAKE_BASE=TRUE 6 20
MAKE_BASE=TRUE NC_PCH_NC5 TRUE NC_PCH_NC5

I1016 TRUE LVDS_CONN_B_CLK_F_N 84 98 I1087 TRUE TPAD_GND_F 55 17 6 NC_PCIE_CLK100M_PE5N TRUE NC_PCIE_CLK100M_PE5N 6 1720 6
MAKE_BASE=TRUE 6 20
MAKE_BASE=TRUE NC_PCH_TP19 TRUE NC_PCH_TP19

I1017 TRUE LED_RETURN_1 84 89 I1273 TRUE Z2_CS_L 54 55 17 6 NC_PCIE_CLK100M_PE5P TRUE NC_PCIE_CLK100M_PE5P 6 1720 6
MAKE_BASE=TRUE 6 20

I1018 TRUE LED_RETURN_2 84 89 I1089 TRUE Z2_DEBUG3 54 55 20 6 NC_PCIE_CLK100M_PE6N TRUE NC_PCIE_CLK100M_PE6N 6 2020 6
MAKE_BASE=TRUE 6 20
TRUE PPCPUVTT_S0 7 10 12 13 15 25 26 40 71 74 101 MAKE_BASE=TRUE NC_PCH_TP17 TRUE NC_PCH_TP17

NC_PCIE_CLK100M_PE6P 6 2020 6 6 20
B I1019 TRUE LED_RETURN_3

I1020 TRUE LED_RETURN_4
84 89
84 89
I1088 TRUE Z2_MISO
I1090 TRUE Z2_BOOST_EN
54 55
55
I618
20 6
20 6
NC_PCIE_CLK100M_PE6P
NC_PCIE_CLK100M_PE7N
TRUE
MAKE_BASE=TRUE
TRUE NC_PCIE_CLK100M_PE7N 6 2020 6 NC_PCH_TP16
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCH_TP16 6 20 B
I1022 TRUE LED_RETURN_5 84 89 I1091 TRUE Z2_BOOT_CFG1 54 55 20 6 NC_PCIE_CLK100M_PE7P TRUE NC_PCIE_CLK100M_PE7P 6 2020 6
MAKE_BASE=TRUE 6 20
MAKE_BASE=TRUE 20 6 NC_PCH_TP14 TRUE NC_PCH_TP14 6 20

I1021 TRUE LED_RETURN_6 I1098 TRUE Z2_CLKIN NC_PSOC_P1_3 NC_PSOC_P1_3
84 89 54 55 54 6 TRUE 6 54 MAKE_BASE=TRUE
TRUE PPVP_FW 7 40 41 MAKE_BASE=TRUE 20 6 NC_PCH_TP13 TRUE NC_PCH_TP13 6 20
TRUE GND I1097 TRUE Z2_KEY_ACT_L 54 55
I614
17 6 NC_SATA_C_D2RN TRUE NC_SATA_C_D2RN 6 17 MAKE_BASE=TRUE
5 TPs TRUE PP1V0_FW 7 40 72 MAKE_BASE=TRUE 20 6 NC_PCH_TP12 TRUE NC_PCH_TP12 6 20
I1095 TRUE Z2_RESET NC_SATA_C_D2RP NC_SATA_C_D2RP 6 17
I627 MAKE_BASE=TRUE
54 55 17 6 TRUE
TRUE PP3V3_S0GPU 7 73 75 80 81 82 83 85 MAKE_BASE=TRUE 20 6 NC_PCH_TP11 TRUE NC_PCH_TP11 6 20
I1096 TRUE PSOC_F_CS_L NC_SATA_C_R2D_CN NC_SATA_C_R2D_CN 6 17
I626 MAKE_BASE=TRUE
54 55 17 6 TRUE
TRUE PP1V05_S0GPU 7 51 75 77 80 82 MAKE_BASE=TRUE 20 6 NC_PCH_TP10 TRUE NC_PCH_TP10 6 20
I1092 TRUE PICKB_L NC_SATA_C_R2D_CP NC_SATA_C_R2D_CP 6 17
I639 MAKE_BASE=TRUE
J4500 (SATA ODD CONN) 54 55 17 6 TRUE
3 TPs TRUE PP1V8_S0GPU_ISNS 7 8 51 76 77 78 79 MAKE_BASE=TRUE 20 6 NC_PCH_TP9 TRUE NC_PCH_TP9 6 20
I1093 TRUE PSOC_MISO 54 55
I638
17 6 NC_SATA_D_D2RN TRUE NC_SATA_D_D2RN 6 17 MAKE_BASE=TRUE
I1024 TRUE PP5V_SW_ODD 42 57 TRUE PPVCORE_GPU 7 50 76 83 MAKE_BASE=TRUE 20 6 NC_PCH_TP8 TRUE NC_PCH_TP8 6 20
I1094 TRUE PSOC_MOSI NC_SATA_D_D2RP NC_SATA_D_D2RP 6 17
I637 MAKE_BASE=TRUE
54 55 17 6 TRUE
I1026 TRUE SMC_ODD_DETECT 42 46 I636 TRUE PP1V8_S0GPU_ISNS_R 7 51 87 MAKE_BASE=TRUE 20 6 NC_PCH_TP7 TRUE NC_PCH_TP7 6 20
I1099 TRUE PSOC_SCLK NC_SATA_D_R2D_CN NC_SATA_D_R2D_CN 6 17
54 55 17 6 TRUE MAKE_BASE=TRUE
I1025 TRUE SATA_ODD_D2R_UF_P 42 99 TRUE PP3V3_S5_AVREF_SMC 46 47 MAKE_BASE=TRUE 20 6 NC_PCH_TP6 TRUE NC_PCH_TP6 6 20
I1100 TRUE SMBUS_SMC_A_S3_SCL 6 33 46 49 55 97 NC_SATA_D_R2D_CP NC_SATA_D_R2D_CP 6 17
I709 MAKE_BASE=TRUE
17 6 TRUE
I1028 TRUE SATA_ODD_D2R_UF_N 42 99 I714 TRUE PP18V5_S3 6 55 MAKE_BASE=TRUE 20 6 NC_PCH_TP5 TRUE NC_PCH_TP5 6 20
I1101 TRUE SMBUS_SMC_A_S3_SDA 6 33 46 49 55 97 17 6 NC_SATA_SSD2_D2RN TRUE NC_SATA_SSD2_D2RN 6 17 MAKE_BASE=TRUE
I1027 TRUE SATA_ODD_R2D_P 42 93 I1156 TRUE PPDCIN_G3H 7 65 66
NC_SATA_SSD2_D2RP MAKE_BASE=TRUE
NC_SATA_SSD2_D2RP 6 17 20 6 NC_PCH_TP4 TRUE
MAKE_BASE=TRUE
NC_PCH_TP4 6 20
17 6 TRUE
I1029 TRUE SATA_ODD_R2D_N 42 93
NC_SATA_SSD2_R2D_CN MAKE_BASE=TRUE
NC_SATA_SSD2_R2D_CN 6 17 20 6 NC_PCH_TP3 TRUE
MAKE_BASE=TRUE
NC_PCH_TP3 6 20
GND J6900 (DC POWER CONN) 17 6 TRUE

NC_PCH_TP2 NC_PCH_TP2
TRUE MAKE_BASE=TRUE 20 6 TRUE 6 20
I1131 TRUE ADAPTER_SENSE NC_SATA_SSD2_R2D_CP NC_SATA_SSD2_R2D_CP 6 17
4 TPs 65 17 6 TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE 20 6 NC_PCH_TP1 TRUE NC_PCH_TP1 6 20
I1132 TRUE PP18V5_DCIN_FUSE 65 2 TPs MAKE_BASE=TRUE
I1160 TRUE PPVTTDDR_S3 7 32 68
PCH_VSS_NCTF<15>
J4501 (SATA HDD CONN) GND TRUE 20 94
I1161 TRUE PP1V8_GPUIFPX PCH_VSS_NCTF<1> 20 94 I1443
TRUE 7 73 82 TRUE
4 TPs 47 46 TP_SMC_P92 TRUE NC_SMC_P92 I1436
TRUE PCH_VSS_NCTF<17> 20 94
I1032 TRUE PP5V_S0_HDD_FLT PCH_VSS_NCTF<2> 20 94
MAKE_BASE=TRUE I1444
42 3 TPs I1437 TRUE
TRUE PCH_VSS_NCTF<19> 6 20 94
I1031 TRUE SATA_HDD_R2D_P 42 93 J6950 (MAIN BATT CONN) NC NO_TESTs NC_USB_WMN NC_USB_WMN I1438 TRUE PCH_VSS_NCTF<5> 20 94 I1445
PCH_VSS_NCTF<19>
5 TPs NO_TEST 6 TRUE 6 TRUE 6 20 94
I1033 TRUE SATA_HDD_R2D_N I1134 TRUE PPVBAT_G3H_CONN PCH_VSS_NCTF<7> I1446
42 93 65 66 MAKE_BASE=TRUE I1439 TRUE
17 6 NC_PCIE_PE5_D2RN TRUE NC_PCIE_PE5_D2RN 6 17 6 NC_USB_WMP TRUE NC_USB_WMP 6 TRUE PCH_VSS_NCTF<21> 20 94
I1035 TRUE SATA_HDD_D2R_UF_N 42 99 I1136 TRUE SMBUS_SMC_BSA_SCL 6 46 49 65 66 97 PCH_VSS_NCTF<9> 20 94 I1447
MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE
17 6 NC_PCIE_PE5_D2RP TRUE NC_PCIE_PE5_D2RP 6 17
I1440
I1448 TRUE PCH_VSS_NCTF<25> 20 94
I1034 TRUE SATA_HDD_D2R_UF_P 42 99 I1135 TRUE SMBUS_SMC_BSA_SDA 6 46 49 65 66 97 NC_PCIE_PE5_R2D_CN MAKE_BASE=TRUE
NC_PCIE_PE5_R2D_CN I1441 TRUE PCH_VSS_NCTF<11> 20 94
PCH_VSS_NCTF<27>
17 6 TRUE 6 17 TRUE 20 94
I1137 TRUE SMC_BS_ALRT_L PCH_VSS_NCTF<12> 20 94 I1449
MAKE_BASE=TRUE TRUE
TRUE GND 4 TPs 17 6 NC_PCIE_PE5_R2D_CP TRUE NC_PCIE_PE5_R2D_CP 6 17 6 NC_USB_EXTDN TRUE NC_USB_EXTDN 6
I1442
I1450 TRUE PCH_VSS_NCTF<29> 20 94
MAKE_BASE=TRUE MAKE_BASE=TRUE
6 NC_USB_EXTDP TRUE NC_USB_EXTDP 6
NC_PCIE_PE6_D2RN NC_PCIE_PE6_D2RN
A J5815 (KBD BACKLIGHT CONN) 2 TPs
TRUE GND 17 6
5 TPs 17 6 NC_PCIE_PE6_D2RP
TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE_PE6_D2RP
6 17
6 17
93 6
93 6
NC_USB_MININ
NC_USB_MINIP
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
NC_USB_MININ
NC_USB_MINIP
6 93
6 93
SYNC_MASTER=K17_REF SYNC_DATE=06/17/2009 A
I1145 TRUE KBDLED_ANODE NC_PCIE_PE6_R2D_CN NC_PCIE_PE6_R2D_CN
55 17 6 TRUE 6 17 MAKE_BASE=TRUE PAGE TITLE
NC_USB_6N NC_USB_6N
I1146 TRUE SMC_KDBLED_PRESENT_L 55
J6995 (BAT LED CONN)
17 6 NC_PCIE_PE6_R2D_CP TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE_PE6_R2D_CP 6 17
19 6
19 6 NC_USB_6P
TRUE
MAKE_BASE=TRUE
TRUE NC_USB_6P 6 19
Functional / ICT Test
MAKE_BASE=TRUE DRAWING NUMBER SIZE
TRUE GND I1140 TRUE PP3V42_G3H
65 66 74
NC_PCIE_PE7_D2RN TRUE NC_PCIE_PE7_D2RN NC_USB_7N TRUE NC_USB_7N
6 7 17 21 23 43 17 6
45 46 47 48 49 50 51 54 MAKE_BASE=TRUE
6 17 19 6
MAKE_BASE=TRUE
6 19
Apple Inc. D
I1142 TRUE SMBUS_SMC_BSA_SDA 6 46 49 65 66 97 17 6 NC_PCIE_PE7_D2RP TRUE NC_PCIE_PE7_D2RP 6 17 19 6 NC_USB_7P TRUE
MAKE_BASE=TRUE
NC_USB_7P 6 19
MAKE_BASE=TRUE REVISION
I1141 TRUE SMBUS_SMC_BSA_SCL 6 46 49 65 66 97 17 6 NC_PCIE_PE7_R2D_CN TRUE NC_PCIE_PE7_R2D_CN 6 17 R
MAKE_BASE=TRUE
FUNC_TEST I1143 TRUE SMC_BIL_BUTTON_L 46 47 65 17 6 NC_PCIE_PE7_R2D_CP TRUE NC_PCIE_PE7_R2D_CP 6 17
GND MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY: BRANCH

TRUE
17 6 NC_PCIE_PE8_D2RN TRUE NC_PCIE_PE8_D2RN 6 17 THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
TRUE GND TRUE GND 17 6 NC_PCIE_PE8_D2RP TRUE NC_PCIE_PE8_D2RP 6 17 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MAKE_BASE=TRUE
6 TPs 17 6 NC_PCIE_PE8_R2D_CN TRUE
MAKE_BASE=TRUE
NC_PCIE_PE8_R2D_CN 6 17
7 OF 132
17 6 NC_PCIE_PE8_R2D_CP TRUE NC_PCIE_PE8_R2D_CP 6 17
MAKE_BASE=TRUE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
"G3Hot" (Always-Present) Rails 3.3V/1.8V Rails DDR Rails "FW" (FireWire) Rails
71 70 68
40 8 7 6 PPBUS_G3H PPBUS_G3H 50 49 35 31 7 6 PP3V3_S5 PP3V3_S5 73 74 84 86 99 101
6 7 31 35 49 50 51 58 72 40 7 PPBUS_FW_FWBOOST PPBUS_FW_FWBOOST 7 40 72
67 66 50
87 83 MIN_LINE_WIDTH=0.4 mm 101 99 86 84 74 73 72 58 51 MIN_LINE_WIDTH=0.6 MM 72 73 68 31 30 28 7 PP1V5_S3 PP1V5_S3 7 28 30 31 68 73 MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM
VOLTAGE=6V VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 MM VOLTAGE=6V
MAKE_BASE=TRUE MAKE_BASE=TRUE VOLTAGE=1.5V MAKE_BASE=TRUE
MAKE_BASE=TRUE
PPBUS_G3H 6 7 8 40 50 66 67 68 70 71 83 PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99 PPBUS_FW_FWBOOST 7 40 72
87 101
PPBUS_G3H 6 7 8 40 50 66 67 68 70 71 83 PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99
87 101 PP1V5_S3 7 28 30 31 68 73
PPBUS_G3H 6 7 8 40 50 66 67 68 70 71 83 PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99 72 40 8 7 PP10V_FW PP10V_FW 7 8 40 72
87 101 PP1V5_S3 7 28 30 31 68 73 MIN_LINE_WIDTH=0.4 MM
PPBUS_G3H 6 7 8 40 50 66 67 68 70 71 83 PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99 MIN_NECK_WIDTH=0.25 MM
87 101 PP1V5_S3 7 28 30 31 68 73 VOLTAGE=10V
PPBUS_G3H 6 7 8 40 50 66 67 68 70 71 83 PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99 MAKE_BASE=TRUE
87 101 PP1V5_S3 7 28 30 31 68 73
PPBUS_G3H 6 7 8 40 50 66 67 68 70 71 83 PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99 PP10V_FW 7 8 40 72
87 101 PP1V5_S3 7 28 30 31 68 73
PPBUS_G3H 6 7 8 40 50 66 67 68 70 71 83 PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99 PP10V_FW 7 8 40 72
87 101
PPBUS_G3H 6 7 8 40 50 66 67 68 70 71 83 PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99
D PPBUS_G3H
87
6 7 8 40 50 66 67 68 70 71 83
87
PP3V3_S5
101
73 57
6 7 31 35 49 50 51 7
58 72 73 74 84 86 99 101
PP1V5_S3RS0 PP1V5_S3RS0
MIN_LINE_WIDTH=0.6 MM
7 57 73 41 40 7 6 PPVP_FW PPVP_FW
6 7 40 41 D
PPBUS_G3H 6 7 8 40 50 66 67 68 70 71 83 PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99 MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
87 101 VOLTAGE=1.5V VOLTAGE=10V
PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99
101
PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99
PPVP_FW 6 7 40 41
69 50 7 6 PPBUS_CPU_IMVP_ISNS PPBUS_CPU_IMVP_ISNS 6 7 50 69 101 PP1V5_S3RS0 7 57 73 PPVP_FW
MIN_LINE_WIDTH=0.4 MM PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99 6 7 40 41
MIN_NECK_WIDTH=0.25 MM 101
VOLTAGE=6V PP3V3_S5 6 7 31 35 49 50 51 58
MAKE_BASE=TRUE 72 73 74 84 86 99 101 PPCPUDDR_ISNS PPCPUDDR_ISNS 7 13 16 31 57
PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99 MIN_LINE_WIDTH=0.6 MM 41 40 39 7 PP3V3_FW_FWPHY PP3V3_FW_FWPHY 7 39 40 41
PPBUS_CPU_IMVP_ISNS 6 7 50 69 101 MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.4 MM
PP3V3_S5 6 7 31 35 49 50 51 58 72 73 74 84 86 99 VOLTAGE=1.5V MIN_NECK_WIDTH=0.2 MM
101 MAKE_BASE=TRUE VOLTAGE=3.3V
MAKE_BASE=TRUE
66 65 7 6 PPDCIN_G3H PPDCIN_G3H 6 7 65 66 51 7 PP3V3_S5_ISNS_R PP3V3_S5_ISNS_R 7 51 67 PPCPUDDR_ISNS 7 13 16 31 57
MIN_LINE_WIDTH=0.6 MM 67 MIN_LINE_WIDTH=0.6 MM PP3V3_FW_FWPHY 7 39 40 41
MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM PPCPUDDR_ISNS 7 13 16 31 57
VOLTAGE=18.5V VOLTAGE=3.3V PP3V3_FW_FWPHY 7 39 40 41
PPDCIN_G3H 6 7 65 66 PP3V3_S5_ISNS_R 7 51 67 68 32 7 6 PPVTTDDR_S3 PPVTTDDR_S3 6 7 32 68 PP1V0_FW
MIN_LINE_WIDTH=0.3 MM 72 40 7 6 PP1V0_FW 6 7 40 72
74 66
MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.4 MM
VOLTAGE=0.75V MIN_NECK_WIDTH=0.2 MM
50 49 48
43 23 21 17 7 6 PP3V42_G3H PP3V42_G3H 74
6 7 17 21 23 43 PP3V3_S3 PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54 MAKE_BASE=TRUE VOLTAGE=1.05V
47 46 45
65 54 51
MIN_LINE_WIDTH=0.3 MM 45 46 47 48 49 50 51 54 65 66 MIN_LINE_WIDTH=0.5 mm 55 56 72 74 88 102 103 MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
PP1V0_FW 6 7 40 72
MAKE_BASE=TRUE MAKE_BASE=TRUE 68 31 30 28 7 PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT 7 28 30 31 68
MIN_LINE_WIDTH=2 mm
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54 MIN_NECK_WIDTH=0.2 mm
50 51 54 65 66 74 55 56 72 74 88 102 103 VOLTAGE=0.75V 72 40 39 7 PPVIN_FW_FWPHY PPVIN_FW_FWPHY 7 39 40 72
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM
50 51 54 65 66 74 55 56 72 74 88 102 103 MIN_NECK_WIDTH=0.2 MM
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54 PP0V75_S0_DDRVTT 7 28 30 31 68 VOLTAGE=1.0V
50 51 54 65 66 74
PP3V3_S3 55 56 72 74 88 102 103 MAKE_BASE=TRUE
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 6 7 17 20 31 32 33 34 35 36 49 50 51 54 PP0V75_S0_DDRVTT 7 28 30 31 68
PP3V42_G3H
50 51 54 65 66 74
PP3V3_S3
55 56 72 74 88 102 103
PP0V75_S0_DDRVTT PPVIN_FW_FWPHY 7 39 40 72
6 7 17 21 23 43 45 46 47 48 49 6 7 17 20 31 32 33 34 35 36 49 50 51 54 7 28 30 31 68
50 51 54 65 66 74 55 56 72 74 88 102 103
PP3V42_G3H PP3V3_S3
PP3V42_G3H
6 7 17 21 23 43 45 46 47 48 49
50 51 54 65 66 74
PP3V3_S3
6 7 17 20 31 32 33
55 56 72 74 88 102
34 35 36 49 50 51 54
103 "GPU" Rails
PP3V42_G3H
6 7 17 21 23 43 45 46 47 48 49
50 51 54 65 66 74
6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3
6 7 17 20 31 32 33 34 35 36 49 50 51 54
55 56 72 74 88 102 103 1.5V/1.05V Rails 85 83 82 81 80 75 73 7 6 PP3V3_S0GPU PP3V3_S0GPU
6 7 73 75 80 81 82
83 85
50 51 54 65 66 74 99 74 72 59 42 34 7 PP1V5_S0 PP1V5_S0 7 34 42 59 72 74 99 MIN_NECK_WIDTH=0.20MM
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54 MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V
50 51 54 65 66 74 55 56 72 74 88 102 103 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54 VOLTAGE=1.5V
PP3V3_S0GPU
C PP3V42_G3H
PP3V42_G3H
50 51 54 65 66 74
6 7 17 21 23 43 45 46 47 48 49
50 51 54 65 66 74
6 7 17 21 23 43 45 46 47 48 49
PP3V3_S3
PP3V3_S3
55 56 72 74 88 102 103
6 7 17 20 31 32 33 34 35 36 49 50 51 54
55 56 72 74 88 102 103
6 7 17 20 31 32 33 34 35 36 49 50 51 54
MAKE_BASE=TRUE
PP1V5_S0 7 34 42 59 72 74 99 PP3V3_S0GPU
6 7 73 75 80 81 82
83 85
6 7 73 75 80 81 82
83 85
C
50 51 54 65 66 74 55 56 72 74 88 102 103 PP1V5_S0 7 34 42 59 72 74 99 PP3V3_S0GPU 6 7 73 75 80 81 82
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54 83 85
50 51 54 65 66 74 55 56 72 74 88 102 103 PP1V5_S0 7 34 42 59 72 74 99 PP3V3_S0GPU 6 7 73 75 80 81 82
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54 83 85
50 51 54 65 66 74 55 56 72 74 88 102 103 PP1V5_S0 7 34 42 59 72 74 99 PP3V3_S0GPU 6 7 73 75 80 81 82
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49
50 51 54 65 66 74
PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54
55 56 72 74 88 102 103
83 85
PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49 PP3V3_S3 6 7 17 20 31 32 33 34
PP1V8_GPUIFPX PP1V8_GPUIFPX
50 51 54 65 66 74 35 36 49 88 73 7 6 PP1V2_S0 PP1V2_S0 6 7 73 88 82 73 7 6 6 7 73 82
PP3V3_S3 50 51 54
556 56 72 74 88 102 103 MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6 MM
7 MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.15 MM
5V Rails PP3V3_S3 1717 20 31 32 33 34 35 36 49 50 51 54
6 55 56 72 74 88 102 103
7 72 74 88 102 103
VOLTAGE=1.2V
MAKE_BASE=TRUE
VOLTAGE=1.8V
MAKE_BASE=TRUE
73 67 57 23 7 PP5V_S5 PP5V_S5 7 23 57 67 73 102 PP3V3_S3 20 31 32 33 34 35 36 49 50 51 54 55 56
6
102 MIN_LINE_WIDTH=0.3 MM 7 17 20 31 32 33 34 35 36 49 50 51 54
55 56 72 74 88 102 103
PP1V2_S0 6 7 73 88 PP1V8_GPUIFPX 6 7 73 82
VOLTAGE=5V
MAKE_BASE=TRUE 102 73 7 PP3V3_S3_ISNS_R PP3V3_S3_ISNS_R 7 73 102
MIN_LINE_WIDTH=0.5 MM 79 78 77 76 51 8 7 6 PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS 6 7 8 51 76 77 78
PP5V_S5 7 23 57 67 73 102 MIN_NECK_WIDTH=0.25 MM 72 17 7 PP1V05_S5 PP1V05_S5 7 17 72 MIN_LINE_WIDTH=0.6 MM 79
VOLTAGE=3.3V MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
PP5V_S5 7 23 57 67 73 102 MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V
VOLTAGE=1.05V MAKE_BASE=TRUE
PP5V_S5 7 23 57 67 73 102 PP3V3_S3_ISNS_R 7 73 102 MAKE_BASE=TRUE
PP1V8_S0GPU_ISNS 6 7 8 51 76 77 78
PP5V_S5 7 23 57 67 73 102 PP1V05_S5 7 17 72 79
PP1V8_S0GPU_ISNS 6 7 8 51 76 77 78
PP5V_S5 7 23 57 67 73 PP3V3_S0 PP3V3_S0 70 71 72 73 74 81 84 85 86 88 99 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 79
102 MIN_LINE_WIDTH=0.3 MM 52 53 55 59 63 64 69 PP1V8_S0GPU_ISNS 6 7 8 51 76 77 78
PP5V_S5 7 23 57 67 73 102 MIN_NECK_WIDTH=0.20MM 101 74 71 40 26 25 15 13 12 10 7 6 PPCPUVTT_S0 PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 71 74 101 79
VOLTAGE=3.3V MIN_LINE_WIDTH=0.6 MM PP1V8_S0GPU_ISNS 6 7 8 51 76 77 78
MAKE_BASE=TRUE ? mA MIN_NECK_WIDTH=0.2 MM 79
VOLTAGE=1.05V
103 83 73 68
43 33 31 7 6 PP5V_S3 PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 70 71 72 73 74 81 84
6 7 8 25 26 27 28 30
85 86 88 99 101
34 37 40 42 47 48 49 MAKE_BASE=TRUE
55 51 47 45 44 MIN_LINE_WIDTH=0.5 mm 52 53 55 59 63 64 69 87 51 7 6 PP1V8_S0GPU_ISNS_R PP1V8_S0GPU_ISNS_R 6 7 51 87
MIN_NECK_WIDTH=0.25 mm PP3V3_S0 84 85 86 88 99 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 71 74 101 MIN_LINE_WIDTH=0.6 MM
VOLTAGE=5V 52 53 55 59 63 64 69 70 71 72 73 74 81 MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE PP3V3_S0 84
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 71 74 101 VOLTAGE=1.25V
52 53 55 59 63 64 69 70 71 72 73 74 81 MAKE_BASE=TRUE
PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 85 86 88 99 101 PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 71 74 101
PP1V8_S0GPU_ISNS_R 6 7 51 87
PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 84 85 86 88 99 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 71 74 101
52 53 55 59 63 64 69 70 71 72 73 74 81
PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 PP1V05_S0GPU_ISNS_R
71 74 101 87 51 7 PP1V05_S0GPU_ISNS_R 7 51 87
PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 84 85 86 88 99 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 71 74 101 MIN_LINE_WIDTH=0.6 MM
PP5V_S3 52 53 55 59 63 64 69 70 71 72 73 74 81 MIN_NECK_WIDTH=0.2 MM
6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 6 7 8 25 26 27 28 30 34 37 40 42 47 48 49
84
PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 71 74 101 VOLTAGE=1.05V
52 53 55 59 63 64 69 70 71 72 73 74 81 MAKE_BASE=TRUE
B PP5V_S3
PP5V_S3
6 7 31 33 43 44 45 47 51 55 68 73 83 103
6 7 31 33 43 44 45 47 51 55 68 73 83 103
PP3V3_S0
PP3V3_S0
85 86 88 99 101
6 49 52 53 55 59 63 64 69 70
857 8 25 26 27 28 30 34 37 40 42 47 48
5271 72 73 74 81 84 85 86 88 99 101
6 PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 71 74 101
PP1V05_S0GPU_ISNS_R 7 51 87 B
7 8 25 26 27 28 30 34 37 40 42 47 48 49
PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 53 55 59 63 64 69 70 71 72 73 74 81 84
866 88 99 101 PPCPUVTT_S0 74 101
6 7 10 12 13 15 25 26 40
PP1V05_S0GPU
7 81 84 85 86 88 99 101 71 82 80 77 75 51 7 6 PP1V05_S0GPU 6 7 51 75 77 80 82
PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 99
8 25 26 27 28 30 34 37 40 42 47 48 49
52 53 55 59 63 64 69 70 71 72 73 74 MIN_LINE_WIDTH=0.6 MM
PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 63 64 69 70 71 72 73 74 81 84 85 86 88 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49
52 53 55 59
Chipset "VCore" Rails VOLTAGE=1.05V
MAKE_BASE=TRUE
PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 50 15 12 7 6 PPVCORE_S0_CPU PPVCORE_S0_CPU 6 7 12 15 50 69
69 MIN_LINE_WIDTH=0.6 MM PP1V05_S0GPU 6 7 51 75 77 80 82
PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103 PP3V3_S0 84 85 86
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 MIN_NECK_WIDTH=0.25 MM
52 53 55 59 63 64 69 70 71 72 73 74 81 VOLTAGE=1.25V PP1V05_S0GPU 6 7 51 75 77 80 82
PP3V3_S0 88 99 101
6 49 52 53 55 59 63 64 69 70 71 72 MAKE_BASE=TRUE
7 8 25 26 27 28 30 34 37 40 42 47 48 PP1V05_S0GPU 6 7 51 75 77 80 82
PP3V3_S0 73 74 81 84 85 86 88 99 101 PPVCORE_S0_CPU 6 7 12 15 50 69
99 101 PP1V05_S0GPU 6 7 51 75 77 80 82
PP3V3_S0 63 64 69 70 71 72 73 74 81 84
6 7 8 25 26 27 28 30 34 37 40
85 86 88
42 47 48 49
67 51 7 PP5V_S3_ISNS_R PP5V_S3_ISNS_R 7 51 67 52 53 55 59 PP1V05_S0GPU 6 7 51 75 77 80 82
MIN_LINE_WIDTH=0.5 MM PP3V3_S0 50 24 13 7 PPVCORE_S0_GFX PPVCORE_S0_GFX 7 13 24 50 70
MIN_NECK_WIDTH=0.25 MM 70 MIN_LINE_WIDTH=0.6 MM PP1V05_S0GPU 6 7 51 75 77 80 82
VOLTAGE=5V PP3V3_S0 70 71 72 74 81 84 85 86 88 99 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE 52 53 55 59 63 64 69 73 VOLTAGE=1.05V PP1V05_S0GPU 6 7 51 75 77 80 82
PP3V3_S0 84 85 86 88 99 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 MAKE_BASE=TRUE
PP5V_S3_ISNS_R 7 51 67 52 53 55 59 63 64 69 70 71 72 73 74 81 PP1V05_S0GPU 6 7 51 75 77 80 82
PP3V3_S0 PPVCORE_S0_GFX 7 13 24 50 70
101 PP1V05_S0GPU 6 7 51 75 77 80 82
PP3V3_S0 63 64 69 70 71 72 73 74 81 84 85 86 88
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49
102
55 53 48 42 23 8 7 6 PP5V_S0 PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 52 53 55 59
87 73 71 70 69 MIN_LINE_WIDTH=0.6 MM PP3V3_S0 99
16 12 7 PPVCORE_S0_CPU_VCAP0 PPVCORE_S0_CPU_VCAP0 7 12 16
MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM 83 76 50 7 6 PPVCORE_GPU PPVCORE_GPU 6 7 50 76 83
VOLTAGE=5V PP3V3_S0 70 71 72 73 74 81 84 85 86 88 99 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 MIN_NECK_WIDTH=0.25 MM MIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUE PP3V3_S0 84 85 86 88 99 101
52 53 55 59 63 64 69 VOLTAGE=1.25V MIN_NECK_WIDTH=0.2 MM
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49 MAKE_BASE=TRUE VOLTAGE=1.2V
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 52 53 55 59 63 64 69 70 71 72 73 74 81 MAKE_BASE=TRUE
PP3V3_S0 6 7 8 25 26
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 2730
2869 16 12 7
PPVCORE_S0_CPU_VCAP1 PPVCORE_S0_CPU_VCAP1 7 12 16 PPVCORE_GPU 6 7 50 76 83
PP3V3_S0 34 376 40 42 47 48 49 52 53 55 59 63 64 MIN_LINE_WIDTH=0.6 MM
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 70 717 72 73 74 81 84 85 86 88 99 101 MIN_NECK_WIDTH=0.25 MM
PP3V3_S0 8
25 26 27 28 30 34 37 40 42 47 48 VOLTAGE=1.25V
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 49 52 53 55 59 63 64 69 70 71 72 MAKE_BASE=TRUE
PP3V3_S0 73 74 81 84 85 86 88 99 101
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102
101
PP3V3_S0 53 55 59 63
6 7 24 13 7 PPVCORE_S0_CPU_VCAP2 PPVCORE_S0_CPU_VCAP2 7 13 24
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 8 25 26 27 28 30 34 37 40 42 47 48 49 52 MIN_LINE_WIDTH=0.6 MM
PP3V3_S0 64 69 70 71 72 73 74 81 84 85 86 88 99
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 VOLTAGE=1.25V
PP3V3_S0 84 85
6 7 8
86
25
88
26
99 101
27 28 30 34 37 40 42 47 48 49 MAKE_BASE=TRUE
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 52 53 55 59 63 64 69 70 71 72 73 74 81
PP3V3_S0 84
PP5V_S0 6 7 8 25 26 27 28 30 34 37 40 42 47 48 49
ENET Rails
A PP5V_S0
6 7 8 23 42 48 53 55 69 70 71 73 87 102
6 7 8 23 42 48 53 55 69 70 71 73 87 102
PP3V3_S0
PP3V3_S0
52 53
85 86
84 85 86
55
88
59
99
63 64 69
101
74 37 27 7
70 71 72
PP3V3_ENET
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49
73 74 81
PP3V3_ENET
7 27 37 74 SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER) A
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 52 53 55 59 63 64 69 70 71 72 73 74 81 MIN_NECK_WIDTH=0.2 MM PAGE TITLE
PP3V3_S0
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102
PP3V3_S0
88 99 101
6 49 52 53 55 59 63 64 69 70 71 72
857 8 25 26 27 28 30 34 37 40 42 47 48
5273 74 81 84 85 86 88 99 101
6
VOLTAGE=3.3V
MAKE_BASE=TRUE Power Aliases
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102 7 8 25 26 27 28 30 34 37 40 42 47 48 49 PP3V3_ENET 7 27 37 74 DRAWING NUMBER SIZE
PP3V3_S0 53 55 59 63 64 69 70 71 72 73 74 81 84
PP5V_S0 6 7 8 23 42 48 53 55 69 70 71 73 87 102
86 88 99 101
Apple Inc. D
101 88 73 72 16 12 7 6 PP1V8_S0 PP1V8_S0 6 7 12 16 72 73 88 101 PP1V2_ENET PP1V2_ENET 7 37 72 73 REVISION
MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.6 MM R
2A max supply MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V VOLTAGE=1.2V
102 73 7 PP5V_S0_ISNS_R PP5V_S0_ISNS_R 7 73 102 MAKE_BASE=TRUE MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY: BRANCH
MIN_NECK_WIDTH=0.25 MM PP1V8_S0 6 7 12 16 72 73 88 101 THE INFORMATION CONTAINED HEREIN IS THE
VOLTAGE=5V PP1V2_ENET 7 37 72 73 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MAKE_BASE=TRUE PP1V8_S0 6 7 12 16 72 73 88 101 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PP1V2_ENET
PP5V_S0_ISNS_R 7 73 102 PP1V8_S0 6 7 12 16 72 73 88 101
7 37 72 73
8 OF 132
PP1V8_S0 6 7 12 16 72 73 88 101
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Thermal Module Holes ZT0981
STDOFF-4.5OD.98H-1.1-3.48-TH
CPU signals
1
ZT0984 CPU_VID<0..6> CPUIMVP_VID<0..6> 69 TP_CPU_VTT_SELECT TP_CPU_VTT_SELECT
ZT0982 STDOFF-4.5OD.98H-1.1-3.48-TH 91 15 12
MAKE_BASE=TRUE
91 12 8
MAKE_BASE=TRUE
8 12 91
STDOFF-4.5OD.98H-1.1-3.48-TH 1 91 13 GFX_VID<0..6> GFXIMVP_VID<0..6> 70

MAKE_BASE=TRUE
1
Top GPU Right 68 31 8 MEMVTT_EN MEMVTT_EN 8 31 68
MAKE_BASE=TRUE
TM Hole
ZT0983 ZT0980
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
1
1
D Left CPU Right CPU Bottom Left GPU ZT0930

STDOFF-4.5OD.98H-1.1-3.48-TH
80 8 NC_GPU_XTALOUT
MAKE_BASE=TRUE NO_TEST=TRUE
NC_GPU_XTALOUT 8 80
D
TM Hole TM Hole TM Hole 93 18 8 NC_LVDS_IG_A_DATAP<3> NC_LVDS_IG_A_DATAP<3> 8 18 93
1
ZT0987 93 18 8 NC_LVDS_IG_A_DATAN<3>
NC_LVDS_IG_A_DATAN<3> 8 18 93
STDOFF-4.5OD.98H-1.1-3.48-TH
Frame Holes 1
93 18 8 NC_LVDS_IG_B_DATAP<3> NC_LVDS_IG_B_DATAP<3> 8 18 93
GMUX ALIASES 93 18 8 NC_LVDS_IG_B_DATAN<3> NC_LVDS_IG_B_DATAN<3> 8 18 93
ZT0915 GPU signals MAKE_BASE=TRUE NO_TEST=TRUE

3R2P5 SH0920
1.4DIA-SHORT-EMI-MLB-M97-M98 91 75 9 PEG_D2R_P<15..0> =PEG_D2R_P<0..15> 93 18 8 6 TP_LVDS_IG_B_CLKP TP_LVDS_IG_B_CLKP 6 8 18 93
1 GND SM 88 87 83 74 8 PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD 8 74 83 87 88 MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
91 75 9 PEG_D2R_N<15..0> =PEG_D2R_N<0..15>
1 MAKE_BASE=TRUE 93 18 8 6 TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKN 6 8 18 93
88 8 TP_LVDS_MUX_SEL_EG TP_LVDS_MUX_SEL_EG 8 88 MAKE_BASE=TRUE
MAKE_BASE=TRUE 91 75 PEG_R2D_C_P<15..0> =PEG_R2D_C_P<0..15> 9
MAKE_BASE=TRUE 18 8 6 TP_LVDS_IG_BKL_PWM TP_LVDS_IG_BKL_PWM 6 8 18
SH0911 88 75 8 EG_RESET_L EG_RESET_L 8 75 88 MAKE_BASE=TRUE
MAKE_BASE=TRUE 91 75 PEG_R2D_C_N<15..0> =PEG_R2D_C_N<0..15> 9
1.4DIA-SHORT-EMI-MLB-M97-M98 LVDS_IG_BKL_ON LVDS_IG_BKL_ON MAKE_BASE=TRUE
ZT0932 SH0910 SM 88 18 8
MAKE_BASE=TRUE
8 18 88
3R2P5 1.4DIA-SHORT-EMI-MLB-M97-M98 1 88 18 8 LVDS_IG_PANEL_PWR LVDS_IG_PANEL_PWR 8 18 88

1 SM MAKE_BASE=TRUE
1 90 88 8 LCD_BKLT_EN LCD_BKLT_EN 8 88 90
** PEG LANES REVERSED. ARD STRAP REQ’D. **
ZT0960 MAKE_BASE=TRUE
3R2P5 R0902 USB Hub Aliases
1 3.0K 2
SH0913 91 25 9 CPU_CFG<3> 1
ZT0971 1.4DIA-SHORT-EMI-MLB-M97-M98 88 75 8 PEX_CLKREQ_L PEX_CLKREQ_L 8 75 88 5%

SH0912 SM MAKE_BASE=TRUE 1/16W 47 36 34 8 EXCARD_OC_L EXCARD_OC_L 8 34 36 47
3R2P5 MF-LF MAKE_BASE=TRUE
1.4DIA-SHORT-EMI-MLB-M97-M98 88 17 8 PEG_CLKREQ_L PEG_CLKREQ_L 8 17 88 402
1 1 MAKE_BASE=TRUE
SM 44 35 8 USB_EXTC_OC_L USB_EXTC_OC_L 8 35 44
MAKE_BASE=TRUE
85 86 88 99 101 93 36 34 8 USB_EXCARD_N USB_EXCARD_N 8 34 36 93

DP_IG_ML_P<3..0> DP_IG_B_ML_P<3..0>
C 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49
74 72 8
PP3V3_S0
MAKE_BASE=TRUE
PM_ENET_EN
PP3V3_S0
PM_ENET_EN
69 70
48 49
6 7 8
30 34
55 59
71
52
25
37
63
72
53 93 85
26 27 28
40 42 47
64
MAKE_BASE=TRUE
DP_IG_ML_N<3..0> DP_IG_B_ML_N<3..0>
18
93 36 34 8
MAKE_BASE=TRUE
USB_EXCARD_P
MAKE_BASE=TRUE
USB_EXCARD_P 8 34 36 93
C
73 74 81 84 93 85 18
ZT0940 SH0914 MAKE_BASE=TRUE MAKE_BASE=TRUE

3R2P5 1.4DIA-SHORT-EMI-MLB-M97-M98 93 85 18 8 DP_IG_AUX_CH_P DP_IG_AUX_CH_P 8 18 85 93
1 SM MAKE_BASE=TRUE
93 85 18 8 DP_IG_AUX_CH_N DP_IG_AUX_CH_N 8 18 85 93
1 GND GND MAKE_BASE=TRUE Rev. A NCs
MAKE_BASE=TRUE
ZT0970 GND
DP_IG_DDC_CLK DP_IG_DDC_CLK NC_ISNS_P1V05S0PCH_N NC_ISNS_P1V05S0PCH_N
3R2P5 GND 85 81 18 8 8 18 81 85 99 50 8 8 50 99
1 SH0923 MAKE_BASE=TRUE MAKE_BASE=TRUE

1.4DIA-SHORT-EMI-MLB-M97-M98 GND 85 81 18 8 DP_IG_DDC_DATA DP_IG_DDC_DATA 8 18 81 85
SM MAKE_BASE=TRUE 99 50 8 NC_ISNS_P1V05S0PCH_P NC_ISNS_P1V05S0PCH_P 8 50 99
MAKE_BASE=TRUE
85 18 8 DP_IG_HPD DP_IG_HPD 8 18 85
1
SH0924 GND MAKE_BASE=TRUE
102 99 8 NC_ISNS_P3V3S0MPCH_N NC_ISNS_P3V3S0MPCH_N 8 99 102
2.0DIA-TALL-EMI-MLB-M97-M98 MAKE_BASE=TRUE
SM NC_ISNS_P3V3S0MPCH_P NC_ISNS_P3V3S0MPCH_P
ZT0934 ZT0931 1 93 17 8 TP_SATA_EXTA_D2R_N TP_SATA_EXTA_D2R_N 8 17 93
102 99 8
MAKE_BASE=TRUE
8 99 102
STDOFF-4.0OD3.0H-SM STDOFF-4.0OD3.0H-SM MAKE_BASE=TRUE

102 99 8 NC_ISNS_PVTTS0PCH_N NC_ISNS_PVTTS0PCH_N 8 99 102
1 1
FW_PLUG_DET_L 93 17 8 TP_SATA_EXTA_D2R_P TP_SATA_EXTA_D2R_P 8 17 93 MAKE_BASE=TRUE
40 20 8 FW_PLUG_DET_L 8 20 40 MAKE_BASE=TRUE
MAKE_BASE=TRUE 102 99 8 NC_ISNS_PVTTS0PCH_P NC_ISNS_PVTTS0PCH_P 8 99 102
SH0916 93 17 8 TP_SATA_EXTA_R2D_C_N TP_SATA_EXTA_R2D_C_N 8 17 93 MAKE_BASE=TRUE
FW643_WAKE_L MAKE_BASE=TRUE
2.0DIA-TALL-EMI-MLB-M97-M98 40 39 8 FW643_WAKE_L 8 39 40
MAKE_BASE=TRUE 93 17 8 TP_SATA_EXTA_R2D_C_P TP_SATA_EXTA_R2D_C_P 8 17 93
ZT0988 SM MAKE_BASE=TRUE
Per WF: R0914 can’t be stuffed, it will break CPU IMON Calculation.
STDOFF-4.5OD.98H-1.1-3.48-TH 1 It will be removed from the design after proto1.
1 SH0917 R0900
2.0DIA-TALL-EMI-MLB-M97-M98 10
ZT0989 SM 79 78 77 76 51 7 6 PP1V8_S0GPU_ISNS 1 2 GPU_FB_A_VREF_DIV 8 32 78
STDOFF-4.5OD.98H-1.1-3.48-TH MAKE_BASE=TRUE
1 1%
1/16W
1 MF-LF GPU_FB_A_VREF_DIV 8 32 78
402
ZT0991 SH0918 AUDIO ALIASES R0901
STDOFF-4.5OD.98H-1.1-3.48-TH 2.0DIA-TALL-EMI-MLB-M97-M98 10 GPU_FB_B_VREF_DIV
B 1
SM
1
SH0919
1
1%
2
MAKE_BASE=TRUE
8 32 79
B
2.0DIA-TALL-EMI-MLB-M97-M98
XW0900
SM
1/16W
MF-LF
GPU_FB_B_VREF_DIV 8 32 79
SM 402
102 87 73 71 70 69 55 53 48 42 23 7 6 PP5V_S0 2 1 PP5V_S0_AUDIO 59 61
SH0930 1
MIN_LINE_WIDTH=0.5 mm
2.0DIA-TALL-EMI-MLB-M97-M98 SM VOLTAGE=5V
SM 2 1 PP5V_S0_AUDIO_AMP_R
Bosses for Flex Protector Bracket 1 XW0901 MIN_LINE_WIDTH=0.5 mm
62
VOLTAGE=5V
ZT0957 SH0921 SM
4.0OD1.65H-M1.6X0.35 2.0DIA-TALL-EMI-MLB-M97-M98
SM
2 1 PP5V_S0_AUDIO_AMP_L 62
1 MIN_LINE_WIDTH=0.5 mm
1
XW0902 MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
ZT0958 SH0931
4.0OD1.65H-M1.6X0.35 2.0DIA-TALL-EMI-MLB-M97-M98
SM BKLT_PWR_PBUS
1
1 R0904
SH0922
2.0DIA-TALL-EMI-MLB-M97-M98 83 71 70 68 67 66 50 40 7 6 PPBUS_G3H 1
0 2 PPVIN_S0_LCDBKLT 8 90
Digital Ground
SM
5% MIN_NECK_WIDTH=0.25 mm
1/10W VOLTAGE=6V
1 MF-LF MAKE_BASE=TRUE GND
SH0932 603 MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
2.0DIA-TALL-EMI-MLB-M97-M98 R0903 PPVIN_S0_LCDBKLT 8 90 VOLTAGE=0V
SM 0
72 40 7 PP10V_FW 1 2
1
SH0902 SH0934 5%
1/10W
2.0DIA-TALL-EMI-MLB-M97-M98 SH0900 2.0DIA-TALL-EMI-MLB-M97-M98 MF-LF
603
SM 2.0DIA-TALL-EMI-MLB-M97-M98 SM
1 SM 1
BKLT_PWR_FW10V
A 1 GMUX_VSYNC SYNC_MASTER=K17_REF SYNC_DATE=06/17/2009 A
PAGE TITLE
SH0933 R0906
SM SH0935 8 BKL_SYNC 8 BKL_SYNC 1
0 2 GMUX_VSYNC 88
Signal Aliases
SH0903 2.0DIA-TALL-EMI-MLB-M97-M98 5%
1
SM
1/16W
MF-LF Apple Inc. D
SM 402 REVISION
SH0901 1 R
1 2.0DIA-TALL-EMI-MLB-M97-M98 R0907
SM 0 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1 2 LVDS_CONN_BKL_SYNC 6 84
1 5% PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
1/16W THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF-LF
402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
9 OF 132
PANEL_VSYNC III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1000 U1000
ARRANDALE ARRANDALE
BGA BGA
(SYM 1 OF 11) (SYM 5 OF 11)
91 18 DMI_S2N_N<0> F7 DMI_RX0* PEG_ICOMPI B12 91 CPU_PEG_COMP RSVD32 W66 NC_TP_CPU_RSVD<32> 6

IN
91 18 DMI_S2N_N<1> J8 DMI_RX1* PEG_ICOMPO A13 RSVD33 W64 NC_TP_CPU_RSVD<33> 6
IN
91 18 DMI_S2N_N<2> K8 DMI_RX2* PEG_RCOMPO D12
IN
J4 B11 RSVD34 AC69 NC_TP_CPU_RSVD<34> 6
91 18 DMI_S2N_N<3> DMI_RX3* PEG_RBIAS 91 CPU_PEG_RBIAS
D 91 18
IN
IN DMI_S2N_P<0> F9 DMI_RX0 G40

RSVD35 AC71 NC_TP_CPU_RSVD<35> 6
D
J6 PEG_RX0* PEG_D2R_N<15> IN 8 75 91 R10121 1
R1010 RSVD36 AA71 NC_TP_CPU_RSVD<36> 6
91 18 DMI_S2N_P<1> DMI_RX1 G38
IN
K9 PEG_RX1* PEG_D2R_N<14> IN 8 75 91 750 49.9 RSVD37 AA69 NC_TP_CPU_RSVD<37> 6
91 18 IN DMI_S2N_P<2> DMI_RX2 H34 1% 1%
J2 PEG_RX2* PEG_D2R_N<13> 8 75 91 1/16W 1/16W
RSVD38 R66
DMI_S2N_P<3> IN NC_TP_CPU_RSVD<38>
91 18 IN DMI_RX3 P34 MF-LF MF-LF 6
PEG_RX3* PEG_D2R_N<12> 8 75 91 402 2 2 402 RSVD39 R64
IN NC_TP_CPU_RSVD<39>
PEG_RX4* G28 PEG_D2R_N<11> 6
DMI
IN 8 75 91
91 18 DMI_N2S_N<0> H17 DMI_TX0*
OUT H25
K15 PEG_RX5* PEG_D2R_N<10> IN 8 75 91 RSVD_NCTF3 BT5 NC_TP_CPU_RSVD<40> 6
91 18 OUT DMI_N2S_N<1> DMI_TX1* H24 AL4
J13 PEG_RX6* PEG_D2R_N<9> IN 8 75 91 91 25 IN CPU_CFG<0> CFG0 (IPU) RSVD_NCTF4 BR5 NC_TP_CPU_RSVD<41> 6
91 18 OUT DMI_N2S_N<2> DMI_TX2* D29 AM2
F10 PEG_RX7* PEG_D2R_N<8> 8 75 91 91 25 CPU_CFG<1> CFG1 (IPU)
91 18 OUT DMI_N2S_N<3> DMI_TX3* B26
IN IN
AK1 RSVD_NCTF2 BV6 NC_TP_CPU_RSVD<42> 6
PEG_RX8* PEG_D2R_N<7> 8 75 91 91 25 CPU_CFG<2> CFG2 (IPU)
G17 D26
IN IN
AK2 RSVD_NCTF1 BV8 NC_TP_CPU_RSVD<43> 6
91 18 OUT DMI_N2S_P<0> DMI_TX0 PEG_RX9* PEG_D2R_N<6> IN 8 75 91 Embedded DisplayPort 91 25 8 IN CPU_CFG<3> CFG3 (IPU)
91 18 DMI_N2S_P<1> M15 DMI_TX1 PEG_RX10* B23 PEG_D2R_N<5> 8 75 91 (eDP) pins 91 25 CPU_CFG<4> AK4 CFG4 (IPU) RSVD45 AV69 TP_CPU_RSVD<45> 6
OUT IN IN
91 18 DMI_N2S_P<2> G13 DMI_TX2 PEG_RX11* D22 PEG_D2R_N<4> 8 75 91 (Auburndale only): 91 25 CPU_CFG<5> AJ2 CFG5 (IPU) RSVD46 AK71 TP_CPU_RSVD<46> 6
OUT IN IN
91 18 DMI_N2S_P<3> J11 DMI_TX3 PEG_RX12* A20 PEG_D2R_N<3> 8 75 91 91 25 CPU_CFG<6> AT2 CFG6 (IPU) RSVD47 AN69 TP_CPU_RSVD<47> 6
OUT IN IN
PEG_RX13* D19 PEG_D2R_N<2> 8 75 91 eDP_AUX# 91 25 CPU_CFG<7> AG7 CFG7 (IPU) RSVD48 AP66 TP_CPU_RSVD<48> 6
IN IN
PEG_RX14* A17 PEG_D2R_N<1> 8 75 91 91 25 CPU_CFG<8> AF4 CFG8 (IPU) RSVD49 AH66 TP_CPU_RSVD<49> 6
IN IN
PEG_RX15* B14 PEG_D2R_N<0> 8 75 91 91 25 CPU_CFG<9> AG2 CFG9 (IPU) RSVD50 AK66 TP_CPU_RSVD<50> 6
IN IN
91 18 FDI_DATA_N<0> L2 FDI_TX0* 91 25 CPU_CFG<10> AH1 CFG10 (IPU) RSVD51 AR71 TP_CPU_RSVD<51> 6
OUT
PEG_RX0 F40 PEG_D2R_P<15> 8 75 91
IN
FDI_DATA_N<1> N7 IN CPU_CFG<11> AC2 AM66 TP_CPU_RSVD<52>
91 18 OUT FDI_TX1* J38 PEG_D2R_P<14> 91 25 IN CFG11 (IPU) RSVD52 6
M4 PEG_RX1 IN 8 75 91
AC4 AK69
91 18 OUT FDI_DATA_N<2> FDI_TX2* G34 91 25 IN CPU_CFG<12> CFG12 (IPU) RSVD53 TP_CPU_RSVD<53> 6
P1 PEG_RX2 PEG_D2R_P<13> IN 8 75 91
AE2 AU71
91 18 OUT FDI_DATA_N<3> FDI_TX3* M34 91 25 IN CPU_CFG<13> CFG13 (IPU) RSVD54 TP_CPU_RSVD<54> 6
N10 PEG_RX3 PEG_D2R_P<12> IN 8 75 91 AD1 AT70
91 18 OUT FDI_DATA_N<4> FDI_TX4* J28 91 25 IN CPU_CFG<14> CFG14 (IPU) RSVD55 TP_CPU_RSVD<55> 6
R7 PEG_RX4 PEG_D2R_P<11> IN 8 75 91
AF8 AR69
91 18 OUT FDI_DATA_N<5> FDI_TX5* G25 91 25 IN CPU_CFG<15> CFG15 (IPU) RSVD56 TP_CPU_RSVD<56> 6
PEG_RX5 PEG_D2R_P<10>
RESERVED
U7 IN 8 75 91
FDI_DATA_N<6> CPU_CFG<16> AF6 (IPU) AU69 TP_CPU_RSVD<57>
FLEXIBLE DISPLAY INTERFACE

91 18 OUT FDI_TX6* K24 91 25 IN CFG16 RSVD57 6
W8 PEG_RX6 PEG_D2R_P<9> IN 8 75 91 AB7 AT67
91 18 OUT FDI_DATA_N<7> FDI_TX7* B28 91 25 IN CPU_CFG<17> CFG17 (IPU) RSVD58 TP_CPU_RSVD<58> 6
PEG_RX7 PEG_D2R_P<8> IN 8 75 91
91 18 FDI_DATA_P<0> K1 FDI_TX0 PEG_RX8 A27 PEG_D2R_P<7> 8 75 91 TP_CPU_RSVD_TP0 AU1 RSVD_TP0 RSVD_TP2 AP2 TP_CPU_RSVD<2> 6
OUT IN
NOTE: HPD must be inverted
C 91 18
91 18
OUT FDI_DATA_P<1>
FDI_DATA_P<2>
N5
N2
FDI_TX1
FDI_TX2
PEG_RX9
PEG_RX10
B25
A24
PEG_D2R_P<6>
PEG_D2R_P<5>
IN 8 75 91
8 75 91
and level-shifted for 6 TP_CPU_RSVD<15> T4 RSVD15
RSVD_TP1 AN7 TP_CPU_RSVD<1> 6 C
OUT IN T2
R2 B21 Auburndale (1.05V). 6 TP_CPU_RSVD<16> RSVD16 RSVD62 AV4 CPU_THERMD_P BI 52 99
91 18 OUT FDI_DATA_P<3> FDI_TX3 PEG_RX11 PEG_D2R_P<4> IN 8 75 91
N9 B19 U1 RSVD63 AU2 CPU_THERMD_N BI 52 99
91 18 OUT FDI_DATA_P<4> FDI_TX4 PEG_RX12 PEG_D2R_P<3> IN 8 75 91 eDP_HPD# 6 TP_CPU_RSVD<17> RSVD17
91 18 FDI_DATA_P<5> R8 FDI_TX5 PEG_RX13 B18 PEG_D2R_P<2> 8 75 91 eDP_AUX 6 TP_CPU_RSVD<18> V2 RSVD18 RSVD64 BE69 TP_CPU_RSVD<64> 6
OUT IN
PCI EXPRESS -- GRAPHICS
91 18 FDI_DATA_P<6> U6 FDI_TX6 PEG_RX14 B16 PEG_D2R_P<1> 8 75 91 RSVD65 BE71 TP_CPU_RSVD<65>

OUT IN
6 TP_CPU_RSVD<19> AV71 RSVD19
6
91 18 FDI_DATA_P<7> W10 FDI_TX7 PEG_RX15 D15 PEG_D2R_P<0> 8 75 91

OUT IN
6 TP_CPU_RSVD<20> AW70 RSVD20 DC_TEST_BV71 BV71 CPU_TEST_BV71_BV69
DC_TEST_BV69 BV69
91 18 FDI_FSYNC<0> AC7 FDI_FSYNC0 PEG_TX0* N40 =PEG_R2D_C_N<0> 8 6 TP_CPU_RSVD<21> AY69 RSVD21
IN OUT
DC_TEST_BV68 BV68 TP_CPU_TEST_BV68
91 18 FDI_FSYNC<1> AC9 FDI_FSYNC1 PEG_TX1* L38 =PEG_R2D_C_N<1> 8 6 TP_CPU_RSVD<22> BB69 RSVD22
IN OUT
DC_TEST_BV5 BV5 TP_CPU_TEST_BV5
PEG_TX2* M32 =PEG_R2D_C_N<2> 8
FDI_INT AB5 OUT TP_CPU_RSVD<23> D8 BV3 CPU_TEST_BV3_BT3
91 18 IN FDI_INT D40 6 RSVD23 DC_TEST_BV3
PEG_TX3* =PEG_R2D_C_N<3> OUT 8 B7 BV1
AA1 A38 6 TP_CPU_RSVD<24> RSVD24 DC_TEST_BV1 CPU_TEST_BV1_BT1
91 18 IN FDI_LSYNC<0> FDI_LSYNC0 PEG_TX4* =PEG_R2D_C_N<4> OUT 8 BT71
AB2 G32 A10 DC_TEST_BT71 CPU_TEST_BT71_BT69
91 18 IN FDI_LSYNC<1> FDI_LSYNC1 PEG_TX5* =PEG_R2D_C_N<5> OUT 8 6 TP_CPU_RSVD<26> RSVD26 BT69
B33 B9 DC_TEST_BT69
PEG_TX6* =PEG_R2D_C_N<6> OUT 8 6 TP_CPU_RSVD<27> RSVD27 BT3
B35 DC_TEST_BT3
PEG_TX7* =PEG_R2D_C_N<7> OUT 8 C5 BT1
L30 6 NC_TP_CPU_RSVD_NCTF<7> RSVD_NCTF7 DC_TEST_BT1
PEG_TX8* =PEG_R2D_C_N<8> OUT 8 A6 BR71
A31 6 NC_TP_CPU_RSVD_NCTF<8> RSVD_NCTF8 DC_TEST_BR71 TP_CPU_TEST_BR71
PEG_TX9* =PEG_R2D_C_N<9> OUT 8 BR1
B32 E3 DC_TEST_BR1 TP_CPU_TEST_BR1
PEG_TX10* =PEG_R2D_C_N<10> OUT 8 6 NC_TP_CPU_RSVD_NCTF<6> RSVD_NCTF6 E71
L28 F1 DC_TEST_E71 TP_CPU_TEST_E71
PEG_TX11* =PEG_R2D_C_N<11> OUT 8 6 NC_TP_CPU_RSVD_NCTF<5> RSVD_NCTF5 E1
N26 DC_TEST_E1 TP_CPU_TEST_E1
PEG_TX12* =PEG_R2D_C_N<12> OUT 8 eDP_TX#<3> C71
M24 DC_TEST_C71 CPU_TEST_C71_A71
G21 DC_TEST_C69 CPU_TEST_C69_A69
J20 DC_TEST_C3 TP_CPU_TEST_C3
PEG_TX15* =PEG_R2D_C_N<15> OUT 8 eDP_TX#<0> A71
DC_TEST_A71
PEG_TX0 L40 =PEG_R2D_C_P<0> 8 DC_TEST_A69 A69
OUT
PEG_TX1 N38 =PEG_R2D_C_P<1> 8 DC_TEST_A68 A68 TP_CPU_TEST_A68
B PEG_TX2 N32
B39
=PEG_R2D_C_P<2>
OUT
OUT 8 DC_TEST_A5 A5 TP_CPU_TEST_A5 B
PEG_TX3 =PEG_R2D_C_P<3> OUT 8
PEG_TX4 B37 =PEG_R2D_C_P<4> 8

OUT
PEG_TX5 H32 =PEG_R2D_C_P<5> 8
OUT
PEG_TX6 A34 =PEG_R2D_C_P<6> 8
OUT
PEG_TX7 D36 =PEG_R2D_C_P<7> 8
OUT
J30 =PEG_R2D_C_P<8> CFG0: PCIe Configuration Select 1 = Single PEG 0 = Bifurcation Enabled
PEG_TX8 OUT 8
B30 =PEG_R2D_C_P<9> CFG3: PCIe Lane Reversal 1 = Normal Operation 0 = Lanes Reversed
PEG_TX9 OUT 8
D33 =PEG_R2D_C_P<10> CFG4: Display Port Presence 1 = eDP Disabled 0 = Embedded Display Port Enabled
PEG_TX10 OUT 8
PEG_TX11 N28 =PEG_R2D_C_P<11> 8

OUT
PEG_TX12 M25 =PEG_R2D_C_P<12> OUT 8 eDP_TX<3> WF: RSVD nets with arrows have offpage marks on CRB schematic.
PEG_TX13 N24 =PEG_R2D_C_P<13> eDP_TX<2>
PEG_TX14 F21 =PEG_R2D_C_P<14>
OUT
OUT
8
8 eDP_TX<1>
WF: RSVD nets with red wires have 0-ohm resistors to GND in CRB schematic.
PEG_TX15 L20 =PEG_R2D_C_P<15> 8 eDP_TX<0>
OUT
A SYNC_MASTER=K17_WFERRY SYNC_DATE=06/09/2009 A
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

10 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
101 74 71 40 26 25 15 13 12 10 7 6 PPCPUVTT_S0
NO STUFF OMIT
D
1
R1100
49.9
R11011
68
R11021
68
1
R1103
1K U1000
R11501
10K
1
R1151
10K
D
1% 5% 5% 5% 5% 5%
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
ARRANDALE 1/16W
MF-LF
1/16W
MF-LF
BGA
2 402 402 2 402 2 2 402 402 2 2 402
(SYM 2 OF 11)
91 CPU_COMP3 AD71 COMP3 BCLK AK7 FSB_CLK133M_CPU_P 20 91
IN
91 CPU_COMP2 AC70 COMP2 BCLK* AK8 FSB_CLK133M_CPU_N 20 91
IN
91 CPU_COMP1 AD69 COMP1
AE66 BCLK_ITP K71 FSB_CLK133M_ITP_P OUT 25 91
MISC
91 CPU_COMP0 COMP0
BCLK_ITP* J70 FSB_CLK133M_ITP_N OUT 25 91
R11101 R11121 M71 PEG_CLK L21 PCIE_CLK100M_CPU_P IN 17 91

TP_CPU_SKTOCC_L
CLOCKS
PROC_DETECT
20 49.9 PEG_CLK* J21 PCIE_CLK100M_CPU_N IN 17 91
1% 1% (GND)
1/16W 1/16W
MF-LF MF-LF DPLL_REF_SSCLK Y2 GFX_CLK120M_DPLLSS_P IN 17 93
402 2 402 2 N61
91 CPU_CATERR_L CATERR* DPLL_REF_SSCLK* W4 GFX_CLK120M_DPLLSS_N IN 17 93
1
R1111 1
R1113 N19 SM_DRAMRST* BJ12 CPU_MEM_RESET_L OUT 31
91 20 BI CPU_PECI PECI
THERMAL
20 49.9
1% 1% SM_RCOMP0 BV33 91 CPU_SM_RCOMP0
DDR3
MISC
1/16W 1/16W
MF-LF MF-LF N67 SM_RCOMP1 BP39 91 CPU_SM_RCOMP1
2 402 2 402 91 69 47 BI CPU_PROCHOT_L PROCHOT*
SM_RCOMP2 BV40 91 CPU_SM_RCOMP2
N17 PM_EXT_TS0* AV66 PM_EXT_TS_L<0> IN 47 91

91 47 20 PM_THRMTRIP_L THERMTRIP* R11601 R11621
OUT
PM_EXT_TS1* AV64 PM_EXT_TS_L<1> IN 47 91
130 100
1% 1%
1/16W 1/16W
N70 PRDY* U71 XDP_PRDY_L OUT 25 91 MF-LF MF-LF
91 25 FSB_CPURST_L RESET_OBS* 402 2 402 2
OUT
(IPU) PREQ* U69 XDP_PREQ_L IN 25 91
M17 (IPU) TCK T67 XDP_TCK IN 25 91

91 18 BI PM_SYNC PM_SYNC 1
R1161
(IPU) TMS N65 XDP_TMS
C 101 74 71 40 26 25 15 13 12 10 7 6 PPCPUVTT_S0
(IPU) TRST* P69 XDP_TRST_L
IN
IN
25 91
25 91
24.9
1%
1/16W
C
AM7 VCCPWRGOOD_1 MF-LF
1
R1120 (IPU) TDI T69 JTAG_CPU_TDI IN 25
2 402
JTAG & MBP

(IPD)
PWR MANAGEMENT
1K TDO T71 JTAG_GMCH_TDO OUT 25
5% Y67
1/16W 91 25 20 IN CPU_PWRGD VCCPWRGOOD_0
MF-LF (IPU) TDI_M P71 JTAG_GMCH_TDI IN 25
2 402 (IPD)
TDO_M T70 JTAG_CPU_TDO OUT 25
91 31 18 PM_MEM_PWRGD AM5 SM_DRAMPWROK W71

IN XDP_DBRESET_L
DBR* OUT 25 27 91
(IPD)
(IPU) BPM0* J69 XDP_BPM_L<0> 25 91
CPUVTTS0_PGOOD H15 OUT
91 71 IN VTTPWRGOOD J67
(IPU) BPM1* XDP_BPM_L<1> OUT 25 91
(IPD) J62 XDP_BPM_L<2>
(IPU) BPM2* OUT 25 91
91 25 XDP_CPUPWRGD Y70 TAPPWRGOOD (IPU) BPM3* K65 XDP_BPM_L<3> 25 91

OUT OUT
(IPU) K62 XDP_BPM_L<4>
R1125 BPM4*
J64
OUT 25 91
1.5K 2 G3 (IPU) BPM5* XDP_BPM_L<5> OUT 25 91

27 IN PLT_RST_BUF_L 1 PLT_RESET_LS1V1_L RSTIN* K69
(IPU) BPM6* XDP_BPM_L<6> OUT 25 91
1%
1/16W (IPU) BPM7* M69 XDP_BPM_L<7> 25 91
OUT
MF-LF
402 R11261
750 1
1%
1/16W
R1170
MF-LF 51
402 2 5%
1/16W
MF-LF
402 2
B B
A SYNC_MASTER=K18_MLB SYNC_DATE=10/14/2009 A
PAGE TITLE
CPU Clock/Misc/JTAG
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

11 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1000 U1000
ARRANDALE ARRANDALE
BGA BGA
(SYM 3 OF 11) (SYM 4 OF 11)
92 29 MEM_A_DQ<0> AT8 SA_DQ0 SA_CK0 BM34 MEM_A_CLK_P<0> 28 92 92 29 MEM_B_DQ<0> BA2 SB_DQ0 SB_CK0 BU33 MEM_B_CLK_P<0> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<1> AT6 SA_DQ1 SA_CK0* BP35 MEM_A_CLK_N<0> 28 92 92 29 MEM_B_DQ<1> AW2 SB_DQ1 SB_CK0* BV34 MEM_B_CLK_N<0> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<2> BB5 SA_DQ2 92 29 MEM_B_DQ<2> BD1 SB_DQ2
D 92 29
BI
BI MEM_A_DQ<3> BB9
AV7
SA_DQ3
SA_CKE0 BF20 MEM_A_CKE<0> OUT 28 92
92 29
BI
BI MEM_B_DQ<3> BE4
AY1
SB_DQ3
SB_CKE0 BT26 MEM_B_CKE<0> OUT 30 92
D
92 29 MEM_A_DQ<4> SA_DQ4 92 29 MEM_B_DQ<4> SB_DQ4
BI
AV6 SA_CK1 BK36 MEM_A_CLK_P<1> OUT 28 92
BI
BC2 SB_CK1 BV38 MEM_B_CLK_P<1> OUT 30 92
92 29 BI MEM_A_DQ<5> SA_DQ5 92 29 BI MEM_B_DQ<5> SB_DQ5
BE6 SA_CK1* BH36 MEM_A_CLK_N<1> OUT 28 92
BF2 SB_CK1* BU39 MEM_B_CLK_N<1> OUT 30 92
92 29 BI MEM_A_DQ<6> SA_DQ6 92 29 BI MEM_B_DQ<6> SB_DQ6
92 29 MEM_A_DQ<7> BE8 SA_DQ7 SA_CKE1 BK24 MEM_A_CKE<1> 28 92 92 29 MEM_B_DQ<7> BH2 SB_DQ7 SB_CKE1 BT24 MEM_B_CKE<1> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<8> BF11 SA_DQ8 92 29 MEM_B_DQ<8> BG4 SB_DQ8
BI BI
92 29 MEM_A_DQ<9> BE11 SA_DQ9 SA_CS0* BH40 MEM_A_CS_L<0> 28 92 92 29 MEM_B_DQ<9> BG1 SB_DQ9 SB_CS0* BP46 MEM_B_CS_L<0> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<10> BK5 SA_DQ10 SA_CS1* BJ47 MEM_A_CS_L<1> 28 92 92 29 MEM_B_DQ<10> BR6 SB_DQ10 SB_CS1* BT43 MEM_B_CS_L<1> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<11> BH13 SA_DQ11 92 29 MEM_B_DQ<11> BR8 SB_DQ11
BI BI
92 29 MEM_A_DQ<12> BF9 SA_DQ12 SA_ODT0 BF43 MEM_A_ODT<0> 28 92 92 29 MEM_B_DQ<12> BJ4 SB_DQ12 SB_ODT0 BV45 MEM_B_ODT<0> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<13> BF6 SA_DQ13 SA_ODT1 BL47 MEM_A_ODT<1> 28 92 92 29 MEM_B_DQ<13> BK2 SB_DQ13 SB_ODT1 BU49 MEM_B_ODT<1> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<14> BK7 SA_DQ14 92 29 MEM_B_DQ<14> BU9 SB_DQ14
BI BI
92 29 MEM_A_DQ<15> BN8 SA_DQ15 SA_DM0 BB10 MEM_A_DM<0> 28 29 92 92 29 MEM_B_DQ<15> BV10 SB_DQ15 SB_DM0 BB4 MEM_B_DM<0> 29 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<16> BN11 SA_DQ16 SA_DM1 BJ10 MEM_A_DM<1> 29 92 92 29 MEM_B_DQ<16> BR10 SB_DQ16 SB_DM1 BL4 MEM_B_DM<1> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<17> BN9 SA_DQ17 SA_DM2 BM15 MEM_A_DM<2> 29 92 92 29 MEM_B_DQ<17> BT12 SB_DQ17 SB_DM2 BT13 MEM_B_DM<2> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<18> BG17 SA_DQ18 SA_DM3 BN24 MEM_A_DM<3> 29 92 92 29 MEM_B_DQ<18> BT15 SB_DQ18 SB_DM3 BP22 MEM_B_DM<3> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<19> BK15 SA_DQ19 SA_DM4 BG44 MEM_A_DM<4> 29 92 92 29 MEM_B_DQ<19> BV15 SB_DQ19 SB_DM4 BV47 MEM_B_DM<4> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<20> BK9 SA_DQ20 SA_DM5 BG53 MEM_A_DM<5> 29 92 92 29 MEM_B_DQ<20> BV12 SB_DQ20 SB_DM5 BV57 MEM_B_DM<5> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<21> BG15 SA_DQ21 SA_DM6 BN62 MEM_A_DM<6> 29 92 92 29 MEM_B_DQ<21> BP12 SB_DQ21 SB_DM6 BU65 MEM_B_DM<6> 29 92
BI OUT BI OUT
92 29 MEM_A_DQ<22> BH17 SA_DQ22 SA_DM7 BH59 MEM_A_DM<7> 29 92 92 29 MEM_B_DQ<22> BV17 SB_DQ22 SB_DM7 BF67 MEM_B_DM<7> 29 92
BI OUT BI OUT
MEM_A_DQ<23> BK17 SA_DQ23 MEM_B_DQ<23> BU16 SB_DQ23
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY B

92 29 BI 92 29 BI
92 29 MEM_A_DQ<24> BN20 SA_DQ24 SA_DQS0* AY5 MEM_A_DQS_N<0> 28 29 92 92 29 MEM_B_DQ<24> BP15 SB_DQ24 SB_DQS0* BE2 MEM_B_DQS_N<0> 29 30 92
BI BI BI BI
92 29 MEM_A_DQ<25> BN17 SA_DQ25 SA_DQS1* BJ7 MEM_A_DQS_N<1> 29 92 92 29 MEM_B_DQ<25> BU19 SB_DQ25 SB_DQS1* BM3 MEM_B_DQS_N<1> 29 92
BI BI BI BI
92 29 MEM_A_DQ<26> BK25 SA_DQ26 SA_DQS2* BN13 MEM_A_DQS_N<2> 29 92 92 29 MEM_B_DQ<26> BV22 SB_DQ26 SB_DQS2* BU12 MEM_B_DQS_N<2> 29 92
BI BI BI BI
92 29 MEM_A_DQ<27> BH25 SA_DQ27 SA_DQS3* BL21 MEM_A_DQS_N<3> 29 92 92 29 MEM_B_DQ<27> BT22 SB_DQ27 SB_DQS3* BT19 MEM_B_DQS_N<3> 29 92
BI BI BI BI
92 29 MEM_A_DQ<28> BJ20 SA_DQ28 SA_DQS4* BH44 MEM_A_DQS_N<4> 29 92 92 29 MEM_B_DQ<28> BP19 SB_DQ28 SB_DQS4* BT52 MEM_B_DQS_N<4> 29 92
BI BI BI BI
MEM_A_DQ<29> BH21 BK51 MEM_A_DQS_N<5> MEM_B_DQ<29> BV19 BV55 MEM_B_DQS_N<5>
C 92 29
92 29
BI
BI MEM_A_DQ<30> BG24
SA_DQ29
SA_DQ30
SA_DQS5*
SA_DQS6* BP58 MEM_A_DQS_N<6>
BI
BI
29 92
29 92
92 29
92 29
BI
BI MEM_B_DQ<30> BV20
SB_DQ29
SB_DQ30
SB_DQS5*
SB_DQS6* BU63 MEM_B_DQS_N<6>
BI
BI
29 92
29 92
C
92 29 MEM_A_DQ<31> BG25 SA_DQ31 SA_DQS7* BE62 MEM_A_DQS_N<7> 29 92 92 29 MEM_B_DQ<31> BT20 SB_DQ31 SB_DQS7* BG69 MEM_B_DQS_N<7> 29 92
BI BI BI BI
92 29 MEM_A_DQ<32> BJ40 SA_DQ32 92 29 MEM_B_DQ<32> BT48 SB_DQ32
BI BI
92 29 MEM_A_DQ<33> BM43 SA_DQ33 SA_DQS0 AY7 MEM_A_DQS_P<0> 28 29 92 92 29 MEM_B_DQ<33> BV48 SB_DQ33 SB_DQS0 BD4 MEM_B_DQS_P<0> 29 30 92
BI BI BI BI
92 29 MEM_A_DQ<34> BF47 SA_DQ34 SA_DQS1 BJ5 MEM_A_DQS_P<1> 29 92 92 29 MEM_B_DQ<34> BV50 SB_DQ34 SB_DQS1 BN4 MEM_B_DQS_P<1> 29 92
BI BI BI BI
92 29 MEM_A_DQ<35> BF48 SA_DQ35 SA_DQS2 BL13 MEM_A_DQS_P<2> 29 92 92 29 MEM_B_DQ<35> BP49 SB_DQ35 SB_DQS2 BV13 MEM_B_DQS_P<2> 29 92
BI BI BI BI
92 29 MEM_A_DQ<36> BN40 SA_DQ36 SA_DQS3 BN21 MEM_A_DQS_P<3> 29 92 92 29 MEM_B_DQ<36> BT47 SB_DQ36 SB_DQS3 BT17 MEM_B_DQS_P<3> 29 92
BI BI BI BI
92 29 28 MEM_A_DQ<37> BH43 SA_DQ37 SA_DQS4 BK44 MEM_A_DQS_P<4> 29 92 92 30 29 MEM_B_DQ<37> BV52 SB_DQ37 SB_DQS4 BT50 MEM_B_DQS_P<4> 29 92
BI BI BI BI
92 29 MEM_A_DQ<38> BN44 SA_DQ38 SA_DQS5 BH51 MEM_A_DQS_P<5> 29 92 92 29 MEM_B_DQ<38> BV54 SB_DQ38 SB_DQS5 BU56 MEM_B_DQS_P<5> 29 92
BI BI BI BI
92 29 MEM_A_DQ<39> BN47 SA_DQ39 SA_DQS6 BM60 MEM_A_DQS_P<6> 29 92 92 29 MEM_B_DQ<39> BT54 SB_DQ39 SB_DQS6 BV62 MEM_B_DQS_P<6> 29 92
BI BI BI BI
92 29 MEM_A_DQ<40> BN48 SA_DQ40 SA_DQS7 BE64 MEM_A_DQS_P<7> 29 92 92 29 MEM_B_DQ<40> BP53 SB_DQ40 SB_DQS7 BJ69 MEM_B_DQS_P<7> 29 92
BI BI BI BI
92 29 MEM_A_DQ<41> BN51 SA_DQ41 92 29 MEM_B_DQ<41> BU53 SB_DQ41
BI BI
92 29 MEM_A_DQ<42> BH53 SA_DQ42 SA_MA0 BT36 MEM_A_A<0> 28 92 92 29 MEM_B_DQ<42> BT59 SB_DQ42 SB_MA0 BT34 MEM_B_A<0> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<43> BJ55 SA_DQ43 SA_MA1 BP33 MEM_A_A<1> 28 92 92 29 MEM_B_DQ<43> BT57 SB_DQ43 SB_MA1 BP30 MEM_B_A<1> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<44> BH48 SA_DQ44 SA_MA2 BV36 MEM_A_A<2> 28 92 92 29 MEM_B_DQ<44> BP56 SB_DQ44 SB_MA2 BV29 MEM_B_A<2> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<45> BJ48 SA_DQ45 SA_MA3 BG34 MEM_A_A<3> 28 92 92 29 MEM_B_DQ<45> BT55 SB_DQ45 SB_MA3 BU30 MEM_B_A<3> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<46> BM53 SA_DQ46 SA_MA4 BG32 MEM_A_A<4> 28 92 92 29 MEM_B_DQ<46> BU60 SB_DQ46 SB_MA4 BV31 MEM_B_A<4> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<47> BN55 SA_DQ47 SA_MA5 BN32 MEM_A_A<5> 28 92 92 29 MEM_B_DQ<47> BV59 SB_DQ47 SB_MA5 BT33 MEM_B_A<5> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<48> BF55 SA_DQ48 SA_MA6 BK32 MEM_A_A<6> 28 92 92 29 MEM_B_DQ<48> BV61 SB_DQ48 SB_MA6 BT31 MEM_B_A<6> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<49> BN57 SA_DQ49 SA_MA7 BJ30 MEM_A_A<7> 28 92 92 29 MEM_B_DQ<49> BP60 SB_DQ49 SB_MA7 BP26 MEM_B_A<7> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<50> BN65 SA_DQ50 SA_MA8 BN30 MEM_A_A<8> 28 92 92 29 MEM_B_DQ<50> BR66 SB_DQ50 SB_MA8 BV27 MEM_B_A<8> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<51> BJ61 SA_DQ51 SA_MA9 BF28 MEM_A_A<9> 28 92 92 29 MEM_B_DQ<51> BR64 SB_DQ51 SB_MA9 BT27 MEM_B_A<9> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<52> BF57 SA_DQ52 SA_MA10 BH34 MEM_A_A<10> 28 92 92 29 MEM_B_DQ<52> BR62 SB_DQ52 SB_MA10 BU42 MEM_B_A<10> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<53> BJ57 SA_DQ53 SA_MA11 BH30 MEM_A_A<11> 28 92 92 29 MEM_B_DQ<53> BT61 SB_DQ53 SB_MA11 BU26 MEM_B_A<11> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<54> BK64 SA_DQ54 SA_MA12 BJ28 MEM_A_A<12> 28 92 92 29 MEM_B_DQ<54> BN68 SB_DQ54 SB_MA12 BT29 MEM_B_A<12> 30 92
BI OUT BI OUT
92 29 MEM_A_DQ<55> BK61 SA_DQ55 SA_MA13 BF40 MEM_A_A<13> 28 92 92 29 MEM_B_DQ<55> BL69 SB_DQ55 SB_MA13 BT45 MEM_B_A<13> 30 92
B 92 29
BI
BI MEM_A_DQ<56> BJ63
BF64
SA_DQ56 SA_MA14 BN28
BN25
MEM_A_A<14>
OUT
OUT 28 92 92 29
BI
BI MEM_B_DQ<56> BJ71
BF70
SB_DQ56 SB_MA14 BV26
BU23
MEM_B_A<14>
OUT
OUT 30 92 B
92 29 BI MEM_A_DQ<57> SA_DQ57 SA_MA15 MEM_A_A<15> OUT 28 92 92 29 BI MEM_B_DQ<57> SB_DQ57 SB_MA15 MEM_B_A<15> OUT 30 92
92 29 MEM_A_DQ<58> BB64 SA_DQ58 92 29 MEM_B_DQ<58> BG71 SB_DQ58

BI BI
92 29 MEM_A_DQ<59> BB66 SA_DQ59 92 29 MEM_B_DQ<59> BC67 SB_DQ59
BI BI
92 29 MEM_A_DQ<60> BJ66 SA_DQ60 92 29 MEM_B_DQ<60> BK70 SB_DQ60
BI BI
92 29 MEM_A_DQ<61> BF65 SA_DQ61 92 29 MEM_B_DQ<61> BK67 SB_DQ61
BI BI
92 29 MEM_A_DQ<62> AY64 SA_DQ62 92 29 MEM_B_DQ<62> BD71 SB_DQ62
BI BI
92 29 MEM_A_DQ<63> BC70 SA_DQ63 92 29 MEM_B_DQ<63> BD69 SB_DQ63
BI BI
92 28 MEM_A_BA<0> BT38 SA_BS0 92 30 MEM_B_BA<0> BV43 SB_BS0

OUT OUT
92 28 MEM_A_BA<1> BH38 SA_BS1 92 30 MEM_B_BA<1> BV41 SB_BS1
OUT OUT
92 28 MEM_A_BA<2> BF21 SA_BS2 92 30 MEM_B_BA<2> BV24 SB_BS2
OUT OUT
92 28 MEM_A_CAS_L BK43 SA_CAS* 92 30 MEM_B_CAS_L BU46 SB_CAS*

OUT OUT
92 28 MEM_A_RAS_L BL38 SA_RAS* 92 30 MEM_B_RAS_L BT40 SB_RAS*
OUT OUT
92 28 MEM_A_WE_L BF38 SA_WE* 92 30 MEM_B_WE_L BT41 SB_WE*
OUT OUT
A SYNC_MASTER=K17_REF SYNC_DATE=04/29/2009 A
PAGE TITLE
CPU DDR3 Interfaces

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

12 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1000 U1000
ARRANDALE ARRANDALE
BGA BGA
16 7 PPVCORE_S0_CPU_VCAP0 (SYM 8 OF 11) PPVCORE_S0_CPU 6 7 12 15 50 69
(SYM 6 OF 11)
BD55 VCAP0_1 VCC_1 AF57 PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 71 74 101
NOTE: VCAP0 is sourced by CPU BD51 AF55 CPU_PSI_L F68 BF60
VCAP0_2 VCC_2 91 69 15 OUT PSI* VTT0_1 Arrandale: 1.05V
Do not connect to power supply, BD48 AF53 BF59
VCAP0_3 VCC_3
CPU_VID<0> A61 VTT0_2 Clarksfield: 1.1V
but provide bypass caps on PCB. BB55 AF51 91 15 8 OUT VID0 BD60
VCAP0_4 VCC_4
CPU_VID<1> D61 VTT0_3 (Controlled by VTT_SELECT pin)
91 15 8 VID1
D
BB51 VCAP0_5 VCC_5 AF50 OUT
CPU_VID<2> D62 VTT0_4 BD59
D
CPU VIDS
BB48 AF48 91 15 8 OUT VID2 BB60
VCAP0_6 VCC_6 A62 VTT0_5
AY57 AF46 91 15 8 OUT CPU_VID<3> VID3 BB59
VCAP0_7 VCC_7 B63 VTT0_6
AY53 AF44 91 15 8 OUT CPU_VID<4> VID4 AY60
VCAP0_8 VCC_8 D64 VTT0_7
AY50 AF42 91 15 8 OUT CPU_VID<5> VID5 AW60
VCAP0_9 VCC_9 D66 VTT0_8
AW57 AF41 91 15 8 OUT CPU_VID<6> VID6 AW35
VCAP0_10 VCC_10 VTT0_9
AW53 VCAP0_11 VCC_11 AD55 91 8 TP_CPU_VTT_SELECT AN1 VTT_SELECT1 VTT0_10 AW33
OUT
AW50 VCAP0_12 VCC_12 AD51 VTT0_11 AW14
91 69 15 PM_DPRSLPVR F66 PROC_DPRSLPVR
AU55 AD48 OUT AW12
AU51 AD44 101 74 71 40 26 25 15 13 12 10 7 6 PPCPUVTT_S0 AU60
VCAP0_14 VCC_14
PPVCORE_S0_CPU VTT_SELECT: 1 = 1.05V, 0 = 1.1V VTT0_13
AU48 AD41 69 50 15 12 7 6
VCAP0_15 VCC_15 VTT0_14 AU59
AR55 VCAP0_16 VCC_16 AB55 VTT0_15 AU12
AR51 VCAP0_17 VCC_17 AB51 R13001 1
R1305 VTT0_16 AR60
AR48 AB48 100 10 AR59
VCAP0_18 VCC_18 1% 1% VTT0_17
AN57 AB44 1/16W 1/16W AR12
VCAP0_19 VCC_19 MF-LF MF-LF A41 VTT0_18
AN53 AB41 402 2 2 402 91 69 50 IN CPUIMVP_IMON ISENSE AN60
VCAP0_20 VCC_20 PLACE_NEAR=U1000.F64:25.4MM VTT0_19
SENSE LINES
AN50 VCAP0_21 POWER VCC_21 AA55 91 69 OUT
PLACE_NEAR=U1000.N13:25.4MM
CPU_VCCSENSE_P F64 VCC_SENSE VTT0_20 AN59
AL57 VCAP0_22 VCC_22 AA51 91 69 CPU_VCCSENSE_N F63 VSS_SENSE VTT0_21 AN35
OUT
AL53 VCAP0_23 VCC_23 AA48 VTT0_22 AN33
91 71 CPU_VTTSENSE_P N13 VTT_SENSE
AL50 AA44 OUT AN17
VCAP0_24 VCC_24 R12 VTT0_23
AK57 AA41 91 71 OUT CPU_VTTSENSE_N VSS_SENSE_VTT AN15
AK53 W55 PLACE_NEAR=U1000.F63:25.4MM PLACE_NEAR=U1000.R12:25.4MM AN14
AK50 VCAP0_27 VCC_27 W51 R13011 1
R1306 VTT0_26 AN12
W48 100 10 AM10
VCC_28 1% 1% VTT0_27
W44 1/16W 1/16W AL60
VCC_29 MF-LF MF-LF VTT0_28
W41 402 2 2 402 AL59
POWER
VCC_30 VTT0_29
U55 101 88 73 72 16 7 6 PP1V8_S0 AL17
CPU CORE SUPPLY VCC_31 W39 VTT0_30
C 16 7 PPVCORE_S0_CPU_VCAP1 VCC_32 U51
U48
W37
VCCPLL1
VCCPLL2
VTT0_31 AL15
AL14
C
1.8V
BD44 VCC_33 U37 VTT0_32
VCAP1_1 U44 VCCPLL3 AL12
NOTE: VCAP1 is sourced by CPU BD41 VCC_34 R39 VTT0_33
VCAP1_2 U41 VCCPLL4 AK35
Do not connect to power supply, BD37 VCC_35 R37 VTT0_34
VCAP1_3 R55 VCCPLL5 AK33
but provide bypass caps on PCB. BB44 VCC_36 VTT0_35
VCAP1_4 R51 AF39
BB41 VCC_37 VTT0_36
VCAP1_5 R48 AF37
BB37 VCC_38 16 PP1V5_S3_CPU_VCCDDR_CLK VTT0_37
1.1V RAIL POWER

VCAP1_6 R44 BB14 AF35
AY46 VCC_39 MIN_LINE_WIDTH=0.4mm VDDQ_CK1 VTT0_38
VCAP1_7 R41 MIN_NECK_WIDTH=0.2mm BB12 AF33
AY42 VCC_40 VOLTAGE=1.5V VDDQ_CK2 VTT0_39
VCAP1_8 P60 AF32
AY39 VCC_41 VTT0_40
VCAP1_9 N55 AF30
AW46 VCC_42 VTT0_41
VCAP1_10 N51 AD39
AW42 VCC_43 VTT0_42
VCAP1_11 N48 AD37
AW39 VCC_44 VTT0_43
VCAP1_12 N44 AD35
AU44 VCC_45 VTT0_44
VCAP1_13 N42 AD33
AU41 VCC_46 VTT0_45
VCAP1_14 M60 AD32
AU37 VCC_47 VTT0_46
VCAP1_15 M51 AD30
AR44 VCC_48 VTT0_47
VCAP1_16 M44 W35
AR41 VCC_49 VTT0_48
VCAP1_17 L55 W33
AR37 VCC_50 VTT0_49
VCAP1_18 K60 W32
AN46 VCC_51 VTT0_50
VCAP1_19 K51 W30
AN42 VCC_52 VTT0_51
VCAP1_20 K44 W28
AN39 VCC_53 VTT0_52
VCAP1_21 J55 W26
AL46 VCC_54 VTT0_53
VCAP1_22 H60 W24
AL42 VCC_55 VTT0_54
VCAP1_23 H51 W23
AL39 VCC_56 VTT0_55
VCAP1_24 H44 U35
AK46 VCC_57 VTT0_56
VCAP1_25 G60 U33
B AK42
AK39
VCAP1_26
VCC_58
VCC_59 G55
VTT0_57
VTT0_58 U32 B
VCAP1_27 G51 U30
VCC_60 VTT0_59
VCC_61 G44 VTT0_60 U28
VCC_62 F55 VTT0_61 U26
VCC_63 E60 VTT0_62 U24
VCC_64 E57 VTT0_63 U23
VCC_65 E53 VTT0_64 R35
VCC_66 E50 VTT0_65 R33
VCC_67 E46 VTT0_66 R32
VCC_68 E42 VTT0_67 R30
VCC_69 D59 VTT0_68 R28
VCC_70 D57 VTT0_69 R26
VCC_71 D55 VTT0_70 R24
VCC_72 D54 VTT0_71 R23
VCC_73 D52 VTT0_72 AY10
VCC_74 D50 VTT0_73 AN9
VCC_75 D48
VCC_76 D47
VCC_77 D45
VCC_78 D43
VCC_79 B60
VCC_80 B56
VCC_81 B53
VCC_82 B49
VCC_83 B46
A VCC_84
VCC_85
B42
A57 SYNC_MASTER=K17_WFERRY SYNC_DATE=06/09/2009 A
PAGE TITLE
A54
VCC_86
VCC_87 A50 CPU Power (1 of 2)
A47 DRAWING NUMBER SIZE
VCC_88
VCC_89 A43 Apple Inc. D
REVISION
R

13 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT 70 50 24 13 7 PPVCORE_S0_GFX
U1000 R14001
ARRANDALE 100
BGA 1%
(SYM 7 OF 11) 1/16W
MF-LF
402 2
D 70 50 24 13 7 PPVCORE_S0_GFX
AN32 VAXG_SENSE AF12 GFX_VSENSE_P PLACE_NEAR=U1000.AF12:25.4MM D
SENSE
LINES
VAXG1 OUT 70 91
AN30 VAXG2 VSSAXG_SENSE AF10 GFX_VSENSE_N 70 91
OUT
AN28 VAXG3 PLACE_NEAR=U1000.AF10:25.4MM
AN26
AN24
VAXG4 R14011
VAXG5 100
AN23 AF71 1%
VAXG6 GFX_VID0 GFX_VID<0> OUT 8 91 1/16W
AN21 AG67 MF-LF
VAXG7 GFX_VID1 GFX_VID<1> OUT 8 91 402 2
AN19 VAXG8 GFX_VID2 AG70 GFX_VID<2> 8 91
OUT
AL32 AH71
GRAPHICS VIDS
VAXG9 GFX_VID3 GFX_VID<3> OUT 8 91
AL30 VAXG10 GFX_VID4 AN71 GFX_VID<4> 8 91
OUT
AL28 VAXG11 GFX_VID5 AM67 GFX_VID<5> 8 91
OUT
AL26 VAXG12 GFX_VID6 AM70 GFX_VID<6> 8 91
OUT
AL24 VAXG13
AL23 GFX_VR_EN AH69 GFX_VR_EN OUT 70 91
VAXG14
AL21 VAXG15 GFX_DPRSLPVR AL71 GFX_DPRSLPVR 70 91
OUT 1
AL19 VAXG16 R1405
AK14 GFX_IMON AL69 GFXIMVP_IMON IN 70 91 4.7K
VAXG17 5%
AK12 1/16W
VAXG18 MF-LF
GRAPHICS
AJ10 402 2
VAXG19
AH14 PPCPUDDR_ISNS 7 16 31 57
VAXG20 BU40
AH12 VDDQ1
VAXG21 BU35
AF28 VDDQ2
VAXG22 BU28
AF26 VDDQ3
VAXG23 BN38
AF24 VDDQ4
VAXG24 BM25
AF23 VDDQ5
VAXG25 BL30
AF21 VDDQ6
VAXG26 BJ38
C AF19
AF17
VAXG27
VAXG28
VDDQ7
VDDQ8 BH32 C
VDDQ9 BH28
AF15 VAXG29
VDDQ10 BG43
AF14 VAXG30
VDDQ11 BF16
AD28 VAXG31
VDDQ12 BF15
AD26 VAXG32
VDDQ13 BD35
AD24 VAXG33
VDDQ14 BD33
AD23 VAXG34
VDDQ15 BD32
AD21 VAXG35
VDDQ16 BD30
AD19
DDR3 -1.5 V RAILS

VAXG36 BD28
AD17 VDDQ17
VAXG37 BD26
VDDQ18
VDDQ19 BD24
VDDQ20 BD23
101 74 71 40 26 25 15 13 12 10 7 6 PPCPUVTT_S0 BD21
W21 VDDQ21
VTT1_1 BD19
W19 VDDQ22
VTT1_2 BD17
U21 VDDQ23
VTT1_3 BD15
U19 VDDQ24
PEG & DMI

VTT1_4 BB35
U17 VDDQ25
VTT1_5 BB33
U15 VDDQ26
VTT1_6
POWER
VDDQ27 BB32
U14 VTT1_7
VDDQ28 BB30
U12 VTT1_8
VDDQ29 BB28
R21 VTT1_9
VDDQ30 BB26
R19 VTT1_10
VDDQ31 BB24
R17 VTT1_11
VDDQ32 BB23
VDDQ33 BB21
B 24 7 PPVCORE_S0_CPU_VCAP2 VDDQ34 BB19
BB17
B
AK62 VDDQ35
VCAP2_1 BB15
NOTE: VCAP2 is sourced by CPU AK60 VDDQ36
VCAP2_2
Do not connect to power supply, AK59 VCAP2_3
but provide bypass caps on PCB. AH60 VCAP2_4
AH59 PP1V1R1V05_S0_CPU_VTT0_DDR 15
VCAP2_5 AW32
AF60 VTT0_DDR
VCAP2_6 AW30
AF59 VTT0_DDR1
VCAP2_7 AW28
AD60 VTT0_DDR2
VCAP2_8 AW26
AD59 VTT0_DDR3
VCAP2_9 AW24
AB60 VTT0_DDR4
VCAP2_10 AW23
AB59 VTT0_DDR5
VCAP2_11 AW21
AA60 VTT0_DDR6
VCAP2_12 AW19
AA59 VTT0_DDR7
VCAP2_13 AW17
W60 VTT0_DDR8
VCAP2_14 AW15
W59 VTT0_DDR9
VCAP2_15 PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 71 74 101
U60 VCAP2_16 VTT1_12 AD15
U59 VCAP2_17 VTT1_13 AD14
R60 VCAP2_18 VTT1_14 AD12
R59 VCAP2_19 VTT1_15 AB12
VTT1_16 AA12
VTT1_17 W17
VTT1_18 W15
VTT1_19 W14
VTT1_20 W12
A VTT1_21 R15
PAGE TITLE
CPU Power (2 of 2)
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

14 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT OMIT
U1000 U1000 U1000

ARRANDALE ARRANDALE ARRANDALE
BGA BGA BGA
(SYM 9 OF 11) (SYM 10 OF 11) (SYM 11 OF 11)
BU62 VSS1 VSS76 AY62 AR19 VSS151 VSS226 BN71 AA28 VSS301 VSS367 K6
BU58 VSS2 VSS77 AY59 AR17 VSS152 VSS227 E68 AA26 VSS302 VSS368 K4
D BU55
BU51
VSS3 VSS78 AY55
AY51
AR15
AR14
VSS153 VSS228 AH28
AH41
AA24
AA23
VSS303 VSS369 J65
J57
D
VSS4 VSS79 VSS154 VSS229 VSS304 VSS370
BU48 VSS5 VSS80 AY48 AR4 VSS155 VSS230 A66 AA21 VSS305 VSS371 J48
BU44 VSS6 VSS81 AY44 AR1 VSS156 VSS231 AH26 AA19 VSS306 VSS372 J47
BU37 VSS7 VSS82 AY41 AP70 VSS157 VSS232 BN1 AA17 VSS307 VSS373 J40
BU32 VSS8 VSS83 AY37 AP64 VSS158 VSS233 A64 AA15 VSS308 VSS374 J9
BU25 VSS9 VSS84 AY35 AN62 VSS159 VSS234 AH24 AA14 VSS309 VSS375 H53
BU21 VSS10 VSS85 AY33 AN55 VSS160 VSS235 AH39 AA4 VSS310 VSS376 H43
BU18 VSS11 VSS86 AY32 AN51 VSS161 VSS236 E5 W69 VSS311 VSS377 H36
BU14 VSS12 VSS87 AY30 AN48 VSS162 VSS237 AH23 W62 VSS312 VSS378 H1
BU11 VSS13 VSS88 AY28 AN44 VSS163 VSS238 C68 W57 VSS313 VSS379 G70
BU7 VSS14 VSS89 AY26 AN41 VSS164 VSS239 AH21 W53 VSS314 VSS380 G57
BP42 VSS15 VSS90 AY24 AN37 VSS165 VSS240 AH19 W50 VSS315 VSS381 G53
BN64 VSS16 VSS91 AY23 AN5 VSS166 VSS241 AH17 W46 VSS316 VSS382 G48
BN6 VSS17 VSS92 AY21 AN4 VSS167 VSS242 AH15 W42 VSS317 VSS383 G47
BM70 VSS18 VSS93 AY19 AM64 VSS168 VSS243 AH4 W6 VSS318 VSS384 G43
BM51 VSS19 VSS94 AY17 AM8 VSS169 VSS244 AG64 W1 VSS319 VSS385 G30
BM44 VSS20 VSS95 AY15 AL62 VSS170 VSS245 AG9 V70 VSS320 VSS386 G24
BM32 VSS21 VSS96 AY14 AL55 VSS171 VSS246 AG6 U64 VSS321 VSS387 G20
BM24 VSS22 VSS97 AY12 AL51 VSS172 VSS247 AF69 U62 VSS322 VSS388 G15
BM17 VSS23 VSS98 AY8 AL48 VSS173 VSS248 AF62 U57 VSS323 VSS389 F61
BL57 VSS24 VSS99 AY4 AL44 VSS174 VSS249 AF1 U53 VSS324 VSS390 F48
BL55 VSS25 VSS100 AW67 AL41 VSS175 VSS250 AE70 U50 VSS325 VSS391 F47
BL48 VSS26 VSS101 AW62 AL37 VSS176 VSS251 AE64 U46 VSS326 VSS392 F28
BL40 VSS27 VSS102 AW59 AL35 VSS177 VSS252 AD62 U42 VSS327 VSS393 F20
BL28 VSS28 VSS103 AW55 AL33 VSS178 VSS253 AD57 U39 VSS328 VSS394 F4
BL20 AW51 AL1 AD53 U9 E37
C BK63
VSS29
VSS30
VSS104
VSS105 AW48 AK70
VSS179
VSS180
VSS254
VSS255 AD50 U4
VSS329
VSS330
VSS395
VSS396 E33 C
BK60 VSS31 VSS106 AW44 AK64 VSS181 VSS256 AD46 T1 VSS331 VSS397 E30
BK53 VSS32 VSS107 AW41 AK55 VSS182 VSS257 AD42 R70 VSS332 VSS398 E16
BK34 VSS33 VSS108 AW37 AK51 VSS183 VSS258 AD4 R62 VSS333 VSS399 E12
BK10 VSS34 VSS109 AV9 AK48 VSS184 VSS259 AC67 R57 VSS334 VSS400 D41
BJ64 VSS35 VSS110 AV1 AK44 VSS185 VSS260 AC64 R53 VSS335 VSS401 D38
BJ21 VSS36 VSS111 AU70 AK41 VSS186 VSS261 AC10 R50 VSS336 VSS402 D34
BH70 VSS39 VSS114 AU53 AK30 VSS189 VSS264 AB70 R5 VSS339 VSS405 D24
BH57 VSS40 VSS115 AU50 AK28 VSS190 VSS265 AB62 P4 VSS340 VSS406 D20
BH55 VSS41 VSS116 AU46 AK26 VSS191 VSS266 AB57 N63 VSS341 VSS407 D17
BH15 VSS45 VSS120 AU33 AK19 VSS195 VSS270 AB42 N46 VSS345 VSS411 B65
BG51 VSS46 VSS121 AU32 AK17 VSS196 VSS271 AB39 N30 VSS346 VSS412 B62
BG36 VSS47 VSS122 AU30 AK15 VSS197 VSS272 AB37 N21 VSS347 VSS413 B58
BF62 VSS48 VSS123 AU28 AJ70 VSS198 VSS273 AB35 N15 VSS348 VSS414 B55
BF30 VSS49 VSS124 AU26 AH62 VSS199 VSS274 AB33 M53 VSS349 VSS415 B51
BE70 VSS52 VSS127 AU21 AH53 VSS202 VSS277 AB28 M1 VSS352 VSS418 A59
BE65 VSS53 VSS128 AU19 BV66 VSS203 VSS278 AB26 L70 VSS353 VSS419 A55
BE9 VSS54 VSS129 AU17 AH51 VSS204 VSS279 AB24 L57 VSS354 VSS420 A52
BE1 VSS55 VSS130 AU15 BV64 VSS205 VSS280 AB23 L48 VSS355 VSS421 A48
B BD57
BD53
VSS56 VSS131 AU14
AU4
AH50
BT68
VSS206 VSS281 AB21
AB19
L47
L13
VSS356 VSS422 A45
A40
B
VSS57 VSS132 VSS207 VSS282 VSS357 VSS423
BD50 VSS58 VSS133 AT64 AH48 VSS208 VSS283 AB17 K64 VSS358 VSS424 A36
BD46 VSS59 VSS134 AT10 BR69 VSS209 VSS284 AB15 K53 VSS359 VSS425 A33
BD42 VSS60 VSS135 AR62 BL71 VSS210 VSS285 AB14 K43 VSS360 VSS426 A29
BD39 VSS61 VSS136 AR57 AH46 VSS211 VSS286 AB9 K36 VSS361 VSS427 A26
BD14 VSS62 VSS137 AR53 BL1 VSS212 VSS287 AA66 K34 VSS362 VSS428 A22
BB71 VSS63 VSS138 AR50 AH37 VSS213 VSS288 AA64 K32 VSS363 VSS429 A19
BB62 VSS64 VSS139 AR46 BR68 VSS214 VSS289 AA62 K25 VSS364 VSS430 A15
BB57 VSS65 VSS140 AR42 R14 VSS215 VSS290 AA57 K17 VSS365 VSS431 A12
BB53 VSS66 VSS141 AR39 AH35 VSS216 VSS291 AA53 K11 VSS366 VSS432 A8
BB50 VSS67 VSS142 AR35 AH44 VSS217 VSS292 AA50 VSS433 B40
BB46 VSS68 VSS143 AR33 H71 VSS218 VSS293 AA46
BB42 VSS69 VSS144 AR32 AH33 VSS219 VSS294 AA42
BB39 VSS70 VSS145 AR30 BR3 VSS220 VSS295 AA39
BB7 VSS71 VSS146 AR28 F71 VSS221 VSS296 AA37
BB1 VSS72 VSS147 AR26 AH32 VSS222 VSS297 AA35
BA70 VSS73 VSS148 AR24 AH42 VSS223 VSS298 AA33
AY71 VSS74 VSS149 AR23 E69 VSS224 VSS299 AA32
AY66 VSS75 VSS150 AR21 AH30 VSS225 VSS300 AA30
PAGE TITLE
CPU Grounds
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

15 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCore HF and Bulk Decoupling CPU Power On Configuration (POC) Straps
3x 470uF 4.5mOhm, 1x 330uF, 15x 22uF 0603, 25x 1uF 0402
Intel recommends all option straps should be provided in layout
PLACEMENT_NOTE (C1600-C1624):
69 50 12 7 6 PPVCORE_S0_CPU
Place on bottom side of U1000.. 101 74 71 40 26 25 15 13 12 10 7 6 PPCPUVTT_S0
CPUPOC4U NO STUFF NO STUFF

1 C1600 1 C1601 1 C1602 1 C1603 1 C1604 1 C1605 1 C1606 1 C1607 1 C1608 1 C1609 1 C1610 1 C1611 1 C1612
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10% 10%
1UF 1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
1UF
10%
R16001 R16021 R16041 R16061 R16081
1K 1K 1K 1K 1K
2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 5% 5% 5% 5% 5%
402 402 402 402 402 402 402 402 402 402 402 402 402 1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF
D 402 2 402 2 402 2 402 2 402 2

D
CPUPOC3U CPUPOC5U
1 1 1 1
R1601 R1603 R1605 R1607
1K 1K 1K 1K
1 C1613 1 C1614 1 C1615 1 C1616 1 C1617 1 C1618 1 C1619 1 C1620 1 C1621 1 C1622 1 C1623 1 C1624 5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF MF-LF MF-LF MF-LF MF-LF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 402 2 402 2 402 2 402
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
402 402 402 402 402 402 402 402 402 402 402 402 CPU_VID<0>
91 12 8 OUT
91 12 8 OUT CPU_VID<1>
PLACEMENT_NOTE (C1625-C1634): CPU_VID<3>
91 12 8 OUT
Place near U1000 on bottom side. 91 12 8 OUT CPU_VID<4>
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF CPU_VID<6>
1 C1626 1 C1627 1 C1628 1 C1629 1 C1630 1 C1631 1 C1632 1 C1633 1 C1634 1 C1691 1 C1694 1 C1698 91 12 8 OUT
PM_DPRSLPVR
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 91 69 12 OUT
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 91 69 12 CPU_PSI_L
OUT
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
603 603 603 603 603 603 603 603 603 603 603 603 NO STUFF NO STUFF CPUPOC4D
R16101 R16121 R16141 R16161 R16181
1K 1K 1K 1K 1K
5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W
PLACEMENT_NOTE (C1635-C1648): MF-LF MF-LF MF-LF MF-LF MF-LF
402 2 402 2 402 2 402 2 402 2
Place near inductors on bottom side.
NO STUFF CPUPOC3D CPUPOC5D NO STUFF
1 1 1 1
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF R1611 R1613 R1615 R1617
1 C1635 1 C1637 1 C1638 1 C1639 1 C1640 1 C1641 1 C1643 1 C1644 1 C1645 1 C1646 1 C1647 1 C1648 1 C1699 5%
1K
5%
1K 1K
5% 5%
1K
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 1/16W 1/16W 1/16W 1/16W
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% MF-LF MF-LF MF-LF MF-LF
2 6.3V
X5R-CERM
6.3V
2 X5R-CERM
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM
6.3V
2 X5R-CERM 2 402 2 402 2 402 2 402
603 603 603 603 603 603 603 603 603 603 603 603 603
C C
VID[2:0] = Reserved (111)
VID[5:3] = GPU Gain Setting (See below)
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF VID[6] = Reserved (0)
1 1 1 1 1 1 1 1 1
C1649 C1650 C1651 C1652 C16A0 C16A1 C16A2 C16A3 C16A4 DPRSLPVR = 1 - IMVP-6.5 compliant controller
330UF 470UF-4MOHM 470UF-4MOHM 470UF-4MOHM 62UF 62UF 62UF 62UF 62UF PSI# = Reserved (0)
20% 20% 20% 20% 20% 20% 20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V 3 2 2.0V 2 11V 2 11V 2 11V 2 11V 2 11V
POLY-TANT POLY-TANT POLY-TANT POLY-TANT ELEC ELEC ELEC ELEC ELEC TABLE_BOMGROUP_HEAD
D2T-SM2 D2T-SM D2T-SM D2T-SM CASE-B2 CASE-B2 CASE-B2 CASE-B2 CASE-B2 BOM GROUP IMAX @ 900mV CPU Gain Setting BOM OPTIONS Equivalent Gain
TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_DIS 000 CPUPOC3D,CPUPOC4D,CPUPOC5D

TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_0_20 20A 001 CPUPOC3D,CPUPOC4D,CPUPOC5U 45
VTT (CPU Uncore) DECOUPLING CPUPOC_IMAX_20_30

CPUPOC_IMAX_30_40
30A
40A
010
011
CPUPOC3D,CPUPOC4U,CPUPOC5D
CPUPOC3D,CPUPOC4U,CPUPOC5U
30
22.5
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
3x 330uF 6 mOhm, 4x 22uF 0805, 7x 10uF 0603, 24x 1uF 0402 TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_40_50 50A 100 CPUPOC3U,CPUPOC4D,CPUPOC5D 18

PLACEMENT_NOTE (C1653-C1656): TABLE_BOMGROUP_ITEM
15 13 12 10 7 6 PPCPUVTT_S0 CPUPOC_IMAX_50_60 60A 101 CPUPOC3U,CPUPOC4D,CPUPOC5U 15

101 74 71 40 26 25 Place on bottom side of U1000. TABLE_BOMGROUP_ITEM
CPUPOC_IMAX_60_70 70A 110 CPUPOC3U,CPUPOC4U,CPUPOC5D 12.857

TABLE_BOMGROUP_ITEM
1 C1653 1 C1654 1 C1655 1 C1656 CPUPOC_IMAX_70_90 90A 111 CPUPOC3U,CPUPOC4U,CPUPOC5U 10

22UF 22UF 22UF 22UF
20% 20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM NOTE: BOM Configurations should not call out CPUPOCnU/D BOMOPTIONs directly.
603 603 603 603
Instead call out appropriate BOM GROUP defined in tables above.
B Place on bottom side of U1000.. B
1 C1657 1 C1658 1 C1659 1 C1660 1 C1661 1 C1662 1 C1663
10UF 10UF 10UF 10UF 10UF 10UF 10UF
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
20%
2 6.3V
X5R
603
20%
6.3V
2 X5R
603
20%
6.3V
2 X5R
603
20%
6.3V
2 X5R
603
20%
6.3V
2 X5R
603
VTT0_DDR DECOUPLING
3x 1uF 0402
PLACEMENT_NOTE (C1664-C1687): L1695
30-OHM-5A Place on bottom side of U1000. PP1V1R1V05_S0_CPU_VTT0_DDR 13
Place on bottom side of U1000. 1 2 MIN_LINE_WIDTH=0.4 mm
0603
VOLTAGE=1.1V
1 C1664 1 C1665 1 C1666 1 C1667 1 C1668 1 C1669 1 C1670 1 C1671 1 C1672 1 C1673 1 C1674 1 C1675 1 C1695 1 C1696 1 C1697
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 10V
X5R
10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 2 10V
X5R 2 10V
X5R
10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
1 C1676 1 C1677 1 C1678 1 C1679 1 C1680 1 C1681 1 C1682 1 C1683 1 C1684 1 C1685 1 C1686 1 C1687
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
402 402 402 402 402 402 402 402 402 402 402 402
PAGE TITLE
CPU Non-GFX Decoupling (1 of 2)

DRAWING NUMBER SIZE
1
C1688 1
C1689 1
C1690 Apple Inc. D
330UF 330UF 330UF REVISION
20% 20% 20% R
3 2 2.0V 3 2 2.0V 3 2 2.0V
POLY-TANT POLY-TANT POLY-TANT
D2T-SM2 D2T-SM2 D2T-SM2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
16 OF 132
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form Factor Schematic Check List Rev 1.1 (doc #395914) table 3.26.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VCAP0 (CPU BSC Package) DECOUPLING
12x 1uF 0402
12 7 PPVCORE_S0_CPU_VCAP0 Place on bottom side of U1000.
1 C1700 1 C1701 1 C1702 1 C1703 1 C1704 1 C1705 1 C1706 1 C1707 1 C1708 1 C1709 1 C1710 1 C1711
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
402 402 402 402 402 402 402 402 402 402 402 402
D D

12x 1uF 0402
12 7 PPVCORE_S0_CPU_VCAP1 Place on bottom side of U1000.
1 C1712 1 C1713 1 C1714 1 C1715 1 C1716 1 C1717 1 C1718 1 C1719 1 C1720 1 C1721 1 C1722 1 C1723
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402 402 402 402 402 402 402 402 402
Memory (CPU VCCDDR) DECOUPLING

5x 1uF 0402
57 31 16 13 7 PPCPUDDR_ISNS
C 1 C1724
1UF
1 C1725
1UF
1 C1726
1UF
1 C1727
1UF
1 C1728
1UF
C
10% 10% 10% 10% 10%
10V
2 X5R 2 10V 2 10V 2 10V 2 10V
X5R X5R X5R X5R
402 402 402 402 402
NOTE: 19x 1uF 0402 caps per Apple SI for CMD and CNTRL lines.
1 C1735 1 C1736 1 C1737 1 C1738 1 C1739 1 C1740 1 C1741 1 C1742 1 C1743 1 C1744 1 C1745 1 C1746 1 C1747 1 C1748 1 C1749 1 C1750 1 C1751 1 C1752 1 C1753
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
10V
2 X5R 2 10V
X5R
10V
2 X5R 10V
2 X5R 2 10V
X5R
10V
2 X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
10V
2 X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402
NOTE: 3x 330uF 6 mOhm caps to be shared between CPU and SO-DIMMs. 2x330uF on CSA73. DG recommends 2x 22uF at SO_DIMM not provided. Decoupling caps at SO-DIMMs on CSA 29 and CSA 31.
1
C1729
330UF
20%
3 2 2.0V
POLY-TANT
D2T-SM2
B B
PLL (CPU VCCSFR) DECOUPLING
1x 22uF 0805, 1x 4.7uF 0603
88 73 72 12 7 6 PP1V8_S0
101
1 C1732 1 C1733
22uF 4.7UF
20% 10%
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM
805 603
DDR Clock (CPU VDDQ_CK) DECOUPLING

1x 1uF 0402
L1734
57 31 16 13 7 PPCPUDDR_ISNS 30-OHM-5A PP1V5_S3_CPU_VCCDDR_CLK 12
1 2
0603
1 C1734
A 1UF
10%
2 10V
X5R PAGE TITLE
402
CPU Non-GFX Decoupling (2 of 2)
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
17 OF 132
actor Schematic Check List Rev 1.1 (doc #395914) table 3.26. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
101 24 23 21 18 17 PP1V05_S0_PCH
101 24 23 21 20 19 18 17 PP3V3_S0_PCH 101 24 23 21 18 17 PP1V05_S0_PCH
1
R1820 R18301 R18901
10K 37.4 90.9
5% 1% 1%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
2 402 402 2 402 2
27 IN PCH_CLK32K_RTCX1 B13 RTCX1 OMIT FWH0/LAD0 D33 LPC_AD<0> BI 6 46 48 88 94 94 37 IN PCIE_ENET_D2R_N BG30 PERN1 OMIT SMBALERT*/GPIO11 B9 SMC_WAKE_SCI_L IN 17 46
(IPU)
27 OUT PCH_CLK32K_RTCX2 D13 RTCX2
U1800 FWH1/LAD1 B33 LPC_AD<1> BI 6 46 48 88 94 94 37 IN PCIE_ENET_D2R_P BJ30 PERP1 U1800 SMBCLK H14 SMBUS_PCH_CLK 64 94
6 25 26 28 30
D IBEX_PEAK_M
FCBGA
FWH2/LAD2
FWH3/LAD3
C32
A32
LPC_AD<2>
LPC_AD<3>
BI
BI
6 46 48 88 94
6 46 48 88 94
94 37
94 37
OUT
OUT
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
BF29
BH29
PETN1
PETP1
IBEX_PEAK_M
FCBGA
SMBDATA C8 SMBUS_PCH_DATA
OUT
BI
32 34 42 48 49
6 25 26 28 30 94
32 34 42 48 49 64
D
17 RTC_RESET_L C14 RTCRST* (1 OF 10) (2 OF 10)
FWH4/LFRAME* C34 LPC_FRAME_L OUT 6 46 48 88 94 94 33 6 IN PCIE_AP_D2R_N AW30 PERN2 SML0ALERT*/GPIO60 J14 PCH_SML0ALERT_L 17
17 PCH_SRTCRST_L D17 SRTCRST* 94 33 6 IN PCIE_AP_D2R_P BA30 PERP2

(IPU) LDRQ0* A34 TP_LPC_DREQ0_L C6 SML_PCH_0_CLK
RTC
LPC
SML0CLK OUT 49 94
PCIE_AP_R2D_C_N BC30 PETN2
SMBUS
94 33 OUT
17 PCH_INTRUDER_L A16 INTRUDER* LDRQ1*/GPIO23 F34 TP_LPC_DREQ1_L SML0DATA G8 SML_PCH_0_DATA BI 49 94
94 33 OUT PCIE_AP_R2D_C_P BD30 PETP2
17 PCH_INTVRMEN_L A14 INTVRMEN SERIRQ AB9 LPC_SERIRQ BI 6 46 48
94 39 IN PCIE_FW_D2R_N AU30 PERN3 SML1ALERT*/GPIO74 M14 PCH_SML1ALERT_L 17
94 39 IN PCIE_FW_D2R_P AT30 PERP3

AK7 HDD SML1CLK/GPIO58 E10 SML_PCH_1_CLK OUT 49 94
94 17 HDA_BIT_CLK_R A30 HDA_BCLK (IPD) SATA0RXN SATA_HDD_D2R_N IN 42 93 94 39 OUT PCIE_FW_R2D_C_N AU32 PETN3
SML1DATA/GPIO75 G12 SML_PCH_1_DATA BI 49 94
SATA0RXP AK6 SATA_HDD_D2R_P IN 42 93 94 39 OUT PCIE_FW_R2D_C_P AV32 PETP3
HDA_SYNC_R D29 HDA_SYNC (IPD) SATA0TXN AK11 SATA_HDD_R2D_C_N
C-LINK
94 17 OUT 42 93
94 34 6 IN PCIE_EXCARD_D2R_N BA32 PERN4
SATA0TXP AK9 SATA_HDD_R2D_C_P OUT 42 93 (IPU) CL_CLK1 T13 TP_CLINK_CLK
94 34 6 IN PCIE_EXCARD_D2R_P BB32 PERP4
17 PCH_SPKR P1 SPKR (IPD) ODD
SATA1RXN AH6 SATA_ODD_D2R_N IN 42 93 94 34 OUT PCIE_EXCARD_R2D_C_N BD32 PETN4 (IPU) CL_DATA1 T11 TP_CLINK_DATA
AH5 SATA_ODD_D2R_P PCIE_EXCARD_R2D_C_P BE32
IHDA
SATA1RXP IN 42 93 94 34 OUT PETP4
94 17 HDA_RST_R_L C30 HDA_RST* (IPD) CL_RST1* T9 TP_CLINK_RESET_L
SATA1TXN AH9 SATA_ODD_R2D_C_N OUT 42 93
6 NC_PCIE_PE5_D2RN BF33 PERN5
SATA1TXP AH8 SATA_ODD_R2D_C_P OUT 42 93
94 59 IN HDA_SDIN0 G30 HDA_SDIN0 (IPD) 6 NC_PCIE_PE5_D2RP BH33 PERP5
AF11 Unused PEG_A_CLKRQ*/GPIO47 H1 PEG_CLKREQ_L
some IbexPeak SKUs

IN 8 17 88
6 NC_HDA_SDIN1 F30 HDA_SDIN1 (IPD) SATA2RXN NC_SATA_C_D2RN 6 6 NC_PCIE_PE5_R2D_CN BG32 PETN5
Not available on
6 NC_HDA_SDIN2 E32 HDA_SDIN2 (IPD) SATA2RXP AF9 NC_SATA_C_D2RP 6 6 NC_PCIE_PE5_R2D_CP BJ32 PETP5
CLKOUT_PEG_A_N AD43 PEG_CLK100M_N
PEG
OUT 75 94
6 NC_HDA_SDIN3 F32 HDA_SDIN3 (IPD) SATA2TXN AF7 NC_SATA_C_R2D_CN 6
6 NC_PCIE_PE6_D2RN BA34 PERN6 CLKOUT_PEG_A_P AD45 PEG_CLK100M_P OUT 75 94
SATA2TXP AF6 NC_SATA_C_R2D_CP 6
6 NC_PCIE_PE6_D2RP AW34 PERP6
94 17 HDA_SDOUT_R B29 HDA_SDO (IPD) Unused NC_SATA_D_D2RN
SATA3RXN AH3 6 6 NC_PCIE_PE6_R2D_CN BC34 PETN6
CLKOUT_DMI_N AN4 PCIE_CLK100M_CPU_N OUT 10 91
(IPU/NO) SATA3RXP AH1 NC_SATA_D_D2RP 6 6 NC_PCIE_PE6_R2D_CP BD34 PETP6
46 17 IN SPI_DESCRIPTOR_OVERRIDE_L H32 HDA_DOCK_EN*/GPIO33 CLKOUT_DMI_P AN2 PCIE_CLK100M_CPU_P OUT 10 91
SATA3TXN AF3 NC_SATA_D_R2D_CN 6
SATA
37 17 IN ENET_ENERGY_DET J30 HDA_DOCK_RST*/GPIO13 6 NC_PCIE_PE7_D2RN AT34 PERN7
SATA3TXP AF1 NC_SATA_D_R2D_CP 6
6 NC_PCIE_PE7_D2RP AU34 PERP7
SSD CLKOUT_DP_N/CLKOUT_BCLK1_N AT1 GFX_CLK120M_DPLLSS_N
C C
PCI-E*
OUT 10 93
SATA4RXN AD9 NC_SATA_SSD2_D2RN NC_PCIE_PE7_R2D_CN AU36 PETN7
support FIS-based
IN 6 6
JTAG_PCH_TCK M3 JTAG_TCK (IPU) CLKOUT_DP_P/CLKOUT_BCLK1_P AT3 GFX_CLK120M_DPLLSS_P
Only ports 4 & 5
port multipliers
25 17 IN OUT 10 93
SATA4RXP AD8 NC_SATA_SSD2_D2RP IN 6 6 NC_PCIE_PE7_R2D_CP AV36 PETP7
25 17 IN JTAG_PCH_TMS K3 JTAG_TMS (IPU)
JTAG SATA4TXN AD6 NC_SATA_SSD2_R2D_CN OUT 6
6 NC_PCIE_PE8_D2RN BG34 PERN8
SATA4TXP AD5 NC_SATA_SSD2_R2D_CP OUT 6 CLKIN_DMI_N AW24 PCIE_CLK100M_PCH_N IN 26 93
25 17 IN JTAG_PCH_TDI K1 JTAG_TDI (IPU) 6 NC_PCIE_PE8_D2RP BJ34 PERP8
eSATA CLKIN_DMI_P BA24 PCIE_CLK100M_PCH_P IN 26 93
SATA5RXN AD3 TP_SATA_EXTA_D2R_N IN 8 93 6 NC_PCIE_PE8_R2D_CN BG36 PETN8
25 17 OUT JTAG_PCH_TDO J2 JTAG_TDO
SATA5RXP AD1 TP_SATA_EXTA_D2R_P IN 8 93 6 NC_PCIE_PE8_R2D_CP BJ36 PETP8
TP_JTAG_PCH_TRST_L J4 JTAG_RST* (IPU) SATA5TXN AB3 TP_SATA_EXTA_R2D_C_N OUT 8 93 CLKIN_BCLK_N AP3 FSB_CLK133M_PCH_N IN 26 93
SATA5TXP AB1 TP_SATA_EXTA_R2D_C_P OUT PCIE_CLK100M_ENET_N AK48 CLKOUT_PCIE0N CLKIN_BCLK_P AP1 FSB_CLK133M_PCH_P
FROM CLK BUFFER

8 93 94 37 OUT IN 26 93
94 37 OUT PCIE_CLK100M_ENET_P AK47 CLKOUT_PCIE0P

94 48 OUT SPI_CLK_R BA2 SPI_CLK
SATAICOMPO AF16 PCH_SATAICOMP
37 17 IN ENET_CLKREQ_L P9 PCIECLKRQ0*/GPIO73 CLKIN_DOT_96N F18 PCH_CLK96M_DOT_N IN 26 93
94 48 OUT SPI_CS0_R_L AV3 SPI_CS0* SATAICOMPI AF15
CLKIN_DOT_96P E18 PCH_CLK96M_DOT_P
SPI
IN 26 93
94 33 OUT PCIE_CLK100M_AP_N AM43 CLKOUT_PCIE1N
TP_SPI_CS1_L AY3 SPI_CS1*
(IPU) SATALED* T3 TP_PCH_SATALED_L 94 33 OUT PCIE_CLK100M_AP_P AM45 CLKOUT_PCIE1P
94 48 OUT SPI_MOSI_R AY1 SPI_MOSI (IPD) CLKIN_SATA_N/CKSSCD_N AH13 PCH_CLK100M_SATA_N IN 26 93
SATA0GP/GPIO21 Y9 SATARDRVR_A_EN OUT 17 25 42 33 25 17 IN AP_CLKREQ_L U4 PCIECLKRQ1*/GPIO18
CLKIN_SATA_P/CKSSCD_P AH12 PCH_CLK100M_SATA_P IN 26 93
94 48 IN SPI_MISO AV1 SPI_MISO (IPU) SATA1GP/GPIO19 V1 SATARDRVR_B_EN OUT 17 25
94 39 OUT PCIE_CLK100M_FW_N AM47 CLKOUT_PCIE2N
94 39 OUT PCIE_CLK100M_FW_P AM48 CLKOUT_PCIE2P
REFCLK14IN P41 PCH_CLK14P3M_REFCLK IN 26 93
40 25 17 IN FW_CLKREQ_L N4 PCIECLKRQ2*/GPIO20
94 34 OUT PCIE_CLK100M_EXCARD_N AH42 CLKOUT_PCIE3N CLKIN_PCILOOPBACK J42 PCH_CLK33M_PCIIN IN 27 93
94 34 OUT PCIE_CLK100M_EXCARD_P AH41 CLKOUT_PCIE3P

74 66 65 54
45 43 23 21 7 6 PP3V42_G3H 72 7 PP1V05_S5
51 50 49 48 47 46 34 17 IN EXCARD_CLKREQ_L A8 PCIECLKRQ3*/GPIO25 XTAL25_IN AH51 PCH_CLK25M_XTALIN IN 27
XTAL25_OUT AH53 PCH_CLK25M_XTALOUT OUT 27

XDP_PCH XDP_PCH XDP_PCH 6 NC_PCIE_CLK100M_PE4N AM51 CLKOUT_PCIE4N
R18021 1
R1803 R18251 R18261 1
R1827 6 NC_PCIE_CLK100M_PE4P AM53 CLKOUT_PCIE4P
20K 20K 51 51 51 XCLK_RCOMP AF38 PCH_XCLK_RCOMP
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
17 PCH_PE4_CLKREQ_L M9 PCIECLKRQ4*/GPIO26
B
402 2 2 402 402 2 402 2 2 402 6 NC_PCIE_CLK100M_PE5N AJ50 CLKOUT_PCIE5N
CLKOUTFLEX0/GPIO64 T45 BRCRYPT_RESET 17 103
6 NC_PCIE_CLK100M_PE5P AJ52 CLKOUT_PCIE5P (IPD)
JTAG_PCH_TMS Default: 0V
CLOCK
17 25
FLEX
R18001 1
R1801 JTAG_PCH_TDI 17 25 103 17 OUT BRCRYPT_PWR_EN H6 PCIECLKRQ5*/GPIO44 CLKOUTFLEX1/GPIO65 P43 ARB_DETECT 17
(IPD)
330K 1M JTAG_PCH_TDO 17 25 Default: 24.576 MHz (unsupported)
5% 5% TP_PCIE_CLK100M_PEBN AK53 CLKOUT_PEG_B_N
1/16W 1/16W JTAG_PCH_TCK 17 25 CLKOUTFLEX2/GPIO66 T42 MLB_RAM_SIZE 17
MF-LF MF-LF RTC_RESET_L 17 TP_PCIE_CLK100M_PEBP AK51 CLKOUT_PEG_B_P (IPD)
402 2 2 402 PCH_SRTCRST_L Default: 14.31818 MHz
17
R18281 17 PCH_PEB_CLKREQ_L P13 PEG_B_CLKRQ*/GPIO56 CLKOUTFLEX3/GPIO67 N50 MLB_RAM_VENDOR 17
PCH_INTRUDER_L 17 (IPD)
51 PP3V3_S5_PCH 18 19 20 21 23 101 Default: 48 MHz
PCH_INTVRMEN_L 17 5%
1/16W PP3V3_S3 6 7 20 31 32 33 34 35 36 49 50 51 54 55
MF-LF
PP3V3_S0_PCH
56 72 74 88 102 103 All 4 CLKOUTFLEX outputs support
402 2
C1802 1 1 C1803 17 18 19 20 21 23 24 101
33.333 MHz and 14.31818 MHz,
1UF 1UF CLKOUTFLEX3 also supports 48 MHz.
10%
10V
10%
10V
R1899 2.2K 1 2 PCH_SPKR 17
X5R 2 2 X5R 5% 1/16W MF-LF 402
402 402 R1815 10K 1 2 SPI_DESCRIPTOR_OVERRIDE_L 17 46
5% 1/16W MF-LF 402
R1816 10K 1 2 ENET_ENERGY_DET 17 37
5% 1/16W MF-LF 402
R1840 10K 1 2 SATARDRVR_A_EN 17 25 42
R1841 10K 5% 1/16W MF-LF 402

1 2 SATARDRVR_B_EN 17 25
5% 1/16W MF-LF 402
R1850 10K 1 2 ENET_CLKREQ_L 17 37
R1810 R1851 10K 1 2 5% 1/16W MF-LF 402
AP_CLKREQ_L 17 25 33
33 R1852 10K 5% 1/16W MF-LF 402
94 17 HDA_BIT_CLK_R 1 2 HDA_BIT_CLK OUT 59 94 1 2 FW_CLKREQ_L 17 25 40
R1853 10K 5% 1/16W MF-LF 402
5% 1 2 EXCARD_CLKREQ_L 17 34
1/16W 5% 1/16W MF-LF 402
MF-LF
402 R1811 R1854 10K 1 2 PCH_PE4_CLKREQ_L 17
R1855 10K 5% 1/16W MF-LF 402

33 1 2 PCH_PEB_CLKREQ_L 17
HDA_SYNC_R 1 2 HDA_SYNC
A 94 17
5%
1/16W
OUT 59 94
R1860 100K 1 2
5%
5%
1/16W MF-LF
1/16W MF-LF 402

402
BRCRYPT_PWR_EN 17 103 SYNC_MASTER=K17_REF SYNC_DATE=08/24/2009 A
PAGE TITLE
R1812 MF-LF
R1870 10K SMC_WAKE_SCI_L
94 17 HDA_RST_R_L 1
33 2
402
HDA_RST_L OUT 59 94 R1871 10K
1
1
2
2
5% 1/16W MF-LF 402
PCH_SML0ALERT_L
17 46
17
PCH SATA/PCIE/CLK/LPC/SPI
R1872 10K 5% 1/16W MF-LF 402 DRAWING NUMBER SIZE
5% 1 2 PCH_SML1ALERT_L
1/16W 5% 1/16W MF-LF 402
17
Apple Inc. D
MF-LF
402 R1813 R1880 10K 1 2 PEG_CLKREQ_L 8 17 88 REVISION
33 5% 1/16W MF-LF 402 R
HDA_SDOUT_R 1 2 HDA_SDOUT
94 17 OUT 59 94
R1895 10K 1 2 BRCRYPT_RESET 17 103
5%
1/16W R1896 10K 1 2
5% 1/16W MF-LF 402
ARB_DETECT NOTICE OF PROPRIETARY PROPERTY: BRANCH
17
MF-LF 5% 1/16W MF-LF 402
402 R1897 10K 1 2 MLB_RAM_SIZE 17
R1898 10K 5% 1/16W MF-LF 402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1 2 MLB_RAM_VENDOR
5% 1/16W MF-LF 402
17
18 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_S5_PCH 17 18 19 20 21 23 101
PP1V05_S0_PCH 17 21 23 24 101
R19051 1
R1900
10K 49.9
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402
91 9 IN DMI_N2S_N<0> BC24 DMI0RXN OMIT FDI_RXN0 BA18 FDI_DATA_N<0> IN 9 91 88 8 OUT LVDS_IG_BKL_ON T48 L_BKLTEN OMIT SDVO_TVCLKINN BJ46 NC_SDVO_TVCLKINN 6
91 9 IN DMI_N2S_N<1> BJ22 DMI1RXN U1800 FDI_RXN1 BH17 FDI_DATA_N<1> IN 9 91 88 8 OUT LVDS_IG_PANEL_PWR T47 L_VDD_EN U1800 SDVO_TVCLKINP BG46 NC_SDVO_TVCLKINP 6
D 91 9
91 9
IN
IN
DMI_N2S_N<2>
DMI_N2S_N<3>
AW20
BJ20
DMI2RXN
DMI3RXN
IBEX_PEAK_M
FCBGA
FDI_RXN2
FDI_RXN3
BD16
BJ16
FDI_DATA_N<2>
FDI_DATA_N<3>
IN
IN
9 91
9 91
8 6 OUT TP_LVDS_IG_BKL_PWM Y48 L_BKLTCTL IBEX_PEAK_M
FCBGA
SDVO_STALLN BJ48 NC_SDVO_STALLN 6 D
SDVO_STALLP BG48 NC_SDVO_STALLP 6
(3 OF 10) FDI_RXN4 BA16 FDI_DATA_N<4> IN 9 91 85 OUT LVDS_IG_DDC_CLK AB48 L_DDC_CLK (4 OF 10)
91 9 IN DMI_N2S_P<0> BD24 DMI0RXP
FDI_RXN5 BE14 FDI_DATA_N<5> IN 9 91 85 BI LVDS_IG_DDC_DATA Y45 L_DDC_DATA SDVO_INTN BF45 NC_SDVO_INTN 6
91 9 IN DMI_N2S_P<1> BG22 DMI1RXP
FDI_RXN6 BA14 FDI_DATA_N<6> IN 9 91 SDVO_INTP BH45 NC_SDVO_INTP 6
91 9 IN DMI_N2S_P<2> BA20 DMI2RXP 6 NC_LVDS_IG_CTRL_CLK AB46 L_CTRL_CLK
FDI_RXN7 BC12 FDI_DATA_N<7> IN 9 91
91 9 IN DMI_N2S_P<3> BG20 DMI3RXP 6 NC_LVDS_IG_CTRL_DATA V48 L_CTRL_DATA (IPD)
(IPD) SDVO_CTRLCLK T51 DP_IG_DDC_CLK OUT 8 81 85
FDI_RXP0 BB18 FDI_DATA_P<0> IN 9 91
(IPD) SDVO_CTRLDATA T53 DP_IG_DDC_DATA BI 8 81 85
91 9 OUT DMI_S2N_N<0> BE22 DMI0TXN FDI_RXP1 BF17 FDI_DATA_P<1> IN 9 91 PCH_LVDS_IBG AP39 LVD_IBG
91 9 OUT DMI_S2N_N<1> BF21 DMI1TXN FDI_RXP2 BC16 FDI_DATA_P<2> IN 9 91 6 NC_PCH_LVDS_VBG AP41 LVD_VBG DDPB_AUXN BG44 DP_IG_AUX_CH_N BI 8 85 93
91 9 OUT DMI_S2N_N<2> BD20 DMI2TXN FDI_RXP3 BG16 FDI_DATA_P<3> IN 9 91

1
R1950 DDPB_AUXP BJ44 DP_IG_AUX_CH_P BI 8 85 93
91 9 OUT DMI_S2N_N<3> BE18 DMI3TXN FDI_RXP4 AW16 FDI_DATA_P<4> IN 9 91 2.37K AT43 LVD_VREFH DDPB_HPD AU38 DP_IG_HPD IN 8 85
DMI
FDI
1%
FDI_RXP5 BD14 FDI_DATA_P<5> IN 9 91 1/16W AT42 LVD_VREFL
91 9 OUT DMI_S2N_P<0> BD22 DMI0TXP MF-LF DDPB_0N BD42 DP_IG_B_ML_N<0> OUT 8
FDI_RXP6 BB14 FDI_DATA_P<6> IN 9 91
2 402
91 9 OUT DMI_S2N_P<1> BH21 DMI1TXP DDPB_0P BC42 DP_IG_B_ML_P<0> OUT 8
FDI_RXP7 BD12 FDI_DATA_P<7> IN 9 91 93 88 OUT LVDS_IG_A_CLK_N AV53 LVDSA_CLK*
91 9 OUT DMI_S2N_P<2> BC20 DMI2TXP DDPB_1N BJ42 DP_IG_B_ML_N<1> OUT 8
93 88 OUT LVDS_IG_A_CLK_P AV51 LVDSA_CLK
91 9 OUT DMI_S2N_P<3> BD18 DMI3TXP DDPB_1P BG42 DP_IG_B_ML_P<1> OUT 8
FDI_INT BJ14 FDI_INT OUT 9 91
LVDS_IG_A_DATA_N<0> DP_IG_B_ML_N<2>
DIGITAL DISPLAY INTERFACE

93 88 OUT BB47 LVDSA_DATA0* DDPB_2N BB40 OUT 8
FDI_FSYNC0 BF13 FDI_FSYNC<0> OUT 9 91 93 88 OUT LVDS_IG_A_DATA_N<1> BA52 LVDSA_DATA1* DDPB_2P BA40 DP_IG_B_ML_P<2> OUT 8
LVDS
FDI_FSYNC1 BH13 FDI_FSYNC<1> OUT 9 91 93 88 OUT LVDS_IG_A_DATA_N<2> AY48 LVDSA_DATA2* DDPB_3N AW38 DP_IG_B_ML_N<3> OUT 8
93 8 OUT NC_LVDS_IG_A_DATAN<3> AV47 LVDSA_DATA3* DDPB_3P BA38 DP_IG_B_ML_P<3> OUT 8

PCH_DMI_COMP BH25 DMI_ZCOMP FDI_LSYNC0 BJ12 FDI_LSYNC<0> OUT 9 91
BF25 DMI_IRCOMP FDI_LSYNC1 BG14 FDI_LSYNC<1> OUT 9 91 93 88 OUT LVDS_IG_A_DATA_P<0> BB48 LVDSA_DATA0 (IPU)
DDPC_CTRLCLK Y49 NC_DP_IG_C_CTRL_CLK 6
93 88 OUT LVDS_IG_A_DATA_P<1> BA50 LVDSA_DATA1
DDPC_CTRLDATA AB49 NC_DP_IG_C_CTRL_DATA 6
LVDS_IG_A_DATA_P<2> AY49 LVDSA_DATA2 (IPD)
SYSTEM POWER
93 88 OUT
46 27 6 IN PM_SYSRST_L T6 SYS_RESET* WAKE* J12 PCIE_WAKE_L IN 6 18 27 33 34
NC_LVDS_IG_A_DATAP<3> AV48 BE44 NC_DP_IG_C_AUXN
MANAGEMENT
93 8 OUT LVDSA_DATA3 DDPC_AUXN 6
27 IN PM_PCH_PWRGD M6 SYS_PWROK CLKRUN*/GPIO32 Y1 PM_CLKRUN_L BI 6 18 46 48 DDPC_AUXP BD44 NC_DP_IG_C_AUXP 6
93 8 6 OUT TP_LVDS_IG_B_CLKN AP48 LVDSB_CLK* DDPC_HPD AV40 NC_DP_IG_C_HPD 6

B17 PWROK LPC_PWRDWN_L OUT 6 18 46 48
TP_LVDS_IG_B_CLKP
C K5 MEPWROK SUS_STAT*/GPIO61 P8
MAKE_BASE=TRUE
LPC_PWRDWN_L 6 18 46 48
93 8 6
93 88
OUT
LVDS_IG_B_DATA_N<0>
AP47
AY53
LVDSB_CLK
LVDSB_DATA0*
DDPC_0N
DDPC_0P
BE40
BD40
NC_DP_IG_C_MLN<0>
NC_DP_IG_C_MLP<0>
6
6
C
OUT
PCH_LAN_RST_L A10 LAN_RST* SUSCLK/GPIO62 F3 PM_CLK32K_SUSCLK OUT 47 94 93 88 OUT LVDS_IG_B_DATA_N<1> AT49 LVDSB_DATA1* DDPC_1N BF41 NC_DP_IG_C_MLN<1> 6
93 88 OUT LVDS_IG_B_DATA_N<2> AU52 LVDSB_DATA2* DDPC_1P BH41 NC_DP_IG_C_MLP<1> 6

91 31 10 OUT PM_MEM_PWRGD D9 DRAMPWROK SLP_S5*/GPIO63 E4 PM_SLP_S5_L OUT 46 47
93 8 OUT NC_LVDS_IG_B_DATAN<3> AT53 LVDSB_DATA3* DDPC_2N BD38 NC_DP_IG_C_MLN<2> 6
46 18 IN PM_RSMRST_L C16 RSMRST* SLP_S4* H7 PM_SLP_S4_L OUT 31 43 46 47 73 74 DDPC_2P BC38 NC_DP_IG_C_MLP<2> 6

93 88 OUT LVDS_IG_B_DATA_P<0> AY51 LVDSB_DATA0
DDPC_3N BB36 NC_DP_IG_C_MLN<3> 6
18 OUT PM_SUS_PWR_ACK M1 SUS_PWR_ACK/GPIO30 SLP_S3* P12 PM_SLP_S3_L OUT 6 31 46 74 86 93 88 OUT LVDS_IG_B_DATA_P<1> AT48 LVDSB_DATA1
DDPC_3P BA36 NC_DP_IG_C_MLP<3> 6
93 88 OUT LVDS_IG_B_DATA_P<2> AU50 LVDSB_DATA2
46 25 IN PM_PWRBTN_L P5 PWRBTN* (IPU) SLP_M* K8 TP_PM_SLP_M_L
93 8 OUT NC_LVDS_IG_B_DATAP<3> AT51 LVDSB_DATA3 (IPU)
DDPD_CTRLCLK U50 NC_DP_IG_D_CTRL_CLK 6
74 47 46 IN SMC_ADAPTER_EN P7 ACPRESENT/GPIO31 TP23 N2 TP_PM_SLP_DSW_L
DDPD_CTRLDATA U52 NC_DP_IG_D_CTRL_DATA 6
(IPD)
46 18 IN PM_BATLOW_L A6 BATLOW*/GPIO72 PMSYNCH BJ10 PM_SYNC BI 10 91 6 NC_CRT_IG_BLUE AA52 CRT_BLUE
DDPD_AUXN BC46 NC_DP_IG_D_AUXN 6
6 NC_CRT_IG_GREEN AB53 CRT_GREEN
PCH_RI_L F14 RI* SLP_LAN* F6 TP_SLP_LAN_L DDPD_AUXP BD46 NC_DP_IG_D_AUXP 6
6 NC_CRT_IG_RED AD53 CRT_RED
DDPD_HPD AT38 NC_DP_IG_D_HPD 6
1
R1906 NC_CRT_IG_DDC_CLK NC_DP_IG_D_MLN<0>
CRT
6 V51 CRT_DDC_CLK DDPD_0N BJ40 6
10K
5% 6 NC_CRT_IG_DDC_DATA V53 CRT_DDC_DATA DDPD_0P BG40 NC_DP_IG_D_MLP<0> 6
1/16W
MF-LF DDPD_1N BJ38 NC_DP_IG_D_MLN<1> 6
2 402 6 NC_CRT_IG_HSYNC Y53 CRT_HSYNC DDPD_1P BG38 NC_DP_IG_D_MLP<1> 6
6 NC_CRT_IG_VSYNC Y51 CRT_VSYNC DDPD_2N BF37 NC_DP_IG_D_MLN<2> 6
101 24 23 21 20 19 17 PP3V3_S0_PCH DDPD_2P BH37 NC_DP_IG_D_MLP<2> 6
PCH_DAC_IREF AD48 DAC_IREF DDPD_3N BE36 NC_DP_IG_D_MLN<3> 6
AB51 CRT_IRTN DDPD_3P BD36 NC_DP_IG_D_MLP<3> 6
R19201 1
R1921 1
R1951
10K 10K 1K
5% 5% 5%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
B 402 2 2 402 2 402
0.5% recommended, Intel okay
B
PM_SUS_PWR_ACK 18
PM_CLKRUN_L with 5% when CRTDAC not used.

6 18 46 48
PM_RSMRST_L 18 46
1
R1925
10K
5%
1/16W
MF-LF
402 2
101 23 21 20 19 18 17 PP3V3_S5_PCH
R19301 1
R1931
10K 10K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402
PM_BATLOW_L 18 46
PCIE_WAKE_L 6 18 27 33 34
PAGE TITLE
PCH DMI/FDI/Graphics
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

19 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
6 NC_PCI_AD<0> H40 AD0 OMIT NV_CE0* AY9 NC_NV_CE_L<0> 6
6 NC_PCI_AD<1> N34 AD1 U1800 NV_CE1* BD1 NC_NV_CE_L<1> 6
D 6
6
NC_PCI_AD<2>
NC_PCI_AD<3>
C44
A38
AD2
AD3
IBEX_PEAK_M
FCBGA
NV_CE2*
NV_CE3*
AP15
BD8
NC_NV_CE_L<2>
NC_NV_CE_L<3>
6
6
D
6 NC_PCI_AD<4> C36 AD4 (5 OF 10)
NV_DQS0 AV9 NC_NV_DQS<0> 6
6 NC_PCI_AD<5> J34 AD5
NV_DQS1 BG8 NC_NV_DQS<1> 6
6 NC_PCI_AD<6> A40 AD6
6 NC_PCI_AD<7> D45 AD7 NV_DQ0/NV_IO0 AP7 NC_NV_DQ<0> 6
6 NC_PCI_AD<8> E36 AD8 NV_DQ1/NV_IO1 AP6 NC_NV_DQ<1> 6
6 NC_PCI_AD<9> H48 AD9 NV_DQ2/NV_IO2 AT6 NC_NV_DQ<2> 6
6 NC_PCI_AD<10> E40 AD10 NV_DQ3/NV_IO3 AT9 NC_NV_DQ<3> 6
6 NC_PCI_AD<11> C40 AD11 NV_DQ4/NV_IO4 BB1 NC_NV_DQ<4> 6
NVRAM
6 NC_PCI_AD<12> M48 AD12 NV_DQ5/NV_IO5 AV6 NC_NV_DQ<5> 6
6 NC_PCI_AD<13> M45 AD13 NV_DQ6/NV_IO6 BB3 NC_NV_DQ<6> 6
6 NC_PCI_AD<14> F53 AD14 NV_DQ7/NV_IO7 BA4 NC_NV_DQ<7> 6
6 NC_PCI_AD<15> M40 AD15 NV_DQ8/NV_IO8 BE4 NC_NV_DQ<8> 6
6 NC_PCI_AD<16> M43 AD16 NV_DQ9/NV_IO9 BB6 NC_NV_DQ<9> 6
6 NC_PCI_AD<17> J36 AD17 NV_DQ10/NV_IO10 BD6 NC_NV_DQ<10> 6
6 NC_PCI_AD<18> K48 AD18 NV_DQ11/NV_IO11 BB7 NC_NV_DQ<11> 6
6 NC_PCI_AD<19> F40 AD19 NV_DQ12/NV_IO12 BC8 NC_NV_DQ<12> 6
6 NC_PCI_AD<20> C42 AD20 NV_DQ13/NV_IO13 BJ8 NC_NV_DQ<13> 6
6 NC_PCI_AD<21> K46 AD21 NV_DQ14/NV_IO14 BJ6 NC_NV_DQ<14> 6
6 NC_PCI_AD<22> M51 AD22 NV_DQ15/NV_IO15 BG6 NC_NV_DQ<15> 6

(IPD) NV_ALE BD3 NC_NV_ALE 6
6 NC_PCI_AD<24> K51 AD24
(IPD) NV_CLE AY6 NC_NV_CLE 6
6 NC_PCI_AD<25> L34 AD25
6 NC_PCI_AD<26> F42 AD26 NV_RCOMP AU2 TP_PCH_NV_RCOMP
(IPU) NV_RB* AV7 NC_NV_RB_L 6
6 NC_PCI_AD<28> G46 AD28
C 6
6
NC_PCI_AD<29>
NC_PCI_AD<30>
F44
M47
AD29
AD30
NV_WR0_RE*
NV_WR1_RE*
AY8
AY5
NC_NV_WR_RE_L<0>
NC_NV_WR_RE_L<1>
6
6
C
6 NC_PCI_AD<31> H36 AD31
NV_WE_CK0* AV11 NC_NV_WE_CK_L<0> 6
6 NC_PCI_C_BE_L<0> J50 C/BE0* NV_WE_CK1* BF5 NC_NV_WE_CK_L<1> 6
6 NC_PCI_C_BE_L<1> G42 C/BE1*

6 NC_PCI_C_BE_L<2> H47 C/BE2*
USBP0N H18 USB_HUB1_UP_N BI 35 93
101 24 23 21 20 18 17 PP3V3_S0_PCH 6 NC_PCI_C_BE_L<3> G34 C/BE3* External Hub 1
USB_HUB1_UP_P
NOTE: Internal pull-downs on all USB pins

USBP0P J18 BI 35 93
R2010
(DPD)
10K 1 2 PCI_INTA_L G38 PIRQA* USBP1N A18 NC_USB_1N
5% 1/16W MF-LF 402
R2011 10K 1 2 PCI_INTB_L H51 PIRQB* USBP1P C18 NC_USB_1P
R2012 10K 5% 1/16W MF-LF 402
1 2 PCI_INTC_L USB_BRCRYPT_N
PCI
B37 PIRQC* USBP2N N20 BI 93 103
R2013 10K 1 2
5% 1/16W MF-LF 402
PCI_INTD_L USB_BRCRYPT_P T57
A44 PIRQD* USBP2P P20 BI 93 103
5% 1/16W MF-LF 402
USBP3N J20 NC_USB_3N
R2014 10K 1 2 PCI_REQ0_L
EHCI1
F51 REQ0*
5% 1/16W MF-LF 402 USBP3P L20 NC_USB_3P
88 19 OUT JTAG_GMUX_TMS A46 REQ1*/GPIO50
USBP4N F20 NC_USB_4N
88 19 OUT JTAG_GMUX_TDI B45 REQ2*/GPIO52
USBP4P G20 NC_USB_4P
19 PCI_REQ3_L M53 REQ3*/GPIO54
USBP5N A20 NC_USB_5N
6 NC_PCI_GNT0_L F48 GNT0* (IPU) USBP5P C20 NC_USB_5P
6 NC_PCI_GNT1_L K45 GNT1*/GPIO51 USBP6N M22 NC_USB_6N 6
6 NC_PCI_GNT2_L F36 GNT2*/GPIO53 USBP6P N22 NC_USB_6P 6
6 NC_PCI_GNT3_L H53 GNT3*/GPIO55 USBP7N B21 NC_USB_7N 6
USBP7P D21 NC_USB_7P 6

19 PCH_GPIO2 B41 PIRQE*/GPIO2
USBP8N H22 USB_HUB2_UP_N BI 36 93
64 19 IN AUD_IP_PERIPHERAL_DET K53 PIRQF*/GPIO3 External Hub 2
USBP8P J22 USB_HUB2_UP_P BI 36 93
MIKEY_MIC_LOAD_DET A36 PIRQG*/GPIO4
(DPD)
19 IN
USBP9N E22 NC_USB_9N
64 19 AUD_I2C_INT_L A48 PIRQH*/GPIO5
USB
IN NC_USB_9P
USBP9P F22
PP3V3_S5_PCH 17 18 19 20 21 23 101
B 6 NC_PCI_RESET_L K6 PCIRST* USBP10N A22 NC_USB_10N

B
EHCI2
USBP10P C22 NC_USB_10P
R2020 10K 1 2 PCI_SERR_L E44 SERR*
G24 NC_USB_11N
R2021 10K 5% 1/16W MF-LF 402 USBP11N
1 2 PCI_PERR_L E50 PERR* 1
R2061 1
R2064 1
R2066
5% 1/16W MF-LF 402 USBP11P H24 NC_USB_11P
R2022 10K 10K 10K 10K
1 2 PCI_IRDY_L A42 IRDY* USBP12N L24 NC_USB_12N 5% 5% 5%
5% 1/16W MF-LF 402 1/16W 1/16W 1/16W
6 NC_PCI_PAR H44 PAR USBP12P M24 NC_USB_12P MF-LF MF-LF MF-LF
R2023 10K 1 2 PCI_DEVSEL_L F46 DEVSEL* USBP13N A24 NC_USB_13N 2 402 2 402 2 402
R2024 10K 5% 1/16W MF-LF 402
1 2 PCI_FRAME_L C46 FRAME* USBP13P C24 NC_USB_13P
5% 1/16W MF-LF 402
R2025 10K 1 2 PCI_PLOCK_L D49 PLOCK* R20601 R20621 R20651
5% 1/16W MF-LF 402 USBRBIAS* B25 93 PCH_USB_RBIAS 10K 10K 10K
R2026 10K 1 2 PCI_STOP_L D41 STOP* USBRBIAS D25
5%
1/16W
5%
1/16W
5%
1/16W
R2027 10K 5% 1/16W MF-LF 402 MF-LF MF-LF MF-LF
1 2 PCI_TRDY_L C48 TRDY* 402 2 402 2 402 2
5% 1/16W MF-LF 402
6 NC_PCI_PME_L M7 PME* (IPU) OC0*/GPIO59 N16 PCH_GPIO59 IN 19 25
OC1*/GPIO40 J16 USB_HUB_SOFT_RESET_L 25 35

40 31 27 OUT PLT_RESET_L D5 PLTRST*
OC2*/GPIO41 F16 PCH_GPIO41 25
94 27 OUT LPC_CLK33M_SMC_R N52 CLKOUT_PCI0 OC3*/GPIO42 L16 PCH_GPIO42 25
27 OUT LPC_CLK33M_LPCPLUS_R P53 CLKOUT_PCI1 OC4*/GPIO43 E14 PCH_GPIO43 25
27 LPC_CLK33M_GMUX_R P46 CLKOUT_PCI2 OC5*/GPIO9 G16 PCH_GPIO9 25
6 NC_PCI_CLK33M_OUT3 P51 CLKOUT_PCI3 OC6*/GPIO10 F12 PCH_GPIO10 25
27 OUT PCH_CLK33M_PCIOUT P48 CLKOUT_PCI4 OC7*/GPIO14 T15 PM_LATRIGGER_L IN 19 25
R20701
22.6
1%
1/16W
MF-LF
R2030 10K 1 2 JTAG_GMUX_TMS 19 88
402 2
A R2031
R2032
10K
10K
1
1
2
2
5%
5%
1/16W MF-LF 402
1/16W MF-LF 402
JTAG_GMUX_TDI
PCI_REQ3_L
19 88
19
SYNC_MASTER=K18_MLB SYNC_DATE=10/07/2009 A
5% 1/16W MF-LF 402 PAGE TITLE
R2035 10K 1 2
5% 1/16W MF-LF 402
PCH_GPIO2 19 PCH PCI/FlashCache/USB
R2036 10K 1 2 AUD_IP_PERIPHERAL_DET 19 64 DRAWING NUMBER SIZE
5% 1/16W MF-LF 402
R2037 10K 1 2 MIKEY_MIC_LOAD_DET 19 D
R2038 10K 1 2 5% 1/16W MF-LF 402
AUD_I2C_INT_L 19 64
Apple Inc. REVISION
5% 1/16W MF-LF 402 R
101 23 21 20 19 18 17 PP3V3_S5_PCH NOTICE OF PROPRIETARY PROPERTY: BRANCH

R2080 10K 1 2 PCH_GPIO59 19 25 THE INFORMATION CONTAINED HEREIN IS THE
R2081 10K 5% 1/16W MF-LF 402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
1 2 PM_LATRIGGER_L 19 25 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/16W MF-LF 402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
20 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IPU* = Only on TACH function. PP3V3_S0_PCH 17 18 19 20 21 23 24 101
47 46 25 20 IN SMC_IG_THROTTLE_L Y3 BMBUSY*/GPIO0 OMIT CLKOUT_PCIE6N AH45 NC_PCIE_CLK100M_PE6N 6
U1800 CLKOUT_PCIE6P AH46 NC_PCIE_CLK100M_PE6P 6

40 20 8 FW_PLUG_DET_L C38 TACH1/GPIO1 (IPU*) R21501 1
R2155
D 88 20
IN
IN GMUX_INT D37 TACH2/GPIO6 (IPU*)

IBEX_PEAK_M
FCBGA CLKOUT_PCIE7N AF48 NC_PCIE_CLK100M_PE7N 6
10K
5%
10K
5%
D
1/16W 1/16W
(6 OF 10) CLKOUT_PCIE7P AF47 NC_PCIE_CLK100M_PE7P 6 MF-LF MF-LF
46 20 IN SMC_RUNTIME_SCI_L J32 TACH3/GPIO7 (IPU*) 402 2 2 402
20 PCH_FCIM_EN_L F10 GPIO8 (IPU) MISC A20GATE U2 PCH_A20GATE

37 20 OUT ENET_LOW_PWR K9 LAN_PHY_PWR_CTRL/GPIO12
CLKOUT_BCLK0_N/CLKOUT_PCIE8N AM3 FSB_CLK133M_CPU_N OUT 10 91
20 PCH_GPIO15 T7 GPIO15 (IPD)
CLKOUT_BCLK0_P/CLKOUT_PCIE8P AM1 FSB_CLK133M_CPU_P OUT 10 91
64 25 20 OUT AUD_IPHS_SWITCH_EN AA2 SATA4GP/GPIO16

PPVTT_S0_PCH 21 23 101
PECI BG10 CPU_PECI BI 10 91
48 20 6 BI LPCPLUS_GPIO F38 TACH0/GPIO17 (IPU*)
CPU
1
42 20 OUT ODD_PWR_EN_L Y7 SCLOCK/GPIO22 RCIN* T1 PCH_RCIN_L R2160
56
5%
20 PCH_GPIO24 H10 MEM_LED/GPIO24 1/16W
PROCPWRGD BE10 CPU_PWRGD OUT 10 25 91 MF-LF
20 PCH_VRM_EN AB12 GPIO27 R2161 2 402
56
THRMTRIP* BD10 PCH_THRMTRIP_L 1 2 PM_THRMTRIP_L IN 10 47 91
31 25 OUT ISOLATE_CPU_MEM_L V13 GPIO28 (IPU)
5%
GPIO
1/16W
TP_PCH_STP_PCI_L M11 STP_PCI*/GPIO34 MF-LF
TP1 BA22 NC_PCH_TP1 6 402
20 OUT MXM_GOOD V6 SATACLKREQ*/GPIO35
TP2 AW22 NC_PCH_TP2 6
25 20 OUT SDCARD_RESET AB7 SATA2GP/GPIO36
88 25 20 OUT JTAG_GMUX_TCK AB13 SATA3GP/GPIO37 TP3 BB22 NC_PCH_TP3 6
88 20 IN JTAG_GMUX_TDO V3 SLOAD/GPIO38
TP4 AY45 NC_PCH_TP4 6 (DPL_B_MON1_N)
20 PCH_GPIO39 P3 SDATAOUT0/GPIO39
TP5 AY46 NC_PCH_TP5 6 (DPL_B_MON1_P)
WOL_EN
C 74 20
74 33 20
OUT
AP_PWR_EN
H3
F1
PCIECLKRQ6*/GPIO45
PCIECLKRQ7*/GPIO46 TP6 AV43 NC_PCH_TP6 6 (DPL_B_MON2_N)

C
OUT
40 20 OUT FW_PWR_EN AB6 SDATAOUT1/GPIO48

TP7 AV45 NC_PCH_TP7 6 (DPL_B_MON2_P)
25 20 OUT ME_TEMP_ALERT_L AA4 SATA5GP/GPIO49
TP8 AF13 NC_PCH_TP8 6 (SATA_OB_ANA)
58 48 20 6 BI SPIROM_USE_MLB F8 GPIO57
TP9 M18 NC_PCH_TP9 6
94 6 PCH_VSS_NCTF<1> A4 VSS_NCTF1
94 6 PCH_VSS_NCTF<2> A49 VSS_NCTF2 TP10 N18 NC_PCH_TP10 6
A5 VSS_NCTF3
A50 VSS_NCTF4 TP11 AJ24 NC_PCH_TP11 6
94 6 PCH_VSS_NCTF<5> A52 VSS_NCTF5
RSVD
A53 VSS_NCTF6 TP12 AK41 NC_PCH_TP12 6 (XCKPLL_MON1_N)
94 TP_PCH_VSS_NCTF<7> B2 VSS_NCTF7
B4 VSS_NCTF8 TP13 AK42 NC_PCH_TP13 6 (XCKPLL_MON1_P)
94 6 PCH_VSS_NCTF<9> B52 VSS_NCTF9
B53 VSS_NCTF10 TP14 M32 NC_PCH_TP14 6
94 6 PCH_VSS_NCTF<11> BE1 VSS_NCTF11

94 6 PCH_VSS_NCTF<12> BE53 VSS_NCTF12 TP15 N32 NC_PCH_TP15 6
BF1 VSS_NCTF13
BF53 VSS_NCTF14 TP16 M30 NC_PCH_TP16 6
NCTF
94 6 PCH_VSS_NCTF<15> BH1 VSS_NCTF15
BH2 VSS_NCTF16 TP17 N30 NC_PCH_TP17 6
94 6 PCH_VSS_NCTF<17> BH52 VSS_NCTF17

BH53 VSS_NCTF18 TP18 H12 NC_PCH_TP18 6
B 94 6 PCH_VSS_NCTF<19> BJ1
BJ2
VSS_NCTF19
VSS_NCTF20 TP19 AA23 NC_PCH_TP19 6
B
94 6 PCH_VSS_NCTF<21> BJ4 VSS_NCTF21
94 PCH_VSS_NCTF<22> BJ49 VSS_NCTF22
NC_1 AB45 NC_PCH_NC1 6
PP3V3_S5_PCH 17 18 19 21 23 101 BJ5 VSS_NCTF23
PP3V3_S3 6 7 17 31 32 33 34 35 36 49 50 51 54 55 BJ50 VSS_NCTF24
56 72 74 88 102 103 NC_3 AB42 NC_PCH_NC3 6
PP3V3_S0_PCH 17 18 19 20 21 23 24 101 94 6 PCH_VSS_NCTF<25> BJ52 VSS_NCTF25
BJ53 VSS_NCTF26
NC_5 T39 NC_PCH_NC5
R2110 10K 1 2 SMC_IG_THROTTLE_L 20 25 46 47 94 6 PCH_VSS_NCTF<27> D1 VSS_NCTF27
6
5% 1/16W MF-LF 402

R2111 10K 1 2 FW_PLUG_DET_L 8 20 40 D2 VSS_NCTF28
5% 1/16W MF-LF 402
R2112 20K 94 6 PCH_VSS_NCTF<29> D53 VSS_NCTF29 (IPD) INIT3_3V* P6 TP_PCH_INIT3V3_L
1 2 GMUX_INT 20 88
5% 1/16W MF-LF 402 E1 VSS_NCTF30
R2113 10K 1 2 SMC_RUNTIME_SCI_L 20 46 E53 VSS_NCTF31 TP24 C10 NC_PCH_SST 6
5% 1/16W MF-LF 402
R2114 10K 1 2 PCH_FCIM_EN_L 20
R2115 2.2K 1 2
5% 1/16W MF-LF 402
ENET_LOW_PWR 20 37
5% 1/16W MF-LF 402
R2116 10K 1 2 PCH_GPIO15 20
5% 1/16W MF-LF 402
R2120 10K 1 2 AUD_IPHS_SWITCH_EN 20 25 64
R2121 10K 5% 1/16W MF-LF 402
1 2 LPCPLUS_GPIO 6 20 48
5% 1/16W MF-LF 402
R2122 10K 1 2 ODD_PWR_EN_L 20 42
5% 1/16W MF-LF 402
R2123 10K 1 2 PCH_GPIO24 20
5% 1/16W MF-LF 402
R2124 10K 1 2 PCH_VRM_EN 20
5% 1/16W MF-LF 402
R2130 10K 1 2 MXM_GOOD 20
R2131 10K 5% 1/16W MF-LF 402

1 2 SDCARD_RESET
A R2132 10K 1 2
5%
5%
1/16W MF-LF 402
1/16W MF-LF 402
JTAG_GMUX_TCK
20 25
20 25 88 SYNC_MASTER=K18_MLB SYNC_DATE=11/13/2009 A
PAGE TITLE
R2133 10K JTAG_GMUX_TDO
R2134 10K
1
1
2
2 5% 1/16W MF-LF 402
PCH_GPIO39
20 88
20
PCH MISC
5% 1/16W MF-LF 402 DRAWING NUMBER SIZE
R2135 10K 1 2 WOL_EN 20 74 D
5% 1/16W MF-LF 402 Apple Inc.
R2136 10K 1 2 AP_PWR_EN 20 33 74 R
REVISION
5% 1/16W MF-LF 402
R2137 10K 1 2 FW_PWR_EN 20 40 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R2138 10K 5% 1/16W MF-LF 402
1 2 ME_TEMP_ALERT_L 20 25 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/16W MF-LF 402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
R2139 100K 1 2 SPIROM_USE_MLB THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% 1/16W MF-LF 402
6 20 48 58
21 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1800 U1800
IBEX_PEAK_M IBEX_PEAK_M
FCBGA FCBGA
23 PP1V05_S0_PCH_VCCA_CLK (10 OF 10) PP1V05_S0_PCH 17 18 21 23 24 101 101 24 23 21 18 17 PP1V05_S0_PCH (7 OF 10) PP3V3_S0_PCH_VCCA_DAC 24
D 52 mA AP51 VCCACLK1 VCCIO5 V24 3062 mA (VCCIO[1-56] total) 1432 mA AB24 VCCCORE1 VCCADAC1 AE50 69 mA D
AP53 VCCACLK2 VCCIO6 V26 AB26 VCCCORE2 VCCADAC2 AE52
USB
CRT
VCCIO7 Y24 AB28 VCCCORE3
GND VSSA_DAC1 AF53
VCCIO8 Y26 AD26 VCCCORE4
320 mA S0, 67 mA M-on AF23 VCCLAN1 VSSA_DAC2 AF51
VCC CORE
AD28 VCCCORE5
AF24 VCCLAN2 PP3V3_S5_PCH 17 18 19 20 21 23 101
AF26 VCCCORE6
VCCSUS3_3_1 V28 163 mA S0, 65 mA S3-S5
PCH output, for decoupling only AF28 VCCCORE7
PPVOUT_S5_PCH_DCPSUSBYP VCCSUS3_3_2 U28 (VCCSUS3_3[1-32] total)
Y20 DCPSUSBYP AF30 VCCCORE8
CLOCK AND MISCELLANEOUS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V VCCSUS3_3_3 U26
AF31 VCCCORE9
PP1V05_S0_PCH VCCSUS3_3_4 U24
1 C2200 24 23 21 18 17
101
1849 mA S0, 700 mA M-on AD38 VCCME1 VCCSUS3_3_5 P28
AH26 VCCCORE10
0.1UF AH28 VCCCORE11 PP3V3_S0_PCH_VCCALVDS 101
20% (VCCME[1-16] total) AD39 VCCME2 VCCSUS3_3_6 P26
10V
LVDS
2 CERM AH30 VCCCORE12 VCCALVDS AH38 < 1 mA
402 AD41 VCCME3 VCCSUS3_3_7 N28
AH31 VCCCORE13
AF43 VCCME4 VCCSUS3_3_8 N26 VSSA_LVDS AH39
AJ30 VCCCORE14
PLACE_NEAR=U1800.Y20:2.54MM AF41 VCCME5 VCCSUS3_3_9 M28
AJ31 VCCCORE15 PP1V8_S0_PCH_VCCTX_LVDS 24
AF42 VCCME6 VCCSUS3_3_10 M26
PP1V05_S0_PCH VCCTX_LVDS1 AP43 59 mA
V39 VCCME7 VCCSUS3_3_11 L28 101 24 23 21 18 17
VCCTX_LVDS2 AP45
V41 VCCME8 VCCSUS3_3_12 L26 3062 mA (VCCIO[1-56] total) AK24 VCCIO24
VCCTX_LVDS3 AT46
V42 VCCME9 VCCSUS3_3_13 J28
23 PP1V05_S0_PCH_VCCAPLL_EXP VCCTX_LVDS4 AT45
Y39 VCCME10 VCCSUS3_3_14 J26
40 mA (if GPIO27 is low) BJ24 VCCAPLLEXP
Y41 VCCME11 VCCSUS3_3_15 H28
Y42 VCCME12 VCCSUS3_3_16 H26 101 24 23 21 18 17 PP1V05_S0_PCH
VCCSUS3_3_17 G28 3062 mA AN20 VCCIO25
PCH output, for decoupling only
PPVOUT_G3_PCH_DCPRTC V9
VCCSUS3_3_18 G26 (VCCIO[1-56] total) AN22 VCCIO26
DCPRTC
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=X.XV VCCSUS3_3_19 F28 AN23 VCCIO27
HVCMOS
101 24 21 PP1V8_S0_PCH VCCSUS3_3_20 F26 AN24 VCCIO28 PP3V3_S0_PCH 17 18 19 20 21 23 24 101
1 C2210 164 mA (VCCVRM[1-4] total) AU24 VCCVRM3 VCCSUS3_3_21 E28 AN26 VCCIO29 VCC3_3_2 AB34 357 mA
0.1UF
C 20%
10V
2 CERM 24 PP1V05_S0_PCH_VCCADPLLA VCCSUS3_3_22
VCCSUS3_3_23
E26
C28
AN28
BJ26
VCCIO30
VCCIO31
VCC3_3_3
VCC3_3_4
AB35
AD35
(VCC3_3[1-14] total) C
402 68 mA BB51 VCCADPLLA1
VCCSUS3_3_24 C26 BJ28 VCCIO32
PLACE_NEAR=U1800.V9:2.54MM BB53 VCCADPLLA2
VCCSUS3_3_25 B27 AT26 VCCIO33
PP1V05_S0_PCH_VCCADPLLB
24 VCCSUS3_3_26 A28 AT28 VCCIO34
69 mA BD51 VCCADPLLB1 VCCSUS3_3_27 A26 AU26 VCCIO35
3062 mA (VCCIO[1-56] total) BD53 VCCADPLLB2 VCCSUS3_3_28 U23 AU28 VCCIO36
PCI-E*
101 24 23 21 18 17 PP1V05_S0_PCH AV26 VCCIO37
PP1V05_S0_PCH 17 18 21 23 24 101 PP1V8_S0_PCH 21 24 101
R2225 AH23 VCCIO21 VCCIO56 V23 3062 mA (VCCIO[1-56] total)
AV28 VCCIO38
VCCVRM2 AT24 164 mA (VCCVRM[1-4] total)
0.2 AW26 VCCIO39
DMI
1 2 PP1V05_S0_PCH_VCCIO_SSC_FLT AJ35 VCCIO22
MIN_LINE_WIDTH=0.2 mm PP5V_S5_PCH_V5REFSUS 23 AW28 VCCIO40 PPVTT_S0_PCH 20 21 23 101
1% MIN_NECK_WIDTH=0.1 mm AH35 VCCIO23
1/6W
MF
C2225 1 VOLTAGE=1.05V V5REF_SUS F24 < 1 mA S0-S5 BA26 VCCIO41 VCCDMI1 AT16 61 mA (1.1V)
402-HF 4.7UF BA28 VCCIO42 VCCDMI2 AU16 58 mA (1.05V)
20%
4V AF34 VCCIO2 PP5V_S0_PCH_V5REF 23
X5R 2 BB26 VCCIO43
115 mA AH34 VCCIO3 V5REF K49 < 1 mA
PCI/GPIO/LPC
402 BB28 VCCIO44

PLACE_NEAR=U1800.V12:2.54MM AF32 VCCIO4
PP3V3_S0_PCH 17 18 19 20 21 23 24 101 BC26 VCCIO45
PCH output, for decoupling only VCC3_3_8 J38 357 mA BC28 VCCIO46
PPVOUT_S0_PCH_DCPSST V12 DCPSST VCC3_3_9 L38 (VCC3_3[1-14] total) BD26 VCCIO47
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=X.XV
VCC3_3_10 M36 BD28 VCCIO48
PCH output, for decoupling only PP3V3R1V8_S0_PCH_VCCPNAND 23 101
1 C2220 PPVOUT_S5_PCH_DCPSUS Y22 DCPSUS
VCC3_3_11 N36 BE26 VCCIO49
VCCPNAND1 AM16 156 mA (1.8V)
0.1UF MIN_LINE_WIDTH=0.2 mm VCC3_3_12 P36 BE28 VCCIO50
20% MIN_NECK_WIDTH=0.2 mm VCCPNAND2 AK16 NOTE: Connect to 3.3V if NAND not used.
10V U35 BG26
NAND / SPI
2 CERM VOLTAGE=X.XV VCC3_3_13 VCCIO51
VCCPNAND3 AK20
402 1 C2230 PP3V3_S0_PCH BG28 VCCIO52
VCCPNAND4 AK19
0.1UF 17 18 19 20 21 23 24 101
BH27 VCCIO53
20% VCC3_3_14 AD13 357 mA (VCC3_3[1-14] total) VCCPNAND5 AK15
10V
2 CERM
402 AN30 VCCIO54 VCCPNAND6 AK13
PLACE_NEAR=U1800.Y22:2.54MM PP1V05_S0_PCH_VCCAPLL_SATA 23
AN31 VCCIO55 VCCPNAND7 AM12
B VCCSATAPLL1
VCCSATAPLL2
AK3
AK1
31 mA (if GPIO27 is low)
101 24 23 21 20 19 18 17 PP3V3_S0_PCH VCCPNAND8 AM13 B
VCCPNAND9 AM15
101 23 21 20 19 18 17 PP3V3_S5_PCH 357 mA (VCC3_3[1-14] total) AN35 VCC3_3_1
PP1V05_S0_PCH 17 18 21 23 24 101
163 mA S0, 65 mA S3-S5 P18 VCCSUS3_3_29 PP3V3_S0M_PCH 23 101
VCCIO9 AH22 3062 mA (VCCIO[1-56] total) 101 24 21 PP1V8_S0_PCH
(VCCSUS3_3[1-32] total) U19 VCCSUS3_3_30 VCCME3_3_1 AM8 85 mA S0, 22 mA M-on
PP1V8_S0_PCH 164 mA (VCCVRM[1-4] total) AT22 VCCVRM1
U20 VCCSUS3_3_31 21 24 101 VCCME3_3_2 AM9
FDI
U22 VCCSUS3_3_32 VCCVRM4 AT20 164 mA (VCCVRM[1-4] total) 23 PP1V05_S0_PCH_VCCAPLL_FDI VCCME3_3_3 AP11
5 mA (if GPIO27 is low) BJ18 VCCFDIPLL VCCME3_3_4 AP9
PCI/GPIO/LPC
101 24 23 21 20 19 18 17 PP3V3_S0_PCH
357 mA V15 VCC3_3_5 VCCIO10 AH19 GPIO27 HDA_SYNC VccVRM PLLs 101 24 23 21 18 17 PP1V05_S0_PCH
SATA
(VCC3_3[1-14] total) V16 VCC3_3_6 VCCIO11 AD20 3062 mA (VCCIO[1-56] total) AM23 VCCIO1
Y16 VCC3_3_7 VCCIO12 AF22 1 (IPU) 0 (IPD) 1.8V Float
VCCIO13 AD19
VCCIO14 AF20
1 (IPU) 1 1.5V Float
VCCIO15 AF19 0 X 1.05V 1.05V
VCCIO16 AH20
Note: 1.5V option consumes more current than 1.8V
VCCIO17 AB19
VCCIO18 AB20 PLLs = VccAClk, VccSATAPLL, VccAPLLEXP & VccFDIPLL
VCCIO19 AB22
VCCIO20 AD22
101 23 21 20 PPVTT_S0_PCH
CPU
< 1 mA AT18 V_CPU_IO1 PP1V05_S0_PCH 17 18 21 23 24 101
AU18 V_CPU_IO2 VCCME13 AA34 1849 mA S0, 700 mA M-on

VCCME14 Y34 (VCCME[1-16] total)
VCCME15 Y35
VCCME16 AA35
PP3V42_G3H PP3V3R1V5_S0_PCH Verify S0 okay

A 49 48 47 46 45 43 23 17 7 6 23 101
A
RTC
HDA
74 66 65 54 51 50
2 mA S0-S5, ~6 uA G3 A12 VCCRTC VCCSUSHDA L30 6 mA S0, < 1 mA S3-S5 SYNC_MASTER=K18_MLB SYNC_DATE=10/02/2009
PAGE TITLE
PCH Power
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

22 OF 132
Current numbers from Ibex Peak EDS Spec Update rev 0.71, doc #386904 (Table 8-3). Pre-Silicon Mobile Estimates. IV ALL RIGHTS RESERVED 21 OF 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AY7 OMIT H49 AB16 OMIT AK30
B11 U1800 H5 AA19 U1800 AK31
B15
IBEX_PEAK_M J24 AA20 IBEX_PEAK_M AK32
FCBGA FCBGA
B19 (9 OF 10) K11 AA22 AK34
(8 OF 10)
B23 K43 AM19 AK35
B31 K47 AA24 AK38
B35 K7 AA26 AK43
B39 L14 AA28 AK46
B43 L18 AA30 AK49
B47 L2 AA31 AK5
B7 L22 AA32 AK8
D BG12 L32 AB11 AL2 D

BB12 L36 AB15 AL52
BB16 L40 AB23 AM11
BB20 L52 AB30 BB44
BB24 M12 AB31 AD24
BB30 M16 AB32 AM20
BB34 M20 AB39 AM22
BB38 N38 AB43 AM24
BB42 M34 AB47 AM26
BB49 M38 AB5 AM28
BB5 M42 AB8 BA42
BC10 M46 AC2 AM30
BC14 M49 AC52 AM31
BC18 M5 AD11 AM32
BC2 M8 AD12 AM34
BC22 N24 AD16 AM35
BC32 P11 AD23 AM38
BC36 AD15 AD30 AM39
BC40 P22 AD31 AM42
BC44 P30 AD32 AU20
BC52 P32 AD34 AM46
BH9 P34 AU22 AV22
BD48 P42 AD42 AM49
BD49 P45 AD46 AM7
BD5 P47 AD49 AA50
BE12 R2 AD7 BB10
C BE16
BE20
R52
T12
AE2
AE4 VSS VSS
AN32
AN50
C
BE24 T41 AF12 AN52
BE30 T46 Y13 AP12
BE34 T49 AH49 AP42
BE38 T5 AU4 AP46
BE42 T8 AF35 AP49
BE46 U30 AP13 AP5
BE48 U31 AN34 AP8
BE50 U32 AF45 AR2
BE6 U34 AF46 AR52
BE8 P38 AF49 AT11
VSS VSS
BF3 V11 AF5 BA12
BF49 P16 AF8 AH48
BF51 V19 AG2 AT32
BG18 V20 AG52 AT36
BG24 V22 AH11 AT41
BG4 V30 AH15 AT47
BG50 V31 AH16 AT7
BH11 V32 AH24 AV12
BH15 V34 AH32 AV16
BH19 V35 AV18 AV20
BH23 V38 AH43 AV24
BH31 V43 AH47 AV30
BH35 V45 AH7 AV34
BH39 V46 AJ19 AV38
BH43 V47 AJ2 AV42
B BH47 V49 AJ20 AV46 B
BH7 V5 AJ22 AV49
C12 V7 AJ23 AV5
C50 V8 AJ26 AV8
D51 W2 AJ28 AW14
E12 W52 AJ32 AW18
E16 Y11 AJ34 AW2
E20 Y12 AT5 BF9
E24 Y15 AJ4 AW32
E30 Y19 AK12 AW36
E34 Y23 AM41 AW40
E38 Y28 AN19 AW52
E42 Y30 AK26 AY11
E46 Y31 AK22 AY43
E48 Y32 AK23 AY47
E6 Y38 AK28
E8 Y43
F49 Y46
F5 P49
G10 Y5
G14 Y6
G18 Y8
G2 P24
G22 T43
G32 AD51
G36 AT8
A G40 AD47 SYNC_MASTER=T22_MLB SYNC_DATE=03/26/2009 A
G44 Y47 PAGE TITLE
G52 AT12 PCH Grounds

AF39 AM6 DRAWING NUMBER SIZE
H16 AT13
Apple Inc. D
H20 AM5 REVISION
R
H30 AK45
H34 AK39 NOTICE OF PROPRIETARY PROPERTY: BRANCH
H38 AV14 THE INFORMATION CONTAINED HEREIN IS THE
H42 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
23 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH VCCRTC BYPASS PCH VCCPNAND BYPASS PCH VCCCORE BYPASS
101
19 18 17 PP3V3_S5_PCH (PCH RTC 3.3V PWR) (PCH NAND 1.8V/3.3V PWR) (PCH 1.05V CORE PWR)
23 21 20
67 57 7 PP5V_S5 PCH V5REF_SUS Filter & Follower
102 73 49 48 47 46 45 43 21 17 7 6 PP3V42_G3H 101 21 PP3V3R1V8_S0_PCH_VCCPNAND 101 24 23 21 18 17 PP1V05_S0_PCH
1 mA S0-S5 (PCH Reference for 5V Tolerance on USB) 74 66 65 54 51 50
2 4 2 mA S0-S5 /
R2400 2 D2400 6 uA G3 PLACE_NEAR=U1800.A12:2.54MM PLACE_NEAR=U1800.AK13:2.54MM 1 C2440 PLACE_NEAR=U1800.AB24:2.54MM
10 NC 0.1UF
5% BAT54DW-X-G C2420 1 1 C2421 1 C2422 C2470 1 1 C2471
NC
1/16W SOT-363 10%
MF-LF 3 1UF 0.1UF 0.1UF 2 16V 10UF 1UF
402 1 10% 10% 10% X5R 20% 10%
6.3V 2 16V
2 X5R 16V
2 X5R 402 6.3V 2 6.3V
2 CERM
CERM X5R
PP5V_S5_PCH_V5REFSUS 21 402 402 402 603 402
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM 1 mA S0-S5
VOLTAGE=5V PLACE_NEAR=U1800.A12:2.54MM PLACE_NEAR=U1800.AB24:2.54MM
C2400 1 PLACE_NEAR=U1800.F24:2.54MM PLACE_NEAR=U1800.A12:2.54MM PCH VCCSUSHDA BYPASS
D 1UF
10%
10V 2
(PCH HD Audio 3.3V/1.5V PWR) D
X5R PP3V3R1V5_S0_PCH PCH VCCIO BYPASS
402 PCH VCCSUS3_3 BYPASS 101 21
(PCH CLK 1.05V PWR)
(PCH SUSPEND PCI 3.3V PWR)
101
PP3V3_S5_PCH PLACE_NEAR=U1800.L30:2.54MM 1 C2445 101 24 23 21 18 17 PP1V05_S0_PCH
19 18 17
23 21 20 1UF
10%
2 6.3V
101 24
PP3V3_S0_PCH PLACE_NEAR=U1800.P18:2.54MM 1 C2425 CERM
402 PLACE_NEAR=U1800.AF32:2.54MM 1 C2475 1 C2476 1 C2477
19 18 17
23 21 20 0.1UF
1UF 1UF 1UF
(VCCSUS3_3 Total)
73 71 42 8 7 6 PP5V_S0 PCH V5REF Filter & Follower 10%
70 69 55 53 48 2 16V
X5R
10% 10% 10%
102 87
1 mA (PCH Reference for 5V Tolerance on PCI) 402 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1 402 402 402
R24012 5 D2400 PCH V_CPU_IO BYPASS
100 NC (PCH 1.1V/1.05V CPU I/O PWR)
5% BAT54DW-X-G PLACE_NEAR=U1800.AH23:2.54MM
NC
1/16W SOT-363 PLACE_NEAR=U1800.AH35:2.54MM

MF-LF 6 163 mA S0 / PCH USB/VCCSUS3_3 BYPASS 101 23 21 20 PPVTT_S0_PCH
402 1
65 mA S3-S5 (PCH SUSPEND USB 3.3V PWR)
PP5V_S0_PCH_V5REF 21 PLACE_NEAR=U1800.AT18:2.54MM PLACE_NEAR=U1800.AT18:2.54MM
MIN_LINE_WIDTH=0.3MM PP3V3_S5_PCH
VOLTAGE=5V
1 mA
101 23 21 20 19 18 17
C2450 1 1 C2451 1 C2452
C2401 1 PLACE_NEAR=U1800.K49:2.54MM 4.7UF 0.1UF 0.1UF PCH VCCIO BYPASS
PLACE_NEAR=U1800.U23:2.54MM 20% 10% 10%
1UF 6.3V 2 2 16V 2 16V (PCH USB 1.05V PWR)
10%
10V 2 PLACE_NEAR=U1800.A26:2.54MM 1 C2426 1 C2427 X5R
603
X5R
402
X5R
402
X5R 0.1UF 0.1UF 101 24 23 21 18 17 PP1V05_S0_PCH
402 10% 10%
2 16V
X5R 2 16V
X5R PLACE_NEAR=U1800.AT18:2.54MM
402 402 PLACE_NEAR=U1800.V24:2.54MM 1 C2480
1UF
10%
PCH VCCIO BYPASS 2 6.3V
CERM
(PCH DMI 1.05V PWR) 402
PCH VCCME3_3 BYPASS PPVTT_S0_PCH
101 23 21 20
(PCH ME 3.3V PWR)
C 101 21 PP3V3_S0M_PCH PLACE_NEAR=U1800.AT16:2.54MM 1 C2455 PCH VCCIO BYPASS
(PCH SATA 1.05V PWR)
C
1UF
10%
PLACE_NEAR=U1800.AM8:2.54MM 1 C2430 2 6.3V
CERM 101 24 23 21 18 17 PP1V05_S0_PCH
0.1UF 402
10%
2 16V
X5R PLACE_NEAR=U1800.AB19:2.54MM 1 C2485
402 1UF
10%
PCH VCCLAN BYPASS 2 6.3V
CERM
(PCH 1.05V LAN Core PWR) 402
PCH CORE/VCC3_3 BYPASS GND
(PCH MISC 3.3V PWR) NO STUFF
PCH VCCIO BYPASS
101 24 23 21 20 19 18 17 PP3V3_S0_PCH PLACE_NEAR=U1800.AF23:2.54MM 1 C2460 (PCH PCIE 1.05V PWR)
1UF
10%
PLACE_NEAR=U1800.V15:2.54MM 1 C2435 2 6.3V
CERM 101 24 23 21 18 17 PP1V05_S0_PCH
0.1UF 402
10%
2 16V
X5R PLACE_NEAR=U1800.AN20:2.54MM
402 C2490 1 1 C2491 1 C2492 1 C2493 1 C2494
PCH VCCME BYPASS 10UF 1UF 1UF 1UF 1UF
20% 10% 10% 10% 10%
(PCH 1.05V ME Core PWR) 6.3V 2 2 6.3V 2 6.3V 2 6.3V 2 6.3V
X5R CERM CERM CERM CERM
PCH VCCAPLLEXP Filter PCH VCC3_3 BYPASS 603 402 402 402 402
101 24 23 21 18 17 PP1V05_S0_PCH
(PCH PCIe PLL PWR) (PCH PCI 3.3V PWR)
PLACE_NEAR=U1800.AN20:2.54MM PLACE_NEAR=U1800.AN20:2.54MM
PLACE_NEAR=U1800.AN20:2.54MM
21 PP1V05_S0_PCH_VCCAPLL_EXP 101 24 23 21 20 19 18 17 PP3V3_S0_PCH PLACE_NEAR=U1800.AD38:2.54MM PLACE_NEAR=U1800.V39:2.54MM PLACE_NEAR=U1800.AN20:2.54MM
VOLTAGE=1.05V
OMIT WF: C2311 not in DG or CRB C2465 1 C2466 1 C2467 1 1 C2468 1 C2469
PLACE_NEAR=U1800.BJ24:2.54MM 1 C2413 PLACE_NEAR=U1800.J38:2.54MM 1 C2436 22UF 22UF 22UF 1UF 1UF
20% 20% 20% 10% 10%
1UF 0.1UF 6.3V
X5R-CERM 2
6.3V
X5R-CERM 2
6.3V
X5R-CERM 2 2 6.3V 2 6.3V
10% 10% CERM CERM
2 6.3V
CERM 2 16V
X5R
603 603 603 402 402
B 402 402
PLACE_NEAR=U1800.AD38:2.54MM
B
PLACE_NEAR=U1800.V39:2.54MM
PLACE_NEAR=U1800.AD38:2.54MM
PCH VCCFDIPLL Filter PCH VCC3_3 BYPASS
(PCH FDI PLL PWR) (PCH SATA 3.3V PWR)
21 PP1V05_S0_PCH_VCCAPLL_FDI 101 24 23 21 20 19 18 17 PP3V3_S0_PCH
MIN_NECK_WIDTH=0.25MM OMIT WF: C2413 not in DG or CRB
VOLTAGE=1.05V
PLACE_NEAR=U1800.BJ18:2.54MM 1 C2415 PLACE_NEAR=U1800.AD13:2.54MM 1 C2437
1UF 0.1UF
10% 10%
2 6.3V
CERM 2 16V
X5R
402 402
PCH VCCSATAPLL Filter PCH VCC3_3 BYPASS

(PCH SATA PLL PWR) (PCH PCIe/DMI 3.3V PWR)
21 PP1V05_S0_PCH_VCCAPLL_SATA 101 24 23 21 20 19 18 17 PP3V3_S0_PCH
VOLTAGE=1.05V
NO STUFF
PLACE_NEAR=U1800.AK1:2.54MM 1 C2417 PLACE_NEAR=U1800.AN35:2.54MM 1 C2438
1UF 0.1UF
10% 10%
2 6.3V
CERM 2 16V
X5R
402 402
PCH VCCACLK Filter PCH VCC3_3 BYPASS

(PCH Misc PLL PWR) (PCH CLK/HVCMOS 3.3V PWR)
A 21 PP1V05_S0_PCH_VCCA_CLK 101 24 23 21 20 19 18 17 PP3V3_S0_PCH SYNC_MASTER=K17_WFERRY SYNC_DATE=06/09/2009 A
MIN_LINE_WIDTH=0.5MM PAGE TITLE
NO STUFF
VOLTAGE=1.05V
PLACE_NEAR=U1800.AP51:2.54MM 1 C2419 PLACE_NEAR=U1800.AB34:2.54MM 1 C2439 PCH Non-GFX Decoupling
1UF 0.1UF DRAWING NUMBER SIZE
10%
2 6.3V
10%
2 16V Apple Inc. D
CERM X5R REVISION
402 402 R

24 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GFX (CPU VCCAXG) DECOUPLING
3x 330uF 6 mOhm (2 stuffed), 3x 22uF 0603, 16x 1uF 0402
70 50 13 7 PPVCORE_S0_GFX
Place on bottom side of U1000.
1 C2500 1 C2501 1 C2502 1

C2505 1
C2506
22UF 22UF 22UF 330UF 330UF
20% 20% 20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 3 2 2.0V
POLY-TANT
3 2 2.0V
POLY-TANT
D
603 603 603 D2T-SM2 D2T-SM2
D
1 C2524 1 C2525 1 C2526 1 C2527 1 C2528 1 C2529 1 C2530 1 C2531 1 C2532 1 C2533 1 C2534 1 C2535 1 C2536 1 C2537 1 C2538 1 C2539
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402

5x 1uF 0402
13 7 PPVCORE_S0_CPU_VCAP2
1 C2510 1 C2511 1 C2512 1 C2513 1 C2514

1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R 2 10V
X5R
402 402 402 402 402
C C
Design recommendations from Calpella Small Form Factor Design Guide Rev 1.5 (doc #407364) table 2-34 and Calpella Small Form F actor Schematic Check List Rev 1.1 (doc #395914) table 3.26.
PLACE_NEAR=U1800.AE50:2.54MM PCH VCCADAC Filter

(PCH DAC PLL PWR)
L2550
101 23 21 20 19 18 17 PP3V3_S0_PCH R2550 180-OHM-1.5A PP3V3_S0_PCH_VCCA_DAC 21
0 1 2 MIN_LINE_WIDTH=0.4 MM
69 mA 1 2 PP3V3_S0_PCH_VCCA_DAC_F MIN_NECK_WIDTH=0.2 MM 69 mA
MIN_LINE_WIDTH=0.5MM 0603 VOLTAGE=3.3V
5%
1/16W
69 mA
VOLTAGE=3.3V
MF-LF
402
C2550 1 1 C2551 1 C2552 PLACE_NEAR=U1800.AE50:2.54MM
10UF 0.1UF 0.01UF
20% 10% 20%
6.3V 2 2 16V 2 16V
X5R X5R CERM
603 402 402
PLACE_NEAR=U1800.AE50:2.54MM
PLACE_NEAR=U1800.AE50:2.54MM
PCH VCCADPLLA Filter

(PCH DPLLA PWR)
L2560
101 23 21 18 17 PP1V05_S0_PCH R2560 10UH-0.12A-0.36OHM PP1V05_S0_PCH_VCCADPLLA 21
0 PP1V05_S0_PCH_VCCADPLLA_F 1 2 MIN_LINE_WIDTH=0.4 MM
137 mA 1 2 MIN_NECK_WIDTH=0.2 MM 68 mA
MIN_LINE_WIDTH=0.5MM VOLTAGE=1.05V
5% 68 mA
MIN_NECK_WIDTH=0.25MM 0603 NO STUFF
1/16W VOLTAGE=1.05V
MF-LF
402 C2560 1 1 C2561 PLACE_NEAR=U1800.BB51:2.54MM
220UF 1UF
20% 10%
2.5V 2 2 6.3V
CERM
B POLY-TANT
CASE-B2-SM1 402 B
PLACE_NEAR=U1800.BB51:2.54MM
PCH VCCADPLLB Filter

(PCH DPLLB PWR)
L2565
R2565 10UH-0.12A-0.36OHM PP1V05_S0_PCH_VCCADPLLB 21
0 MIN_LINE_WIDTH=0.4 MM
1 2 PP1V05_S0_PCH_VCCADPLLB_F 1 2 MIN_NECK_WIDTH=0.2 MM 69 mA
MIN_LINE_WIDTH=0.5MM 0603 VOLTAGE=1.05V
5%
1/16W
69 mA
MIN_NECK_WIDTH=0.25MM NO STUFF
VOLTAGE=1.05V
MF-LF
402 C2565 1 1 C2566 PLACE_NEAR=U1800.BD51:2.54MM
220UF 1UF
20% 10%
2.5V 2 2 6.3V
CERM
POLY-TANT
CASE-B2-SM1 402
PLACE_NEAR=U1800.BD51:2.54MM
PLACE_NEAR=U1800.AP43:2.54MM PCH VCCTX_LVDS Filter

L2570 (PCH LVDS TX PWR)
101 21 PP1V8_S0_PCH 0.1UH PP1V8_S0_PCH_VCCTX_LVDS 21
1 2 MIN_LINE_WIDTH=0.4 MM
59 mA MIN_NECK_WIDTH=0.2 MM 59 mA
0805
VOLTAGE=1.8V
C2570 1 1 C2571 1 C2572 PLACE_NEAR=U1800.AP43:2.54MM

22UF 0.01UF 0.01UF
20% 20% 20%
6.3V 16V 16V
A X5R-CERM 2
603
2 CERM
402
2 CERM
402 SYNC_MASTER=K17_WFERRY SYNC_DATE=06/09/2009 A
PLACE_NEAR=U1800.AP43:2.54MM PAGE TITLE
PLACE_NEAR=U1800.AP43:2.54MM
CPU/PCH GFX Decoupling
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R
Design recommendations from Calpella Design Guide Rev 1.5 (doc #398905) Section 3.25.3 tables 161 and 162.
25 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Calpella Processor mini XDP

101 74 71 40 26 15 13 12 10 7 6 PPCPUVTT_S0
XDP_CPU_BPM CRITICAL XDP

RP2600 XDP_CONN 1
R2615
91 10 IN XDP_BPM_L<0> 1 8
J2600 51
5%
91 10 IN XDP_BPM_L<1> 2 0 7 LTH-030-01-G-D-NOPEGS 1/16W
5% F-ST-SM MF-LF
91 10 IN XDP_BPM_L<2> 3 1/16W 6
2 402
SM-LF
D 91 10 IN XDP_BPM_L<3> 4 5
91 10 BI XDP_PREQ_L OBSFN_A0
2
4
1
3 OBSFN_C0 CPU_CFG<8> IN 9 91
D
XDP_CPU_CFG 91 10 IN XDP_PRDY_L OBSFN_A1 6 5 OBSFN_C1 CPU_CFG<9> IN 9 91
RP2601 8 7
91 9 IN CPU_CFG<12> 1 8 XDP_OBSDATA_A<0> OBSDATA_A0 10 9 OBSDATA_C0 CPU_CFG<0> IN 9 91
91 9 IN CPU_CFG<13> 2 0 7 XDP_OBSDATA_A<1> OBSDATA_A1 12 11 OBSDATA_C1 CPU_CFG<1> IN 9 91

5%
91 9 IN CPU_CFG<14> 3 1/16W 6 14 13
SM-LF
91 9 IN CPU_CFG<15> 4 5 XDP_OBSDATA_A<2> OBSDATA_A2 16 15 OBSDATA_C2 CPU_CFG<2> IN 9 91
XDP_OBSDATA_A<3> OBSDATA_A3 18 17 OBSDATA_C3 CPU_CFG<3> IN 8 9 91

PLACEMENT_NOTE=Place R2601 close to R2600 to minimize stubs. 20 19
91 9 IN CPU_CFG<17> OBSFN_B0 22 21 OBSFN_D0 CPU_CFG<10> IN 9 91
91 9 IN CPU_CFG<16> OBSFN_B1 24 23 OBSFN_D1 CPU_CFG<11> IN 9 91

26 25
91 10 IN XDP_BPM_L<4> OBSDATA_B0 28 27 OBSDATA_D0 CPU_CFG<4> IN 9 91

32 31

XDP XDP_BPM_L<7> 36 35 CPU_CFG<7>
91 10 IN OBSDATA_B3 OBSDATA_D3 IN 9 91
R2610 38 37
1K
91 20 10 IN CPU_PWRGD 1 2 XDP_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 FSB_CLK133M_ITP_P IN 10 91
PM_PWRBTN_L 42 41 FSB_CLK133M_ITP_N XDP
5% 46 25 18 OUT HOOK1 ITPCLK#/HOOK5 IN 10 91
1/16W
MF-LF VCC_OBS_AB 44 43 VCC_OBS_CD R2611
402
XDP_CPUPWRGD 46 45 91 XDP_CPURST_L
1K FSB_CPURST_L
91 10 IN HOOK2 RESET#/HOOK6 1 2
IN 10 91
TP_XDP_HOOK3 HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L OUT 10 25 27 91 5% PLACE_NEAR=U1000.N70:1.00MM
1/16W
50 49 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. MF-LF
402
48 42 34 32 30 28 26 25 17 6 BI SMBUS_PCH_DATA SDA 52 51 TDO XDP_TDO 25 91
94 64 49
48 42 34 32 30 28 26 25 17 6 BI SMBUS_PCH_CLK SCL 54 53 TRSTn XDP_TRST_L OUT 10 91
C 94 64 49
91 10 XDP_TCK
TCK1
TCK0
NC
56
58
55
57
TDI
TMS
XDP_TDI
XDP_TMS
25 91 C
OUT OUT 10 91
60 59 XDP_PRESENT#
XDP_NORMAL&XDP_CPU XDP XDP
R2690 C2600 1
998-1571
1 C2601
0 0.1uF 0.1uF
10 OUT JTAG_CPU_TDI 1 2 XDP_TDI 25 91
10%
16V 2
10%
X5R 2 16V
X5R
XDP_CPU 5%
1/16W 402 402
R2695 MF-LF
402
JTAG_CPU_TDO 1
0 2 XDP_TDO
10 IN 25 91
XDP_NORMAL 5%
1/16W
1
R2691 MF-LF
402
0
5%
1/16W
MF-LF
402 2
XDP_GMCH
R2696
Calpella PCH mini XDP
JTAG_GMCH_TDI 1
0 2
10 OUT 101 99 88 86 85 84
49 48 47 42 40 37 34 30 28 27 26 8 7 6 PP3V3_S0
XDP_NORMAL&XDP_GMCH 5% 81 74 73 72 71 70 69 64 63 59 55 53 52 NOTE: This is not the standard XDP pinout.
1/16W
R2692 MF-LF USE WITH 920-0782 ADAPTER FLEX TO SUPPORT PCH DEBUGGING.
402 CRITICAL
JTAG_GMCH_TDO 0
10 IN
1 2 XDP_CONN
5%
1/16W J2650
MF-LF
402
DF40C-60DS-0.4V
F-ST-SM
1 2
TP_XDPPCH_OBSFN_A<0> OBSFN_A0 3 4 OBSFN_C0 ISOLATE_CPU_MEM_L IN 20 31 PCH GPIO28
TP_XDPPCH_OBSFN_A<1> OBSFN_A1 5 6 OBSFN_C1 SMC_IG_THROTTLE_L IN 20 46 47 PCH GPIO0
B PCH OC0# 19 IN PCH_GPIO59 OBSDATA_A0
7
9
8
10 OBSDATA_C0 FW_CLKREQ_L IN 17 40 PCH GPIO20
B
PCH OC1# 35 19 IN USB_HUB_SOFT_RESET_L OBSDATA_A1 11 12 OBSDATA_C1 AP_CLKREQ_L IN 17 33 PCH GPIO18
13 14
PCH OC2# 19 IN PCH_GPIO41 OBSDATA_A2 15 16 OBSDATA_C2 SATARDRVR_A_EN IN 17 42 PCH GPIO21

PCH OC3# 19 IN PCH_GPIO42 OBSDATA_A3 17 18 OBSDATA_C3 SATARDRVR_B_EN IN 17 PCH GPIO19
19 20
TP_XDPPCH_OBSFN_B<0> OBSFN_B0 21 22 OBSFN_D0 TP_XDPPCH_OBSFN_D<0>
TP_XDPPCH_OBSFN_B<1> OBSFN_B1 23 24 OBSFN_D1 TP_XDPPCH_OBSFN_D<1>
25 26
PCH OC4# 19 IN PCH_GPIO43 OBSDATA_B0 27 28 OBSDATA_D0 SDCARD_RESET IN 20 PCH GPIO36

PCH OC5# 19 IN PCH_GPIO9 OBSDATA_B1 29 30 OBSDATA_D1 JTAG_GMUX_TCK IN 20 88 PCH GPIO37
31 32
PCH OC6# 19 IN PCH_GPIO10 OBSDATA_B2 33 34 OBSDATA_D2 AUD_IPHS_SWITCH_EN IN 20 64 PCH GPIO16

PCH OC7# 19 IN PM_LATRIGGER_L OBSDATA_B3 35 36 OBSDATA_D3 ME_TEMP_ALERT_L IN 20 PCH GPIO49
37 38
88 74 46 27 IN ALL_SYS_PWRGD PWRGD/HOOK0 39 40 ITPCLK/HOOK4 TP_XDPPCH_HOOK4

46 25 18 PM_PWRBTN_L HOOK1 41 42 ITPCLK#/HOOK5 TP_XDPPCH_HOOK5
VCC_OBS_AB 43 44 VCC_OBS_CD
TP_XDPPCH_HOOK2 HOOK2 45 46 RESET#/HOOK6 XDPPCH_PLTRST_L IN 27 1K series R on PCH Support Page
TP_XDPPCH_HOOK3 HOOK3 47 48 DBR#/HOOK7 XDP_DBRESET_L 10 25 27 91
49 50 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
48 42 34 32 30 28 26 25 17 6
94 64 49
SMBUS_PCH_DATA SDA 51 52 TDO JTAG_PCH_TDO IN 17
48 42 34 32 30 28 26 25 17 6
94 64 49
SMBUS_PCH_CLK SCL 53 54 TRSTn TP_XDPPCH_TRST_L
TCK1 NC
55 56 TDI JTAG_PCH_TDI OUT 17
17 OUT JTAG_PCH_TCK TCK0 57 58 TMS JTAG_PCH_TMS OUT 17
A 59 60 XDP_PRESENT#
PAGE TITLE
998-2515 eXtended Debug Port (XDP)

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

26 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
L2700 PLACE_NEAR=L2700.2:2 mm:NO_VIA

PLACE_NEAR=U2700.1:2 mm PLACE_NEAR=U2700.24:2 mm
101 99 88 86 85 84
49 48 47 42 40 37 34 30 28 27 25 8 7 6 PP3V3_S0 FERR-120-OHM-1.5A PLACE_NEAR=U2700.5:2 mm PLACE_NEAR=U2700.29:2 mm
81 74 73 72 71 70 69 64 63 59 55 53 52
1 2 PLACE_NEAR=U2700.17:2 mm
PP3V3_S0_CK505_F
VOLTAGE=3.3V
C2700 1 1 C2705 1 C2706 1 C2707 1 C2708 1 C2709
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10% 10% 10%
6.3V 16V 16V 16V 16V 16V
X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
603 402 402 402 402 402
L2710 PLACE_NEAR=L2710.2:2 mm:NO_VIA

PPCPUVTT_S0 FERR-120-OHM-1.5A
C 101 74 71 40 25 15 13 12 10 7 6
1 2 PP1V05_S0_CK505_F
PLACE_NEAR=U2700.15:2 mm
PLACE_NEAR=U2700.18:2 mm C
0402 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
C2710 1 1 C2715 1 C2716
10UF 0.1UF 0.1UF
20% 10% 10%
6.3V 2 2 16V 2 16V
X5R X5R X5R
603 402 402
CRITICAL
Y2730
18
15
29
24
17
14.31818 NOTE: REF/FS pin is input until first CK_PWRGD rising edge.
1
PLACE_NEAR=Y2730.1:2 mm:NO_VIA 1 2 PLACE_NEAR=Y2730.2:2 mm:NO_VIA
FS=0 => 133MHz BCLKs, FS=1 => 100MHz BCLKs
VDD_CPU_IO
VDD_SRC_IO
VDD_27
VDD_DOT
VDD_REF
VDD_CPU
VDD_SRC
5X3.2-SM All other output frequencies are fixed.
C2730 1 1 C2731
18pF 18pF (IPD)
5%
50V
5%
50V REF_FS 30 PCH_CLK14P3M_REFCLK OUT 17 93 PCH REFCLK 14.31818MHz
CERM 2 2 CERM
402 402 CRITICAL USB 8 TP_CK505_USB Unused 48MHz
U2700 CPU0* 22 FSB_CLK133M_PCH_N OUT 17 93
R2790 1
CK505_CLK14P3M_XIN 28 XIN
SL28776
QFN CPU0 23 FSB_CLK133M_PCH_P 17 93 PCH BCLK 133MHz
OUT
10K CK505_CLK14P3M_XOUT
5% 27 XOUT
1/16W BYPASS=U2790::5 mm CPU1* 19 TP_CK505_CPU1N
MF-LF
402 2 C2790 1 49 48 42 34 32 30 28 25 17 6
94 64 IN SMBUS_PCH_CLK 32 SCLK CPU1 20 TP_CK505_CPU1P Unused BCLK 133MHz
0.1UF
20% 5 74HC1G00GWDG SMBUS_PCH_DATA 31 SDATA SRC1* 14 PCIE_CLK100M_PCH_N
10V 1 49 48 42 34 32 30 28 25 17 6 BI OUT 17 93
CERM 2 SC70-5 94 64
402 SRC1 13 PCIE_CLK100M_PCH_P OUT 17 93 PCH DMI/PCIe 100MHz

U2790 4 CK505_CKPWRGD 25 CK_PWRGD/PWRDWN*
69 IN CPUIMVP_CLK_EN_L 2 SRC0*/SATA* 11 PCH_CLK100M_SATA_N OUT 17 93
74 IN CK505_27MHZ_EN_L 16 27MHZ_OE*
SRC0/SATA 10 PCH_CLK100M_SATA_P 17 93 PCH SATA 100MHz
B 3
No internal pull.
27M_NSS 6 CK505_CLK27M
OUT
27
B
Must be strapped appropriately
TP_CK505_CLK27M_SS GPU 27MHz Clocks (Single-Ended)
or connected to logic for 27M_SS 7
Muxed Graphics implementations. PCH_CLK96M_DOT_N
DOT96* 4 OUT 17 93
VSS_DOT
VSS_REF
VSS_CPU
VSS_SRC
DOT96 3 PCH_CLK96M_DOT_P PCH USB Clock 96MHz
VSS_27
OUT 17 93
THRM
PAD
21
12
26
33
PAGE TITLE
Clock (CK505)
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

27 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Platform Reset Connections

PCH RTC Crystal Unbuffered
R2881 LPCPLUS_RESET_L OUT 6 27 48 88 94
R2810 C2810 33
12pF 40 31 27 19 IN PLT_RESET_L 1 2 LPCPLUS_RESET_L OUT 6 27 48 88 94
PCH_CLK32K_RTCX2 0 1 2 MAKE_BASE=TRUE MAKE_BASE=TRUE

17 IN
1 2 PCH_CLK32K_RTCX2_R 5%
1/16W
5% MF-LF
1/16W 5% 402 R2883
R28111 MF-LF CRITICAL 50V 33
CERM SMC_LRESET_L
D
3
402 1 2
D 10M 402 OUT 46
2 4
5% Y2810 NC 5%
1/16W 32.768K NC 1/16W
MF-LF
MF-LF SM-2 C2811 R2882 402
1
402 2
12pF 0
1 2
1 2 ENET_RESET_L OUT 37 95
17 OUT PCH_CLK32K_RTCX1
5%
5% 1/16W
MF-LF
50V
CERM 402 R2888
402 0
1 2 AP_RESET_L OUT 33
PCH 25MHz Crystal R2871

0
5%
1/16W
MF-LF
402
1 2 PCA9557D_RESET_L OUT 32
C2815 5%
1/16W
XDP
R2815 12pF MF-LF
R2889
PCH_CLK25M_XTALOUT 0 PCH_CLK25M_XTALOUT_R 1 2 402
17 IN 1 2
1
1K 2 XDPPCH_PLTRST_L OUT 25
DCI 5%
1/16W 5% 5%
1 CRITICAL 50V
R2816 MF-LF CERM 1/16W
3
402 402 R2887 MF-LF
10M
2 4
Y2815 NC 402
5% 1
0 2 GMUX_RESET_L
1/16W 25.0000M NC 27 88
MF-LF SM-3.2X2.5MM C2816 5%
MAKE_BASE=TRUE
1
402 2
12pF 1/16W GMUX_RESET_L OUT 27 88
1 2 MF-LF
17 OUT PCH_CLK25M_XTALIN 402
5%
R2893
50V 1
0 2 BKLT_PLT_RST_L OUT 90
CERM
402 5%
1/16W
Caesar II (ENET) 25MHz Crystal MF-LF

402
PLT_RESET_L OUT 19 27 31 40
C C2820 101 99 88 86 85 84 81
PP3V3_S0
Series R is R4283 C
R2820 27pF
48 47 42 40 37 34 30 28 27 26 25 8 7 6
95 37 IN BCM5764_CLK25M_XTALO 1
200 2 BCM5764_CLK25M_XTALO_R 1 2
74 73 72 71 70 69 64 63 59 55 53 52 49
Buffered
NO STUFF 5%
1/16W 5%
1 CRITICAL 50V 5 MC74VHC1G08
R2821 MF-LF CERM R2884
3
402 1 SC70-HF
10M 402 0
2 4
5% Y2820 NC
U2880 4 27 10 PLT_RST_BUF_L 1 2 EXCARD_RESET_L OUT 34
1/16W 25.0000M NC 2 MAKE_BASE=TRUE
5%
MF-LF SM-3.2X2.5MM C2821 1/16W
1
402 2 1
27pF 3 R2880 MF-LF
402
95 37 OUT BCM5764_CLK25M_XTALI 1 2 C2880 1 5%
100K
PLT_RST_BUF_L
0.1UF 1/16W OUT 10 27
5% 20% MF-LF
50V 10V VTT voltage divider on CPU page
CERM CERM 2 2 402
402 402
Ethernet WAKE# Isolation

PP3V3_ENET 7 37 74
1
R2830 R2825
Q2830 PLACE_NEAR=U1800.N52:5mm 22
1 10K 94 19 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 46 94
SSM3K15FV 5%
1/16W 5%
G
SOD-VESM-HF MF-LF 1/16W

B 2 402
MF-LF
402
PLACE_NEAR=U1800.P53:5mm
R2826
22
B
D
34 33 18 6 OUT PCIE_WAKE_L 37 27 ENET_WAKE_L ENET_WAKE_L IN 27 37 19 IN LPC_CLK33M_LPCPLUS_R 1 2 LPC_CLK33M_LPCPLUS OUT 6 48 94

3 2 MAKE_BASE=TRUE
5%
1/16W
R2827 MF-LF
PLACE_NEAR=U1800.P46:5mm 402
LPC_CLK33M_GMUX_R 27 19 LPC_CLK33M_GMUX_R 1
22 2 LPC_CLK33M_GMUX
27 19 IN OUT 88
MAKE_BASE=TRUE
5%
1/16W
MF-LF R2829
402
PLACE_NEAR=U1800.P48:5mm 22
19 IN PCH_CLK33M_PCIOUT 1 2 PCH_CLK33M_PCIIN OUT 17 93
5%
1/16W
PLACE_NEAR=U2700.6:5mm R2824 MF-LF
402
0
27 26 IN CK505_CLK27M 27 26 CK505_CLK27M 1 2 GPU_CLK27M OUT 80 81 98
5%
1/16W
MF-LF
PCH S0 PWRGD 402
101 99 88 86 85 84 81 74 73
47 42 40 37 34 30 28 27 26 25 8 7 6
72 71 70 69 64 63 59 55 53 52 49 48
PP3V3_S0 PCH Reset Button
101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49
PP3V3_S0
R28501 1 C2850 1
10K 0.1UF
20%
R2895
5% 10V 10K
1/16W 2 CERM 5%
MF-LF 402 XDP 1/16W
402 2 MF-LF
R2896 2 402
0
A 5 MC74VHC1G08
91 25 10 IN XDP_DBRESET_L 1
5%
2 PM_SYSRST_L BI 6 18 46
88 74 46 25 IN ALL_SYS_PWRGD 1 SC70-HF 1/16W PAGE TITLE
U2850 4 PM_PCH_PWRGD OUT 18

MF-LF
402
OMIT
Chipset Support
69 IN CPUIMVP_PGOOD 2
1 DRAWING NUMBER SIZE
R2897 D
3 0
5%
Apple Inc. REVISION
1/16W R
MF-LF
2 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
SILK_PART=SYS RESET THE INFORMATION CONTAINED HEREIN IS THE
28 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
73 68 31 30 7 PP1V5_S3
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Power aliases required by this page:
- =PP1V5_S0_MEM_A
- =PP1V5_S3_MEM_A
1 C2910 1 C2911 1 C2912 1 C2913 1 C2914 1 C2915 1 C2916 1 C2917 1 C2918 1 C2919 1 C2920 1 C2921 1 C2922 1 C2923
- =PP0V75_S0_MEM_VTT_A
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
- =PPSPD_S0_MEM_A (2.5 - 3.3V) 2 10V
CERM
10V
2 CERM 10V
2 CERM 10V
2 CERM 10V
2 CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM 10V
2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402
Signal aliases required by this page: 1 C2900 1 C2901
- =I2C_SODIMMA_SCL
10UF 10UF
- =I2C_SODIMMA_SDA 20% 20%
6.3V
2 X5R 6.3V
2 X5R
D BOM options provided by this page:
(NONE)
603 603
32 PP0V75_S3_MEM_VREFDQ_A D
1
C2930 1
C2931
2.2UF 0.1UF
20% 20%
6.3V 10V
2 CERM 2 CERM
402-LF 402
1 VREFDQ VSS 2
3 VSS DQ4 4 =MEM_A_DQ<4> BI 29
KEY
92 11 IN MEM_A_CKE<0> 73 CKE0 CKE1 74 MEM_A_CKE<1> IN 11 92 29 BI =MEM_A_DQ<0> 5 DQ0 DQ5 6 =MEM_A_DQ<5> BI 29
75 76 =MEM_A_DQ<1> 7 CRITICAL 8
VDD VDD 29 BI DQ1 VSS
77 78 9 10
92 11 IN MEM_A_BA<2>
NC
79
NC J2900 A15
BA2 F-RT-THB A14 80
MEM_A_A<15>
MEM_A_A<14>
IN
IN
11 92
11 92 92 29 11 IN MEM_A_DM<0> 11
VSS
DM0J2900 DQS0*
DQS0 12
MEM_A_DQS_N<0>
MEM_A_DQS_P<0>
BI
BI
11 29 92
11 29 92
81 82 13 VSS F-RT-THB VSS 14
(SYMBOL 2 OF 2)
DDR3-SODIMM-DUAL-K6
VDD VDD
DDR3-SODIMM-DUAL-K6
(SYMBOL 1 OF 2)
92 11 IN MEM_A_A<12> 83 A12/BC* A11 84 MEM_A_A<11> IN 11 92 29 BI =MEM_A_DQ<2> 15 DQ2 DQ6 16 =MEM_A_DQ<6> BI 29
92 11 IN MEM_A_A<9> 85 A9 A7 86 MEM_A_A<7> IN 11 92 29 BI =MEM_A_DQ<3> 17 DQ3 DQ7 18 =MEM_A_DQ<7> BI 29

87 VDD VDD 88 19 VSS VSS 20

92 11 IN MEM_A_A<3> 95 A3 A2 96 MEM_A_A<2> IN 11 92 29 BI =MEM_A_DQS_N<1> 27 DQS1* DM1 28 =MEM_A_DM<1> IN 29
92 11 IN MEM_A_A<1> 97 A1 A0 98 MEM_A_A<0> IN 11 92 29 BI =MEM_A_DQS_P<1> 29 DQS1 RESET* 30 MEM_RESET_L IN 30 31

92 11 IN MEM_A_CLK_P<0> 101 CK0 CK1 102 MEM_A_CLK_P<1> IN 11 92 29 BI =MEM_A_DQ<10> 33 DQ10 DQ14 34 =MEM_A_DQ<14> BI 29
92 11 IN MEM_A_CLK_N<0> 103 CK0* CK1* 104 MEM_A_CLK_N<1> IN 11 92 29 BI =MEM_A_DQ<11> 35 DQ11 DQ15 36 =MEM_A_DQ<15> BI 29
C 92 11 MEM_A_A<10>
105
107
VDD
A10/AP
VDD
BA1
106
108 MEM_A_BA<1> 11 92 29 =MEM_A_DQ<16>
37
39
VSS
DQ16
VSS
DQ20
38
40 =MEM_A_DQ<20> 29
C
IN IN BI BI
92 11 IN MEM_A_BA<0> 109 BA0 RAS* 110 MEM_A_RAS_L IN 11 92 29 BI =MEM_A_DQ<17> 41 DQ17 DQ21 42 =MEM_A_DQ<21> BI 29
92 11 IN MEM_A_WE_L 113 WE* S0* 114 MEM_A_CS_L<0> IN 11 92 29 BI =MEM_A_DQS_N<2> 45 DQS2* DM2 46 =MEM_A_DM<2> IN 29
92 11 IN MEM_A_CAS_L 115 CAS* ODT0 116 MEM_A_ODT<0> IN 11 92 29 BI =MEM_A_DQS_P<2> 47 DQS2 VSS 48

117 VDD VDD 118 49 VSS DQ22 50 =MEM_A_DQ<22> BI 29
92 11 IN MEM_A_A<13> 119 A13 ODT1 120 MEM_A_ODT<1> IN 11 92 29 BI =MEM_A_DQ<18> 51 DQ18 DQ23 52 =MEM_A_DQ<23> BI 29
MEM_A_CS_L<1> 121 S1* NC 122 =MEM_A_DQ<19> 53 DQ19 VSS 54

92 11 IN NC 29 BI
123 VDD VDD 124 55 VSS DQ28 56 =MEM_A_DQ<28> BI 29
125 TEST VREFCA 126 =MEM_A_DQ<24> 57 DQ24 DQ29 58 =MEM_A_DQ<29>
NC 29 BI BI 29
127 VSS VSS 128 29 BI =MEM_A_DQ<25> 59 DQ25 VSS 60
29 BI =MEM_A_DQ<32> 129 DQ32 DQ36 130 =MEM_A_DQ<36> BI 29
61 VSS DQS3* 62 =MEM_A_DQS_N<3> BI 29
29 BI =MEM_A_DQ<33> 131 DQ33 DQ37 132 MEM_A_DQ<37> BI 11 29 92 29 IN =MEM_A_DM<3> 63 DM3 DQS3 64 =MEM_A_DQS_P<3> BI 29
133 VSS VSS 134 65 VSS VSS 66
29 BI =MEM_A_DQS_N<4> 135 DQS4* DM4 136 =MEM_A_DM<4> IN 29 29 BI =MEM_A_DQ<26> 67 DQ26 DQ30 68 =MEM_A_DQ<30> BI 29
29 BI =MEM_A_DQS_P<4> 137 DQS4 VSS 138 29 BI =MEM_A_DQ<27> 69 DQ27 DQ31 70 =MEM_A_DQ<31> BI 29

139 VSS DQ38 140 =MEM_A_DQ<38> BI 29
71 VSS VSS 72
29 BI =MEM_A_DQ<34> 141 DQ34 DQ39 142 =MEM_A_DQ<39> BI 29 KEY
29 BI =MEM_A_DQ<35> 143 DQ35 VSS 144

145 VSS DQ44 146 =MEM_A_DQ<44> BI 29 516-0229
29 BI =MEM_A_DQ<41> 149 DQ41 VSS 150

151 VSS DQS5* 152 =MEM_A_DQS_N<5> BI 29
29 IN =MEM_A_DM<5> 153 DM5 DQS5 154 =MEM_A_DQS_P<5> BI 29

155 VSS VSS 156
157 158
B 29
29
BI
BI
=MEM_A_DQ<42>
=MEM_A_DQ<43> 159
DQ42
DQ43
DQ46
DQ47 160
=MEM_A_DQ<46>
=MEM_A_DQ<47>
BI
BI 29
29
B
161 VSS VSS 162

167 VSS VSS 168
29 BI =MEM_A_DQS_N<6> 169 DQS6* DM6 170 =MEM_A_DM<6> IN 29
29 BI =MEM_A_DQS_P<6> 171 DQS6 VSS 172

173 VSS DQ54 174 =MEM_A_DQ<54> BI 29
29 BI =MEM_A_DQ<50> 175 DQ50 DQ55 176 =MEM_A_DQ<55> BI 29 PP0V75_S3_MEM_VREFCA_A 32
29 BI =MEM_A_DQ<51> 177 DQ51 VSS 178

179 VSS DQ60 180 =MEM_A_DQ<60> BI 29

1
C2935 1
C2936
29 BI =MEM_A_DQ<57> 183 DQ57 VSS 184 2.2UF 0.1UF
20% 20%
185 VSS DQS7* 186 =MEM_A_DQS_N<7> BI 29 2
6.3V
2
10V
CERM CERM
29 IN =MEM_A_DM<7> 187 DM7 DQS7 188 =MEM_A_DQS_P<7> BI 29
402-LF 402
189 VSS VSS 190


195 VSS VSS 196
MEM_A_SA<0> 197 SA0 EVENT* 198 MEM_EVENT_A_L OUT 30 46 47
99 88 86 85 84
63 59 55 53 52
27 26 25 8 7 6 PP3V3_S0 199 VDDSPD SDA 200 SMBUS_PCH_DATA BI 6 17 25 26 30 32 34 42 48 49 64 "Factory" (top) slot
49 48 47 42 40 37 34 30 94
81 74 73 72 71 70 69 64
101 MEM_A_SA<1> 201 SA1 SCL 202 SMBUS_PCH_CLK IN 6 17 25 26 30 32 34 42 48 49 64
94
203 VTT VTT 204 PP0V75_S0_DDRVTT 7 30 31 68
1 1
1
C2940 R2940 R2941
A 2
2.2UF
20%
6.3V
10K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
516-0229
SPD ADDR=0xA0(WR)/0xA1(RD)
CERM
402 402
PAGE TITLE
402-LF 2 2
DDR3 SO-DIMM Connector A
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

29 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU CHANNEL A DQS 0 -> DIMM A DQS 0 CPU CHANNEL B DQS 0 -> DIMM B DQS 0
92 29 28 11 MEM_A_DQS_N<0> MEM_A_DQS_N<0> 11 28 29 92 92 30 29 11 MEM_B_DQS_N<0> MEM_B_DQS_N<0> 11 29 30 92
92 29 28 11 MEM_A_DQS_P<0> MEM_A_DQS_P<0> 11 28 29 92 92 30 29 11 MEM_B_DQS_P<0> MEM_B_DQS_P<0> 11 29 30 92
92 29 28 11 MEM_A_DM<0> MEM_A_DM<0> 11 28 29 92 92 30 29 11 MEM_B_DM<0> MEM_B_DM<0> 11 29 30 92
92 11 MEM_A_DQ<7> =MEM_A_DQ<7> 28 92 11 MEM_B_DQ<7> =MEM_B_DQ<7> 30
D 92 11 MEM_A_DQ<0>
MAKE_BASE=TRUE
=MEM_A_DQ<4> 28 92 11 MEM_B_DQ<0>
MAKE_BASE=TRUE
=MEM_B_DQ<0> 30
D
92 11 MEM_A_DQS_N<1> =MEM_A_DQS_N<1> 28 92 11 MEM_B_DQS_N<1> =MEM_B_DQS_N<1> 30
92 11 MEM_A_DQS_P<1> =MEM_A_DQS_P<1> 28 92 11 MEM_B_DQS_P<1> =MEM_B_DQS_P<1> 30
92 11 MEM_A_DM<1> =MEM_A_DM<1> 28 92 11 MEM_B_DM<1> =MEM_B_DM<1> 30
C 92 11 MEM_A_DQS_N<3>
MAKE_BASE=TRUE
=MEM_A_DQS_N<3> 28 92 11 MEM_B_DQS_N<3>
MAKE_BASE=TRUE
=MEM_B_DQS_N<3> 30
C
92 29 28 11 MEM_A_DQ<37> MEM_A_DQ<37> 11 28 29 92 92 30 29 11 MEM_B_DQ<37> MEM_B_DQ<37> 11 29 30 92
B 92 11 MEM_A_DQS_P<5> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQS_P<5> 28 92 11 MEM_B_DQS_P<5> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQS_P<5> 30 B
MEM_A_DQS_P<7> =MEM_A_DQS_P<7> MEM_B_DQS_P<7> =MEM_B_DQS_P<7>
A 92 11
92 11 MEM_A_DM<7> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DM<7>
28
28
92 11
92 11 MEM_B_DM<7> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DM<7>
30
30 SYNC_MASTER=K18_MLB SYNC_DATE=06/19/2009 A
PAGE TITLE
92 11 MEM_A_DQ<62> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ<63> 28 92 11 MEM_B_DQ<62> MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_B_DQ<62> 30 DDR3 Byte/Bit Swaps
92 11 MEM_A_DQ<61> =MEM_A_DQ<56> 28 92 11 MEM_B_DQ<61> =MEM_B_DQ<57> 30 DRAWING NUMBER SIZE
92 11 MEM_A_DQ<60>
MAKE_BASE=TRUE
=MEM_A_DQ<61> 28 92 11 MEM_B_DQ<60>
MAKE_BASE=TRUE
=MEM_B_DQ<56> 30
Apple Inc. D
92 11 MEM_A_DQ<59> =MEM_A_DQ<59> 28 92 11 MEM_B_DQ<59> =MEM_B_DQ<59> 30 REVISION
MAKE_BASE=TRUE MAKE_BASE=TRUE R
92 11 MEM_A_DQ<57> =MEM_A_DQ<57> 28 92 11 MEM_B_DQ<57> =MEM_B_DQ<60> 30 NOTICE OF PROPRIETARY PROPERTY: BRANCH
92 11 MEM_A_DQ<56> =MEM_A_DQ<60> 28 92 11 MEM_B_DQ<56> =MEM_B_DQ<61> 30 THE INFORMATION CONTAINED HEREIN IS THE
MAKE_BASE=TRUE MAKE_BASE=TRUE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
30 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
73 68 31 28 7 PP1V5_S3
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
1 C3110 1 C3111 1 C3112 1 C3113 1 C3114 1 C3115 1 C3116 1 C3117 1 C3118 1 C3119 1 C3120 1 C3121 1 C3122 1 C3123
- =PP0V75_S0_MEM_VTT_B
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
- =PPSPD_S0_MEM_B (2.5 - 3.3V) 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM 10V
2 CERM 10V
2 CERM 2 10V
CERM 2 10V
CERM
10V
2 CERM 10V
2 CERM 2 10V
CERM
10V
2 CERM 10V
2 CERM 10V
2 CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402
Signal aliases required by this page: 1 C3100 1 C3101
- =I2C_SODIMMB_SCL
10UF 10UF
- =I2C_SODIMMB_SDA 20% 20%
2 6.3V
X5R
6.3V
2 X5R
D BOM options provided by this page:
(NONE)
603 603
32 PP0V75_S3_MEM_VREFDQ_B D
1
C3130 1
C3131
2.2UF 0.1UF
20% 20%
6.3V 10V
2 CERM 2 CERM
402-LF 402
1 VREFDQ VSS 2
3 VSS DQ4 4 =MEM_B_DQ<4> BI 29
KEY
92 11 MEM_B_CKE<0> 73 CKE0 CKE1 74 MEM_B_CKE<1> 11 92 29 =MEM_B_DQ<0> 5 DQ0 OMIT DQ5 6 =MEM_B_DQ<5> 29
IN IN BI BI
75 76 =MEM_B_DQ<1> 7 CRITICAL 8
VDD VDD 29 BI DQ1 VSS
77 NC OMIT A15 78 MEM_B_A<15> 9 VSS DQS0* 10 MEM_B_DQS_N<0>
92 11 IN MEM_B_BA<2> 79 BA2J3100 A14 80 MEM_B_A<14>
IN
IN
11 92
11 92 92 29 11 IN MEM_B_DM<0> 11 DM0J3100 DQS0

F-RT-BGA6 VSS
12 MEM_B_DQS_P<0>
BI
BI
11 29 92
11 29 92
81 VDD F-RT-BGA6 VDD 82 13 VSS 14
DDR3-SODIMM
(1 OF 2)
83 84 15 16
(2 OF 2)
DDR3-SODIMM
92 11 IN MEM_B_A<12> A12/BC* A11 MEM_B_A<11> IN 11 92 29 BI =MEM_B_DQ<2> DQ2 DQ6 =MEM_B_DQ<6> BI 29
92 11 IN MEM_B_A<9> 85 A9 A7 86 MEM_B_A<7> IN 11 92 29 BI =MEM_B_DQ<3> 17 DQ3 DQ7 18 =MEM_B_DQ<7> BI 29


92 11 IN MEM_B_A<3> 95 A3 A2 96 MEM_B_A<2> IN 11 92 29 BI =MEM_B_DQS_N<1> 27 DQS1* DM1 28 =MEM_B_DM<1> IN 29
92 11 IN MEM_B_A<1> 97 A1 A0 98 MEM_B_A<0> IN 11 92 29 BI =MEM_B_DQS_P<1> 29 DQS1 RESET* 30 MEM_RESET_L IN 28 31

92 11 IN MEM_B_CLK_P<0> 101 CK0 CK1 102 MEM_B_CLK_P<1> IN 11 92 29 BI =MEM_B_DQ<10> 33 DQ10 DQ14 34 =MEM_B_DQ<14> BI 29
92 11 IN MEM_B_CLK_N<0> 103 CK0* CK1* 104 MEM_B_CLK_N<1> IN 11 92 29 BI =MEM_B_DQ<11> 35 DQ11 DQ15 36 =MEM_B_DQ<15> BI 29
C 92 11 MEM_B_A<10>
105
107
VDD
A10/AP
VDD
BA1
106
108 MEM_B_BA<1> 11 92 29 =MEM_B_DQ<16>
37
39
VSS
DQ16
VSS
DQ20
38
40 =MEM_B_DQ<20> 29
C
IN IN BI BI
92 11 IN MEM_B_BA<0> 109 BA0 RAS* 110 MEM_B_RAS_L IN 11 92 29 BI =MEM_B_DQ<17> 41 DQ17 DQ21 42 =MEM_B_DQ<21> BI 29
92 11 IN MEM_B_WE_L 113 WE* S0* 114 MEM_B_CS_L<0> IN 11 92 29 BI =MEM_B_DQS_N<2> 45 DQS2* DM2 46 =MEM_B_DM<2> IN 29
92 11 IN MEM_B_CAS_L 115 CAS* ODT0 116 MEM_B_ODT<0> IN 11 92 29 BI =MEM_B_DQS_P<2> 47 DQS2 VSS 48

117 VDD VDD 118 49 VSS DQ22 50 =MEM_B_DQ<22> BI 29
92 11 IN MEM_B_A<13> 119 A13 ODT1 120 MEM_B_ODT<1> IN 11 92 29 BI =MEM_B_DQ<18> 51 DQ18 DQ23 52 =MEM_B_DQ<23> BI 29
MEM_B_CS_L<1> 121 S1* NC 122 =MEM_B_DQ<19> 53 DQ19 VSS 54

92 11 IN NC 29 BI
123 VDD VDD 124 55 VSS DQ28 56 =MEM_B_DQ<28> BI 29
125 TEST VREFCA 126 29 BI =MEM_B_DQ<24> 57 DQ24 DQ29 58 =MEM_B_DQ<29> BI 29
127 VSS VSS 128 29 BI =MEM_B_DQ<25> 59 DQ25 VSS 60
29 BI =MEM_B_DQ<32> 129 DQ32 DQ36 130 =MEM_B_DQ<36> BI 29
61 VSS DQS3* 62 =MEM_B_DQS_N<3> BI 29
29 BI =MEM_B_DQ<33> 131 DQ33 DQ37 132 =MEM_B_DQ<37> BI 29 29 IN =MEM_B_DM<3> 63 DM3 DQS3 64 =MEM_B_DQS_P<3> BI 29
133 VSS VSS 134 65 VSS VSS 66
29 BI =MEM_B_DQS_N<4> 135 DQS4* DM4 136 =MEM_B_DM<4> IN 29 29 BI =MEM_B_DQ<26> 67 DQ26 DQ30 68 =MEM_B_DQ<30> BI 29
29 BI =MEM_B_DQS_P<4> 137 DQS4 VSS 138 29 BI =MEM_B_DQ<27> 69 DQ27 DQ31 70 =MEM_B_DQ<31> BI 29

139 VSS DQ38 140 =MEM_B_DQ<38> BI 29
71 VSS VSS 72
92 29 11 BI MEM_B_DQ<37> 141 DQ34 DQ39 142 =MEM_B_DQ<39> BI 29 KEY
29 BI =MEM_B_DQ<35> 143 DQ35 VSS 144

145 VSS DQ44 146 =MEM_B_DQ<44> BI 29 516s0806
29 BI =MEM_B_DQ<41> 149 DQ41 VSS 150

151 VSS DQS5* 152 =MEM_B_DQS_N<5> BI 29
29 IN =MEM_B_DM<5> 153 DM5 DQS5 154 =MEM_B_DQS_P<5> BI 29

155 VSS VSS 156
157 158
B 29
29
BI
BI
=MEM_B_DQ<42>
=MEM_B_DQ<43> 159
DQ42
DQ43
DQ46
DQ47 160
=MEM_B_DQ<46>
=MEM_B_DQ<47>
BI
BI 29
29
B
161 VSS VSS 162

167 VSS VSS 168
29 BI =MEM_B_DQS_N<6> 169 DQS6* DM6 170 =MEM_B_DM<6> IN 29
29 BI =MEM_B_DQS_P<6> 171 DQS6 VSS 172

173 VSS DQ54 174 =MEM_B_DQ<54> BI 29
29 BI =MEM_B_DQ<50> 175 DQ50 DQ55 176 =MEM_B_DQ<55> BI 29 PP0V75_S3_MEM_VREFCA_B 32
29 BI =MEM_B_DQ<51> 177 DQ51 VSS 178

179 VSS DQ60 180 =MEM_B_DQ<60> BI 29

1
C3135 1
C3136
29 BI =MEM_B_DQ<57> 183 DQ57 VSS 184 2.2UF 0.1UF
20% 20%
185 VSS DQS7* 186 =MEM_B_DQS_N<7> BI 29 2
6.3V
2
10V
1 CERM CERM
R3140 29 =MEM_B_DM<7> 187 DM7 DQS7 188 =MEM_B_DQS_P<7> 29
402-LF 402
IN BI
10K 189 190
5% VSS VSS
1/16W
MF-LF 29 BI =MEM_B_DQ<58> 191 DQ58 DQ62 192 =MEM_B_DQ<62> BI 29
2
402
195 VSS VSS 196
MEM_B_SA<0> 197 SA0 EVENT* 198 MEM_EVENT_A_L OUT 28 46 47
101 99
70 69 64 63 59 55
28 27 26 25 8 7 6PP3V3_S0 199 VDDSPD SDA 200 SMBUS_PCH_DATA BI 6 17 25 26 28 32 34 42 48 49 64
53 52 49 48 47 42 40 37 34
88 86 85 84 81 74 73 72 71 MEM_B_SA<1> 201 202 SMBUS_PCH_CLK
94 "Expansion" (bottom) slot
R3141 203
SA1 SCL
204
IN 6 17 25 26 28 32 34 42 48 49 64
94
1
10K 2
VTT VTT PP0V75_S0_DDRVTT 7 28 31 68
MTG PINS
5% 205 MTG PIN MTG PIN
206
1
C3140 1/16W
MF-LF 207 208
A 2.2UF
20%
6.3V
402
209
MTG PIN
MTG PIN
MTG PIN
MTG PIN
2 CERM 211 MTG PIN MTG PIN 212 PAGE TITLE
402-LF
DDR3 SO-DIMM Connector B
DRAWING NUMBER SIZE
516s0806
Apple Inc. D
SPD ADDR=0xA4(WR)/0xA5(RD) REVISION
R

31 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. D
D WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
1V5 S0 "PGOOD" for CPU
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L 99 86 84 74 73 72 58 51 50 49 35 7 6PP3V3_S5
101
74 73 47 46 43 18 IN PM_SLP_S4_L PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

CPUMEM_S0
1 PPCPUDDR_ISNS PM_MEM_PWRGD
R3205 57 16 13 7 OUT 10 18 91
10K 1
R3222
5%
1/16W 10K
MF-LF 5%
2 402 1/16W CRITICAL 6
MF-LF
P1V5CPU_EN 2 402 D Q3220
OUT 73
R32201
27.4K DMB53D0UV
55 54 51 50 49 36 35 34 33 32 20 17 7 6 PP3V3_S3 CPUMEM_S0 1% SOT-563
103 102 88 74 72 56 1/16W
CPUMEM_S0 Q3205 D 6 MF-LF
402 2
PM_MEM_PWRGD_L 2 G
R32011 SSM6N15FEAPE
SOT563
100K
5% 3 CRITICAL
1/16W
MF-LF
402 2 2 G S 1 P1V5_S0_DIV 5 Q3220 S
DMB53D0UV 1
P1V5CPU_EN_L SOT-563
4
NO STUFF
CPUMEM_S0
D 3 D
CPUMEM_S0 R32211 C3220 1
Q3200 3
Q3205 33.2K
1% 0.001UF
SSM6N15FEAPE SSM6N15FEAPE 20%
C SOT563 SOT563
1/16W
MF-LF
402 2
50V
CERM 2
402
C
5 G S 4 4 S G 5
25 20 IN ISOLATE_CPU_MEM_L PM_SLP_S3_L IN 6 18 46 74 86
CPUMEM_S0
1
R3210
10K
5%
1/16W
MF-LF
2 402
MEMVTT_EN OUT 8 31 68
PP5V_S3
83 73 68 55 51 47 45 44 43 33 31 7 6
103
CPUMEM_S0 CPUMEM_S0
CPUMEM_S0
Q3210 D 6
MEMVTT Clamp
1 1 SSM6N15FEAPE Ensures CKE signals are held low in S3
R3215 R3202 SOT563
100K 100K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2 2 G S 1 68 30 28 7 PP0V75_S0_DDRVTT
MEMVTT_EN_L CPUMEM_S0
R32501
CPUMEM_S0 CPUMEM_S0 10 75mA max load @ 0.75V
CPUMEM_S0 D 6 D 5%
Q3215 Q3200 3
Q3210 1/10W
MF-LF
60mW max power
SSM6N15FEAPE SSM6N15FEAPE 603 2
SSM6N15FEAPE SOT563 SOT563
VTTCLAMP_L
G 2
SOT563
2 G S 1 4 S G 5 83 73 68 55 51 47 45 44 43 33 31 7 6 PP5V_S3 CPUMEM_S0
103
Q3250 D 6
B CPUMEM_S0 B
D
PLT_RESET_L IN 19 27 40
SSM6N15FEAPE
R32511
6
SOT563
100K
5%
1/16W
MF-LF
402 2 2 G S 1
PP1V5_S3 7 28 30 68 73
CPUMEM_S0 VTTCLAMP_EN
CPUMEM_S0
Q3215 1
SSM6N15FEAPE R3216 CPUMEM_S0
NO STUFF
MEMRESET_ISOL_LS5V_L
20K Q3250 D 3
C3251 1
5
SOT563 5% SSM6N15FEAPE
1/16W
G
MF-LF SOT563 0.001UF

20%
2 402 50V
CERM 2
S
31 10 CPU_MEM_RESET_L CPU_MEM_RESET_L MEM_RESET_L 28 30

402
IN OUT
MAKE_BASE=TRUE 5 G S 4
3
4
68 31 8 IN MEMVTT_EN
CPUMEM_S3
R3217
1
0 2
5%
1/16W
MF-LF
402
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

S0 0 1 1 1 1 1 CPU_MEM_RESET_L 1 1
1 0 1 1 1 1 1 1 1
to 2 0 0 1 1 1 1 0 1
3 0 0 0 1 X 1 0 0
A S3 4 0 0 1 1 X 1 0 1
PAGE TITLE
to 5
6
0
0
1
1
1
1
1
1
0 (*)
1
1
1
1
1
1
1
CPU Memory S3 Support
DRAWING NUMBER SIZE
S0 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
Apple Inc. D
REVISION
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO. R

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 THE INFORMATION CONTAINED HEREIN IS THE
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 32 OF 132
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Must not enable more than two SO-DIMM margining
50 49 36 35 34 33 31 20 17 7 6 PP3V3_S3 buffers at once or VRef source may be overloaded.
103 102 88 74 72 56 55 54 51
VREFMRGN
OMIT
R3318 68 7 6 PPVTTDDR_S3 R3303
200 PLACE_NEAR=J2900.1:2.54mm
SHORT2 10mA max load 1 2
1 PP3V3_S3_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm 1%
NONE MIN_NECK_WIDTH=0.2 mm VREFMRGN VREFMRGN 1/16W
NONE VOLTAGE=3.3V MF-LF
NONE
402
C3300 1 1 C3301 VREFMRGN
VREFMRGN
402
PP0V75_S3_MEM_VREFDQ_A
2.2UF 0.1UF CRITICAL C3303 1 VREFMRGN MIN_LINE_WIDTH=0.3 mm
28
20% 20%
0.1UF
B1 U3302 MIN_NECK_WIDTH=0.2 mm
D
6.3V 2
CERM
402-LF
10V
2 CERM
402
VREFMRGN
U3300
20%
10V
CERM 2
A2
V+
MAX4253
UCSP
A1
R3304
133
VOLTAGE=0.75V
D
8
402 VREFMRGN_DQ_SODIMMA_BUF 1 2
VDD 1%
A3 A4 PLACE_NEAR=R3303.2:1mm
48 42 34 32 30 28 26 25 17 6 IN SMBUS_PCH_CLK 6 SCL
MSOP VOUTA
1 VREFMRGN_SODIMMA_DQ V- 1/16W
94 64 49 MF-LF
B4 402
DAC5574
48 42 34 32 30 28 26 25 17 6 BI SMBUS_PCH_DATA 7 SDA VOUTB 2 VREFMRGN_SODIMMB_DQ
94 64 49
9 A0 VOUTC 4 VREFMRGN_SODIMMS_CA
Addr=0x98(WR)/0x99(RD) 10 A1 VREFMRGN_MEMVREG_FBVREF
VOUTD 5 VREFMRGN
NOTE: MEMVREG and FRAMEBUF share R3305
GND
1
200 2 PLACE_NEAR=J3100.1:2.54mm
3 a DAC output, cannot enable VREFMRGN
both at the same time! 1
R3301 1%
1/16W
100K MF-LF
402
5%
1/16W VREFMRGN PP0V75_S3_MEM_VREFDQ_B 30
MF-LF B1 U3302 VREFMRGN MIN_LINE_WIDTH=0.3 mm
2 402 C2 MIN_NECK_WIDTH=0.2 mm
V+
MAX4253 R3306 VOLTAGE=0.75V
UCSP
OMIT C1 VREFMRGN_DQ_SODIMMB_BUF 1
133 2
R3319 C3 C4 1% PLACE_NEAR=R3305.2:1mm
SHORT2 V- 1/16W
1 PP3V3_S3_VREFMRGN_CTRL B4
MF-LF
MIN_LINE_WIDTH=0.3 mm 402
NONE MIN_NECK_WIDTH=0.2 mm
NONE
NONE
VOLTAGE=3.3V CRITICAL
VREFMRGN
16
402 VREFMRGN VREFMRGN
C3302 1 VREFMRGN
0.1UF
20%
VCC R3309
1
R3302 200 PLACE_NEAR=J2900.126:2.54mm
10V
CERM 2 U3301 100K
1 2
402 PCA9557 5% 1%
QFN 1/16W 1/16W
(OD) P0 6 NC MF-LF MF-LF
3 A0 VREFMRGN_DQ_SODIMMA_EN 2 402 VREFMRGN 402
PP0V75_S3_MEM_VREFCA_A
P1 7 VREFMRGN
C3304 1 VREFMRGN
28
C
C Addr=0x30(WR)/0x31(RD) 4 A1
5 A2
P2 9
P3 10
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
0.1UF
20%
A2
B1
V+
U3303
MAX4253
UCSP R3310
VOLTAGE=0.75V
10V 133
P4 11 VREFMRGN_CA_SODIMMB_EN CERM 2 A1 VREFMRGN_CA_SODIMMA_BUF 1 2
402
P5 12 VREFMRGN_MEMVREG_EN A3 A4 1% PLACE_NEAR=R3309.2:1mm
V- 1/16W
48 42 34 32 30 28 26 25 17 6 IN SMBUS_PCH_CLK 1 SCL P6 13 VREFMRGN_FRAMEBUF_EN MF-LF
94 64 49 B4 402
48 42 34 32 30 28 26 25 17 6
94 64 49 BI SMBUS_PCH_DATA 2 SDA P7 14 NC
THRM RESET* 15 VREFMRGN
PAD GND
R3311
17
8
1
200 2
PLACE_NEAR=J3100.126:2.54mm
1%
VREFMRGN 1/16W
MF-LF
1
R3307 VREFMRGN
402
PP0V75_S3_MEM_VREFCA_B 30
100K VREFMRGN MIN_LINE_WIDTH=0.3 mm
PCA9557D_RESET_L 5% C2
B1 U3303 MIN_NECK_WIDTH=0.2 mm
27 IN 1/16W
MF-LF V+
MAX4253
UCSP R3312 VOLTAGE=0.75V
2 402 C1 VREFMRGN_CA_SODIMMB_BUF 1
133 2
RST* on ’platform reset’ so that system
watchdog will disable margining. C3 C4 1%
1/16W
PLACE_NEAR=R3311.2:1mm
V- MF-LF
NOTE: Margining will be disabled across all B4 402
soft-resets and sleep/wake cycles.
VREFMRGN
Required zero ohm resistors when no VREF margining circuit stuffed 1
R3308 VREFMRGN
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 100K
5%
1/16W
C3305 1 VREFMRGN
116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3303,R3305 VREFMRGN_NOT 0.1UF VREFMRGN
MF-LF
2 402
20%
10V C2
B1 U3304
CERM 2 MAX4253 R3314
116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3309,R3311 VREFMRGN_NOT 402 V+ UCSP
B C1 VREFMRGN_MEMVREG_BUF
22.6K2
1 DDRREG_FB OUT 68 B
C4 1% PLACE_NEAR=R7320.2:1mm
C3 1/16W
V- MF-LF
B4 402
Page Notes VREFMRGN

1
VREFMRGN
R3316
Power aliases required by this page: R3313 49.9 2
VREFMRGN 1 GPU_FB_A_VREF_DIV OUT 8 78
- =PP3V3_S3_VREFMRGN 100K B1 U3304
5% 1% PLACE_NEAR=R0900.2:1mm
- =PPVTT_S3_DDR_BUF 1/16W A2 MAX4253 1/16W
MF-LF V+ UCSP MF-LF
402
Signal aliases required by this page: 2 402 A1 VREFMRGN_FRAMEBUF_BUF
VREFMRGN
- =I2C_VREFDACS_SCL A3 A4
- =I2C_VREFDACS_SDA V- R3317
B4 49.9 2
- =I2C_PCA9557D_SCL 1 GPU_FB_B_VREF_DIV OUT 8 79
- =I2C_PCA9557D_SDA 1%
1/16W
PLACE_NEAR=R0901.2:1mm
MF-LF
BOM options provided by this page: VREFMRGN 402
VREFMRGN - Stuffs VREF Margining 1
R3315
Circuitry. 100K
5%
VREFMRGN_NOT - Bypasses VREF Margining 1/16W
MF-LF
Circuitry. 2 402
A MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG GPU Frame Buffer (1.8V, 70% VRef) SYNC_MASTER=K17_WFERRY SYNC_DATE=06/09/2009 A
PAGE TITLE
DAC Channel: A B C C D D FSB/DDR3/FRAMEBUF Vref Margining

DRAWING NUMBER SIZE
PCA9557D Pin: 1 2 3 4 5 6 Apple Inc. D
REVISION
Nominal value 0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A) 1.267V (DAC: 0x8B) R
Margined target: 0.300V - 1.200V (+/- 450mV) 1.998V - 1.002V (+/- 498mV) 1.056V - 1.442V (+/- 180mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH
DAC range: 0.000V - 1.501V (0x00 - 0x74) 0.000V - 1.501V (0x00 - 0x74) 0.000V - 3.300V (0x00 - 0xFF) PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
VRef current: +3.4mA - -3.4mA (- = sourced) +33uA - -33uA (- = sourced) +6.0mA - -5.0mA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
33 OF 132
SHEET
DAC step size: 7.69mV / step @ output 8.59mV / step @ output 1.51mV / step @ output III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP_PWR_EN IN 20 74
D 3V S3 WLAN FET D
25 17 OUT AP_CLKREQ_L MOSFET TPCP8102
CHANNEL P-TYPE
6 D Q3401
SSM6N15FEAPE RDS(ON) 20-30 MOHM @2.5V
SOT563
LOADING 0.727 A (EDP)
1
S G 2
6 AP_CLKREQ_Q_L CRITICAL
CRITICAL Q3450
TPCP8102
155S0367 R3452
0.002 23V1K-SM
727 MA PEAK
L3404 MIN_LINE_WIDTH=1 mm
1%
5 6 7 8
MIN_NECK_WIDTH=0.5 mm MIN_LINE_WIDTH=1 mm
FERR-120-OHM-3A 1/4W MIN_NECK_WIDTH=0.5
1 2 3
PLACEMENT_NOTE=Place close to J3401. 606 MA NOMINAL MAX MF mm
C3431 PP3V3_WLAN 1 1206
S
102 103
D
6
94 6 PCIE_AP_R2D_P 1 2 0.1uF PCIE_AP_R2D_C_P 17 94
2 57 33 PP3V3_WLAN_F 1 2 PP3V3_S3 49 50 51 54 55 56
6 7 17 20
IN 31 32 33 34 35 36
MIN_LINE_WIDTH=1 mm
94 6 PCIE_AP_R2D_N 1 2 0.1uF 10% 16V X5R 402 PCIE_AP_R2D_C_N IN 17 94 MIN_NECK_WIDTH=0.5 mm 0603 3 4 72 74 88
PP3V3_WLAN_R
4G
10% 16V X5R 402 1
C3422 1
C3421 1 1
C3420 C3451 1 R3451
C3430 10K
516S0582 PLACEMENT_NOTE=Place close to J3401. 0.1uF
20%
0.1uF
20%
10UF
20%
0.033UF
10%
5%
1/16W
10V 10V 10V 16V
2 2 2 2 MF-LF
CRITICAL CERM CERM X5R C3450 X5R
402 402 805
0.1UF 402 R3450 2
402
J3401
500913-0302
PLACEMENT_NOTE=Place close to J3401. PLACEMENT_NOTE=Place close to Q3450. 1 2 P3V3WLAN_SS 1
33K
2 PM_WLAN_EN_L IN 74
32
F-ST-SM
31
PCIE_AP_D2R_P
PCIE_AP_D2R_N
OUT
OUT
6 17 94
6 17 94
CRITICAL
L3401 AIRPORT 10%
16V
5%
1/16W
MF-LF
C 90-OHM-100MA
DLP11S
SYM_VER-1
PLACEMENT_NOTE=Place close to Q3450. X5R
402
402
C
2 1 4 3 PCIE_CLK100M_AP_P 17 94
IN
4 3 99 6 PCIE_CLK100M_AP_CONN_P
6 5 ISNS_AIRPORT_P
99 6 PCIE_CLK100M_AP_CONN_N
8 7
1 2 PCIE_CLK100M_AP_N IN 17 94
OUT 57 99
OUT 57 99
10 PLACEMENT_NOTE=Place close to J3401.
9 ISNS_AIRPORT_N
12 11
NC
14 13
NC
16 15 L3403
18
20
17
19
BLUETOOTH 90-OHM
DLP0NS
SYM_VER-1
CRITICAL
PLACE_NEAR=J3401.21:2.54MM
22 21 99 6 CONN_USB2_BT_P
4 3 USB_BT_P BI 36 93
24 23 99 6 CONN_USB2_BT_N
26 25 1 2 USB_BT_N BI 36 93
28 27 6 PP3V3_S3_BT_F PLACEMENT_NOTE=Place close to J3401.
30 29 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
L3406
1 C3432
2 1 PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54
34 33 0.01UF 55 56 72 74 88 102 103
10%
2 16V FERR-120-OHM-1.5A
CERM 0402-LF
402
PLACEMENT_NOTE=PLACE L3406 NEAR J3401.
PLACEMENT_NOTE=PLACE C3432 NEAR J3401
B RC (R3453 AND C3453)VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN B
3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET
PP3V3_WLAN_F 33 57
PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54
1
55 56 72 74 88 102 103
PCIE_WAKE_L 6 18 27 34
R3453
OUT 110K
5%
U3402
74LVC1G17 5
1/16W
MF-LF
402
2
TC7SZ08AFEAPE 5 SOT353-1
SOT665
A
2 WLAN_SMIT_BUF 4 2 R3455
1
6 AP_RESET_CONN_L 4
U3401
Y NC WLAN_SMIT_RC 1 2 WLAN_SMIT_DISCHRG
1 5%
B
3 1 1/16W
MF-LF
CRITICAL 3 NC 1 402 3 D Q3401
C3453 1 R3454
62K SSM6N15FEAPE
J3402 518S0767 AP_RESET_L IN 27
1UF
10%
6.3V
5% NOSTUFF
1/16W
SOT563
819Q-3506-K281 CERM
402
2
2
MF-LF
402
F-RT-SM S G 5
4
8
6 6 PP5V_S3_ALSCAMERA_F
5 SMBUS_SMC_A_S3_SCL 6 46 49 55 97 MIN_LINE_WIDTH=0.5 mm
IN
4 SMBUS_SMC_A_S3_SDA 275 mA peak
BI 6 46 49 55 97 MIN_NECK_WIDTH=0.25 mm
3 99 6 USB_CAMERA_CONN_P
206 mA nominal max
A
2
1
99 6 USB_CAMERA_CONN_N ALS L3408
FERR-120-OHM-1.5A
PLACEMENT_NOTE=Place close to J3402
2 1 PP5V_S3 6 7 31 43 44 45 47 51 55 68 73 83 103
PAGE TITLE
7 CRITICAL
L3407
CAMERA 1 C3452
0402-LF
X16/ALS/CAMERA CONNECTOR
DRAWING NUMBER SIZE
90-OHM
DLP0NS PLACE_NEAR=J3402.6:2.54MM 0.1uF D
SYM_VER-1 20%
10V
2 CERM
Apple Inc. REVISION
4 3 USB_CAMERA_P BI 35 93 402 R

1 2 USB_CAMERA_N BI 35 93 THE INFORMATION CONTAINED HEREIN IS THE
PLACEMENT_NOTE=Place close to J3402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
34 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
EXPRESSCARD/34 FLEX CONNECTOR
L3502
90-OHM
DLP0NS
SYM_VER-1
CRITICAL
93 36 34 8 BI USB_EXCARD_N USB_EXCARD_N
MAKE_BASE=TRUE
4 3 USB2_EXCARD_CONN_N 6 34 99 J3500
502250-8627
F-RT-SM
29
93 36 34 8 BI USB_EXCARD_P USB_EXCARD_P 1 2 USB2_EXCARD_CONN_P 6 34 99
INPUT DECOUPLING MAKE_BASE=TRUE
PLACE_NEAR=J3500.3:4mm 27
26
24
25 PCIE_EXCARD_R2D_P 6 34 94
88 74 72 56 55
32 31 20 17 7 6
54 51 50 49 36 35 34 33
PP3V3_S3 L3503
90-OHM-100MA 94 17 6
94 34 6
OUT
PCIE_EXCARD_R2D_N
PCIE_EXCARD_D2R_P 22
23
103 102 DLP11S 21 PCIE_EXCARD_D2R_N
1 C3530 1 C3531 SYM_VER-1 20
19 PCIE_CLK100M_EXCARD_CONN_P
OUT 6 17 94
0.1uF 10uF 94 17 IN PCIE_CLK100M_EXCARD_N 4 3 PCIE_CLK100M_EXCARD_CONN_N 6 34 99 99 34 6 PCIE_CLK100M_EXCARD_CONN_N 18 6 34 99

20% 20% 17 EXCARD_CPPE_L 6 34
10V
2 CERM 6.3V
2 X5R 34 6 EXCARD_CLKREQ_CONN_L 16
15 PP3V3_S0_EXCARD_SWITCH 6 34
402 603 34 6 PP3V3_S0_EXCARD_SWITCH 14
94 17 IN PCIE_CLK100M_EXCARD_P 1 2 PCIE_CLK100M_EXCARD_CONN_P 6 34 99
13 PLT_RESET_SWITCH_L 6 34
34 6 PP3V3_S3_EXCARD_SWITCH 12
PLACE_NEAR=J3500.19:4mm 11 PCIE_WAKE_L 6 18 27 33
PP1V5_S0_EXCARD_SWITCH 10 OUT
34 6
9 PP1V5_S0_EXCARD_SWITCH 6 34
PLACE_NEAR=J3500.24:4mm 49 48 42 32 30 28 26 25 17 6 SMBUS_PCH_DATA 8
PP1V5_S0 94 64
BI 7 SMBUS_PCH_CLK
99 74 72 59 42 34 7 BI 6 17 25 26 28 30 32 42 48 49 64
6
C3571 NC 5
NC
94
1 C3534 1 C3535 94 17 IN PCIE_EXCARD_R2D_C_N 1 2 0.1uF PCIE_EXCARD_R2D_N 6 34 94 34 6 EXCARD_CPUSB_L 4

3 USB2_EXCARD_CONN_P
0.1uF 10uF 94 17 IN PCIE_EXCARD_R2D_C_P 1 2 0.1uF 10% 16V X5R 402 PCIE_EXCARD_R2D_P 6 34 94 99 34 6 USB2_EXCARD_CONN_N 2 6 34 99
20% 20% 1
10V
2 CERM 6.3V
2 X5R 10% 16V X5R 402
402 603 C3570 28
C PLACE_NEAR=J3500.25:4mm C
518S0647
OMIT
54 51 50 49 36 35 34 33 32 31 20 17 7 6 PP3V3_S3 R3504
103 102 88 74 72 56 55 SHORT2
1 PP3V3_S3_EXCARD_R
MIN_LINE_WIDTH=0.5mm
NONE MIN_NECK_WIDTH=0.25mm
NONE VOLTAGE=3.3V
NONE
402
OMIT
101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 R3503
74 73 72 71 70 69 64 63 59 55 53 52 49 SHORT2
1 PP3V3_S0_EXCARD_R
OUTPUT DECOUPLING
NONE MIN_NECK_WIDTH=0.2mm
NONE VOLTAGE=3.3V
NONE PP3V3_S3_EXCARD_SWITCH 6 34
402 VOLTAGE=3.3V
MIN_LINE_WIDTH=.3mm
OMIT MIN_NECK_WIDTH=0.2mm
1 C3500 1 C3503
CRITICAL 0.1uF 10uF
99 74 72 59 42 34 7 PP1V5_S0 R3502 20%
10V
20%
SHORT2 U3500 2 CERM 2 6.3V
X5R
1 PP1V5_S0_EXCARD_R 402 603
NONE
MIN_NECK_WIDTH=0.2mm
TPS2231
NONE VOLTAGE=1.5V 17 AUXIN QFN AUXOUT 15
NONE
402 2 VIN3P3 VOUT3P3 3
VOLTAGE=3.3V PP3V3_S0_EXCARD_SWITCH 6 34
12 VIN1P5 VOUT1P5 11 MIN_LINE_WIDTH=.6mm
SMC_EXCARD
SMC_EXCARD_PWR_EN R3500 01 2 5% EXCARD_SHDN_L_R 20 SHDN* PERST* 8
1 C3501 1 C3504
0.1uF 10uF
(IPU)
46 IN MF-LF 402 1/16W

B 27 IN
TP_EXCARD_STBY_L
EXCARD_RESET_L
1
6
STBY*
SYSRST*
CPPE*
CPUSB*
10
9
10%
16V
2 X5R
402
20%
2 6.3V
X5R
603
B
47 36 8 IN EXCARD_OC_L 19 OC* (IPU)
NC 4 NC0 RCLKEN 18 EXCARD_RCLKEN 34

(IPU) PP1V5_S0_EXCARD_SWITCH 6 34
NC 5 NC1 VOLTAGE=1.5V
MIN_LINE_WIDTH=.6mm
NC 13 NC2 MIN_NECK_WIDTH=0.11mm
1 C3502 1 C3505
0.1uF 10uF
NC 14 NC3 10% 20%
NC 16 NC4 THRML_PAD 21 2 16V
X5R 2 6.3V
X5R
GND 402 603
7
All pull-ups to AUXIN rail PLT_RESET_SWITCH_L 6 34
EXCARD_CPPE_L 6 34
54 51 50 49 36 35 34 33 32 31 20 17 7 6 PP3V3_S3 EXCARD_CPUSB_L 6 34
103 102 88 74 72 56 55
SMC_EXCARD_NOT
C3550 1
0.1uF
20%
R35501
10V 0
CERM 2 5%
1/16W SMC_EXCARD
402 MF-LF
5
34 6 EXCARD_CPUSB_L 1 74HC1G00GWDG
SC70-5
402 2 R3551
0
U3551 4 EXCARD_CP 1 2 SMC_EXCARD_CP OUT 46 47
34 6 EXCARD_CPPE_L 2 5%
1/16W 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0
MF-LF 74 73 72 71 70 69 64 63 59 55 53 52 49
3 402
5
A 34 EXCARD_RCLKEN 1 74HC1G00GWDG
SC70-5
EXCARD_CLKREQ_L SYNC_MASTER=K17_WFERRY SYNC_DATE=06/09/2009 A
1 EXCARD_CLKREQ_CONN 2
U3560 4 OUT 17
PAGE TITLE
R3561
100K 3
ExpressCard Connector
1% DRAWING NUMBER SIZE
1/16W
MF-LF
402 2 A2 U3561 C3560 1 Apple Inc. D
SN74LVC1G04YZPR 0.1uF REVISION
R
34 6 EXCARD_CLKREQ_CONN_L B1 C2 20%
10V
BGA CERM 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
C1 402
35 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
54 51 50 49 36 35 34 33 32 31 20 17 7 6 PP3V3_S3
103 102 88 74 72 56 55
USB HUB-1 99 86 84 74 73 72 58 51 50 49 31 7 6PP3V3_S5

101
R3640
20K
5%
1/16W
MF-LF
402
1
1
R3641
R3642 10K
NOSTUFF 5%
100K
5%
1/16W
1 C3641
100PF
1/16W
MF-LF
2402
MF-LF 5%
2 402 50V
2 CERM
402 USB_HUB_RESET
D L3658
FERR-120-OHM-1.5A 6
USB_HUB_RESET_L D
3
103 102 88 74 72
34 33 32 31 20 17 7 6PP3V3_S3 1 2 PPUSB_HUB1_VDDPLL3V3 D
56 55 54 51 50 49 36 35
0402 MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM Q3640 D
Q3640
VOLTAGE=3.3V 2N7002DW-X-G
P3V3S3_EN_RC 2 2N7002DW-X-G
1 C3636
0.01UF
1 C3637
100PF
1 C3638
10UF
1 C3639
0.1UF
PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54
55 56 72 74 88 102 103
G S SOT-363 5 G S SOT-363
10% 5% 20% 10% 1
2 16V
CERM
402
2 50V
CERM
402
2 6.3V
X5R
603
16V
2 X7R-CERM
402
1 C3623
0.1UF
1 C3625
0.1UF
C3626
0.01UF
C3629
1
0.01UF
1 1 C3640
0.47UF
4
10% 10% 10% 10% 10%

16V
2 X7R-CERM 16V
2 X7R-CERM 16V
2 CERM 2 16V 2 6.3V
CERM CERM-X5R
402 402 402 402 402
1 C3618
10UF
20%
6.3V
L3629
FERR-120-OHM-1.5A MIN_LINE_WIDTH=0.4MM
2 X5R
603 1 2 VOLTAGE=3.3V
PPUSB_HUB1_VDDA3V3
0402 PPUSB_HUB1_VDD1V8
1 C3642
0.01UF
1 C3643
100PF
1 C3644
10UF
1 C3645
0.1UF
1 C3646
0.1UF
1 C3647
0.1UF
VOLTAGE=1.8V
10% 5% 20% 10% 10% 10% PPUSB_HUB1_VDD1V8PLL
2 16V
CERM
402
50V
2 CERM
402
6.3V
2 X5R
603
2 16V
X7R-CERM
402
2 16V
X7R-CERM
402
2 16V
X7R-CERM
402
1 C3628
0.1UF
1 C3630
1UF
VOLTAGE=1.8V 1 C3624
0.1UF
1 C3627
1UF
10%
16V
2 X7R-CERM
10%
2 16V
X5R
10% 10% 402 402
16V
2 X7R-CERM 2 16V
X5R D3645
402 402 SOD-523
54 51 50 49 36 35 34 33 32 31 20 17 7 6
103 102 88 74 72 56 55
PP3V3_S3 25 19 IN USB_HUB_SOFT_RESET_L 2 1
BAT54XV2T1
29
10
VDD33PLL 36
VDD33CR 15
VDD33 23
VDD18 14
VDD18PLL 34
5
NOSTUFF HUB1_NONREM0_1
C CRITICAL
R3697 1
R3699
1
VDDA33
C
Y3600 10K 5%
10K
5%
24.000M-60PPM-16PF 1/16W 1/16W
1 2 MF-LF MF-LF
CRITICAL CRITICAL 4022 2402
5X3.2X1.4-SM
C3619 1 1 C3620 U3600
18PF 5%
R3691
1M 5%
18PF QFN
50V 1 2 50V USX2061
CERM 2 2 CERM USB_HUB1_TEST 11 TEST USBDN1_DM/PRT_DIS_M1 1 USB_CAMERA_N
402 5% 402 BI 33 93
Camera
1/16W OMIT USBDN1_DP/PRT_DIS_P1 2 USB_CAMERA_P BI 33 93
MF-LF 36 35 USB_HUB_RESET_L 26 RESET*
402 3
33 USBDN2_DM/PRT_DIS_M2 USB_IR_N BI 45 93
CRITICAL USB_HUB1_XTAL1 XTAL1/CLKIN 4 IR Receiver
32 USBDN2_DP/PRT_DIS_P2 USB_IR_P BI 45 93
USB_HUB1_XTAL2 XTAL2
USBDN3_DM/PRT_DOS_M3 6 USB_EXTB_N 43 93
USB_HUB1_LOCAL_PWR 28 BI
SUSP_IND/LOCAL_PWR/NON_REM0 7 USB_EXTB_P External B
USBDN3_DP/PRT_DIS_P3 BI 43 93
USB_HUB1_SMBDATA 22 SDA/SMBDATA/NON_REM1
USBDN4_DM/PRT_DIS_M4 8 USB_EXTC_N 44 93
PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54
BI 55 56 72 74 88 102 103
USB_HUB1_SMBCLK 24 9 USB_EXTC_P External C
SCL/SMBCLK/CFG_SEL0 USBDN4_DP/PRT_DIS_P4 BI 44 93
103 102 88 74 72 USB_HUB1_CFG_SEL1 25 HS_IND/CFG_SEL1 PRTPWR1 12 TP_USB_HUB1_PRTPWR1

50 49 36 35
20 17 7 6 PP3V3_S3 16
34 33 32 31
56 55 54 51 PRTPWR2 NC_USB_HUB1_PRTPWR2
HUB1_NONREM1_1 NOSTUFF PRTPWR3 18 NC_USB_HUB1_PRTPWR3
C3634 R36921
1
R3694 1
R3698
10K PRTPWR4 20 NC_USB_HUB1_PRTPWR4 R36821
R36041 1
0.1UF 4 NOSTUFF 10K 10K
5% 5% 13
10K
5%
10K 10% VCC
5%
1/16W 1/16W 1/16W IPU OCS1* TP_USB_HUB1_OCS1 1/16W
5% MF-LF MF-LF MF-LF
1/16W 2 16V
X5R U3614 MF-LF
4022 2402 2402 IPU OCS2* 17 NC_USB_HUB1_OCS2 4022
MF-LF 402
4022 AT24C02B OCS3* 19 USB_EXTB_OC_L
SOT23-5 IPU IN 43
SDA 3 OCS4* 21 USB_EXTC_OC_L

WP_HUB1 5 WP IPU IN 8 44
SCL 1
B GND
RBIAS 35 USB_HUB1_RBIAS B
VBUS_DET 27 USB_HUB1_VBUS_DET
2 HUB1_NONREM1_0
HUB1_NONREM0_0
30 USB_HUB1_UP_N
R3665
1
10K
1
R3666 1
R3667 1
R3668 USBUP_DM
USBUP_DP 31 USB_HUB1_UP_P
BI 19 93
CRITICAL
5% 10K
5%
10K 5%
100
5%
BI 19 93
1
R3600
1/16W 1/16W 1/16W 1/16W THRML_PAD 12K
MF-LF MF-LF MF-LF MF-LF
37
1%
2402 2402 2402 2 402 1/16W
MF
2 402
SEL1 SEL0 DESCRIPTION

0 0 Internal Default with Self powered Operation
0 1 SMBUS Slave Config
1 0 Internal Default with Bus powered Operation
1 1 EEPROM Supported
BOM TABLE TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM
338S0720 2 IC,ASSP,USB2.0,HUB CNTROL,4 PRT,36QFN U3600,U3700 CRITICAL USBHUB_2514

TABLE_5_ITEM
A 338S0824 2 IC,USB2514B,USB 2.0,HUB CNTRL,4 PRT,36QFN U3600,U3700 CRITICAL
CRITICAL
USBHUB_2514B
TABLE_5_ITEM SYNC_MASTER=K18_MLB SYNC_DATE=10/07/2009 A
338S0721 2 IC,USX2061,USB 2.0,HUB CNTRL,4 PRT,36QFN U3600,U3700 USBHUB_2061 PAGE TITLE
NON_REM1
0 0
NON_REM0 DESCRIPTION
All ports are Non removable TABLE_BOMGROUP_HEAD
USB HUB 1 DRAWING NUMBER SIZE
0 1 Port 1 is non removable BOM GROUP BOM OPTIONS D
1 0 Port 1 and 2 are non removable TABLE_BOMGROUP_ITEM Apple Inc. REVISION
HUB1_ALLREM HUB1_NONREM1_0,HUB1_NONREM0_0
1 1 Port 1, 2 and 3 are non Removable TABLE_BOMGROUP_ITEM
R
HUB1_1NONREM HUB1_NONREM1_0,HUB1_NONREM0_1 NOTICE OF PROPRIETARY PROPERTY: BRANCH

TABLE_BOMGROUP_ITEM
HUB1_2NONREM HUB1_NONREM1_1,HUB1_NONREM0_0 THE INFORMATION CONTAINED HEREIN IS THE

TABLE_BOMGROUP_ITEM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
HUB1_3NONREM HUB1_NONREM1_1,HUB1_NONREM0_1 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
36 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
USB HUB-2
D D
FERR-120-OHM-1.5A
L3758
54 51 50 49 36 35 34 33 32 31 20 17 7 6PP3V3_S3 1 2 PPUSB_HUB2_VDDPLL3V3
103 102 88 74 72 56 55
VOLTAGE=3.3V
1 C3736
0.01UF
1 C3737
100PF
1 C3738
10UF
1 C3739
0.1UF
PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54
55 56 72 74 88 102 103
10% 5% 20% 10%

2 16V
CERM
402
2 50V
CERM
402
6.3V
2 X5R
603
16V
2 X7R-CERM
402
1 C3723
0.1UF
1 C3725
0.1UF
C3726
0.01UF
C3729
1
0.01UF
1
10% 10% 10% 10%
2 16V
X7R-CERM 2 16V
X7R-CERM
16V
2 CERM 16V
2 CERM
402 402 402 402
1 C3718
10UF
20%
6.3V
L3729
FERR-120-OHM-1.5A VOLTAGE=3.3V
2 X5R MIN_LINE_WIDTH=0.4MM
603 1 2 MIN_NECK_WIDTH=0.2MM PPUSB_HUB2_VDDA3V3
0402 PPUSB_HUB2_VDD1V8
1 C3742
0.01UF
1 C3743
100PF
1 C3744
10UF
1 C3745
0.1UF
1 C3746
0.1UF
1 C3747
0.1UF
VOLTAGE=1.8V
10%
2 16V
CERM
5%
50V
2 CERM
20%
2 6.3V
X5R
10%
2 16V
X7R-CERM
10%
16V
2 X7R-CERM
10%
2 16V
X7R-CERM
PPUSB_HUB2_VDD1V8PLL
1 C3728
0.1UF
1 C3730
1UF
402 402 603 402 402 402 MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
1 C3724
0.1UF
1 C3727
1UF
10%
2 16V
X7R-CERM
10%
2 16V
X5R
10% 10% 402 402
16V
2 X7R-CERM 2 16V
X5R
402 402
54 51 50 49 36 35 34 33 32 31 20 17 7 6 PP3V3_S3
103 102 88 74 72 56 55
C C
29
10
VDD33PLL 36
VDD33CR 15
VDD33 23
VDD18 14
VDD18PLL 34
5
NOSTUFF HUB2_NONREM0_1
CRITICAL
Y3700
R3797
10K
1 1
R3799
10K
VDDA33
24.000M-60PPM-16PF 5% 5%
1 2 1/16W 1/16W
MF-LF MF-LF
CRITICAL CRITICAL 4022 2 402
5X3.2X1.4-SM
C3719 1 1 C3720 U3700
18PF 5%
R3791
1M 5%
18PF QFN
50V 1 2 2 50V USX2061
CERM 2 CERM USB_HUB2_TEST 11 TEST USBDN1_DM/PRT_DIS_M1 1 USB_BT_N
402 5% 402 BI 33 93
Bluetooth
1/16W OMIT USBDN1_DP/PRT_DIS_P1 2 USB_BT_P BI 33 93
MF-LF 35 IN USB_HUB_RESET_L 26 RESET*
402 3
33 USBDN2_DM/PRT_DIS_M2 USB_TPAD_N BI 54 93
CRITICAL USB_HUB2_XTAL1 XTAL1/CLKIN 4 Trackpad/Keyboard
32 USBDN2_DP/PRT_DIS_P2 USB_TPAD_P BI 54 93
USB_HUB2_XTAL2 XTAL2
USBDN3_DM/PRT_DOS_M3 6 USB_EXCARD_N 8 34 93
USB_HUB2_LOCAL_PWR 28 BI
SUSP_IND/LOCAL_PWR/NON_REM0 7 USB_EXCARD_P SD Card/Express Card
USBDN3_DP/PRT_DIS_P3 BI 8 34 93
USB_HUB2_SMBDATA 22 SDA/SMBDATA/NON_REM1
USBDN4_DM/PRT_DIS_M4 8 USB_EXTA_N 43 93 PP3V3_S3 6 7 17 20 31 32 33 34 35 36 49 50 51 54
BI
USB_HUB2_SMBCLK 24 9 USB_EXTA_P External A 55 56 72 74 88 102 103
SCL/SMBCLK/CFG_SEL0 USBDN4_DP/PRT_DIS_P4 BI 43 93
1
USB_HUB2_CFG_SEL1 25 HS_IND/CFG_SEL1 PRTPWR1 12 TP_USB_HUB2_PRTPWR1 R3782
54 51 50 49 36 35 34 33 32 31 20 17 7 6 PP3V3_S3 16 NC_USB_HUB2_PRTPWR2
10K
103 102 88 74 72 56 55 PRTPWR2 5%
NOSTUFF 18 1/16W
HUB2_NONREM1_1 PRTPWR3 NC_USB_HUB2_PRTPWR3 MF-LF
R37921
1
R3794 1
R3798
10K PRTPWR4 20 NC_USB_HUB2_PRTPWR4 4022
R37041 4 NOSTUFF 10K 10K
5% 5% 13
10K VCC
5%
1/16W 1/16W 1/16W IPU OCS1* TP_USB_HUB2_OCS1
5% MF-LF MF-LF 17
1/16W U3714 MF-LF
4022 2402 2402 IPU OCS2* NC_USB_HUB2_OCS2
MF-LF
4022 AT24C02B OCS3* 19 EXCARD_OC_L
SOT23-5 IPU IN 8 34 47
B 1 C3734
0.1UF
WP_HUB2 5 WP
SDA 3
SCL 1
IPU OCS4* 21
35
USB_EXTA_OC_L IN 43
B
10% RBIAS USB_HUB2_RBIAS
2 16V
X5R GND
27 USB_HUB2_VBUS_DET
402 2 VBUS_DET
HUB2_NONREM1_0 HUB2_NONREM0_0 30 USB_HUB2_UP_N
USBUP_DM
1
R3765 R3766
1
10K
R3767
10K
1 1
R3768
100 USBUP_DP 31 USB_HUB2_UP_P
BI
BI
19 93
19 93
CRITICAL
1
10K
5% 5% 5% 5% THRML_PAD
R3700
1/16W 1/16W 1/16W 1/16W 12K
MF-LF MF-LF MF-LF
37
MF-LF 1%
2402 2402 2402 2 402 1/16W
MF
2 402
SEL1 SEL0 DESCRIPTION

K17/K18 configuration: 0 0 Internal Default with Self powered Operation
0 1 SMBUS Slave Config
1 0 Internal Default with Bus powered Operation
1 1 EEPROM Supported
NON_REM1 NON_REM0 DESCRIPTION

A 0 0 All ports are removable TABLE_BOMGROUP_HEAD
0 1 Port 1 is non removable BOM GROUP BOM OPTIONS PAGE TITLE
1
1
0
1
Port 1 and 2 are non removable
Port 1, 2, and 3 are non removable
HUB2_ALLREM HUB2_NONREM1_0,HUB2_NONREM0_0
TABLE_BOMGROUP_ITEM
USB HUB 2 DRAWING NUMBER SIZE

TABLE_BOMGROUP_ITEM
HUB2_1NONREM HUB2_NONREM1_0,HUB2_NONREM0_1
Apple Inc. D
TABLE_BOMGROUP_ITEM
REVISION
HUB2_2NONREM HUB2_NONREM1_1,HUB2_NONREM0_0 R
TABLE_BOMGROUP_ITEM
HUB2_3NONREM HUB2_NONREM1_1,HUB2_NONREM0_1 NOTICE OF PROPRIETARY PROPERTY: BRANCH

37 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BCM57765 SR pins are internal 1.2V switching regulator.
If unused: Okay to float all 4 pins. (Broadcom not so sure now)
If used: VDD/VDDP connect to =PP3V3_ENET_PHY (add bypassing), LX connects to inductor, VFB to =PP1V2_ENET_PHY
TP_BCM57765_SR_VDDP BCM57765_SR_LX 37
BCM57765 BCM57765_SR_VDD BCM57765_SR_VFB CRITICAL
PP3V3_ENET R3915
37 37
L3920
74 37 27 7
0 FERR-600-OHM-0.5A PP1V2_ENET 7 37 72 73
86mA (1000base-T, Caesar II) 1 2 37 BCM57765_VDDO_PIN20 1 2
MIN_LINE_WIDTH=0.4 mm PP1V2_ENET_PHY_AVDDL 396mA (1000base-T, Caesar II)
CRITICAL 5% MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.4 mm SM
L3900 1/16W
MF-LF
BCM57765 VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
FERR-600-OHM-0.5A 402
R3900 C3921 1 1 C3920
1 2 37 PP3V3_ENET_PHY_XTALVDDH 1
0 2 37 BCM57765_XTALVDDH 0.1UF 4.7UF
MIN_LINE_WIDTH=0.4 mm MIN_LINE_WIDTH=0.4 mm 10% 10%
SM MIN_NECK_WIDTH=0.2 mm 5% MIN_NECK_WIDTH=0.2 mm 16V 2 6.3V
X7R-CERM 2
D VOLTAGE=3.3V
C3900 1
0.1UF
1/16W
MF-LF
402
VOLTAGE=3.3V 402
X5R-CERM
603
CRITICAL
D
10%
16V L3925
CRITICAL X7R-CERM 2 FERR-600-OHM-0.5A
402
L3905 PP1V2_ENET_PHY_PCIEPLL
1 2
FERR-600-OHM-0.5A MIN_NECK_WIDTH=0.2 mm SM
1 2 VOLTAGE=1.2V
PP3V3_ENET_PHY_BIASVDDH
SM MIN_LINE_WIDTH=0.4 mm
C3926 1 1 C3925
VOLTAGE=3.3V 0.1UF 4.7UF
1 C3905 10%
16V
10%
2 6.3V
0.1UF X7R-CERM 2 X5R-CERM
10% 402 603
16V
2 X7R-CERM CRITICAL
CRITICAL
L3910
402 L3930
FERR-600-OHM-0.5A
FERR-600-OHM-0.5A
PP1V2_ENET_PHY_GPHYPLL 1 2
1 2 PP3V3_ENET_PHY_AVDDH MIN_LINE_WIDTH=0.4 mm
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SM
SM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V
VOLTAGE=3.3V
R3910 1 1 C3910 1 C3911 C3931 1 1 C3930
4.7K 0.1UF 0.1UF 0.1UF 4.7UF
5% 10% 10% 10% 10%
16V
2 X7R-CERM 16V
2 X7R-CERM 16V 2 6.3V
1/16W
MF-LF
X7R-CERM 2 X5R-CERM
402 2 402 402 402 603
BCM57765 BCM57765
R39401 1
R3941 C3915 1 1 C3916 C3936 1 1 C3935
4.7K 4.7K 4.7UF 0.1UF 0.1UF 10UF
42
48
BIASVDDH 37
VDDC 17
20
56
62
VDDC 14
REGCTL12 15
VDDIO 16
WAKE* 13
39
45
51
29
32
GPHY_PLLVDDL 36
VDDC 35
VDDC 61
10% 10% 10% 10%
7
5% 5% 6.3V 16V 16V
1/16W 1/16W X5R-CERM 2 2 X7R-CERM X7R-CERM 2 2 6.3V
X5R
C C
VDDIO
XTALVDDH
VDDIO
VDDIO
MF-LF MF-LF 603 402 402 805
101 99 88 86 85 84 81
PP3V3_S0
PCIE_PLLVDDL
48 47 42 40 37 34 30 28 27 26 25 8 7 6 402 2 2 402 AVDDH AVDDL
74 73 72 71 70 69 64 63 59 55 53 52 49
BCM57765
1
C3950 R3942
1K
0.1uF 5%
PCIE_ENET_D2R_N 1 2 1/16W CRITICAL
94 17 OUT MF-LF
2 402 OMIT
10%
16V C3951 37 BCM57765_VMAIN_PRSNT 58 SMB_DATA (IPD)
U3900 TRD0_P 40 ENET_MDI_P<0> 38 95 CR_BUS_PWR is not for SD Card power,
X5R BI
402 0.1uF BCM5764M ENET_MDI_N<0>
QFN-8X8 TRD0_N 41 BI 38 95 just decoupling for BCM57765 CR I/Os.
94 17 OUT PCIE_ENET_D2R_P 1 2
94 PCIE_ENET_D2R_C_N 27 PCIE_TXD_N
VERSION 2 TRD1_P 44 ENET_MDI_P<1> BI 38 95
10%
16V
94 PCIE_ENET_D2R_C_P 28 PCIE_TXD_P TRD1_N 43 ENET_MDI_N<1> BI 38 95 BCM57765 BCM57765 BCM57765
C3955 X5R
402 94 PCIE_ENET_R2D_P 33 PCIE_RXD_P TRD2_P 46 ENET_MDI_P<2> BI 38 95 C3970 1 1 C3971 1 C3972
0.1uF TRD2_N 47 ENET_MDI_N<2> BI 38 95
4.7UF 0.1UF 0.1UF
94 PCIE_ENET_R2D_N 34 PCIE_RXD_N 10% 10% 10%
PCIE_ENET_R2D_C_P 1 2 TRD3_P 50 ENET_MDI_P<3> 6.3V 16V 2 16V
94 17 IN BI 38 95
X5R-CERM 2 2 X7R-CERM X7R-CERM
94 17 PCIE_CLK100M_ENET_P 31 PCIE_REFCLK_P TRD3_N 49 ENET_MDI_N<3> 38 95
603 402 402
10% IN BI
16V C3956 94 17 IN PCIE_CLK100M_ENET_N 30 PCIE_REFCLK_N
X5R
402 0.1uF PP3V3R1V8_SW_SD_VIO
GPIO_0/SERIAL_DO 5
(IPD)
NC MIN_LINE_WIDTH=0.3 mm
94 17 IN PCIE_ENET_R2D_C_N 1 2 95 27 IN ENET_RESET_L 11 PERST* (IPD) MIN_NECK_WIDTH=0.2 mm
GPIO_1/SERIAL_DI 8 VOLTAGE=3.3V BCM57765
BCM57765 ENET_CLKREQ_L 12 CLKREQ* BCM57765_MEDIA_SENSE R3972 0 ENET_ENERGY_DET
R3943 10%
16V 17 OUT (OD) GPIO_2 9 1 2
OUT 17 37
X5R 5% 1/16W MF-LF 402
ENET_WAKE_L 1
0 2 402 BCM57765_WAKE_L 3 LINKLED* (OD)
37 27 OUT
NC 1 NC
(See note) 5%
1/16W
MF-LF 20 IN ENET_LOW_PWR 4 LOW_PWR (IPD) PCIE_VDDL 26 BCM57765_CR_CMD 37
WAKE# 402
DC0 21 NC
Must isolate from PCIe WAKE# if PHY 37 BCM57765_SMB_CLK 6 VDDC
is powered-down in S3/S5. Standard BCM57765_SMB_DATA 10 UART_MODE (IPD-BCM5764M) DC4 25
NC
N-channel FET isolation suggested. DC3 24
37 BCM5764_SCLK 66 SCLK NC
B 23
B
(IPU)
If PHY is always powered then alias BCM5764_MISO 64 DC2 NC
37 SI 22
=ENET_WAKE_L to PCIE_WAKE_L. BCM5764_MOSI 65 DC1 NC
37 SO 52
NC NC
37 BCM5764_CS_L 63 CS*
VMAIN_PRSNT 53 BCM57765_CR_DATA<5> 37
TP_BCM5764_SPD100LED_L 2 SPD100LED* VAUX_PRSNT 54 BCM57765_CR_DATA<6> 37
TP_BCM5764_TRAFFICLED_L 67 TRAFFICLED* VDDC 55 BCM57765_CR_DATA<7> 37
SMB_CLK 59 BCM57765_CE_L_MS_INS_L 37
95 27 IN BCM5764_CLK25M_XTALI 18 XTALI
ENERGY_DET 60 BCM57765_CR_LED 37
95 27 OUT BCM5764_CLK25M_XTALO 19 XTALO
57
DC5 NC
BCM5764_RDAC 38 RDAC SPD1000LED* 68 TP_BCM57765_XD_DET
THRM_PAD
PHY Non-Volatile Memory BCM5764M Support
69
1
R3965 All parts below BOMOPTIONed BCM5764M
1.24K
ROM contains MAC address, PCIe config 1% BCM5764M pin-function BCM5764M
1/16W R3980 0 1
info as well as code for Bonjour proxy. MF-LF 60-ENERGY_DET 37 BCM57765_CR_LED 2 ENET_ENERGY_DET 17 37
Required for proper PHY operation. 2 402 5% 1/16W MF-LF 402

13-WAKE* 37 BCM57765_SR_VFB R3981 0 1 2 ENET_WAKE_L (See note) 27 37
(Required ROM size TBD) 5% 1/16W MF-LF 402
74 37 27 7 PP3V3_ENET 53-VMAIN_PRSNT 37 BCM57765_CR_DATA<5> R3982 1K 1 2 PP3V3_S0 84 85 86 88 99 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49
5% 1/16W MF-LF 402 52 53 55 59 63 64 69 70 71 72 73 74 81
59-SMB_CLK 37 BCM57765_CE_L_MS_INS_L R3983 4.7K 1 2 PP3V3_ENET 7 27 37 74
R3984 4.7K 5% 1/16W MF-LF 402

58-SMB_DATA 37 BCM57765_VMAIN_PRSNT 1 2
R3985 5% 1/16W MF-LF 402
6
1 C3990 54-VAUX_PRSNT 37 BCM57765_CR_DATA<6> 1K 1 2

0.1UF R3986 0 5% 1/16W MF-LF 402
VCC
10% 16-VDDIO 37 BCM57765_SR_LX 1 2
16V 5% 1/16W MF-LF 402
U3990 2 X7R-CERM
402 20-XTALVDDH 37 BCM57765_VDDO_PIN20 R3987 0 1 2 PP3V3_ENET_PHY_XTALVDDH 37
AT45DB011D 5% 1/16W MF-LF 402
BCM5764_SCLK 2
SOIC-8S1
BCM5764_MOSI 55-VDDC 37 BCM57765_CR_DATA<7> R3988 0 1 2 PP1V2_ENET 7 37 72 73
SI 1 5% 1/16W MF-LF 402
37 SCK
OMIT
37
17-VDDC BCM57765_XTALVDDH R3989 0 1 2
A BCM5764_CS_L 4 14-VDDC
37
37 BCM57765_SR_VDD R3998 0 1 2 5%
5%
1/16W
1/16W
MF-LF
MF-LF
402
402
37 CS*
BCM5764_MISO 06-VDDC 37 BCM57765_SMB_CLK R3999 0 1 2 PAGE TITLE
SO 8
5 WP*
BCM57765 BCM5764M
37
L3999
5% 1/16W MF-LF 402
Ethernet PHY (Caesar II/IV)
3 1 1 FERR-600-OHM-0.5A DRAWING NUMBER SIZE
RESET* R3990 R3997 D
GND 4.7K 4.7K 26-PCIE_VDDL 37 BCM57765_CR_CMD PLACE_NEAR=U3900.26:4 mm 1 2 Apple Inc.
5% 5% REVISION
7
1/16W 1/16W Keep net short, BCM5764M BCM5764M SM CRITICAL R

MF-LF MF-LF
2 402 2 402 with no stubs. C3999 1 1 C3998
NOTE: Pull-down on SO plus internal pull-ups on 0.1UF 4.7UF
10% 10% THE INFORMATION CONTAINED HEREIN IS THE
other 3 SPI pins configures BCM57765 for the 16V 2 6.3V
X7R-CERM 2 X5R-CERM PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
Atmel AT45DB011D (1Mbit) ROM. If a different 402 603
ROM is used then the straps must change.
PLACE_NEAR=U3900.26:4 mm PLACE_NEAR=L3999.1:4 mm I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
39 OF 132
NOTE: BCM5764M requires SI pull-down instead of SO.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)
D D
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP
1 C4000 1 C40021 C40041 C4006
0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10%
2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
402 402 402 402
CRITICAL
T4000
SM
95 37 BI ENET_MDI_P<0> 1 12 99 ENETCONN_P<0>
ESD_HOT=True
95 37 BI ENET_MDI_N<0> 2 11 99 ENETCONN_N<0> CRITICAL
3 10 ENET_CTAP0
ESD_HOT=True J4000
RJ45-M97-3
TX F-RT-TH
TLA-6T213HF 9
C 4 9 ENET_CTAP1 10
C
95 37 BI ENET_MDI_N<1> 5 8 99 ENETCONN_N<1> 1
ESD_HOT=TRUE 2
95 37 BI ENET_MDI_P<1> 6 7 99 ENETCONN_P<1> 3
RX ESD_HOT=TRUE 4
5
CRITICAL 6
T4001
SM
7
95 37 BI ENET_MDI_N<2> 1 12 99 ENETCONN_N<2> 8
ESD_HOT=TRUE
95 37 BI ENET_MDI_P<2> 2 11 99 ENETCONN_P<2> 11
ESD_HOT=TRUE 12
3 10 ENET_CTAP2
TX
514-0636
TLA-6T213HF
4 9 ENET_CTAP3
95 37 BI ENET_MDI_N<3> 5 8 99 ENETCONN_N<3>
ESD_HOT=TRUE
95 37 BI ENET_MDI_P<3> 6 7 99 ENETCONN_P<3>
RX ESD_HOT=TRUE
Transformers should be
mirrored on opposite
sides of the board
R4000
75
1R40011
75
1
R4002
75
R4003
75
1
5% 5%
1/16W 1/16W
5%
1/16W
5%
1/16W
CRITICAL
B MF-LF
4022
MF-LF
4022
MF-LF
2402 2
MF-LF
402 C4008
1000PF B
ENET_BOB_SMITH_CAP
1 2
MIN_NECK_WIDTH=0.25 mm 10%
2KV
CERM
1206
PLACE_NEAR=T4001.2:5mm PLACE_NEAR=T4000.2:5mm
C1
C3
F1
F3
C1
C3
F1
F3
A1
A3
D1
D3
A1
A3
D1
D3
CRITICAL CRITICAL
D4000 D4001
HDMIULC64F3 HDMIULC64F3
WLCSP WLCSP
B2
E2
B2
E2
PAGE TITLE
Ethernet Connector
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

40 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_FW_FWPHY 7 39 40 41
7 mA I/O
138 mA
C4120 1 C4121 1 C4122 1 C4123 1 C4124 1

1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2
CERM CERM CERM CERM CERM
402 402 402 402 402
L4130
120-OHM-0.3A-EMI
D 114 mA FireWire PHY PP3V3_FW_FWPHY_VDDA 1 2 D
MIN_LINE_WIDTH=0.4 MM 0402-LF
VOLTAGE=3.3V
C4130 1 C4131 1 C4132 1
1UF 1UF 1UF
10% 10% 10%
6.3V 2 6.3V 2 6.3V 2
CERM CERM CERM
402 402 402
L4110 L4135
72 40 7 PPVIN_FW_FWPHY 120-OHM-0.3A-EMI 120-OHM-0.3A-EMI
1 2 PP1V0_FW_FWPHY_AVDD 25 mA PCIe SerDes 17 mA PCIe SerDes PP3V3_FW_FWPHY_VP25 1 2
135 mA
0402-LF MIN_LINE_WIDTH=0.4 MM MIN_LINE_WIDTH=0.4 MM 0402-LF
MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V VOLTAGE=3.3V
1 C4110 1 C4111 C4135 1 C4136 1
1UF 1UF 1UF 1UF
10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM
6.3V 2
CERM
6.3V 2
CERM
402 402 402 402
110 mA Digital Core 0 mA VReg PWR
1 C4100 1 C4101 1 C4102 1 C4103 1 C4104 1 C4105 1 C4106 C4141 1 1 C4140

1UF 1UF 1UF 1UF 1UF 1UF 1UF 0.1UF 1UF
10% 10% 10% 10% 10% 10% 10% 20% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
10V
CERM 2 2 6.3V
CERM
402 402 402 402 402 402 402 402 402
C PLACE_NEAR=U1800.AU32:3mm
PLACE_NEAR=U1800.AV32:3mm
C
B12
C13
E10
H12
M12
N11
C12
G12
L11
A12
L10
K12
C4170
1 10%
2 16V PCIE_FW_R2D_C_N
A1
B1
E2
H2
K2
L1
N3
C1
F1
J1
L3
M2
D5
D6
D8
L5
L6
L9
IN 17 94
0.1UF X5R 402
VDD10 VDD33 VDDH VP VP25 VREG_PWR C4171
1 10%
2 16V PCIE_FW_R2D_C_P IN 17 94
B13 ATBUSB OMIT N8 PCIE_FW_R2D_N 0.1UF X5R 402
NC PCIE_RXD0N 94
A13 ATBUSH CRITICAL N7 PCIE_FW_R2D_P

PCIE_RXD0P 94
NC
A11 ATBUSN
U4100 PCIE_TXD0N N5 94 PCIE_FW_D2R_C_N C4175
1 10%
2 16V PCIE_FW_D2R_N
NC 0.1UF OUT 17 94
FW643 PCIE_TXD0P N6 94 PCIE_FW_D2R_C_P X5R 402

41 IN FWPHY_DS0 F12 DS0 (IPD) NT-19 C4176
1 10%
2 16V
BGA PCIE_FW_D2R_P OUT 17 94
41 IN FWPHY_DS1 E12 DS1 (IPD) NT-20 0.1UF X5R 402
REFCLKN N9 PCIE_CLK100M_FW_N IN 17 94
41 IN FWPHY_DS2 E13 DS2 (IPD) NT-21 PCI EXPRESS PHY
REFCLKP N10 PCIE_CLK100M_FW_P IN 17 94 PLACE_NEAR=U4100.N5:3mm
PLACE_NEAR=U4100.N6:3mm
96 41 BI NC_FW0_TPAN B8 TPA0N
96 41 6 BI NC_FW0_TPAP A8 TPA0P
NT-4 (IPU) TCK M4 TP_FW643_TCK
96 41 40 BI FW_PORT1_TPA_N B5 TPA1N
NT-3 (IPU) TDI N2 NC_FW643_TDI 6
96 41 40 BI FW_PORT1_TPA_P A5 TPA1P TEST CONTROLLER PP3V3_FW_FWPHY 7 39 40 41
(IPU) TDO M1 TP_FW643_TDO
41 6 BI NC_FW2_TPAN B3 TPA2N
NT-1 (IPU) TMS M3 TP_FW643_TMS
41 6 BI NC_FW2_TPAP A3 TPA2P 1394 PHY FW643_LDO
96 41 6 BI NC_FW0_TPBN B9 TPB0N NT-2 (IPU) TRST* N1 FW643_TRST_L R41651 1
R4166
96 41 6 BI NC_FW0_TPBP A9 TPB0P 10K 10K
5% 5%
96 41 40 BI FW_PORT1_TPB_N B6 TPB1N 1/16W 1/16W
MF-LF MF-LF
96 41 40 BI FW_PORT1_TPB_P A6 TPB1P 402 2 2 402
NT-10 (IPD)WAKE* C2 FW643_WAKE_L OUT 8 40
41 6 BI NC_FW2_TPBN B4 TPB2N
41 PPVP_FW_CPS FIXME!!! - TYPO IN SYMBOL REGCTL REGCLT D13 FW643_REGCTL
41 6 BI NC_FW2_TPBP A4 TPB2P
POWER MANAGEMENT VAUX_DETECT E1 FW643_VAUX_DETECT
R41601 41 BI NC_FW0_TPBIAS B7 TPBIAS0 NT-12 (IPD) VAUX_DISABLE D2 TP_FW643_VAUX_ENABLE
B 200K
1%
1/16W
41 40
41 6
BI
BI
FW_P1_TPBIAS
NC_FW2_TPBIAS
C3 TPBIAS1
A2 TPBIAS2
NT-13 (OD) CLKREQN L2 FW_CLKREQ_PHY_L OUT 40
1
R4164
10K
B
MF-LF 5%
402 2 1/16W
FW643_R0 B11 R0 MF-LF
FW643_TPCPS B10 TPCPS 2 402
NT-16 (IPD) SCIFCLK G2 TP_FW643_SCIFCLK
SCIF NT-14 (IPD) SCIFDAIN G1 TP_FW643_SCIFDAIN
C4150 TP_FW643_NAND_TREE K1 NAND_TREE NT-OUT
R4150 NT-17 SCIFDOUT H1 TP_FW643_SCIFDOUT
22PF FW643_REXT L8 REXT
1 2 412 NOTE: NT-xx notes show NT-15 (IPD) SCIFMC F2 TP_FW643_SCIFMC
FW_CLK24P576M_XO 1 2 FW_CLK24P576M_XO_R F13 XO
FW_CLK24P576M_XI G13 NAND tree order.
5% CRITICAL 1%
1/16W
XI NT-9
50V Y4150 MF-LF
1
CERM 402 TP_FW643_SE M13 SE (IPD)

402 NC 24.576MHZ R41611 1
R4170 SERIAL EEPROM NT-7 SCL N12 FW643_SCL
2 4
SM-3.2X2.5MM TP_FW643_SM N13 SM (IPD)

C4151 NC 2.94K
1%
191
1% TP_FW643_MODE_A J2 MODE_A (IPD) NT-18
CONTROLLER NT-6 SDA M11 TP_FW643_SDA
3
22PF 1/16W 1/16W

TP_FW643_CE L13
1 2 MF-LF MF-LF CE (IPD)
402 2 2 402 TP_FW643_FW620_L D12 FW620* (IPU) MISCELLANEOUS
5% TP_FW643_JASI_EN D1 JASI_EN (IPD) NT-11
50V
CERM 6 NC_FW643_AVREG A10 AVREG CHIP RESET NT-5 PERST* N4 FW_RESET_L 40
402 IN
TP_FW643_VBUF H13 VBUF
FW643_PU_RST_L K13 1
FW_RESET* (IPU) NT-8 R4163
TP_FW643_OCR10_CTL J12 OCR_CTL_V10
10K
5%
R41621 1 C4162 NC
J13 OCR_CTL_V12 (Reserved)
1/16W
MF-LF
470K 0.33UF 2 402
5% 10% VSS VREG_VSS
1/16W
MF-LF 2 6.3V
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10
L12
402 2 CERM-X5R
402
PAGE TITLE
FireWire LLC/PHY (FW643)

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

41 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page: 3.3V FW FET
- =PPBUS_S5_FWPWRSW (system supply for bus power)
- =PP3V3_FW_LATEVG_ACTIVE I(max) = 1.7A (85C) 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
PP3V3_S0
74 73 72 71 70 69 64 63 59 55 53 52 49
- =PPVP_FW_SUMNODE (power passthru summation node) 1
101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
PP3V3_S0 R4281
Signal aliases required by this page: 74 73 72 71 70 69 64 63 59 55 53 52 49 100K
(NONE)
U4201 R4280 5%
1/16W
C4201 1 TPS22924 10K MF-LF
1UF CSP 72 39 7 PPVIN_FW_FWPHY 1 2
2 402
BOM options provided by this page: 10%
A2 A1 PP3V3_FW_FWPHY 7 39 40 41
6.3V 2 VIN VOUT 1%
- FW_PORT_FAULT_PU B2 B1 1/16W
CERM MF-LF
D 40 20 IN FW_PWR_EN
402
C2 ON
CRITICAL 402
3 CRITICAL D
GND P1V0_FW_RC 5 Q4299
DMB53D0UV
C4281
C1
1
SOT-563
PP3V3_FW_FWPHY 1UF 4
41 40 39 7
10%
6.3V 2
CERM
402
FW_PLUG_DET_L 8 20 40
PPCPUVTT_S0
1.05V FW FET
R42771 1
R4276 10 7 6
101 74 71 40 26 25 15 13 12
10K
5% 5%
100K U4202
1/16W 1/16W C4202 1 TPS22924
MF-LF MF-LF 1UF CSP P1V0_RESET_GATE
402 2 2 402 10%
A2 A1 PP1V0_FW 6 7 72
3 CRITICAL 6.3V 2
CERM
B2 VIN VOUT B1 R4283
402 10K
FW_WAKE 5 Q4276 CRITICAL 1 2 PLT_RESET_L IN
31
19
27
DMB53D0UV C2 ON 5%
SOT-563 1/16W
NOSTUFF GND MF-LF
4 CRITICAL 6 402
C4276
C1
1
0.1UF D Q4299
10%
2 16V
X5R DMB53D0UV
402 FW_CLKREQ_L OUT 17 25 SOT-563
2 G
FW_RESET_L OUT 39
CRITICAL 6
D Q4276 Q4261 D 3
DMB53D0UV S
SOT-563
SSM6N15FEAPE
SOT563 1
39 8 FW643_WAKE_L 2 G
PP1V05_FW PGOOD/FW_RESET_L
C 5 G S 4
FireWire Port Power Switch
C
S
1
40
40 39 IN FW_CLKREQ_PHY_L 39 FW_CLKREQ_PHY_L
MAKE_BASE=TRUE
CRITICAL
CRITICAL
F4260 D4260
1.5A-24V SM
CRITICAL PP10V_FW 1 2 PP10V_FW_D 1 2 PPVP_FW
72 8 7 6 7 41
Q4260 MIN_LINE_WIDTH=0.5 mm
NDS9407 1812L15024HF VOLTAGE=10V CRS08-1.5A-30V
SOI-HF
8 PPBUS_FW_FWBOOST 7 72
87 83 71 70 68 67 66 50 8 7 6 PPBUS_G3H 3
7
2
6
1 1
R4260 C4260 1 5
470K 0.1UF
1 5% 10%
R4262 1/16W
MF-LF 25V
X5R 2 4
10K 2 402 402
5%
1/16W
MF-LF FWPWR_EN_L_DIV
402 2
B 4 B
(SYM-VER2)
FWPWR_EN_TRI S SOT-363
1 74 71 40 26 25 15 13 12 10 7 6 PPCPUVTT_S0
5
G BSS8402DW R4261 101
Q4262 330K
1 5%
R4263 D 1/16W
MF-LF 1 1
10 3 2 402
1
R4275 R4270 R4271
5%
1/16W 1K 330K 56K FW_PLUG_DET_L OUT 8 20 40
MF-LF 5% 5% 5%
402 2 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF
FWPWR_EN_TRI_R 2 402 2 402 2 402 3 CRITICAL
FWPWR_EN_L
FW_DET_MIRROR FW_PLUG_DET 5 Q4275
6 D 6 FW_PWR_EN_L DMB53D0UV
Late-VG Protection Q4261 NOSTUFF SOT-563
D SSM6N15FEAPE
SOT563 C4261 1 CRITICAL 3 6 CRITICAL 1 C4270 4
Q4262 0.1UF
10%
Q4270 5 2
Q4270 0.1UF
101 99 88 86 85 84 81 74 73 PP3V3_S0 2 G BSS8402DW 25V 2 BC847CDXV6TXG BC847CDXV6TXG 10%
47 42 40 37 34 30 28 27 26 25 8 7 6
72 71 70 69 64 63 59 55 53 52 49 48 SOT-363 X5R SOT563 SOT563 16V
S 402 2 X5R
PLACE_NEAR=U4200.1:4mm (SYM-VER1) 2 G S 1 4 1 402
1 C4200 1
0.1UF FW_P1_TPBIAS_R FW_DET_EMIT
10%
2 16V
X5R 1 1
402 R4272 R4273
1K 12K
1
VCC CRITICAL 6 5% 5%
1/16W 1/16W
PLACE_NEAR=J4310.4:4mm
U4200 D Q4275 MF-LF MF-LF
TPD4S1394 2 402 2 402
LLP DMB53D0UV
96 41 39 BI FW_PORT1_TPA_P 8 D1+ VCLMP 3 TP_FW_LATEVG_VCLMP SOT-563
FW_PORT1_TPA_N 7 D1- FW_PWR_EN 2 G
A 96 41 39
96 41 39
BI
FW_PORT1_TPB_P 6 D2+ CRITICAL

FWPWR_EN 4 FWPWR_EN 40 20 IN PLACE_NEAR=C4360.1:4mm
BI PAGE TITLE
FW_PORT1_TPB_N 5 D2-
96 41 39 BI GND 1
R4201 S FireWire Port Power
2
100K DRAWING NUMBER SIZE

5% 1
1/16W
MF-LF Apple Inc. D
2 402 R
REVISION

41 39 IN
FW_P1_TPBIAS PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
42 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
41 40 39 7 PP3V3_FW_FWPHY
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG R43821 R43801
10K 10K
1% 1%
1/16W 1/16W
MF-LF MF-LF
- =GND_CHASSIS_FW_PORT1 402 2 402 2
- =GND_CHASSIS_FW_EMI_R
41 39 FWPHY_DS0 FWPHY_DS0 39 41
(NONE)
FireWire PHY Config Straps 41 39
MAKE_BASE=TRUE
FWPHY_DS2 FWPHY_DS2
D
D NOTE: This page is expected to contain
Configures PHY for:
MAKE_BASE=TRUE
39 41
the necessary aliases to map the 41 39 FWPHY_DS1 FWPHY_DS1 39 41

MAKE_BASE=TRUE
FireWire TPA/TPB pairs to their - 1-port Portable Power Class (0)
appropriate connectors and/or to
properly terminate unused signals. - Port "1" Bilingual (1394B) R43811
10K
1%
BOM options provided by this page: 1/16W
MF-LF
(NONE) 402 2
NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints 41 39 NC_FW0_TPBIAS NC_FW0_TPBIAS MAKE_BASE=TRUE 39 41
to apply to entire TPA/TPB XNets. 41 39 6 NC_FW2_TPBIAS NC_FW2_TPBIAS MAKE_BASE=TRUE 6 39 41
96 41 39 NC_FW0_TPAN NC_FW0_TPAN MAKE_BASE=TRUE 39 41 96

1394b implementation based on Apple
96 41 39 6 NC_FW0_TPAP NC_FW0_TPAP MAKE_BASE=TRUE 6 39 41 96
FireWire Design Guide (FWDG 0.6, 5/14/03)
41 39 6 NC_FW2_TPAN NC_FW2_TPAN MAKE_BASE=TRUE 6 39 41
41 39 6 NC_FW2_TPAP NC_FW2_TPAP MAKE_BASE=TRUE 6 39 41
96 41 39 6 NC_FW0_TPBN NC_FW0_TPBN MAKE_BASE=TRUE 6 39 41 96
96 41 39 6 NC_FW0_TPBP NC_FW0_TPBP MAKE_BASE=TRUE 6 39 41 96
Termination 41 39 6 NC_FW2_TPBN
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
MAKE_BASE=TRUE 6 39 41
41 39 6 MAKE_BASE=TRUE 6 39 41
Place close to FireWire PHY
BSS8402DW
TI PHYs require 1uF even though
FW_P1_TPBIAS
Q4300
40 39
FW spec calls out 0.33uF
SOT-363
(SYM-VER2)
C 1 C4360 C
0.33UF
10%
2 6.3V
CERM-X5R Cable Power
PPVP_FW
D
402
3
41 40 7 6
41 39PPVP_FW_CPS MAKE_BASE=TRUE PPVP_FW_CPS 39 41 CRITICAL
L4310 Note: Trace PPVP_FW_PORT1 must handle up to 5A
VOLTAGE=12.6V FERR-250-OHM
R43111 41 40 7 6 PPVP_FW
G
470K 1 2 PPVP_FW_PORT1_F
5
5% SM MIN_LINE_WIDTH=0.5 mm
1/16W MIN_NECK_WIDTH=0.25 mm
MF-LF VOLTAGE=33V
402 2 1 C4314
0.01UF
10%
CPS_EN_L_DIV 2 50V
X7R
402
R43121
1
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
R4360 R43611
330K
5%
PORT 1
1/16W
56.2 56.2 MF-LF BILINGUAL
1% 1% 402 2
1/16W 1/16W CPS_EN_L
MF-LF MF-LF
PLACE_NEAR=U4100.A5:2mm 2 402 402 2 PLACE_NEAR=U4100.B5:2mm
96 41 40 39 FW_PORT1_TPA_P FW_PORT1_TPA_P 39 40 41 96 6 CRITICAL

MAKE_BASE=TRUE
FW_PORT1_TPA_N FW_PORT1_TPA_N D J4310
96 41 40 39 39 40 41 96 1394B-M97
MAKE_BASE=TRUE Q4300 F-RT-TH
96 41 40 39 FW_PORT1_TPB_P FW_PORT1_TPB_P 39 40 41 96
2 G BSS8402DW TPB- TPB(R)
MAKE_BASE=TRUE 41 40 39 7 PP3V3_FW_FWPHY 96 41 40 39 FW_PORT1_TPB_N 1 TPB-
SOT-363
96 41 40 39 FW_PORT1_TPB_N FW_PORT1_TPB_N 39 40 41 96
S (SYM-VER1) ESD_HOT=TRUE (FW_PORT1_BREF) 9 TPB<R> OUTPUT
MAKE_BASE=TRUE
SIGNAL_MODEL=EMPTY 1 96 41 40 39 FW_PORT1_TPB_P 2 TPB+ TPB+
VP
PLACE_NEAR=U4100.B6:4mm 1 SIGNAL_MODEL=EMPTY PLACE_NEAR=U4100.A6:4mm 8

ESD_HOT=TRUE VP
R4362 R43631
B 56.2
1%
56.2
1% (GND_FW_PORT1_VG)
NC 7
6
NCSC/NC
VG
B
1/16W 1/16W
MF-LF MF-LF 96 41 40 39 FW_PORT1_TPA_N 3 TPA- TPA-
VG
2 402 402 2
FW_PORT1_AREF 5 INPUT
ESD_HOT=TRUE TPA<R>
96 41 40 39 FW_PORT1_TPA_P 4 TPA+ TPA(R)

TPA+
FW_PORT1_TPB_C ESD_HOT=TRUE
10
ESD_HOT=TRUE 11
1 C4364 R4364
1 C4319 1 12 CHASSIS
4.99K 0.1uF PLACE_NEAR=J4310.5:3mm
GND
220pF 1% 10% 13
5% 1/16W 50V 2
2 25V
CERM MF-LF X7R
603-1
402 402 2
1
R4319 AREF needs to be isolated from all
1M
5% local grounds per 1394b spec 514S0605
1/16W
MF-LF
2 402 When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
BREF should be hard-connected to logic

ground for speed signaling and connection
A SYNC_MASTER=K18_MLB SYNC_DATE=07/08/2009 A
PAGE TITLE
FireWire Ports
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

43 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ODD Power Control CRITICAL
Q4590
TPCP8102
23V1K-SM
PP5V_SW_ODD_R
PP5V_S0
8
102 87 73 71 70 69 55 53 48 42 23 8 7 6 MIN_LINE_WIDTH=0.6mm
3
7
VOLTAGE=5V
6
1
R45961
5
NOTE: 3.3V must be S0 if 5V is S3 or S5 to 1 C4595
G
100K 0.068UF
D
4
ensure the drive is unpowered in S3/S5. 5%
D 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0
1/16W
MF-LF
402 2 R4595
10%
10V
2 CERM
402
C4596
74 73 72 71 70 69 64 63 59 55 53 52 49 0.01UF
ODD_PWR_EN_LS5V_L 1
100K 2 ODD_PWR_SS 1 2
R45971 5%
10%
100K 1/16W
16V
5% D 6 MF-LF
1/16W
MF-LF
Q4596 402 CERM
402
402 2 SSM6N15FEAPE CRITICAL
SOT563
ODD_PWR_EN R4598 1 3 ISNS_ODD_P OUT 57 99
0.002
1%
2 G S 1 1/4W
D 3 MF ISNS_ODD_N
Q4596 1206 2 4 OUT 57 99
SSM6N15FEAPE
SOT563
5 G S 4
99 74 72 59 42 34 7 PP1V5_S0
20 IN ODD_PWR_EN_L
NO STUFF NO STUFF
1 1
R4519 R4520
100K 100K
5% 5%
1/16W 1/16W
57 6 PP5V_SW_ODD RDRV_8515_A1&RDRV_8515_A2 MF-LF MF-LF
MIN_NECK_WIDTH=0.4mm R4513 2 402 2 402
VOLTAGE=5V
SMBUS_PCH_CLK 2
0 1 SATARDRVR_A_I2C_SCL
49 48 34 32 30 28 26 25 17 6 IN 42
94 64
5%
1/16W
MF-LF
402
RDRV_8515_A1&RDRV_8515_A2
C SATA ODD Port 49 48 34 32 30 28 26 25 17 6

94 64 BI SMBUS_PCH_DATA 2
R4514
0 1 SATARDRVR_A_I2C_SDA 42
C
5%
1/16W
MF-LF
99 74 72 59 42 34 7 PP1V5_S0 402 PP1V5_S0 7 34 42 59 72 74 99
RDRV_8515_A1&RDRV_8515_A2 NO STUFF
R4515 R4517
2
0 0
5% 5%
1/16W 1/16W
FL4520 MF-LF MF-LF
J4500 90-OHM-100MA
DLP11S
402 402
1
CRITICAL 55560-0168 CRITICAL SYM_VER-1
M-ST-SM-LF SATARDRVR_A_B_SD
2 1
3 4 99 SATA_ODD_R2D_UF_P 1 2 C4521 SATA_ODD_R2D_C_P IN 17 93 SATARDRVR_A_I2C_EN 42
42
10% 16V CERM 402

SATARDRVR_A_A_SD 42
4 3 SATA_ODD_R2D_P 0.01UF NO STUFF
101 99 88 86 85 84 81
93 6
R4516 NO STUFF
PP3V3_S0 C4520
2
48 47 42 40 37 34 30 28 27 26 25 8 7 6
6 5 SATA_ODD_R2D_N 2 1 SATA_ODD_R2D_UF_N 1 2 SATA_ODD_R2D_C_N 0 R4518
2
74 73 72 71 70 69 64 63 59 55 53 52 49 93 6 99 17 93
IN 5% 0
8 7 0.01UF 10% 16V CERM 402 1/16W 5%
PLACE_NEAR=J4500.5:4mm MF-LF 1/16W
10 9 99 6 SATA_ODD_D2R_UF_N 402 MF-LF
402
FL4525
1
R45901 12 11 99 6 SATA_ODD_D2R_UF_P
1
90-OHM-100MA
33K 14 13 DLP11S
5% 16 15 CRITICAL SYM_VER-1
1/16W
MF-LF 4 3 93 SATA_ODD_D2R_C_N 1 2 C4526 SATA_ODD_D2R_N OUT 17 93
402 2 10% 16V CERM 402
0.01UF
516S0617 1 2 93 SATA_ODD_D2R_C_P 1 2 C4525 SATA_ODD_D2R_P 17 93
OUT
46 6 SMC_ODD_DETECT 0.01UF 10% 16V CERM 402 RDRV_BYPASS
OUT
PLACE_NEAR=J4500.11:4mm R4521 RDRV_BYPASS
2
51.1 1 C4531 1 2
Indicates disc presence 93 42 SATA_HDD_D2R_C_P SIGNAL_MODEL=EMPTY SATA_HDD_D2R_BYPASS_P SATA_HDD_D2R_P 17 42 93
1% RDRV_BYPASS 0.01UF 10% 16V CERM 402

1/16W
C4542 10PF SIGNAL_MODEL=EMPTY
B
PLACE_NEAR=L4500.1:3mm PLACE_NEAR=L4500.2:3mm
SATA HDD Port PLACE_NEAR=U4510.6:3mm
PLACE_NEAR=U4510.6:3mm
MF-LF
402
RDRV_BYPASS
C4541 10PF
CERM 402
RDRV_BYPASS
5% 50V SIGNAL_MODEL=EMPTY B
99 74 72 59 42 34 7 PP1V5_S0 SIGNAL_MODEL=EMPTY R4522 RDRV_BYPASS
1 C4501 1 C4502 CRITICAL SATA_HDD_D2R_C_N
CERM 402 5% 50V
2
51.1 1 SATA_HDD_D2R_BYPASS_N C4522 1 2 SATA_HDD_D2R_N
0.1UF 0.1UF 93 42 17 42 93
20%
10V CRITICAL
20%
10V R4599 NO STUFF 1 C4514 1 C4519 RDRV_BYPASS 1% SIGNAL_MODEL=EMPTY 0.01UF 10% 16V CERM 402
2 CERM 2 CERM 0.002 R4510 R4511 1UF 0.01UF R4523 1/16W
MF-LF
SIGNAL_MODEL=EMPTY
2
RDRV_BYPASS
7
34
PP1V5_S0 402 L4500 402 1%
1/4W 5%
0 0
5%
10%
2 6.3V
10%
16V SATA_HDD_R2D_UF_N 2
0 1
402
SATA_HDD_R2D_BYPASS_N C4523 1 2 SATA_HDD_R2D_C_N
42
59
FERR-70-OHM-4A MF 1/16W 1/16W CERM-X5R 2 CERM 99 42 17 42 93
72 1206 MF-LF MF-LF 402 402

SIGNAL_MODEL=EMPTY 5% RDRV_BYPASS 0.01UF 10% 16V CERM 402
PP5V_S0_HDD_FLT 1 2 PP5V_S0_HDD_R 1 2 PP5V_S0
74
99
6
MIN_LINE_WIDTH=0.6mm MIN_LINE_WIDTH=0.6mm 3
6 7 8 23 42 48 53 55 69
70 71 73 87 102
402 402 1/16W
MF-LF R4524 RDRV_BYPASS
SIGNAL_MODEL=EMPTY
1
0603 4 0 1
MIN_NECK_WIDTH=0.4mm MIN_NECK_WIDTH=0.4mm 402
C4524 1
16
ISNS_HDD_P SATA_HDD_R2D_UF_P 2 SATA_HDD_R2D_BYPASS_P 2 SATA_HDD_R2D_C_P
6
VOLTAGE=5V PLACE_NEAR=J4501.1:3mm VOLTAGE=5V OUT 57 99 OMIT 42 17 42 93
99
ISNS_HDD_N SIGNAL_MODEL=EMPTY 5% 0.01UF 10% 16V CERM 402
FL4502
90-OHM-100MA
OUT 57 99
VDD 1/16W
MF-LF
SIGNAL_MODEL=EMPTY
DLP11S
SYM_VER-1
CRITICAL U4510 402
C4518 1 2 SATA_HDD_D2R_P OUT
CRITICAL 4 3 93 42 SATA_HDD_D2R_C_P C4516 1 2 99 SATA_HDD_D2R_RDRV_IN_P PS8515A 10% 16V CERM 402
17 42 93
10% 16V CERM 402 TQFN 99 SATA_HDD_D2R_RDRV_OUT_P 0.01UF

J4501
QT500166-L020
0.01UF
C4515 1
1
2
A_INP CRITICAL A_OUTP 15 C4517 1 2 SATA_HDD_D2R_N OUT 17 42 93
M-ST-SM
1 2 93 42 SATA_HDD_D2R_C_N 2 99 SATA_HDD_D2R_RDRV_IN_N A_INN A_OUTN 14 99 SATA_HDD_D2R_RDRV_OUT_N 10% 16V CERM 402
10% 16V CERM 402 0.01UF
1 2 PLACE_NEAR=J4501.6:4mm 0.01UF 4
99 SATA_HDD_R2D_RDRV_OUT_N B_OUTN B_INN 12 99 SATA_HDD_R2D_RDRV_IN_N C4513 1 2
5 SATA_HDD_R2D_C_N
B_INP 11
17 42 93
3 4 99 6 SATA_HDD_D2R_UF_P 99 SATA_HDD_R2D_RDRV_OUT_P B_OUTP IN
0.01UF 10% 16V CERM 402
5 6 99 6 SATA_HDD_D2R_UF_N 99 SATA_HDD_R2D_RDRV_IN_P
SATARDRVR_A_EN 7
NC
7 8 25 17 IN
17
EN C4512 1 2 SATA_HDD_R2D_C_P IN 17 42 93
9 10 SATARDRVR_A_AUTOPWR_EN AUTOPW_EN 10% 16V CERM 402
93 6 SATA_HDD_R2D_N 0.01UF
11 12 SATA_HDD_R2D_P SATARDRVR_A_I2C_EN 10 I2C_EN A_SD 20 SATARDRVR_A_A_SD
NC 93 6
FL4501 42
8
42
13 14 90-OHM-100MA SATARDRVR_A_I2C_ADDR I2C_ADDR B_SD 9 SATARDRVR_A_B_SD 42
15 16 DLP11S
SYM_VER-1
NC CRITICAL
SATARDRVR_A_I2C_SCL 19
3 4 SATA_HDD_R2D_UF_N C4511 1 2 42 SCL_CTL
A 516S0350
99 42
0.01UF 10% 16V CERM 402 42 SATARDRVR_A_I2C_SDA 18 SDA_CTL

GND THRM PAGE TITLE
2 1 C4510 1 2 RDRV_8515_A1&RDRV_8515_A2 PAD
99 42 SATA_HDD_R2D_UF_P R4512 SATA Connectors
2
0.01UF 10% 16V CERM 402 0
3
13
21
PLACE_NEAR=J4501.12:4mm 5% DRAWING NUMBER SIZE
1/16W
MF-LF
338S0778 D
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 402 SATA REDRIVER Apple Inc. REVISION
1
R
338S0769 1 SATA 3GB/S REDRIVER, LOW POWER U4510 CRITICAL RDRV_8511
338S0778 1 SATA 3GB/S REDRIVER, LOW POWER U4510 CRITICAL RDRV_8515_A1
338S0848 1 SATA 3GB/S REDRIVER, LOW POWER U4510 CRITICAL RDRV_8515_A2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
45 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Port Power Switch Left USB Port A

CRITICAL CRITICAL
Q4690 L4605
FERR-220-OHM-2.5A
TPS2064DGN
103 83 73 68 55 51 47 45 44 33 31 7 6 PP5V_S3 2 IN
OUT1
7 PP5V_S3_RTUSB_A_ILIM 1 2 6 PP5V_S3_RTUSB_A_F
MSOP MIN_LINE_WIDTH=0.5 mm 0603 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm MIN_NECK_WIDTH=0.375 mm
PM_SLP_S4_L USB_EXTA_OC_L 8 VOLTAGE=5V VOLTAGE=5V CRITICAL
74 73 47 46 31 18 36 OUT
3
OC1*
EN1 OUT2 6 PP5V_S3_RTUSB_B_ILIM C4605 1
PLACE_NEAR=J4600.1:8mm J4600
MIN_LINE_WIDTH=0.5 mm 0.01uF USB
1 USB_EXTB_OC_L 5 20% CRITICAL
R4690 35 OUT OC2* MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V 16V F-RT-TH-M97-4
5.1K 4
EN2
CERM 2
402 L4600
90-OHM-100MA
5
5% 6
1/16W DLP11S
MF-LF USB_PWR_EN GND TPAD SYM_VER-1
2 402 1 9 CRITICAL CRITICAL 99 USB2_EXTA_MUXED_N 4 3 99 6 USB2_LT1_N 1

C4690 1 1 C4691 C4695 1
10UF 0.1UF
10UF
1
C4696 C4617
10UF
1 1
C4616 2
C4692 1 20%
6.3V 2
20%
2 10V 20%
100UF
20% 20%
100UF
20%
99 USB2_EXTA_MUXED_P 1 2 99 6 USB2_LT1_P 3
0.47UF X5R CERM 6.3V 2 6.3V
2 POLY-TANT 6.3V 2 2 6.3V 4
10% 603 402 X5R X5R POLY-TANT
C 10V 2
X5R
402
603 CASE-B2-SM 603 CASE-B2-SM
2 5 3 4
7
C
NC
IO
NC
IO
6 VBUS 8
1 GND
D4600
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
L4615
FERR-220-OHM-2.5A
1 2 6 PP5V_S3_RTUSB_B_F
VOLTAGE=5V
1 C4615
0.01uF PLACE_NEAR=J4610.1:8mm
20%
2 16V
CERM
402
CRITICAL
J4610
USB/SMC Debug Mux USB
F-RT-TH-M97-4
5
SMC_DEBUG_YES CRITICAL 6
PP3V42_G3H
L4610
90-OHM-100MA
49 48 47 46 45 23 21 17 7 6 SIGNAL_MODEL=USB_MUX
74 66 65 54 51 50 DLP11S
SYM_VER-1 1
SMC_DEBUG_YES 1 USB_EXTB_N 4 3 USB_LT2_N 2
R4650 93 35 BI 99 6
B C4650 1 10K 99 6 USB_LT2_P 3

B
9
0.1UF 5% 4
20% 1/16W
10V VCC MF-LF 93 35 BI USB_EXTB_P 1 2
CERM 2 2 402
48 47 46 6 SMC_RX_L 402 5 M+ Y+ 1 PLACE_NEAR=J4610.2:8mm 7
IN
SMC_TX_L 4 M- Y- 2 2 5 3 4 8
48 47 46 6 OUT U4650
NC
IO
NC
IO
PI3USB102ZLE 6 VBUS
93 36 USB_EXTA_P 7 D+ TQFN
BI
USB_EXTA_N 6 D- CRITICAL 1 GND
93 36 BI
8 OE* SEL 10 USB_DEBUGPRT_EN_L IN 46
GND SEL=0 Choose SMC D4610

RCLAMP0502N
SEL=1 Choose USB SLP1210N6
3
CRITICAL
SMC_DEBUG_NO
R4651
1
0
5%
2
SMC_DEBUG_NO
Left USB Port B
1/16W
MF-LF
402 R4652
1
0 2
5%
1/16W
MF-LF
402
PAGE TITLE
External USB Connectors

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

46 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Port Power Switch LEFT USB PORT C

ENABLE TIED LOW SO INPUT POWER SOURCE MUST BE S3!!!
CRITICAL CRITICAL
U4780 L4725
FERR-220-OHM-2.5A
TPS2068
103 83 73 68 55 51 47 45 43 33 31 7 6 PP5V_S3 2 IN1 OUT1
6 PP5V_S3_RTUSB_C_ILIM 1 2 6 PP5V_S3_RTUSB_C_F
MSOP MIN_LINE_WIDTH=0.5 mm 0603 MIN_LINE_WIDTH=0.5 mm
3 MIN_NECK_WIDTH=0.375 mm MIN_NECK_WIDTH=0.375 mm
IN2 VOLTAGE=5V
C4725 1 VOLTAGE=5V CRITICAL
OUT2 7
0.01uF
PLACE_NEAR=J4720.1:8mm J4720
35 8 USB_EXTC_OC_L 5 OC*
20% CRITICAL USB
OUT 16V F-RT-TH-M97-4
4 EN* 8
CERM 2
402 L4720
90-OHM-100MA
5
OUT3 6
DLP11S
GND TPAD SYM_VER-1
1 9 CRITICAL 4 3 99 6 USB_LT3_N 1
C4780 1 1 C4781 C
C 10UF
20%
0.1UF
20%
C4785 1
10UF
1
C4786
100UF 1 2 99 6 USB_LT3_P
2
3
6.3V 2 10V
2 CERM 20% 20%
X5R 6.3V 2 2 6.3V 4
603 402 X5R POLY-TANT
603 CASE-B2-SM PLACE_NEAR=J4720.2:8mm
2 5 3 4
7
NC
IO
NC
IO
6 VBUS 8
1 GND
D4720
RCLAMP0502N
SLP1210N6
93 35 BI USB_EXTC_N
USB_EXTC_P CRITICAL
93 35 BI
B B
PAGE TITLE
PROJECT SPECIFIC CONNS

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

47 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OMIT
R4801
83 73 68 55 51 47 45 44 43 33 31 7 6PP5V_S3
SHORT
1 2 PP5V_S3_IR_USB
NONE MIN_NECK_WIDTH=0.25 mm
NONE VOLTAGE=5V
NONE
402
1 C4801
0.1UF
10%
16V
2 X7R-CERM
402
14
VCC
U4800
CY7C63803-LQXC QFN
93 35 BI USB_IR_P 12 P1.0/D+ P0.0 7 NC
DIFFERENTIAL_PAIR=USB2_IR 13 P1.1/D- 6
USB_IR_N P0.1
93 35 BI
DIFFERENTIAL_PAIR=USB2_IR NC
15 P1.2/VREG
IR_VREF_FILTER INT0/P0.2 5
NC
NC
16 P1.3/SSEL INT1/P0.3 4 NC
NC
17 P1.4/SCLK INT2/P0.4 3 NC
R4800
1 C480318 P1.5/SMOSI TIO0/P0.5 2 IR_RX_OUT_RC 1
100 2 IR_RX_OUT
1UF NC IN 6 45
10% 19 P1.6/SMISO TIO1/P0.6 1 5%
10V
2 X5RNC NC 1/16W
MF-LF
402-1
NC
8 CRITICAL 402
9 OMIT
NC 1 C4804
NC
10 P/N 338S0633 0.001UF
20 10%
C NC
NC
21 NC 2 50V
CERM
402
C
NC
22
NC
23
24
NC THRML
PAD VSS
25
11
B PLACE_NEAR=J4800.2:5mm
B
R4805
PP3V42_G3H_LIDSWITCH_R 1
10 2 PP3V42_G3H
J4800
FF18-6A-R11AD-B-3H
6
VOLTAGE=3.42V
1/16W
5%
MF-LF
402
R4806
6 7 17 21 23 43 46 47 48 49 50
51 54 65 66 74
CRITICAL
F-RT-SM
6 PP5V_S3_IR_R 1 10 2 PP5V_S3 6 7 31 33 43 44 45 47 51 55 68 73 83 103
MIN_LINE_WIDTH=0.5 mm 1/16W 402
1
2
VOLTAGE=5V
5%
MF-LF R4807
100 2
3 6 SMC_LID_R 1 SMC_LID 46 47 54
1/16W 402
4 5%
MF-LF R4808
5 6 SYS_LED_ANODE_R 1 4.7 2 SYS_LED_ANODE 6 47
1/16W 402
6 5%
MF-LF
IR_RX_OUT 6 45
518S0692 1 1 1 1
C4805 C4806 C4807 C4808
0.1UF 0.1UF 0.001UF 0.001UF
10% 10% 10% 10%
2 16V 2 16V 2 50V 2 50V
X7R-CERM X7R-CERM CERM CERM
402 402 402 402
PAGE TITLE
Front Flex Support

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

48 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups. PP3V3_S5_AVREF_SMC
47 6
49 48 47 45 43 23 21 17 7 6 PP3V42_G3H
74 66 65 54 51 50
C4902 1 1 C4903 1 C4904 1 C4905 1 C4906

22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20%
6.3V 2 2 10V 10V
2 CERM 10V
2 CERM 10V
2 CERM
CERM CERM
805 402 402 402 402
D R4999 PLACE_NEAR=U4900.M12:10mm
PLACE_NEAR=U4900.M12:10mm
SMC_VCL PLACE_NEAR=U4900.E1:3mm
D
1
4.7 2 PP3V3_S5_SMC_AVCC
MIN_LINE_WIDTH=0.25 MM C4907 1
M12
H10
L11
5% MIN_NECK_WIDTH=0.20 MM 0.47UF
B1
M1
E1
1/16W VOLTAGE=3.3V
MF-LF
402
C4920 1 10%
6.3V
0.1UF CERM-X5R 2
20% 402
U4900 10V
CERM 2
AVCC VCC VCL AVREF
34 OUT SMC_EXCARD_PWR_EN B12 P10 H8S2117 P60 L13 SMC_PM_G2_EN OUT 74
402
U4900 R49091 1
R4901
47 OUT TP_SMC_RSTGATE_L A13 P11 LGA-HF P61 K12 NC NC E5 NC 10K 10K
ALL_SYS_PWRGD H8S2117 5% 5%
88 74 27 25 IN A12 P12 (1 OF 3) P62 K11 NC LGA-HF 1/16W 1/16W
MF-LF MF-LF
74 IN RSMRST_PWRGD B13 P13 OMIT P63 J12 NC 402 2 2 402
(3 OF 3)
NC D11 P14 P64 K13 SMC_ADAPTER_EN OUT 18 47 74
OMIT MD1 D1 SMC_MD1 IN 6 48
18 OUT PM_RSMRST_L C13 P15 P65 J10 NC MD2 H1 SMC_KBC_MDE
69 OUT CPUIMVP_VR_ON C12 P16 P66 J11 SMC_PROCHOT_3_3_L IN 47 66 48 47 6 IN SMC_RESET_L D3 RES*
25 18 OUT PM_PWRBTN_L D10 P17 P67 H12 SMC_BIL_BUTTON_L IN 6 47 65
47 SMC_XTAL A3 XTAL
47 6 OUT NC_ESTARLDO_EN D13 P20 P70 N10 SMC_CPU_ISENSE IN 50 47 SMC_EXTAL A2 EXTAL NMI E3 SMC_NMI IN 6 48
NC E11 P21 P71 M11 SMC_CPU_VSENSE IN 50
NC D12 P22 P72 L10 SMC_GPU_ISENSE IN 51
NC F11 P23 P73 N11 SMC_GPU_VSENSE IN 50

ETRST H3 SMC_TRST_L IN 6 48
47 TP_SMC_P24 E13 P24 P74 N12 SMC_DCIN_ISENSE IN 50
SMC_PBUS_VSENSE NO STUFF
NC E12 P25 P75 M13 IN 50 AVSS L9 1 1 1
50 47 SMC_BMON_MUX_SEL F13 P26 P76 N13 SMC_BATT_ISENSE IN 50 VSS R4902 R4998 R4903
SMC_GFX_ISENSE 10K 10K 0
NC E10 P27 P77 L12 IN 47 50 5% 5% 5%
1/16W 1/16W 1/16W
XW4900
D2
L3
F10
B11
C5
MF-LF MF-LF MF-LF
94 88 48 17 6 BI LPC_AD<0> A9 P30 P80 A7 SMC_WAKE_SCI_L OUT 17 SM 2 402 2 402 2 402
94 88 48 17 6 BI LPC_AD<1> D9 P31 P81 B6 NC 2 1
94 88 48 17 6 BI LPC_AD<2> C8 P32 P82 C7 PM_CLKRUN_L OUT 6 18 48
LPC_AD<3> LPC_PWRDWN_L PLACE_NEAR=U4900.L3:4mm

C 94 88 48 17 6
94 88 48 17 6
BI
IN LPC_FRAME_L
B7
A8
P33
P34
P83
P84
D5
A6 SMC_TX_L
IN
OUT
6 18 48
6 43 46 47 48
C
27 IN SMC_LRESET_L D8 P35 P85 B5 SMC_RX_L IN 6 43 46 47 48
GND_SMC_AVSS 47 50 51
94 27 IN LPC_CLK33M_SMC D7 P36 P86 C6 (OC) SMBUS_SMC_MGMT_SCL BI 49 57 97 102
48 17 6 BI LPC_SERIRQ D6 P37
P90 J4 SMC_ONOFF_L IN 6 47 54
NC D4 P40 P91 G3 SMC_BC_ACOK IN 47 65 66
65 47 SMC_BATT_ULP_L A5 P41 P92 H2 TP_SMC_P92 6 47
102 97 57 49 BI SMBUS_SMC_MGMT_SDA (OC) B4 P42 P93 G1 PM_SLP_S3_L IN 6 18 31 74 86
56 OUT SMS_PWRDN A1 P43 P94 H4 PM_SLP_S4_L IN 18 31 43 47 73 74
NC C2 P44 P95 G4 PM_SLP_S5_L IN 18 47 NOTE: P94 and P95 are shorted, P95 could be spare.
NC B2 P45 P96 F4 SMC_CLK32K IN 47
81 OUT SMC_GFX_THROTTLE_L C1 P46 P97 F1 (OC) SMBUS_SMC_0_S5_SDA BI 49 52 82
55 OUT SMC_SYS_KBDLED C3 P47
48 47 46 43 6 OUT SMC_TX_L G2 P50

48 47 46 43 6 IN SMC_RX_L F3 P51
82 52 49 BI SMBUS_SMC_0_S5_SCL (OC) E4 P52
U4900
(DEBUG_SW_1) 47 SMC_PA0 N3 PA0 H8S2117 PE0 K1 SMC_CASE_OPEN IN 47
17 OUT SPI_DESCRIPTOR_OVERRIDE_L (OC) N1 PA1 LGA-HF PE1 J3 SMC_TCK IN 6 47 48
27 18 6 OUT PM_SYSRST_L (OC) M3 PA2 (2 OF 3) PE2 K2 SMC_TDI IN 6 47 48
43 OUT USB_DEBUGPRT_EN_L (OC) M2 PA3 OMIT PE3 J1 SMC_TDO OUT 6 47 48
47 30 28 BI MEM_EVENT_A_L (OC) N2 PA4 PE4 K4 SMC_TMS IN 6 47 48
B 47
65 47
BI
BI
MEM_EVENT_B_L
SYS_ONEWIRE
(OC)
(OC)
L1
K3
PA5
PA6
PF0 K5 G3_POWERON_L IN 47
B
PF1 N5 SMC_SYS_LED OUT 47
18 OUT PM_BATLOW_L (OC) L2 PA7
PF2 M6 SMC_LID IN 45 47 54
NC B8 PB0 PF3 L5 NC
20 OUT SMC_RUNTIME_SCI_L C9 PB1 PF4 M5 NC
42 6 IN SMC_ODD_DETECT B9 PB2 PF5 N4 TP_SMC_PF5 47
47 25 20 SMC_IG_THROTTLE_L (See below) A10 PB3 PF6 L4 NC

47 34 IN SMC_EXCARD_CP C10 PB4 PF7 M4 NC
NC B10 PB5
PG0 M8 NC
47 IN SMC_EXCARD_OC_L C11 PB6
PG1 N7 SMS_INT_L IN 47 NOTE: SMS Interrupt can be active high or low, rename net accordingly.
81 IN SMC_GFX_OVERTEMP_L A11 PB7
PG2 K8 (OC) SMBUS_SMC_BSA_SDA BI 6 49 65 66 97 If SMS interrupt is not used, pull up to SMC rail.
53 OUT SMC_FAN_0_CTL G11 PC0 PG3 K7 (OC) SMBUS_SMC_BSA_SCL BI 6 49 65 66 97
53 OUT SMC_FAN_1_CTL G13 PC1 PG4 K6 (OC) SMBUS_SMC_A_S3_SDA BI 6 33 49 55 97
47 6 OUT NC_SMC_FAN_2_CTL F12 PC2 PG5 N6 (OC) SMBUS_SMC_A_S3_SCL BI 6 33 49 55 97
47 6 OUT NC_SMC_FAN_3_CTL H13 PC3 PG6 M7 (OC) SMBUS_SMC_B_S0_SDA BI 49 52 97
53 IN SMC_FAN_0_TACH G10 PC4 PG7 L6 (OC) SMBUS_SMC_B_S0_SCL BI 49 52 97
53 IN SMC_FAN_1_TACH G12 PC5

PH0 E2 SMC_PROCHOT OUT 47
47 6 IN NC_SMC_FAN_2_TACH H11 PC6
PH1 F2 SMC_THRMTRIP OUT 47
47 6 IN NC_SMC_FAN_3_TACH J13 PC7
PH2 J2 NC
56 IN SMS_X_AXIS M10 PD0 PH3 A4 NC_ALS_GAIN OUT 6 47
56 IN SMS_Y_AXIS N9 PD1 PH4 B3 NC

56 IN SMS_Z_AXIS K10 PD2 PH5 C4 NC
51 47 IN SMC_GPU_1V8_ISENSE L8 PD3
51 47 IN SMC_CPUVTT_ISENSE M9 PD4
SMC_1V5_S3_ISENSE N8
A 51 47
50 47
IN
IN SMC_GFX_VSENSE K9
PD5
PD6 SYNC_MASTER=K17_WFERRY SYNC_DATE=06/09/2009 A
50 47 IN SMC_CPU_HI_ISENSE L7 PD7 PAGE TITLE
SMC
DRAWING NUMBER SIZE
SMC_PB3: Apple Inc. D

REVISION
R
SMC_IG_THROTTLE_L for MG systems.
Otherwise, TP/NC okay (was ISENSE_CAL_EN) NOTICE OF PROPRIETARY PROPERTY: BRANCH
49 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NC_SMC_FAN_2_CTL NC_SMC_FAN_2_CTL
SMC Reset "Button" / Brownout Detect MAKE_BASE=TRUE
6 46 47
SMC FSB to 3.3V Level Shifting
47 46 6 NC_SMC_FAN_2_TACH NC_SMC_FAN_2_TACH 6 46 47
MAKE_BASE=TRUE 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0
47 46 6 NC_SMC_FAN_3_CTL NC_SMC_FAN_3_CTL 6 46 47 74 73 72 71 70 69 64 63 59 55 53 52 49
48 47 46 45 43 23 21 17 7 6 PP3V42_G3H MAKE_BASE=TRUE
74 66 65 54 51 50 49
47 46 6 NC_SMC_FAN_3_TACH NC_SMC_FAN_3_TACH 6 46 47
MAKE_BASE=TRUE 1 1
1
R5061 R5060
CRITICAL R5000 100K 10K
C5000 1 1K NC_ESTARLDO_EN NC_ESTARLDO_EN 5%
1/16W
5%
1/16W
0.1uF 47 46 6 6 46 47
20%
10V
U5000 5%
1/16W
NC_ALS_GAIN
MAKE_BASE=TRUE
NC_ALS_GAIN
MF-LF
2 402
MF-LF
2 402 TO SMC
CERM 2 NCP303LSN MF-LF 47 46 6 6 46 47
402 SOT23-5-HF 2 402 MAKE_BASE=TRUE
SMC_PROCHOT_3_3_L 46
TP_SMC_RSTGATE_L TP_SMC_RSTGATE_L OUT
47 46 46 47
D
SMC_MANUAL_RST_L
OMIT NC
5
4
CD
NC
OUT
IN
1
2
SMC_RESET_L OUT 6 46 48 66 MAKE_BASE=TRUE
6
D
1
R5001 GND SMC_BC_ACOK SMC_BC_ACOK
0
C5001 1 3
66 65 47 46
MAKE_BASE=TRUE
46 47 65 66
D Q5060
SILK_PART=SMC_RST 5% 0.01UF 50 47 46 SMC_BMON_MUX_SEL SMC_BMON_MUX_SEL 46 47 50 DMB53D0UV
1/10W 10% MAKE_BASE=TRUE
MF-LF 16V SOT-563
CERM 2 SMC_BATT_ULP_L SMC_BATT_ULP_L CPU_PROCHOT_BUF 2 G
2 603 402 65 47 46
MAKE_BASE=TRUE
46 47 65
47 46 25 20 SMC_IG_THROTTLE_L SMC_IG_THROTTLE_L 20 25 46 47
MAKE_BASE=TRUE TO CPU R5062 3
47 46 SMS_INT_L
MAKE_BASE=TRUE
SMS_INT_L 46 47
91 69 10 BI CPU_PROCHOT_L 1
3.3K 2 CPU_PROCHOT_L_R 5 Q5060 S
DMB53D0UV
D 3 5% SOT-563 1
Q5032 50 47 46 SMC_GFX_VSENSE SMC_GFX_VSENSE 46 47 50
1/16W
MF-LF 4
48 47 46 45 43 23 21 17 7 6 PP3V42_G3H SSM6N15FEAPE MAKE_BASE=TRUE 402
74 66 65 54 51 50 49 SOT563 6 D
50 47 46 SMC_CPU_HI_ISENSE SMC_CPU_HI_ISENSE
MAKE_BASE=TRUE
46 47 50 Q5059
U5001 SSM6N15FEAPE
5 51 47 46 SMC_CPUVTT_ISENSE SMC_CPUVTT_ISENSE 46 47 51 SOT563
1 SN74LVC1G02 5 G S 4 MAKE_BASE=TRUE
54 IN SMC_TPAD_RST_L SOT553-5
4 51 47 46 SMC_1V5_S3_ISENSE SMC_1V5_S3_ISENSE 46 47 51
SMC_TPAD_RST MAKE_BASE=TRUE
SMC_ONOFF_L 2 SMC_GFX_ISENSE SMC_GFX_ISENSE 1 S G 2
54 47 46 6 IN 02 50 47 46 46 47 50
MAKE_BASE=TRUE
3
SMC_PROCHOT IN 46
51 47 46 SMC_GPU_1V8_ISENSE SMC_GPU_1V8_ISENSE 46 47 51
MAKE_BASE=TRUE
91 20 10 OUT PM_THRMTRIP_L
47 46 TP_SMC_P24 TP_SMC_P24 46 47
MAKE_BASE=TRUE
47 46 6 TP_SMC_P92 TP_SMC_P92 6 46 47 3 D
MAKE_BASE=TRUE Q5059
SMC AVREF Supply 47 46 TP_SMC_PF5 TP_SMC_PF5
MAKE_BASE=TRUE
46 47 SSM6N15FEAPE
SOT563
CRITICAL
SMC_EXCARD
VR5020
C 47 46 45 43 23 21 17 7 6
74 66 65 54 51 50 49 48
PP3V42_G3H REF3333
SOT23-3 PP3V3_S5_AVREF_SMC
6 46
47 46 SMC_EXCARD_OC_L
R5095
1
0 2 EXCARD_OC_L 8 34 36
4 S G 5
SMC_THRMTRIP 46
C
OUT IN IN
1 IN OUT 2 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V 5%
1/16W
GND MF-LF
3
1 C5026 402
0.01UF
10%
16V
2 CERM
402
1 C5020 C5025 1
0.47UF 10uF
10%
6.3V
2 CERM-X5R
20%
6.3V 2
X5R
SMC G3Hot 32kHz Oscillator 48 47 46 45 43 23 21 17 7 6
74 66 65 54 51 50 49
PP3V42_G3H
402 603 To support timed wake-up events in G3Hot
54 47 46 6 SMC_ONOFF_L R5070 10K 1 2
GND_SMC_AVSS SMC_OSC_YES G3_POWERON_L R5072 10K 1 2 5% 1/16W MF-LF 402
TABLE_ALT_HEAD
46 50 51
L5010 46
SMC_LID R5071 100K 1 2

5% 1/16W MF-LF 402
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
VOLTAGE=0V PP3V42_G3H FERR-120-OHM-0.2A 54 46 45
5% 1/16W MF-LF 402
PART NUMBER 48 47 46 45 43 23 21 17 7 6
74 66 65 54 51 50 49
1 2 PP3V42_G3H_SMC_CLK_F 48 46 43 6 SMC_TX_L R5073 10K 1 2
5% 1/16W MF-LF 402
353S1381 353S1912 ALL Intersil ISL60002-33
TABLE_ALT_ITEM
0603 MIN_LINE_WIDTH=0.2 MM 48 46 43 6 SMC_RX_L R5074 100K 1 2

MIN_NECK_WIDTH=0.2 MM SMC_OSC_YES SMC_OSC_YES SYS_ONEWIRE NO STUFF R5075 2.0K 1 2 5% 1/16W MF-LF 402
VOLTAGE=3.425V 65 46
C5002 1 1 C5003 SMC_TMS R5077 10K 1 2 5% 1/16W MF-LF 402
4.7UF 0.1UF 48 46 6
5% 1/16W MF-LF 402
20%
6.3V 2
20% SMC_TDO R5078 10K 1 2
2 10V
48 46 6
CERM CERM R5079 10K 5% 1/16W MF-LF 402
SMC_TDI 1 2
SMC Crystal Circuit CRITICAL
603 402 48 46 6
48 46 6 SMC_TCK R5080 10K 1 2

5% 1/16W MF-LF 402
R5081 10K 5% 1/16W MF-LF 402
C5010 12 65 46 6 SMC_BIL_BUTTON_L 1 2
R5010 15pF VDD 66 65 47 46 SMC_BC_ACOK R5087 470K 1 2 5% 1/16W MF-LF 402
0 1 2 NO STUFF R5093 10K 5% 1/16W MF-LF 402
46 SMC_XTAL 1 2 SMC_XTAL_R U5010 47 46 SMS_INT_L 1 2
5%
5%
32.768KHZ-9-3.6V
SG-3040LC-SM R5011 65 47 46 SMC_BATT_ULP_L R5096 100K 1 2 5% 1/16W MF-LF 402
1/16W
MF-LF
CRITICAL 50V OMIT OUT SMC_CLK32K_R 1
22 2 SMC_CLK32K 5% 1/16W MF-LF 402
1 7
402 Y5010 1 CERM
402
VIO
5%
OUT 46
SMC_PA0 R5091 100K 1 2

20.00MHZ 46
B 5X3.2-SM
2 C5011 NC
NC
2
3
NC0
NC1
NC4
NC5
8
9
NC
NC
1/16W
MF-LF
402 SMC_EXCARD_NOT
5% 1/16W MF-LF 402
B
15pF 4 10 SMC_EXCARD_OC_L R5092 100K 1 2
1 2 NC NC2 NC6 NC 47 46
46 SMC_EXTAL 5% 1/16W MF-LF 402
NC 5 NC3 NC7 11 NC
5% GND
50V
CERM 6 74 46 18 SMC_ADAPTER_EN R5085 10K 1 2
402 R5086 10K 5% 1/16W MF-LF 402
46 SMC_CASE_OPEN 1 2
5% 1/16W MF-LF 402
R5012 46 34 SMC_EXCARD_CP R5088 10K 1 2

R5090 100K 5% 1/16W MF-LF 402
0 PM_SLP_S5_L 1 2
System (Sleep) LED Circuit 94 18 IN PM_CLK32K_SUSCLK 1 2
46 18
74 73 46 43 31 18 PM_SLP_S4_L R5094 100K 1 2

5% 1/16W MF-LF 402
5% 5% 1/16W MF-LF 402
1/16W
MF-LF
68 55 51 45
7 6 PP5V_S3 402
44 43 33 31
103 83 73
R50311 1
R5030
CPU PM_EXTTS_L / MEM_EVENT_L Level Shifting 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49
PP3V3_S0
523 20 MEM_EVENT_B_L R5089 10K 1 2
1% 1% 46
1/16W 1/16W 5% 1/16W MF-LF 402
MF-LF
402 2
MF-LF
2 402
R5044
0
1 2 PM_EXT_TS_L<1> OUT 10 91
SYS_LED_ILIM
5%
1/16W
101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 MF-LF
74 73 72 71 70 69 64 63 59 55 53 52 49 402
SYS_LED_L_VDIV
1 PM_EXT_TS_L<0> OUT 10 91
R5042
1 10K 6
R5032 5% TO CPU
1/16W
1.47K 6 5 4 CRITICAL 101 99 88 86 85 84 81
PP3V3_S0 MF-LF D
Q5040
A 1%
1/16W
MF-LF D B E Q5030
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49 2 402
MEM_EVENT 2
2N7002DW-X-G
SOT-363 SYNC_MASTER=K17_REF SYNC_DATE=06/17/2009 A
402 2 DMB54D0UV
R5040 1
G S
Debug Power "Buttons" PAGE TITLE
SYS_LED_L
SOT-563
10K
5% 3 1 SMC Support
1/16W SMC_ONOFF_L OUT 6 46 47 54 DRAWING NUMBER SIZE
Q1
Q2 MF-LF
402 2
D
Q5040 OMIT OMIT D
FROM DIMMS 2N7002DW-X-G 1 1 Apple Inc.
S G C 47 46 30 28 IN MEM_EVENT_A_L 5 G S
SOT-363 R5016 R5015 R
REVISION
0 0
5% 5%
1 2 3 47 46 30 28 BI MEM_EVENT_A_L 4 1/10W 1/10W NOTICE OF PROPRIETARY PROPERTY: BRANCH
MAKE_BASE=TRUE MF-LF MF-LF
603 2 2 603 THE INFORMATION CONTAINED HEREIN IS THE
TO/FROM SMC PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
SILK_PART=PWR_BTN SILK_PART=PWR_BTN THE POSESSOR AGREES TO THE FOLLOWING: PAGE
46 SMC_SYS_LED SYS_LED_ANODE 6 45
PLACEMENT_NOTE=Place R5015 on top side I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
50 OF 132
IN OUT
PLACEMENT_NOTE=Place R5016 on bottom side III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
M-ST-SM
49 47 46 45 43 23 21 17 7 6 PP3V42_G3H 31 32
74 66 65 54 51 50
102 87 73 71 70 69 55 53 42 23 8 7 6 PP5V_S0
1 2 LPC_CLK33M_LPCPLUS IN 6 27 94
94 88 46 17 6 BI LPC_AD<0> 3 4 LPC_AD<2> BI 6 17 46 88 94
94 88 46 17 6 BI LPC_AD<1> 5 6 LPC_AD<3> BI 6 17 46 88 94
7 8
48 6 IN SPI_ALT_MOSI 9 10 SPIROM_USE_MLB OUT 6 20 58
48 6 OUT SPI_ALT_MISO 11 12 SPI_ALT_CLK IN 6 48
94 88 46 17 6 IN LPC_FRAME_L 13 14 SPI_ALT_CS_L IN 6 48
46 18 6 OUT PM_CLKRUN_L 15 16 LPC_SERIRQ BI 6 17 46
47 46 6 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 6 18 46
94 88 27 6 IN LPCPLUS_RESET_L 19 20 SMC_TDI OUT 6 46 47
47 46 6 OUT SMC_TDO 21 22 SMC_TCK OUT 6 46 47
46 6 IN SMC_TRST_L 23 24 SMC_RESET_L OUT 6 46 47 66
46 6 OUT SMC_MD1 25 26 SMC_NMI OUT 6 46
47 46 43 6 IN SMC_TX_L 27 28 SMC_RX_L OUT 6 43 46 47

29 30 LPCPLUS_GPIO OUT 6 20
C 33 34 C
516S0573
SPI Bus Series Termination

SPI_ALT_MISO 6 48
SPI_ALT_MOSI 6 48
SPI_ALT_CLK 6 48
SPI_ALT_CS_L 6 48
LPCPLUS LPCPLUS LPCPLUS LPCPLUS

1 1 1 1
R5128 R5127 R5126 R5125 PLACE_NEAR=J5100.14:5mm
0 47 47 47 PLACE_NEAR=J5100.12:5mm
5% 5% 5% 5% PLACE_NEAR=J5100.9:5mm
1/16W 1/16W 1/16W 1/16W PLACE_NEAR=J5100.11:5mm
2 402 2 402 2 402 2 402
PLACE_NEAR=U1800.AV3:5mm R5110 R5120

15 47
94 17 IN SPI_CS0_R_L 1 2 94 SPI_CS0_L 1 2 SPI_MLB_CS_L OUT 58
1/16W 1/16W
B PLACE_NEAR=U1800.BA2:5mm R5111
15
MF-LF
402 R5121
47
MF-LF
402 B
94 17 IN SPI_CLK_R 1 2 94 SPI_CLK 1 2 SPI_MLB_CLK OUT 58
1/16W 1/16W
PLACE_NEAR=U1800.AY1:5mm R5112 MF-LF R5122 MF-LF
402 402
SPI_MOSI_R 1
15 2 94 SPI_MOSI 1
47 2 SPI_MLB_MOSI
94 17 IN OUT 58
1/16W 1/16W
MF-LF R5123 MF-LF
402 402
15
94 17 OUT SPI_MISO 1 2 SPI_MLB_MISO IN 58
5% PLACE_NEAR=U6100.2:5mm
1/16W
MF-LF
402
101 99 88 86 85 84
49 47 42 40 37 34 30 28 27 26 25 8 7 6PP3V3_S0
81 74 73 72 71 70 69 64 63 59 55 53 52 EFI_DEBUG
EFI_DEBUG EFI_DEBUG 1 C5101
1 1 0.1UF
R5101 R5103 20%
10V
0 0
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
8
VCC
EFI_DEBUG
2 CERM
402 EFI Debug ROM
U5101
DEBUGROM_E2 3 E2 M24M01-R SMBUS_PCH_DATA
SO8N SDA 5 BI 6 17 25 26 28 30 32 34 42 49 64
94
DEBUGROM_E1 2 E1
CRITICAL SCL 6 SMBUS_PCH_CLK
A 7 WC*
E0/NC0 1
IN 6 17 25 26 28 30 32 34 42 49 64
94
SYNC_MASTER=T22_MLB SYNC_DATE=03/30/2009 A
NC PAGE TITLE
NO STUFF NO STUFF
1
R5102 1R5104
VSS
4 LPC+SPI Debug Connector
DRAWING NUMBER SIZE
0 0
5%
1/16W
5%
1/16W Apple Inc. D
MF-LF MF-LF Write: 0xAC 0xAE REVISION
2 402 2 402 Read: 0xAD 0xAF
R

51 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH SMBus "0" Connections SMC "0" SMBus Connections SMC "Battery A" SMBus Connections
101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 48 47 46 45 43 23 21 17 7 6 PP3V42_G3H
74 73 72 71 70 69 64 63 59 55 53 52 49 74 73 72 71 70 69 64 63 59 55 53 52 49 74 66 65 54 51 50
Ibex Peak-M R52001 1

R5201 SO-DIMM "A" SMC R52501 1
R5251 GPU Temp (Ext) SMC R52801 1
R5281 Battery Charger
1K 1K 4.7K 4.7K 2.0K 2.0K
5% 5% J2900 5% 5% 5% 5%
U1800 1/16W 1/16W U4900 1/16W 1/16W EMC1414: U5550 U4900 1/16W 1/16W ISL6258 - U7000
MF-LF MF-LF (Write: 0xA0 Read: 0xA1) MF-LF MF-LF MF-LF MF-LF
(MASTER) 402 2 2 402 (MASTER) 402 2 2 402 (Write: 0x98 Read: 0x99) (MASTER) 402 2 2 402 (Write: 0x12 Read: 0x13)
94 82
52 49
48
26
42
25
34
17 6 SMBUS_PCH_CLK SMBUS_PCH_CLK 32 34 42
6 17 25 82 52 49 46 SMBUS_SMC_0_S5_SCL 46 SMBUS_SMC_0_S5_SCL SMBUS_SMC_0_S5_SCL 46 49 52 65 49 46 6 SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL 6 46 49
D
32
94
48
26
30
64
42
25
28
49
34
17 6
MAKE_BASE=TRUE
SMBUS_PCH_DATA SMBUS_PCH_DATA
26 28 30
48 49 64
32 34 42
6 17 25 82 52 49 46 SMBUS_SMC_0_S5_SDA
82 MAKE_BASE=TRUE
52 49
46 SMBUS_SMC_0_S5_SDA SMBUS_SMC_0_S5_SDA
82
46 49 52
97 66
65 49 46 6 SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA
65 66 97
6 46 49
D
32
94
30
64
28
49
MAKE_BASE=TRUE 26 28 30
48 49 64
MAKE_BASE=TRUE 82 97 66 MAKE_BASE=TRUE 65 66 97
94
VRef DACs SO-DIMM "B" GPU Temp (Int) Battery

J3100
U2900 GT216: U8000 J6955
(Write: 0x98 Read: 0x99)
(Write: 0xA4 Read: 0xA5)
(Write: 0x9E Read: 0x9F)
Battery (See Table)
94 64 49
28 26 25 17 6 SMBUS_PCH_CLK SMBUS_PCH_CLK
64 94
32 34 42
SMBUS_SMC_0_S5_SCL 52
46
Battery Manager - (Write: 0x16 Read: 0x17) SMBUS_SMC_BSA_SCL
6 17 25 6 46 49
48 42 34 32 30 26 28 30
94 48 49
49
82 Battery LED Driver - (Write: 0x36 Read: 0x37) 65 66 97
94 64 49 52
28 26 25 17 6
48 42 34 32 30
SMBUS_PCH_DATA SMBUS_PCH_DATA 32 34 42
6 17 25 SMBUS_SMC_0_S5_SDA 46
49
Battery Temp - (Write: 0x90 Read: 0x91) SMBUS_SMC_BSA_SDA 6 46 49
26 28 30 65 66 97
48 49 64 82
Margin Control CK505 (Clock)

U2901 U2700 SMC "A" SMBus Connections SMC "Management" SMBus Connections
(Write: 0x30 Read: 0x31) (Write: 0xD2 Read: 0xD3) NOTE: SMC RMT bus remains powered and may be active in S3 state
94
The bus formerly known as "Battery B"
94 64 49
28 26 25 17 6
48 42 34 32 30
SMBUS_PCH_CLK SMBUS_PCH_CLK 32 34 42
6 17 25 55 54 51 50 36 35 34 33 32 31 20 17 7 6 PP3V3_S3 99 86 84 74 73 72 58 51 50 35 31 7 6 PP3V3_S5
26 28 30 103 102 88 74 72 56 101
48 49 64
94 64 49
28 26 25 17 6
48 42 34 32 30
6 17 25
26 28 30
48 49 64
94
SMC R52701 1
R5271 Trackpad SMC R52901 1
R5291 Sensor ADC A
1K 1K 4.7K 4.7K
5% 5% 5% 5%
U4900 1/16W 1/16W J5800 U4900 1/16W 1/16W U5930
EFI Debug Serial ExpressCard Slot (MASTER)
MF-LF
402 2
MF-LF
(Write: 0x90 Read: 0x91) (MASTER)
MF-LF MF-LF
(Write: 0x10 Read: 0x11)
U5101 2 402 102
402 2 2 402
97
J3500 SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SCL 97
SMBUS_SMC_MGMT_SCL 57 49
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SCL 102
(Write: 0xAC 0xAE) 49 46 33 6 6 33 97 57 49 46 46 46 49 57
(Read: 0xAD 0xAF) (Address via ARP)
C 94 64 49
28 26 25 17 6 SMBUS_PCH_CLK SMBUS_PCH_CLK
94
32 34 42
6 17 25
97 55
49 46 33 6
97 55
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
46 49 55
97
6 33
46 49 55
102
97 57 49 46
102
SMBUS_SMC_MGMT_SDA
102 97 MAKE_BASE=TRUE
57 49
46 SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
SMBUS_SMC_MGMT_SDA
97
102
46 49 57
97
C
48 42 34 32 30 26 28 30
48 49 64
94 64 49
28 26 25 17 6
48 42 34 32 30
6 17 25
26 28 30
48 49 64
94
ALS Sensor ADC B

J3401 UC210
XDP Connectors Mikey (Write: 0x72 Read: 0x73) (Write: 0x32 Read: 0x33)
J2600 & J2650 U6800 SMBUS_SMC_A_S3_SCL 97
SMBUS_SMC_MGMT_SCL 102
6 33 46 49 57
(MASTER) (Write: 0x72 Read: 0x73) 46 49 55 97
94 SMBUS_SMC_A_S3_SDA 97
6 33 SMBUS_SMC_MGMT_SDA 102
46 49 57
49 48 42
26 25 17 6 SMBUS_PCH_CLK SMBUS_PCH_CLK 32 34 42
6 17 25 46 49 55 97
34 32 30 28 26 28 30
94 64 48 49 64
49 48 42
26 25 17 6
34 32 30 28
6 17 25
26 28 30
94 64 48 49 64
94
HDD Re-driver Control

SMC "B" SMBus Connections
U4510 88 86 85 84 81 74 73 72 71 70 69 64
PP3V3_S0
37 34 30 28 27 26 25 8 7 6
(Write: 0x94 Read: 0x95) 63 59 55 53 52 49 48 47 42 40
101 99
SMBUS_PCH_CLK 42 48 49
6 17 25 26 28
30 32 34
SMBUS_PCH_DATA
64 94
42 48 49
6 17 25 26 28 SMC R52601 1
R5261 CPU Temp
30 32 34
64 94
4.7K 4.7K
5% 5%
U4900 1/16W 1/16W EMC1414: U5570
MF-LF MF-LF
(MASTER) 402 2 2 402 (Write: 0x98 Read: 0x99)
97
52 49
97 52 49 46 SMBUS_SMC_B_S0_SCL 46 SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SCL 46 49 52
B SMBUS_SMC_B_S0_SDA
97 MAKE_BASE=TRUE
52 49
SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SDA
97
B
PCH "SMLink 0" Connections 52 49 46
97
46
MAKE_BASE=TRUE
46 49 52
97
101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49
PP3V3_S0

R5211
8.2K 8.2K
5% 5%
U1800 1/16W 1/16W
MF-LF MF-LF
(MASTER) 402 2 2 402
94 17 SML_PCH_0_CLK
MAKE_BASE=TRUE
94 17 SML_PCH_0_DATA
MAKE_BASE=TRUE
PCH "SMLink 1" Connections

101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49
PP3V3_S0
NO STUFF NO STUFF
R5221
8.2K 8.2K R5223
A U1800
5%
1/16W
MF-LF
5%
1/16W
MF-LF
05%
(Write: 0x90 Read: 0x91) 402 2 1/16W PAGE TITLE
2 402
94 17 SML_PCH_1_CLK 1
MF-LF
402
2
K17 SMBus Connections
94 17 SML_PCH_1_DATA
MAKE_BASE=TRUE
1 2
Apple Inc. D
R5222 R
REVISION
0
5%
1/16W
MF-LF
SMLink 1 is slave port to 402 THE INFORMATION CONTAINED HEREIN IS THE
access PCH & CPU via PECI. I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 52 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU Voltage Sense / Filter PBUS Voltage Sense & Filter
PLACE_NEAR=U4900.M11:10mm DCIN Current Sense Filter
XW5309 R5309
69 15 12 7 6 PPVCORE_S0_CPU SM
Q5315
4.53K
1 2 CPUVSENSE_IN 1 2 SMC_CPU_VSENSE OUT 46 FDG6332CG PLACE_NEAR=U4900.N12:10mm
SC70-6
1%
Place short near U1000 center 1/16W P-CHN R5380
MF-LF 1
C5309 83 71 70 68 67 66 50 40 8 7 6 PPBUS_G3H 4.53K
SMC_DCIN_ISENSE
402
0.22UF
87
4 S D 3 PPBUS_G3H_VSENSE
66 IN CHGR_AMON 1 2
OUT 46
20% 1%
6.3V MIN_LINE_WIDTH=0.20 mm
2 PLACE_NEAR=U4900.M11:10mm MIN_NECK_WIDTH=0.20 mm 1/16W
X5R
402 1
VOLTAGE=6V
1
MF-LF 1
C5380
R5315 G R5385 PLACE_NEAR=U4900.M13:10mm 402
0.22UF
20% PLACE_NEAR=U4900.N12:10mm
GND_SMC_AVSS 46 47 50 51 100K 5 12.7K 6.3V
5% 1% 2 X5R
1/16W 1/16W
D GPU Voltage Sense / Filter

MF-LF
402
2
MF-LF
402
2
Rthevenin = 4504 ohms
402
GND_SMC_AVSS 46 47 50 51
D
PLACE_NEAR=U4900.N11:10mm PBUSVSENS_EN_DIV SMC_PBUS_VSENSE OUT 46
XW5359 R5359
83 76 7 6 PPVCORE_GPU SM
1 2 GPUVSENSE_IN 1
4.53K
2 SMC_GPU_VSENSE OUT 46
R5316 1 R5386 1 1
C5385
100K 6.98K 0.22UF
1% 5% 1%
20% PLACE_NEAR=U4900.M13:10mm
Place short near U8000 center 1/16W 1/16W 1/16W
MF-LF
402
1
C5359 MF-LF MF-LF 2
6.3V
X5R
402 402
0.22UF 2 2 402
20%
6.3V PLACE_NEAR=U4900.M13:10mm
2 X5R
PBUSVSENS_EN_L GND_SMC_AVSS 46 47 50 51
402 PLACE_NEAR=U4900.N11:10mm
6
CPU VCore High Side Current Sensor
D
PP3V42_G3H
N-CHN
Q5315 48 47 46 45 43 23 21 17 7 6
74 66 65 54 51 50 49
GFX Voltage Sense / Filter 74 73 PM_SLP_S3_L_R 2 G FDG6332CG
SC70-6 1 C5388
PLACE_NEAR=U4900.K9:10mm S
Enables PBUS VSense divider when high.
70 24 13 7 PPVCORE_S0_GFX
XW5399
SM R5399 1
0.1UF
20%
GFXVSENSE_IN
1 2 1
4.53K2 SMC_GFX_VSENSE 2 10V
CERM
3
OUT 46 47
402
PLACEMENT_NOTE=Place near U1000 1% 69 7 6 OUT PPBUS_CPU_IMVP_ISNS V+
1/16W PLACE_NEAR=U4900.L7:10mm
MF-LF
402
1 C5399 OMIT U5388
0.22UF R5335
20%
6.3V R5388 1 3 99 ISNS_CPU_N
5 IN-
INA213 6 CPUVCORE_HISIDE_IOUT 1
4.53K
2 X5R PLACE_NEAR=U4900.K9:10mm SC70 OUT 2 SMC_CPU_HI_ISENSE OUT 46 47
402
0.001
1% 1%
1W 1/16W
GND_SMC_AVSS 46 47 50 51 MF 99 ISNS_CPU_P 4 IN+ REF 1 MF-LF 1
C5335
1206 GAIN: 50X 402
2 4 0.22UF
20%
PLACE_NEAR=U4900.L7:10mm
83 71 70 68 67 66 50 40 8 7 6
87 IN PPBUS_G3H GND 2
6.3V
X5R
2
C 1
CRITICAL
C5300 1
CRITICAL
C5301 1
CRITICAL
C5302 1
CRITICAL
C5303 1
CRITICAL
C5304 1
CRITICAL
C5305 1
CRITICAL
C5306
402
C
100UF 100UF 68UF 68UF 68UF 68UF 68UF
20% 20% 20% 20% 20% 20% 20%
2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V
TANT TANT POLY-TANT POLY-TANT POLY-TANT POLY-TANT POLY-TANT
BMON Current Sense - Entire circuit must be near SMC (U4900) D-HF D-HF CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM
48 47 46 45 43 23 21 17 7 6 PP3V42_G3H
74 66 65 54 51 50 49 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
BMON_ENG
BMON_ENG 1 C5369 102S0858 1 RES,1/2W,1%,0.010 OHM,SMD R5388
BMON_ENG U5313 10V
0.1uF
20%
NC7SB3157P6XG 2 CERM
1 C5318 SC70 SEL
BMON_INA_OUT 1 B1 6 SMC_BMON_MUX_SEL 402 CPU VCore Load Side Current Sense / Filter
0.1uF IN 46 47
20% BMON_ENG PP3V3_S3
3
54 51 50 49 36 35 34 33 32 31 20 17 7 6
2 10V
CERM
1 103 102 88 74 72 56 55
REGULATOR SIDE: 402 V+ 2 5 1
GND VCC C5354
U5323 R5391 0.1UF
20%
CHGR_CSO_R_P
INA214
CHGR_BMON 3
0
4 BMON_AMUX_OUT 145.3K2 SMC_BATT_ISENSE CRITICAL 2
10V
OUT 6 U5350
5 IN- CERM
99 66 OUT SC70 66 IN OUT 46
R5350 402
B0 A
VER 1 BMON_ENG 1/16W
1%
CPUIMVP_IMON 1
6.65K
2 CPUISENS_P 1 5 OPA333DCKG4
99 66 IN CHGR_CSO_R_N 4 IN+ REF 1 1
R5371 MF-LF 1 C5390 91 69 12 IN + SC70-5 R5353 PLACE_NEAR=U4900.N10:5mm
402
0.022UF 1% V+ 4
4.53K
BMON_PROD 100K 10%
1/16W CPUVCORE_IOUT 1 2 SMC_CPU_ISENSE OUT 46
LOAD SIDE: GND R5330 5%

1/16W 2 16V
CERM-X5R
MF-LF
402
V- 1%
2
0 1 MF-LF 402
3
-
1/16W
2
2402 R5351 2 MF-LF

402
1
C5353
5% 10K 0.22UF
1/16W PLACE_NEAR=U4900.N13:10mm 1 2 CPUISENS_N 20%
Gain: 3x
MF-LF 2
6.3V
Monitors battery discharge 402 1%
1/16W
X5R
402
GAIN: 100X MF-LF
R5352
current from battery to PBUS 402 GND_SMC_AVSS 46 47 50 51
B 1
20.0K
2 B
GND_SMC_AVSS 46 47 50 51 1%
1/16W SIGNAL_MODEL=EMPTY
MF-LF
INA214 has gain of 100V/V 402 NO STUFF

C5357
U5303 only senses current up to 6.6A 470PF
1 2
10% SIGNAL_MODEL=EMPTY
50V
CERM
402
GFX/AXG Current Sense
54 51 50 49 36 35 34 33 32 31 20 17 7 6 PP3V3_S3
103 102 88 74 72 56 55
PCH VCore Current Sense 1 C5344

0.1UF
20%
101 99
PP3V3_S5
CRITICAL 2
10V
51 49 35 31 7 6
86 84 74 73 72 58
DEBUG_ADC R5342 U5340 CERM
402
PLACE_NEAR=U4900.L12:10mm
6.65K2 5 OPA333DCKG4
1 C5320 99 70 IN GFXIMVP_CS_R_P 1 99 GFX_ISNS_R_P 1 + SC70-5 R5379
0.1UF 1% V+ 4.53K
20%
10V
1/10W 4 GFXIMVP_ISNS_IOUT 1 2 SMC_GFX_ISENSE OUT 46 47
2 MF-LF
CERM 603 1%
402 3 V-
CRITICAL R5341 - GAIN: 150X
1/16W
MF-LF
3
DEBUG_ADC PCH VCore Current Sense Filter 6.65K2

2 402 1 C5379
V+ PLACE_NEAR=UC210.23:10mm GFXIMVP_CS_R_N 1 99 GFX_ISNS_R_N 0.22UF
99 70 IN 20%
DEBUG_ADC PLACE_NEAR=U4900.L12:10mm
U5305 R5370 1%
1/10W
2
6.3V
X5R
INA210 4.53K MF-LF SIGNAL_MODEL=EMPTY 402
99 8 IN NC_ISNS_P1V05S0PCH_N
5 IN- SC70 OUT 6 PCHCORE_IOUT 1 2 ADC2_CH1 OUT 102 603
R5343
1% DEBUG_ADC NO STUFF 1 1M
1/16W C5340 1 R5340 1 2
99 8 IN NC_ISNS_P1V05S0PCH_P
4 IN+ REF 1 MF-LF 1
C5370 470PF 1M
1%
A GND
GAIN: 200X
402
0.22UF
20%
6.3V
10%
50V
CERM 2
1%
1/16W
MF-LF
1/16W
MF-LF NO STUFF
402 SIGNAL_MODEL=EMPTY
2 X5R 402 2 402 PAGE TITLE
PLACE_NEAR=UC210.23:10mm
2
402
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
C5343
470PF
Current & Voltage Sensing
1 2 DRAWING NUMBER SIZE
Apple Inc. D
10% REVISION
50V R
CERM
402
53 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_S5 Current Sense GPU VCore Current Sense
PP3V42_G3H CRITICAL
48 47 46 45 43 23 21 17 7 6
74 66 65 54 50 49
DEBUG_ADC GPU VCore Current Sense Filter
1 C5401 R5409 U5410
2.87K 8 OPA2333 PLACE_NEAR=U4900.L10:10mm
0.1UF
20%
83 IN GFXIMVP6_IMON1 2 99 GPUISENS_P DFN R5411
5
10V
2 1% V+ 4.53K
CRITICAL CERM
402 PP3V3_S5 Current Sense Filter 1/16W
MF-LF
7 GPUVCORE_IOUT 1 2 SMC_GPU_ISENSE OUT 46
402 6 V- 1%
3
DEBUG_ADC PLACE_NEAR=UC210.24:5mm
1/16W
V+ R5410 THRM
4 MF-LF
402
1
C5408
84 74 73 72 58 51 50 49 35 31 7 6 OUT PP3V3_S5 DEBUG_ADC 10K 9 0.22UF PLACE_NEAR=U4900.L10:10mm
101 99 86
CRITICAL U5405 R5402 1 2 99 GPUISENS_N Gain: 1.4x 20%
D R5401 2 4
ISNS_PP3V3_S5_N 5 IN-
INA214
6 3V3_S5_IOUT 1
4.53K
2 ADC2_CH2
1%
2
6.3V
X5R
402
D
SC70 OUT
102 1/16W
0.002 OUT MF-LF
1% 1% DEBUG_ADC 402 GND_SMC_AVSS 46 47 50 51
1W 1/16W
99 MF ISNS_PP3V3_S5_P 4 IN+ REF 1 MF-LF 1
C5402 R5412
0612 402 4.02K
1 3 0.22UF 1 2
67 7 IN PP3V3_S5_ISNS_R GND
20%
6.3V
Gain: 100x 2 X5R PLACE_NEAR=UC210.24:5mm
1%
1/16W SIGNAL_MODEL=EMPTY
2
402 MF-LF
402
NO STUFF
C5407
470PF
1 2
10%
50V SIGNAL_MODEL=EMPTY
CERM
402
PP5V_S3 Current Sense

GPU VCore Current Sense and GPU 1.8V Current Sense share
99 86 84 74 73 72 58 51 50 49 35 31 7 6
101
PP3V3_S5
DEBUG_ADC
dual package opamp U5410
1 C5403
0.1UF
20%
2 10V PP5V_S3 Current Sense Filter
CERM
CRITICAL 402
3
DEBUG_ADC
V+ PLACE_NEAR=UC210.1:5mm GPU 1.8V Current Sense
73 68 55 47 45 44 43 33 31 7 6 PP5V_S3 DEBUG_ADC
103 83 OUT
CRITICAL U5421 R5404
1 3 ISNS_PP5V_S3_N INA213 PP3V3_S5
R5403 5 IN- 6 5V_S3_IOUT 14.53K2 ADC2_CH3 99 86 84 74 73 72 58 51 50 49 35 31 7 6
SC70 OUT 102 101

0.002 OUT
1% 1% 1 C5410
C 99
1/4W
MF ISNS_PP5V_S3_P4 IN+
1206 2 4 REF 1
1/16W
MF-LF
402
DEBUG_ADC
1 C5404 0.1UF
20%
C
0.22UF 2 10V
PP5V_S3_ISNS_R 20% CERM
2 6.3V
67 7 IN GND Gain: 50x 402
X5R PLACE_NEAR=UC210.1:5mm
402 PP1V8_S0GPU_ISNS_R CRITICAL GPU 1.8V Current Sense Filter
2
87 7 6 IN
R5415
U5410
8 OPA2333 PLACE_NEAR=U4900.L8:10mm
1 3 3.09K R5418
R5413 ISNS_P1V8GPU_P 1 2 ISNS_P1V8GPU_R_P3 DFN
0.001 1%
V+ 1 1V8_S0GPU_IOUT 1
4.53K
2 SMC_GPU_1V8_ISENSE OUT 46 47
1% 1/16W
1W MF-LF 2 V- 1%
MF 402 1/16W
1206
2 4
R5414 THRM
4 MF-LF 1
C5411
3.09K 402
99 ISNS_P1V8GPU_N 1 2 99 ISNS_P1V8GPU_R_N 9 0.22UF
20% PLACE_NEAR=U4900.L8:10mm
79 78 77 76 8 7 6 OUT PP1V8_S0GPU_ISNS 1% Gain: 324x 2
6.3V
X5R
1/16W
MF-LF 402
402
1.5V S3 Current Sense NO STUFF 1

C5409 1 R5416
1M R5417
470PF 1% 1M SIGNAL_MODEL=EMPTY
10% 1/16W 1 2
PP3V3_S3 50V
55 54 50 49 36 35 34 33 32 31 20 17 7 6 CERM 2 MF-LF
103 102 88 74 72 56
402 2 402
1%
1/16W
NO STUFF
1 C5440 SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY MF-LF C5412
402 470PF
0.1UF
20% 1 2
10V
2 CERM
R5444 402 10% SIGNAL_MODEL=EMPTY
99 68 ISNS_1V5_S3_P 1
3.40K2
99 ISNS_1V5_S3_R_P CRITICAL 1.5V S3 Current Sense Filter 50V
CERM
IN 402
1% U5440
1/16W 5 OPA333DCKG4 PLACE_NEAR=U4900.L8:10mm
MF-LF 1
402 + SC70-5 R5440
V+ 4.53K
4 ISNS_1V5_S3_IOUT 1 2 SMC_1V5_S3_ISENSE 46 47
B R5443 3
-
V- 1%
1/16W
OUT
B
2 MF-LF 1
C5490
3.40K2 Gain: 294x 402
99 68 IN ISNS_1V5_S3_N 1 99 ISNS_1V5_S3_R_N 0.22UF
20% PLACE_NEAR=U4900.L8:10mm
1%
1/16W
2
6.3V
X5R GPU 1.05V Current Sense
MF-LF 402
402 99 86 84 74 73 72 58 51 50 49 35 31 7 6 PP3V3_S5
GND_SMC_AVSS 46 47 50 51 101 DEBUG_ADC
NO STUFF 1 1 C5423
C5442 1 R5442 R5441
0.1UF
470PF 1M 1
1M
2 SIGNAL_MODEL=EMPTY CRITICAL 20%
10% 1% 10V
1/16W PP1V05_S0GPU DEBUG_ADC 2
3
50V 82 80 77 75 7 6 OUT CERM
CERM 2 MF-LF 1%
NO STUFF 402 PLACE_NEAR=UC210.22:5mm
2 402
1/16W V+
402 MF-LF
402 C5441 DEBUG_ADC
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY 470PF CRITICAL U5423 R5430
1 2
R5419 1 3
ISNS_PP1V05_N INA213 4.53K
0.005
5 IN- SC70 OUT 6 1V05_GPU_IOUT 1 2 ADC2_CH0 OUT 102
10% 1% 1% DEBUG_ADC
50V SIGNAL_MODEL=EMPTY 1/4W 1/16W
CERM
402
99 MF-HF ISNS_PP1V05_P 4 IN+ REF 1 MF-LF 1
C5430
1206 402
2 4 0.22UF
20%
GND 2
6.3V
87 7 PP1V05_S0GPU_ISNS_R Gain: 50x X5R PLACE_NEAR=UC210.22:5mm
IN
2
402
CPUVTT 1.05V Current Sense

PLACE_NEAR=U4900.M9:10mm
R5499
0
A 71 IN CPUVTTS0_IMON 1
5%
2 SMC_CPUVTT_ISENSE OUT 46 47
SYNC_MASTER=K17_CHENGD SYNC_DATE=06/04/2009 A
1/16W PAGE TITLE
MF-LF
402
1 C5499 Current Sensing
0.022UF
10% PLACE_NEAR=U4900.M9:10mm DRAWING NUMBER SIZE
2 16V
CERM-X5R
402 Apple Inc. D
REVISION
GND_SMC_AVSS 46 47 50 51 R

54 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CPU Proximity/CPU Die/PCH Proximity/Battery Charger Proximity

R5570
101 99 88 86 85 84 81
PP3V3_S0 1
47 2 PP3V3_S0_CPUTHMSNS_R
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49 MIN_LINE_WIDTH=0.25 mm
1/16W
MF-LF
0.1uF R55711 1
402 1 20% R5572
VDD 2 10V
CERM 10K 10K
402 5% 5%
U5570 1/16W
MF-LF
1/16W
MF-LF
PLACE_NEAR=U5570.2:5mm EMC1414-A 402 2 2 402
PLACE_NEAR=U5570.3:5mm MSOP
99 9 CPU_THERMD_P 2 DP1 THERM*/ADDR 7 CPUTHMSNS_THM_L
BI
SIGNAL_MODEL=EMPTY
Detect CPU Die Temperature

C5571 1 3 DN1 ALERT* 8 CPUTHMSNS_ALERT_L
0.0022uF CRITICAL
4 DP2/DN3 9
10%
50V SMDATA SMBUS_SMC_B_S0_SDA BI 46 49 97
CERM 2
402 5 DN2/DP3 SMCLK 10 SMBUS_SMC_B_S0_SCL 46 49 97
CPU_THERMD_N BI
99 9 BI GND
6
Detect Battery Charger Proximity Temperature
99 CPUTHMSNS_D2_P Placement note:
C Q5502 SIGNAL_MODEL=EMPTY
Place U5570 under CPU
C
BC846BMXXH 2 3
SOT732-3 C5590 1
1 Q5504 1 0.0022uF
10%
Placement note: BC846BMXXH
SOT732-3
50V
CERM 2
Place Q5502 on bottom side 2 402
3
close to battery charger circuit 99 CPUTHMSNS_D2_N Write Address: 0x98
Read Address: 0x99
Detect PCH Proximity Temperature PLACE_NEAR=U5570.4:5mm
Placement note:
Place Q5504 under PCH
Note: EMC1414 can perform Beta

Compensation for External Diode 1 only
B B
GPU Proximity/GPU Die/Left Heat Pipe/Right Fin Stack
R5550
47
101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 1 2 PP3V3_S0_GPUTHMSNS_R
74 73 72 71 70 69 64 63 59 55 53 52 49 MIN_LINE_WIDTH=0.38 mm
1/16W
MF-LF
402 0.1uF
20%
2 10V
CERM
R55511 1
R5552
99 81 80 BI GPU_TDIODE_P PLACE_NEAR=U5550.3:5mm 402 10K 10K
1 5% 5%
1/16W 1/16W
SIGNAL_MODEL=EMPTY VDD MF-LF MF-LF
402 2 2 402
Detect GPU Die Temperature C5551 1
U5550
0.0022uF EMC1414-A
10%
50V MSOP
CERM 2 2 DP1 THERM*/ADDR 7 GPUTHMSNS_THM_L
402
99 81 80 GPU_TDIODE_N 3 DN1 ALERT* 8 GPUTHMSNS_ALERT_L

BI
Detect Right Fin Stack Temperature
GPUTHMSNS_D_P CRITICAL
4 DP2/DN3 9 SMBUS_SMC_0_S5_SDA
99 SMDATA BI 46 49 82
Q5501 3 SIGNAL_MODEL=EMPTY 5 DN2/DP3 SMCLK 10 SMBUS_SMC_0_S5_SCL BI 46 49 82

BC846BMXXH 2
SOT732-3
Q5503 1 C5552 1 GND
1 0.0022uF 6
BC846BMXXH 10%
Placement note: SOT732-3
2
50V
CERM 2
Place Q5501 on bottom side 402
A close to the right fin stack
3
99 GPUTHMSNS_D_N Placement note:
Place U5550 near GPU
Detect Left Heat Pipe Temperature PAGE TITLE
Placement note: PLACE_NEAR=U5550.5:5mm Thermal Sensors
DRAWING NUMBER SIZE
Place on top side under left heat pipe near GPU
Write Address: 0x98 Apple Inc. D
REVISION
Read Address: 0x99 R

55 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C Left Fan Right Fan C

102 87 73 71 70 69 55 53 48 42 23 8 7 6 PP5V_S0 102 87 73 71 70 69 55 53 48 42 23 8 7 6 PP5V_S0
101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49
PP3V3_S0 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49
PP3V3_S0
CRITICAL CRITICAL
J5650 J5660
R5650 1 78171-0004
M-RT-SM
R5660 1 78171-0004
M-RT-SM
47K 5 47K 5
5% 5%
1/16W 1/16W
MF-LF MF-LF
R5655 402 2 1 R5665 402 2 1
SMC_FAN_0_TACH 1
47K 2 6 FAN_LT_TACH 2 SMC_FAN_1_TACH 1
47K 2 6 FAN_RT_TACH 2
46 OUT 46 OUT
5% 3 5% 3
1/16W 1/16W
MF-LF 4 MF-LF 4
402 402
R56511 6 R56611 6
100K 100K
5% 5 5% 2
1/16W Q5660 1/16W Q5660
MF-LF
402 2 G 2N7002DW-X-G
SOT-363
518S0521 MF-LF
402 2 G 2N7002DW-X-G
SOT-363
518S0521
46 IN SMC_FAN_0_CTL 4 S D 3 6 FAN_LT_PWM 46 IN SMC_FAN_1_CTL 1 S D 6 6 FAN_RT_PWM
B B
PAGE TITLE
Fan Connectors
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

56 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KEYBOARD CONNECTOR
PSOC USB CONTROLLER TMP102
IC PIN NAME CURRENT
V+ 10UA
R_SNS
2.55 KOHM
V_SNS
0.0255 V
POWER
0.255E-6 W
CRITICAL
J5713
80UA 0.204 V 16.32E-6 W APN 518S0637
3V3 LDO VDD 60MA MAX 10 OHM 0.6 V 36E-3 W NC 32
USB INTERFACES TO MLB
TRACKPAD PICK BUTTONS VOUT 60MA MAX 0.2 OHM 0.012 V 0.72E-3 W
SPI HOST TO Z2 KEYBOARD SCANNER PSOC VDD 8MA (TYP) 1.5 OHM 0.012 V 96E-6 W 54 51 50 49 36 35 34 33 32 31 20 17 7 6
PP3V3_S3
30
D 14MA (MAX) 0.021 V 294E-6 W
103 102 88 74 72 56 55
WS_KBD1
29 D
PP3V3_S3_PSOC 54 54 6
28
18V BOOSTER VIN 4MA (MAX) 4.7 OHM 0.0188 V 75.2E-6 W WS_KBD2
WS_KBD23 6 54
WS_KBD22 6 54
WS_KBD21 6 54
WS_KBD20 6 54
WS_KBD19 6 54
WS_KBD18 6 54
54 6
27
54 6 WS_KBD3 26
55 6 PICKB_L WS_KBD4
54 6
BUTTON_DISABLE 25
54
54 6 WS_KBD5 24
55 Z2_HOST_INTN WS_KBD6
54 6
WS_LEFT_SHIFT_KEY 23
54
54 6 WS_KBD7 22
54 WS_LEFT_OPTION_KEY WS_KBD8
54 6
21
PSOC PROGRAMMING CONNECTOR TPAD_DEBUG 54 6 WS_KBD9
CRITICAL 20
56
55
54
53
52
51
50
49
48
47
46
45
44
43
TEST POINTS ARE FOR ON BOARD PROGRAMMING APN 518S0430 54 6 WS_KBD10 19
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
J5702 R5714 54 6 WS_KBD11 18
FH19C-4S-0.5SH25 WS_KBD15_C 1 470 2
54 6 WS_KBD12 17
54 WS_CONTROL_KEY 1
P2_3 P2_2 42 WS_KBD17 6 54 F-RT-SM1 54
WS_KBD13
5 54 6
16
55 6 Z2_KEY_ACT_L 2
P2_1 P2_0 41 WS_KBD16N 54 NC 1%
1/16W WS_KBD14
54 6
55 6 Z2_BOOT_CFG1 3
P4_7 CRITICAL P4_6 40 WS_KBD15_C 54 MF-LF 15
103 PP3V3_S3 1 402 6 WS_KBD15_CAP
TP_P4_5
Z2_DEBUG3
4
5
P4_5 U5701 P4_4 39
38
WS_KBD14 6 54
WS_KBD13 6 54
36 35 34 33 32 31 20 17 7 6
102 88 74 72 56 55 54 51 50 49
2 6 WS_KBD16_NUM
14
13
55 6 P4_3 CY8C24794 P4_2
ISSP_SCLK_P1_1 3 54 6 WS_KBD17 12
Z2_RESET 6
P4_1 MLF P4_0 37 WS_KBD12 6 54 54 6 ISSP CLOCK
6 WS_KBD18
55 6
PSOC_MISO 7
P3_7 (SYM-VER2) P3_6 36 WS_KBD11 6 54 54 6 ISSP_SDATA_P1_0 4 ISSP DATA R5715 54
11
6 WS_KBD19
55 6
10K
PSOC_F_CS_L 8
P3_5 APN 337S2983 P3_4 35 WS_KBD10 6 54 54 WS_KBD16N 1 2 54
10
6 WS_KBD20
55 6
6 54
9
PSOC_MOSI 9 P3_3 P3_2 34 WS_KBD9 6 54 NC 1%
6 WS_KBD21
55 6
OMIT 1/16W 54
PSOC_SCLK 10 33 WS_KBD8 6 54 MF-LF 8
55 6 P3_1 P3_0 6 WS_KBD22
Z2_MISO 11
P5_7 P5_6 32 WS_KBD7 6 54
402
R5710 54
7
6 WS_KBD23
55 6
54
Z2_CS_L 12 31 WS_KBD1 6 54 1K 6
55 6 P5_5 P5_4 47 46 6 SMC_ONOFF_L 1 2 6 WS_KBD_ONOFF_L
OUT 5
55 Z2_MOSI 13
P5_3 P5_2 30 WS_KBD2 6 54 5% 47 46 45 43 23 21 17 7 PP3V42_G3H
6
Z2_SCLK 14 29 WS_KBD3 6 54 1/16W 74 66 65 54 51 50 49 48 4
55 P5_1 P5_0
P7_7
P7_0
P1_0
P1_2
P1_4
P1_6
15 P1_7
16 P1_5
17 P1_3
18 P1_1
MF-LF WS_LEFT_SHIFT_KBD
C 402
54 6
3
C
19 VSS
22 VDD
THRML 1 C5710 WS_LEFT_OPTION_KBD

20 D+
21 D-
54 6
57 2
PAD 0.1UF 54 6 WS_CONTROL_KBD
20% PLACE_NEAR=J5713.5:2mm 1
23
24
25
26
27
28
2 10V
CERM PLACE_NEAR=R5710.1:2mm
402
TP_PSOC_SCL WS_KBD4 6 54
ISOLATION CIRCUIT NC 31
F-RT-SM
FF14-30A-R11B-B-3H
WS_KBD5 6 54 49 48 47 46 45 43 23 21 17 7 6 PP3V42_G3H C5725
74 66 65 54 51 50
WS_KBD6 6 54 0.1UF
TP_PSOC_SDA
ISSP_SDATA_P1_0 6 54
CRITICAL
2
20%
10V
1
SMC_MANUAL_RESET LOGIC
ISSP SDATA/I2C SDA 5 TC7SZ08AFEAPE
103PP3V3_S3 2 SOT665 CERM
50 49 36 35 34 33 32 31 20 17 7 6
102 88 74 72 56 55 54 51 A 402 48 47 46 45 43 23 21 17 7 6 PP3V42_G3H
NC_PSOC_P1_3 4 WS_LEFT_SHIFT_KEY 54 74 66 65 54 51 50 49
6
Z2_CLKIN 6 55
WS_LEFT_SHIFT_KBD 1
U5725 Y 1 C5758
54 6 B 0.1UF
10%
3 2 16V
X7R-CERM
402
TP_P7_7
54 6 ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL C5726
0.1UF
48 47 46 45 43 23 21 17 7 6 PP3V42_G3H 2 1
74 66 65 54 51 50 49
APN 311S0406
20%
CRITICAL 10V CRITICAL
R5701 5 TC7SZ08AFEAPE CERM
103 PP3V3_S3 2 SOT665 402 5
SN74LVC1G10
USB_TPAD_P 1
24 2 USB_TPAD_R_P
49 36 35 34 33 32 31 20 17 7 6
102 88 74 72 56 55 54 51 50 A
4 WS_LEFT_OPTION_KEY 54 54 6 WS_LEFT_SHIFT_KBD 1 A SC70
93 36 BI U5726 Y WS_LEFT_OPTION_KBD 4
5%
1/16W
PP3V3_S3_PSOC 54 54 6 WS_LEFT_OPTION_KBD 1 B
54 6
WS_CONTROL_KBD
U5703Y
3 B 47
MF-LF
54 6 6
C SMC_TPAD_RST_L
402 3
B TO MLB CONNECTOR
2
B
R5702
USB_TPAD_N 1
24 2 USB_TPAD_R_N
93 36 BI C5727 1
5%
1/16W 0.1UF R5769 1
R5770 1
R5771
MF-LF PP3V42_G3H 2 1 33K 33K
402 49 48 47 46 45 43 23 21 17 7 6 5% 33K
74 66 65 54 51 50 5% 5%
1/16W 1/16W
MF-LF 1/16W
20% MF-LF
CRITICAL 10V 2 402
MF-LF
5 TC7SZ08AFEAPE CERM 2 402 402
49 36 35 34 33 32 31 20 17 7 6
PP3V3_S3 2 A
SOT665
402
2
103 102 88 74 72 56 55 54 51 50
4 WS_CONTROL_KEY 54
U5727 Y
54 6 WS_CONTROL_KBD 1 B
3
U5701 CHIP DECOUPLING
PLACE C5701, C5702 & C5703 PLACE C5704, C5705 & C5706
CLOSE TO U5701VDD
PIN 22 CLOSE TO U5701 VDD PIN 49
TPAD BUTTONS DISABLE
R5704 BUTTON_DISABLE PLACE THESE COMPONENTS CLOSE TO J5800
PP3V3_S3_PSOC 1
1.5 2 PP3V3_S3 54
54 MIN_LINE_WIDTH=0.50MM 6 7 17 20 31 32 33 34 35 36 49 50 51 54
VOLTAGE=3.3V 5%
55 56 72 74 88 102 103
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
1/16W
MF-LF
1 C5701 1 C5702 1 C5703 1 C5704 1 C5705 1 C5706 402
4.7UF 100PF 0.1UF 100PF 0.1UF 4.7UF
20%
6.3V
5%
50V
10%
16V
5%
50V
10%
16V
20%
6.3V
Q5701
2 X5R 2 CERM 2 X7R-CERM 2 CERM 2 X7R-CERM 2 X5R SSM3K15FV D 3
603 402 402 402 402 603 SOD-VESM-HF
PAGE TITLE
THE TPAD BUTTONS WILL BE DISABLE
SMC_LID
1 G S 2 WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
WELLSPRING 1
47 46 45 DRAWING NUMBER SIZE
IN
LID CLOSE => SMC_LID_LC < 0.50V
Apple Inc. D
REVISION
R

57 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION
- DROOP LINE REGULATION
D
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
D
- STARTUP TIME LESS THAN 2MS
PP5V_S3 APN 152S0504 - R5812,R5813,C5818 MODIFIED
103 83 73 68 51 47 45 44 43 33 31 7 6
CRITICAL
L5801
IPD FLEX CONNECTOR
3.3UH-870MA D5802 R5806
R5805
2
SOD-323
PP18V5_S3_SW 0 PP18V5_S3
1/16W
MF-LF
INPUT_SW 1 2 BOOST_SW 1 2 MIN_LINE_WIDTH=0.50MM 1 2
402
6 55
5%
APN 516S0689
0
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.50MM
0.50MM VLF3010AT-SM-HF VOLTAGE=18.5V 5% MIN_NECK_WIDTH=0.20MM
0.20MM MIN_NECK_WIDTH=0.20MM B0520WSXG 1/16W VOLTAGE=18.5V
APN 371S0313 MF-LF
1
SWITCH_NODE=TRUE 402 CRITICAL
1
MIN_LINE_WIDTH=0.50MMPP5V_S3_BOOSTER
R5812 J5800
1 C5818 1M 55560-0228
1 C5800 39PF 1% M-ST-SM
VOLTAGE=5V 1/16W
5%
0.1UF MF-LF TPAD_GND_F
2
20%
APN 353S1401 2
50V
CERM 2 402 55 6
2 1
2 10V
CERM VIN
402
54 6 Z2_CS_L
4 3 Z2_KEY_ACT_L 6 54
402
54 6 Z2_DEBUG3
6 5 Z2_RESET 6 54
1
U5805 4 BOOST_FB
1 C5819 PSOC_F_CS_L 6 54
54 Z2_MOSI
L FB 8 7
TPS61045
1UF
54 6 Z2_MISO PICKB_L 6 54
10% 10 9
QFN 25V
3 5 2 PSOC_MISO 6 54
54 Z2_SCLK
X5R 12 11
DO CTRL Z2_BOOST_EN 603-1
6 55
CRITICAL 55 6 Z2_BOOST_EN
14 13 PSOC_MOSI 6 54
SW 8 1
R5813 54 Z2_HOST_INTN
16 15 PSOC_SCLK 6 54
PGND
71.5K Z2_BOOT_CFG1 18 17 SMBUS_SMC_A_S3_SDA 6
GND
THRML 54 6 33 46 49
1% 97
PAD 1
R5811 1/16W 54 6
Z2_CLKIN 20 19 SMBUS_SMC_A_S3_SCL
MF-LF
1 C5816 1 C5817 100K 33 32 31 20 17 7 6 PP3V3_S3 PP18V5_S3 6 55
6
22 21
7
9
2 402 54 51 50 49 36 35 34
103 102 88 74 72 56
0.1UF 2.2UF 1%
1/16W
10% 10%
16V 16V MF-LF
2 X7R-CERM 2 X5R 2 402
C R5801
0
402 603
C
1 2 55 6 TPAD_GND_F
VOLTAGE=0V
5% MIN_LINE_WIDTH=0.50MM
1/10W MIN_NECK_WIDTH=0.20MM
MF-LF
603
B B
Keyboard LED Driver

PP3V3_S0 CRITICAL
101 99 88 86 85 84
48 47 42 40 37 34 30 28 27 26 25 8 7 6 102 87 73 71 70 69 53 48 42 23 8 7 6 PP5V_S0
81 74 73 72 71 70 69 64 63 59 53 52 49
L5850 HF APN 152s0898 J5815 pin 1 is grounded
10UH-0.58A-0.35OHM CRITICAL
on keyboard backlight flex
To detect Keyboard backlight, SMC will R58531 1 2 KBDLED_SW
MIN_LINE_WIDTH=0.3 MM J5815
470K 1098AS-SM
tristate SMC_SYS_KBDLED: 5%
1/16W
1 C5850
1UF
SWITCH_NODE=TRUE
FF18-4A-R11AD-B-3H
F-RT-SM
1
MF-LF SMC_KDBLED_PRESENT_L
402 2 10% VIN 55 6
1
LOW = keyboard backlight present 2 16V
X5R 2
603 SW 3
HIGH= keyboard backlight not present 3
46
IN SMC_SYS_KBDLED 6 CTRL LED 5 6 KBDLED_ANODE 4

BOM OPTION: KBDLED_YES MIN_NECK_WIDTH=0.25 MM
CRITICAL 1
R5855 APN 518S0691
NO STUFF U5850
A R5853 ALWAYS PRESENT R58541 R58521 LT3491
DFN
10
1%
1/16W
4.7K 10K MF-LF PAGE TITLE
5%
1/16W
MF-LF
5%
1/16W
MF-LF
2 402 KBD BACKLIGHT CONNECTOR WELLSPRING 2
402 2 402 2 CAP 4 KBDLED_CAP DRAWING NUMBER SIZE
THRML MIN_NECK_WIDTH=0.25 MM
Apple Inc. D
GND PAD 1 C5855 REVISION
7
2
1UF R
10%
35V
2 X5R NOTICE OF PROPRIETARY PROPERTY: BRANCH
603
SMC_KDBLED_PRESENT_L
55 6
58 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Analog SMS
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
C C
54 51 50 49 36 35 34 33 32 31 20 17 7 6 PP3V3_S3
103 102 88 74 72 55 Desired orientation when
1 C5922 1 C5926 placed on board top-side:
14
1
0.1UF
10%
10UF
20%
R5921 VDD
16V
2 X5R 2 4V
X5R
10K
5%
1/16W
MF-LF
U5920
AP344ALH
402 603
4022 LGA +Y
1 FS VOUTX 12 SMS_X_AXIS OUT 46
SMS_PWRDN SMS_PWRDN 5 Front of system

56 46 IN 56 46 PD CRITICAL 10 SMS_Y_AXIS +X
MAKE_BASE=TRUE 2 VOUTY OUT 46
SMS_SELFTEST ST +Z (up)
VOUTZ 8 SMS_Z_AXIS OUT 46
15 RES
NC 4 RES
1
R5922 NC 3 NC NC 11 NC
10K
5% NC 6 NC NC 13 NC Circle indicates pin 1 location when placed
1/16W
MF-LF NC 9 NC NC 16 NC 1 C5923 1 C5924 1 C5925 in correct orientation
2 402 GND 0.01UF 0.01UF 0.01UF
10% 10% 10%
2 16V 2 16V 2 16V
7
CERM CERM CERM
402 402 402
B B
PAGE TITLE
Sudden Motion Sensor (SMS)

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

59 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DEBUG_ADC DEBUG_ADC
R6003 R6004
PP5V_S5 10 102 PP5V_S5_DEBUG_ADC_AVDD_FILT 102 PP5V_S5_DEBUG_ADC_DVDD_FILT 10 PP5V_S5
102 73 67 57 23 7 7 23 57 67 73 102
MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM
PLACE_NEAR=R3452.1:3mm PLACE_NEAR=R4598.2:3mm 5% MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM 5%
VOLTAGE=5V
1/16W VOLTAGE=5V 1/16W
XW6010
SM
XW6020
SM
MF-LF
402
DEBUG_ADC DEBUG_ADC DEBUG_ADC DEBUG_ADC MF-LF
402
PP3V3_WLAN_F 1 2 3V3_WLAN_F_XW PP5V_SW_ODD 1 2 5V_SW_ODD_XW
1 C6000 1 C6001 1 C6002 1 C6003
33 42 6
0.1UF 10UF 0.1UF 10UF
20% 20% 20% 20%
DEBUG_ADC DEBUG_ADC 10V
2 CERM 2 6.3V 10V
2 CERM 2 6.3V
X5R X5R
1 1 PLACE_NEAR=U6000.23:8mm 402 603 402 603
R6010 PLACE_NEAR=U6000.22:8mm
R6020
12
13
21
649K 1M
1% 1%
1/16W DEBUG_ADC 1/16W DEBUG_ADC
MF-LF MF-LF AVDD DVDD
2 402 R6012 2 402 R6022 DEBUG_ADC
226K 2 226K 2 U6000 R6001 D
D 3V3_WLAN_F_DIV
DEBUG_ADC
1
1%
ADC_CH0 57 5V_SW_ODD_DIV
DEBUG_ADC
1
1%
ADC_CH1 57
57 ADC_CH0 22 CH0
LTC2309
QFN AD0 14 1
33 2
PLACE_NEAR=U4900.F1:10mm
SMBUS_SMC_MGMT_SDA BI 46 49 97
1
1/16W DEBUG_ADC 1
1/16W DEBUG_ADC ADC_CH1 23
102
R6011 MF-LF R6021 MF-LF CH1 AD1 15 5%
1M
402 1 C6012 681K
402 1 C6022 57
ADC_CH2 24 CH2
DEBUG_ADC 1/16W
MF-LF
DEBUG_ADC
2.2UF 2.2UF 57
402
1%
1/16W 10% 1%
1/16W 10% 57 ADC_CH3 1 CH3 SDA 17 ADC_SDA R6002 PLACE_NEAR=U4900.E4:10mm
MF-LF 2 6.3V
X5R MF-LF 2 6.3V
X5R 33 SMBUS_SMC_MGMT_SCL
2 402 402 2 402 402 57 ADC_CH4 2 CH4 SCL 16 ADC_SCL 1 2 IN 46 49 97
102
57 ADC_CH5 3 CH5 5%
PLACE_NEAR=U6000.22:10mm PLACE_NEAR=U6000.23:10mm 1/16W
57 ADC_CH6 4 CH6 VREF 7 ADC_VREF MF-LF
402
57 ADC_CH7 5 CH7
6 COM REFCOMP 8 ADC_REFCOMP
DIVIDER: ~ 2/5 DEBUG_ADC DEBUG_ADC DEBUG_ADC
DIVIDER: ~ 2/3
I2C ADDRESS: 0X10 / 0X11 GND
THRM
PAD
1 C6004 1 C6005 1 C6006
ADC RANGE: 0V TO 4.096V 0.1UF 10UF 2.2UF
20% 20% 20%
9
10
11
18
19
20
25
LSB: 0.001V 10V
2 CERM 6.3V
2 X5R 2 6.3V
CERM
402 603 402-LF
102 73 67 57 23 7 PP5V_S5
DEBUG_ADC DEBUG_ADC
1 C6030 1 C6040
0.1UF 0.1UF
DEBUG_ADC 20% DEBUG_ADC 20%
2 10V
CERM
10V
2 CERM
R6030 402 R6050 402
243 PLACE_NEAR=U6000.24:5mm 499 DEBUG_ADC
99 33 IN ISNS_AIRPORT_P 1 2 99 ISNS_AIRPORT_R_P DEBUG_ADC 99 42 IN ISNS_ODD_P 1 2 99 ISNS_ODD_R_P
1% U6030 DEBUG_ADC 1% U6040 DEBUG_ADC
1/16W 8 OPA2333 1/16W 5 OPA333DCKG4
C MF-LF
402 3
V+
DFN
1 ISNS_AIRPORT_IOUT 1 226K 2
R6034
ADC_CH2 57
MF-LF
402
1 +
V+
SC70-5
4 ISNS_ODD_IOUT
R6054
1
226K 2
ADC_CH4 57
C
DEBUG_ADC 2 1%
DEBUG_ADC 1%
V- 1/16W DEBUG_ADC V- 1/16W DEBUG_ADC
R6031 THRM MF-LF R6051 3
- MF-LF
ISNS_AIRPORT_N 1
243 2 99 ISNS_AIRPORT_R_N 9
4
GAIN: 1239X 402 1 C6034 ISNS_ODD_N 1
499 2 99 ISNS_ODD_R_N
2
GAIN: 561X 402 1 C6054
99 33 IN 2.2UF 99 42 IN 2.2UF
1% 10% 1% 10%
1/16W 6.3V
2 X5R 1/16W 2 6.3V
MF-LF MF-LF X5R
402 402 402 PLACE_NEAR=U6000.2:5mm 402
DEBUG_ADC PLACE_NEAR=U6000.24:5mm DEBUG_ADC
NO STUFF DEBUG_ADC
1 NO STUFF DEBUG_ADC
1
C6032 1 R6032 R6033 C6052 1 R6052 R6053
470PF 301K 1
301K 2 SIGNAL_MODEL=EMPTY
470PF 280K 1
10% 1% 10% 1%
50V 1/16W 50V 1/16W
CERM 2 MF-LF 1% NO STUFF CERM 2 MF-LF 1% NO STUFF
2 402 1/16W 1/16W
402 MF-LF 402 2 402 MF-LF
402 C6033 402 C6053
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 470PF U6030 is dual package for CPU MEM VDD and AIRPORT sensors SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
470PF
1 2 1 2
10% SIGNAL_MODEL=EMPTY 10% SIGNAL_MODEL=EMPTY

50V 50V
CERM CERM
402 402
73 7 IN PP1V5_S3RS0 PLACE_NEAR=U6000.1:5mm
DEBUG_ADC 102 73 67 57 23 7 PP5V_S5
CRITICAL R6040 U6030 DEBUG_ADC
1.82K2 DEBUG_ADC DEBUG_ADC
R6045 1 3 99 DDRISNS_P 1
8 OPA2333 C6041
0.001 1% 99 DDRISNS_R_P 5 DFN R6044 R6060 0.1UF
20%
1% DEBUG_ADC 1/16W V+ 226K 2 412 DEBUG_ADC 10V PLACE_NEAR=U6000.3:5mm
1W
R6041 MF-LF 7 CPUDDR_IOUT 1 ADC_CH3 OUT 57 99 42 IN ISNS_HDD_P 1 2 99 ISNS_HDD_R_P CERM
MF
1206 2 4 1.82K2
402
6 V- 1% 1% U6041 402 DEBUG_ADC
99 DDRISNS_N 1 99 DDRISNS_R_N 1/16W DEBUG_ADC 1/16W 5 OPA333DCKG4
MF-LF
1%
THRM
4
GAIN: 549X 402 1 C6044 MF-LF
402
1 + SC70-5 R6064
31
13 7 PPCPUDDR_ISNS 1/16W 9
2.2UF V+ 226K 2
B 16 OUT MF-LF
402 10%
6.3V
2 X5R
DEBUG_ADC
V-
4 ISNS_HDD_IOUT 1
1%
ADC_CH5 57
B
402 R6061 3
-
1/16W
MF-LF
DEBUG_ADC
NO STUFF DEBUG_ADC
DEBUG_ADC ISNS_HDD_N 1
412 2 99 ISNS_HDD_R_N
2
GAIN: 845X 402 1 C6064
1
R6042
99 42 IN 2.2UF
C6042 1 R6043 1% 10%
470PF 1M 1M SIGNAL_MODEL=EMPTY 1/16W 2 6.3V
X5R
1% 1 2 MF-LF
10% 1/16W 402 402
50V 1% DEBUG_ADC
CERM 2 MF-LF
1/16W NO STUFF NO STUFF DEBUG_ADC PLACE_NEAR=U6000.3:5mm
402 2 402 1
MF-LF
402 C6043 C6062 1 R6062 R6063
SIGNAL_MODEL=EMPTY 470PF 470PF 348K 1
SIGNAL_MODEL=EMPTY
1 2 10% 1%
50V 1/16W
CERM 2 MF-LF 1% NO STUFF
1/16W
10% 402 2 402 MF-LF
50V
CERM
SIGNAL_MODEL=EMPTY
402 C6063
402
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 470PF
1 2
102 73 67 57 23 7 PP5V_S5 PLACE_NEAR=D9710.2:3mm
DEBUG_ADC
1 C6050 XW6080
SM
10%
50V
SIGNAL_MODEL=EMPTY
PPVOUT_S0_LCDBKLT CERM
0.1UF 89 84 6 1 2 VOUT_S0_LCDBKLT_XW 402
20%
2 10V
CERM
402 DEBUG_ADC
1
PLACE_NEAR=U6000.4:5mm R6080 PLACE_NEAR=U6000.5:5mm
3
1M
V+ 1%
DEBUG_ADC 1/16W DEBUG_ADC
MF-LF
U6050 R6074 2 402 R6082
INA210
ISNS_LCDBKLT_IOUT 1 226K 2
226K 2
99 89 IN ISNS_LCDBKLT_N 5 IN- SC70 OUT 6 ADC_CH6 57 VOUT_S0_LCDBKLT_DIV 1 ADC_CH7 57
DEBUG_ADC 1% DEBUG_ADC 1%
ISNS_LCDBKLT_P
1/16W DEBUG_ADC 1
1/16W DEBUG_ADC
99 89 IN
4 IN+ REF 1
GAIN: 200X
MF-LF
402 1 C6074 R6081 MF-LF
402 1 C6082
52.3K
A GND
2.2UF
10%
6.3V
2 X5R
1%
1/16W
MF-LF
2.2UF
10%
2 6.3V
X5R
2
PAGE TITLE
402 2 402 402
PLACE_NEAR=U6000.5:5mm DEBUG SENSORS AND ADC
PLACE_NEAR=U6000.4:5mm DRAWING NUMBER SIZE
Apple Inc. D
REVISION
DIVIDER: ~ 1/20 R

60 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
99 86 84 74 73 72 51 50 49 35 31 7 6 PP3V3_S5
101
1
R6101 C6100 1 CRITICAL
8
3.3K 0.1UF VCC
5% 20%
1/16W
MF-LF 10V
CERM 2 U6100
2 402 402 32MBIT
SOP
48 IN SPI_MLB_CLK 6 SCLK SI/SIO0 5 SPI_MLB_MOSI IN 48
MX25L3205DM2I-12G
SPI_MLB_CS_L 1 CE*
OMIT
48 IN
SO/SIO1 2 SPI_MLB_MISO OUT 48
SPI_WP_L 3 WP*/ACC
48 20 6 IN SPIROM_USE_MLB 7 HOLD*
NOTE: If HOLD* is asserted GND
4
ROM will ignore SPI cycles.
B B
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

61 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO CODEC
APPLE P/N 353S2592
99 74 72 42 34 7 PP1V5_S0 PP5V_S0_AUDIO IN 8 59 61
PP3V3_S0 IN
84 85 86 88 99 101
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49
52 53 55 59 63 64 69 70 71 72 73 74 81
C6200 1 1 C6201 PP4V5_AUDIO_ANALOG IN 59 60

4.7UF 0.47UF CRITICAL
20% 10%
4V
X5R 2
10V
2 X5R C6203 1 1
C6204 C6205 1 1 C6206 C6207 1 1 C6208
0.47UF 0.47UF 1UF 0.47UF 10UF
D
402 402
C6202 1
10%
10V
X5R 2
10UF
20%
2 16V
10%
10V
X5R 2
10%
10V
2 X5R
10%
10V
X5R 2
20%
10V
2 X5R
D
POLY-TANT
10UF 402 CASE-B2-SM 402 402-1 402 805
20% GND_AUDIO_HPAMP 59 61 62
16V 2
62 61 59 GND_AUDIO_HPAMP POLY-TANT
24
46
25
CASE-B2-SM EXT_HP_AMP
9
60 59 PP4V5_AUDIO_ANALOG
IN
C6209 1 1 C6210 VD VA_REF VA_HP VA GND_AUDIO_CODEC
1
R6206
1
R6200 10UF 10UF 59 60 61 64
0
20%
6.3V
20%
6.3V VBIAS_DAC 29 VBIAS_DAC 5%
2.67K X5R 2 2 X5R 1/16W
1% CRITICALHPOUT_L 38 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_L OUT 61 62 MF-LF
1/16W 603-3 603-3 CS4206_FP 44 VHP_FILT+
AUD_HP_PORT_R 2 402
MF-LF HPOUT_R 40 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM
2 402
CS4206_FN 41 VHP_FILT- U6200 OUT 60 61
CS4206ACNZC HPREF 39 MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM AUD_INT_HP_REF IN 63

QFN
NC TP_AUD_GPIO_0 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 TP_AUD_LO2_L_P
HP AMP CNTRL 61 OUT AUD_GPIO_1 12 GPIO1/DMIC_SDA2 LINEOUT_L1-
/SPDIF_OUT2
34 TP_AUD_LO2_L_N
MAC SPKR AMP CNTRL 62 60 OUT AUD_GPIO_2 14 GPIO2 LINEOUT_R1+ 36 AUD_LO2_R_P OUT 62 LFE SPKR AMP (FC/LFE)
15 GPIO3 LINEOUT_R1- 37 AUD_LO2_R_N OUT 62
1
D6200
SOD-523
13 SENSE_A LINEOUT_L2+ 31 AUD_LO3_L_P OUT 62
BAT54XV2T1 CS4206_FLYP LINEOUT_L2- 30 AUD_LO3_L_N OUT 62
2 CS4206_FLYC
45 FLYP
LINEOUT_R2+ 32 AUD_LO3_R_P OUT 62 WFR SPKR AMPS (L2/R2)
LINEOUT_R2- 33 AUD_LO3_R_N 62
WIN SPKR AMP CNTRL 62 OUT AUD_GPIO_3 C6211 1 1 C6212 43 FLYC OUT
2.2UF 2.2UF 42 FLYN
20% 20%
6.3V
CERM 2
6.3V
2 CERM MICBIAS 16 AUD_CODEC_MICBIAS OUT 64
402-LF 402-LF
3 VL_HD
CS4206_FLYN
64 AUD_SENSE_A VCOM 28 CS4206_VCOM
IN
NC
1 VL_IF
AUD_LI_N IN 59 60
C 94 17 HDA_BIT_CLK 6 BITCLK
LINEIN_L+ 21 AUD_LI_P_L IN 60
C
IN AUD_LI_N
LINEIN_C- 22 MAKE_BASE=TRUE 60 59
94 17 IN HDA_SYNC LINEIN_R+ 23 AUD_LI_P_R IN 60
R6201 10 SYNC
AUD_LI_N IN 59 60
33
94 17 HDA_SDIN0 1 2 AUD_SDI_R 8 SDI MICIN_L+ 18 AUD_MIC_INL_P 64
OUT
5% 5 SDO MICIN_L- 17 AUD_MIC_INL_N
IN
64
EXTERNAL MIC INPUT
1/16W IN
MF-LF
402
MICIN_R+ 19 AUD_MIC_INR_P IN 64
11 RESET*
94 17 IN HDA_SDOUT MICIN_R- 20 AUD_MIC_INR_N IN 64 INTERNAL MIC INPUT
94 17 IN HDA_RST_L
63 IN AUD_SPDIF_IN 47 SPDIF_IN
VREF+_ADC 27 CS4206_VREF_ADC
CS4206_SPDIF_OUT 48 SPDIF_OUT MIN_LINE_WIDTH=0.20MM NC
R6202 MIN_NECK_WIDTH=0.15MM
33
AUD_SPDIF_OUT 1 2 DMIC_SCL 4 TP_AUD_DMIC_CLK
63 OUT
5% R62031 NC
1/16W 100K
MF-LF 1%
402 1/16W DGND THRM_PAD AGND
MF-LF
402 2
49
26
CRITICAL CRITICAL
C6213 1 1
C6214
1UF 10UF
NOSTUFF 10%
20V 2
20%
1 2 16V
R6204 TANT
CASE-R-HF
POLY-TANT
CASE-B2-SM
0
5%
1/16W
MF-LF
2 402
64 61 60 59 GND_AUDIO_CODEC
B XW6201 B
SM
1 2 GND_AUDIO_HPAMP 59 61 62
VOLTAGE=0V
DIFF FSINPUT= 2.45VRMS

SE FSINPUT= 1.22VRMS AUDIO 4.5V REGULATOR
APPLE P/N 353S2234
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
L6250 MIN_LINE_WIDTH=0.40MM U6201
FERR-220-OHM MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V MAX8840-4.5V
UDFN
61 59 8 PP5V_S0_AUDIO 1 2 AUD_4V5_REG_IN 1 IN OUT 6 PP4V5_AUDIO_ANALOG 59 60
VOLTAGE=4.5V
0402 CRITICAL
R6250 C6253
101 99 88 86 85 84 81
PP3V3_S0 1K AUD_REG_SHDN_L 3 SHDN* BP 4
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49
1 2 0.01UF
5% GND NC 5 MAX8840_BP 1 2 CRITICAL
1/16W MIN_LINE_WIDTH=0.20MM
MF-LF MIN_NECK_WIDTH=0.15MM C6254 1 1
C6255
2
402 C6251 1 1 C6252 10%

16V 1UF 47UF
1 C6250 1UF 0.001UF CERM 10%
10V 20%
10% 10% 402 2 10V
0.1UF 10V 2 2 50V X5R 2 TANT
10% X5R CERM 402 1206-LLP
16V 402 402
2 X5R
A 402 XW6200
SM SYNC_MASTER=K17_REF SYNC_DATE=05/30/2009 A
1 2 GND_AUDIO_CODEC 59 60 61 64
PAGE TITLE
VOLTAGE=0V
AUDIO:CODEC
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

62 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CODEC Nom SE RIN = 20K OHMS
FC = 5 HZ Max
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
NET RIN = 18K OHMS
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM
CRITICAL
R6300 C6300
3.3UF
7.87K2
63 IN AUD_LI_INL
1 AUD_LI_LF 2 1 AUD_LI_P_L
MIN_LINE_WIDTH=0.3MM OUT
59
MIN_NECK_WIDTH=0.2MM 1% MIN_NECK_WIDTH=0.2MM
1/16W 10%
D
MF-LF
402
16V
TANT
SMA-HF1
D
1 NOSTUFF
R6301 1 C6301
21.5K 820PF
1% 10%
1/16W 50V
MF-LF 2 CERM
402 2 402
CRITICAL
C6302
3.3UF
63 60 IN AUD_LI_GND
2 1 AUD_LI_N
59 60
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
10%
1 16V
R6303 TANT
SMA-HF1
10
1%
1/16W
MF-LF
2 402
64 61 60 59 IN GND_AUDIO_CODEC
MIN_NECK_WIDTH=.2MM
MIN_LINE_WIDTH=.3MM CRITICAL
R6306 C6303
3.3UF
7.87K2
63 IN AUD_LI_INR
1 AUD_LI_RF 2 1 AUD_LI_P_R
59
1/16W 10%
MF-LF 16V
402 TANT
SMA-HF1
NOSTUFF
C R63051
21.5K
1 C6304 C
1% 820PF
1/16W 10%
MF-LF 2 50V
CERM
402 2 402
CRITICAL
C6305
3.3UF
63 60 IN AUD_LI_GND 2 1 AUD_LI_N
59 60
10%
16V
TANT
SMA-HF1
SE-TO-DIFF CONVERTER
CRITICAL
C6353 R6353 R6354
3.3UF
AUD_HP_PORT_R 2 1 AUD_SE_DIFF_IN 1
21K 2 AUD_SE_DIFF_IN_R 1
10.5K2
61 59
1% 1%
10% 1/16W 1/16W
16V MF-LF MF-LF
TANT 402 402
SMA-HF1
AUD_GPIO_2
59 62
B IN
B
B4
C3 V- C4
AUD_LO1_R_P
U6350 C1 OUT 62
UCSP
C2
V+ MAX4253
B1 CRITICAL
R6355
1
2.21K2
1%
1/16W
MF-LF
402 R6357
AUD_SE_DIFF_P_INV 1
2.21K2
1%
1/16W
R6358 MF-LF
402
1
2.21K2
1%
1/16W
MF-LF
402 R6356
AUD_SE_DIFF_N_INV 1
2.21K2
1%
1/16W
MF-LF
402
59 PP4V5_AUDIO_ANALOG
R63501 CRITICAL
A 21K
1%
1/16W
A2
B1
V+
MAX4253
UCSP
MF-LF AUD_LO1_R_N PAGE TITLE
A1
C6350 1
4.7UF
1 C6351
0.47UF
402 2
U6350
A4
OUT 62
AUDIO: LINE IN
20% 10%
AUD_SE_DIFF_VBIAS A3
V- DRAWING NUMBER SIZE
6.3V 2
X5R 2 10V
X5R
CRITICAL
MIN_NECK_WIDTH=0.15MM B4
Apple Inc. D
402 402 1
R6351 1
C6352 R
REVISION
21K 3.3UF
1%
1/16W 10% NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF-LF 2 16V
402 2 TANT THE INFORMATION CONTAINED HEREIN IS THE
SMA-HF1 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
GND_AUDIO_CODEC
64 61 60 59
63 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
HEADPHONE AMPLIFIER (AK4201)
APN:353S2347
VOLTAGE GAIN:1.53
PLACE XW5802 & XW5803 NEAR PP5V_S0_AUDIO
D XW6502
SM
RUN PP5V_AUDIO_HPAMP_* NETS OVER GND D
61 59 8 PP5V_S0_AUDIO 1 2 PP5V_AUDIO_HPAMP_PVDD_F
VOLTAGE=5V
MIN_LINE_WIDTH=0.40MM EXT_HP_AMP EXT_HP_AMP
C6500 1 1 C6501
10UF 0.001UF
20% 10%
10V 2 2 50V
X5R CERM
805 402
XW6503
SM
61 59 8 PP5V_S0_AUDIO 1 2 PP5V_AUDIO_HPAMP_AVDD_F
VOLTAGE=5V
MIN_LINE_WIDTH=0.40MM EXT_HP_AMP EXT_HP_AMP
C6502 1 1 C6503
10UF 0.1UF
5
20% 10%
10V 16V
AVDD
PVDD
X5R 2 2 X5R
AUD_HPAMP_OUTL
805 61
U6500 EXT_HP_AMP
AK4201EU R6515
USON
0
61 IN AUD_HPAMP_INL_M 1 LIN LOUT 2 1 2 AUD_HPAMP_OUTL_R OUT 61 63
12 EXT_HP_AMP MIN_LINE_WIDTH=0.30MM
61 IN AUD_HPAMP_INR_M RIN CRITICAL ROUT 11 5%
1/10W
8 MF-LF
PDN* CN 6 AK4201_CN 603
EXT_HP_AMP MIN_LINE_WIDTH=0.40MM
CP 7 MIN_NECK_WIDTH=0.20MM
R6501 EXT_HP_AMP AUD_HPAMP_OUTR 61
CRITICAL MIN_LINE_WIDTH=0.30MM
0 PVEE 10 MIN_NECK_WIDTH=0.20MM
AUD_GPIO_1 1 2 AUD_HPAMP_MUTE_L 1 C6505
4 VSS1
VSS2
59 IN
5% THRM 1UF EXT_HP_AMP
1/16W PAD 10%
10V
MF-LF 2 X5R R6525
C
13
402
C
AK4201_PVEE
402 0
AK4201_CP 1 2 AUD_HPAMP_OUTR_R OUT 61 63
MIN_LINE_WIDTH=0.40MM MIN_LINE_WIDTH=0.30MM
EXT_HP_AMP 1/10W
MF-LF
R65001 603
100K
5%
1/16W
MF-LF
R65161 1
R6526
402 2 21K 21K
EXT_HP_AMP 1% 1%
CRITICAL 1/16W 1/16W
MF-LF MF-LF
PLACE XW5800 NEAR U5800 PINS 1/12
1 C6504 402 2 2 402
1UF EXT_HP_AMP
10%
XW6500
10V
2 X5R L6535
SM
402 FERR-220-OHM-2.5A
64 60 59 GND_AUDIO_CODEC 1 2 GND_AUDIO_HPAMP_PGND 1 2 AUD_LO_GND_R OUT 61 63
VOLTAGE=0V VOLTAGE=0V
MIN_LINE_WIDTH=0.60MM 0603 MIN_LINE_WIDTH=0.60 MM
MIN_NECK_WIDTH=0.20MM EXT_HP_AMP MIN_NECK_WIDTH=0.20 MM
1
R6531
13.7K
1%
1/16W
MF-LF EXT_HP_AMP
2 402 XW6501
R6530 SM
21K
AK4201_VSS2 1 2 AUD_LO_FDBK 1 2 AUD_LO_GND_R IN 61 63
1/16W
MF-LF
402
CS4206A HP OUT ZOBEL NETWORK & 1ST ORDER DAC FILTER

B 1ST ORDER DAC FILTER PLACEHOLDER B
LP:42.10 KHZ
INT_HP_AMP
EXT_HP_AMP EXT_HP_AMP
R6552 R6510 R6511
AUD_HP_PORT_L 0 AUD_HPAMP_OUTL_R
62 61 59 IN
1 2
OUT 61 63
AUD_HP_PORT_L 13.7K2 21K
MIN_LINE_WIDTH=0.30MM 62 61 59 IN
1 1 2 AUD_HPAMP_OUTL 61
1/10W 1% 1%
1
R6550 MF-LF
603
1/16W
MF-LF
1/16W
MF-LF
39 NOSTUFF 402 402
5%
1/16W CRITICAL
MF-LF NOSTUFF
402 2 1 C6552 CRITICAL
2200PF
AUD_Z_L 5% C6511
NC MIN_LINE_WIDTH=0.30MM
50V
2 C0G-CERM 180PF
603 61 AUD_HPAMP_INL_M 1 2
C6550 1 OUT
0.1UF INT_HP_AMP 5%
10% 50V
16V CERM
X7R-CERM 2
402
R6554 402
0
1 2 AUD_LO_GND_R OUT 61 63
62 59 IN GND_AUDIO_HPAMP 5%
1/10W
MF-LF NOSTUFF
603 CRITICAL
C6551 1
0.1UF
10% NOSTUFF C6521
16V 180PF
X7R-CERM 2 CRITICAL AUD_HPAMP_INR_M 1 2
61
AUD_Z_R
402 1 C6553 OUT
NC MIN_LINE_WIDTH=0.30MM 2200PF 5%
MIN_NECK_WIDTH=0.20MM 5% 50V
50V CERM
2 C0G-CERM
A R65511 402
39
5%
603
SYNC_MASTER=K17_REF
PAGE TITLE
1/16W INT_HP_AMP EXT_HP_AMP EXT_HP_AMP
MF-LF
402 2 R6553 R6520 R6521 AUDIO: HEADPHONE OUT
0 13.7K2 21K DRAWING NUMBER SIZE
AUD_HP_PORT_R 1 2 AUD_HPAMP_OUTR_R AUD_HP_PORT_R 1 1 2 AUD_HPAMP_OUTR
61 60 59 IN
5%
OUT 61 63 61 60 59 IN
1% 1%
61
Apple Inc. D
1/10W 1/16W 1/16W REVISION
MF-LF MF-LF MF-LF R
603 402 402
65 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
5X MONO SPEAKER AMPLIFIERS (SSM2315)
APN: 353S2500
GAIN = +6 DB
FC (SPEAKERS BL/BR) = ~737 HZ
FC (SPEAKERS FL/FR/LFE) = ~90 HZ
PLACE C6615 CLOSE TO VDD PIN PLACE C6611/C6612 CLOSE TO PVDD PIN
62 8 PP5V_S0_AUDIO_AMP_L
CRITICAL
L6610 C6613 CRITICAL CRITICAL
FERR-1000-OHM 0.0027UF R6611
GND_AUDIO_HPAMP 1 2 SPKRAMP_BL_IN_L_N 1 2 99 SPKRAMP_BL_IN_C_N 1
0 2
C6615 1 C6612 1 1 C6611
61 59
1UF 0.001UF
IN 47UF
D
B1
B2
D 0402
10%
50V
CERM
5%
1/16W
MF-LF
10%
10V
X5R 2
402 VDD PVDD
20%
6.3V 2
POLY-TANT
10%
50V
2 CERM
402
402 2012-LLP
402
L6611 CRITICAL U6610 SPKRAMP_BL_OUT_P OUT 6 63 99
C6614 SSM2315 MIN_LINE_WIDTH=0.50 MM
FERR-1000-OHM 0.0027UF R6612 99 SSM2315BL_IN_N C1 IN- WLCSP OUT+ C3 MIN_NECK_WIDTH=0.20 MM
AUD_HP_PORT_L 1 2 SPKRAMP_BL_IN_L_P 1 2 99 SPKRAMP_BL_IN_C_P
0
61 59 IN 1 2 99 SSM2315BL_IN_P A1 IN+ OUT_ A3
0402 5% CRITICAL
10% 1/16W C2 SD* SPKRAMP_BL_OUT_N
L6601 50V
CERM
MF-LF MIN_LINE_WIDTH=0.50 MM
OUT 6 63 99
FERR-1000-OHM 402 R6602 402

GND MIN_NECK_WIDTH=0.20 MM
AUD_GPIO_2 1 2
AUD_GPIO_2_L 0
1 2
A2
B3
60 59 IN
0402 NOSTUFF 5% NOSTUFF 1
L6602 SHOULD BRIDGE SPLIT BETWEEN
GND_AUDIO_CODEC & DIGITAL GND D6600 1/16W
MF-LF C6600 1 R6600
SOD-523 402
1UF 100K
2 1 10% 5%
10V 1/16W
X5R 2 MF-LF
BAT54XV2T1 402 2 402
62 AUD_SPKRAMP_MAC_SHDN_L
PLACE C6625 CLOSE TO VDD PIN
62 8 PP5V_S0_AUDIO_AMP_L
CRITICAL PLACE C6621/C6622 CLOSE TO PVDD PIN
L6620 C6623
FERR-1000-OHM 0.022UF R6621 CRITICAL CRITICAL
AUD_LO3_L_N 2 SPKRAMP_FL_IN_L_N 2 99 SPKRAMP_FL_IN_C_N
0 C6625 1 1 C6621
59 IN
1 1 1 2
1UF C6622 1
B1
B2
0402 5% 10% 100UF 0.001UF
10% 1/16W 10V 20% 10%
25V MF-LF X5R 2 6.3V 2 50V
X7R 402 VDD PVDD TANT
2 CERM
402
0402 CASE-AL1 402
L6621 CRITICAL U6620 SPKRAMP_FL_OUT_P OUT 6 63 99
FERR-1000-OHM C6624 R6622

SSM2315
WLCSP OUT+ C3
0.022UF 99 SSM2315FL_IN_N C1 IN-
AUD_LO3_L_P 2 SPKRAMP_FL_IN_L_P 2 99 SPKRAMP_FL_IN_C_P 0
C 59 IN
1
0402
1 1
5%
2 99 SSM2315FL_IN_P A1 IN+
CRITICAL
OUT_ A3 C
10% 1/16W C2 SD* SPKRAMP_FL_OUT_N
L6602 25V
X7R
MF-LF
402
OUT 6 63 99
FERR-1000-OHM 0402 GND

AUD_GPIO_3 1 2
A2
B3
59 IN
0402
L6602 SHOULD BRIDGE SPLIT BETWEEN
GND_AUDIO_CODEC & DIGITAL GND R66011
100K
5%
62 AUD_SPKRAMP_WIN_SHDN_L 1/16W
MF-LF
402 2
PLACE C6635 CLOSE TO VDD PIN

62 8 PP5V_S0_AUDIO_AMP_R
PLACE C6631/C6632 CLOSE TO PVDD PIN
CRITICAL
FERR-1000-OHM 0.0027UF R6631
AUD_LO1_R_N 1 2 SPKRAMP_BR_IN_L_N 1 2 99 SPKRAMP_BR_IN_C_N 1
0 2
C6635 1 C6632 1 1 C6631
60 IN 1UF 47UF 0.001UF
B1
B2
0402 5% 10% 20% 10%
10% 1/16W 10V 2 6.3V 2 50V
2 CERM
50V MF-LF X5R POLY-TANT
CERM 402 402 VDD PVDD 2012-LLP 402
402
CRITICAL U6630 SPKRAMP_BR_OUT_P
L6631 C6634 SSM2315 MIN_LINE_WIDTH=0.50 MM
OUT 6 63 99
FERR-1000-OHM 0.0027UF R6632 99 SSM2315BR_IN_N C1 IN- WLCSP OUT+ C3 MIN_NECK_WIDTH=0.20 MM

AUD_LO1_R_P 1 2 SPKRAMP_BR_IN_L_P 1 2 99 SPKRAMP_BR_IN_C_P
0 SSM2315BR_IN_P A1 IN+
60 IN
1 2 99 OUT_ A3
0402 5% CRITICAL
10%
50V
1/16W C2 SD* SPKRAMP_BR_OUT_N OUT 6 63 99
MF-LF MIN_LINE_WIDTH=0.50 MM
CERM 402 MIN_NECK_WIDTH=0.20 MM
402 GND
62 AUD_SPKRAMP_MAC_SHDN_L
B3
A2
B B
L6640 CRITICAL
FERR-1000-OHM C6643 R6641 CRITICAL CRITICAL
0.022UF
AUD_LO3_R_N 1
99
2
SPKRAMP_FR_IN_L_N 1 2 99 SPKRAMP_FR_IN_C_N 1
0 2
C6645 1 C6642 1 1 C6641
59 IN 1UF 100UF 0.001UF
B1
B2
0402 5% 10% 20% 10%
10%
25V
1/16W
MF-LF
10V
X5R 2
6.3V 2
TANT
2 50V
CERM
X7R 402 402 VDD PVDD CASE-AL1 402
0402
L6641 CRITICAL U6640 SPKRAMP_FR_OUT_P OUT 6 63 99
C6644 SSM2315 MIN_LINE_WIDTH=0.50 MM
FERR-1000-OHM 0.022UF R6642 99 SSM2315FR_IN_N C1 IN- WLCSP OUT+ C3 MIN_NECK_WIDTH=0.20 MM
AUD_LO3_R_P 2 SPKRAMP_FR_IN_L_P 2 99 SPKRAMP_FR_IN_C_P 0
59 IN
1 1 1 2 99 SSM2315FR_IN_P A1 IN+ OUT_ A3
0402
10%
5%
1/16W
CRITICAL
C2 SD* SPKRAMP_FR_OUT_N OUT 6 63 99
25V MF-LF MIN_LINE_WIDTH=0.50 MM
X7R 402 MIN_NECK_WIDTH=0.20 MM
0402 GND
62 AUD_SPKRAMP_WIN_SHDN_L
A2
B3
CRITICAL
FERR-1000-OHM 0.022UF R6651
AUD_LO2_R_N 1
99
2
SPKRAMP_LFE_IN_L_N 1 2 99 SPKRAMP_LFE_IN_C_N 1
0 2
C6655 1 C6652 1 1 C6651
A 59 IN 1UF 100UF 0.001UF
A
B1
B2
0402 5% 10% 20% 10% SYNC_MASTER=K17_REF SYNC_DATE=05/30/2009

10% 1/16W 10V 2 6.3V 2 2 50V
25V MF-LF X5R TANT CERM PAGE TITLE
X7R 402 VDD PVDD 402
0402
CRITICAL
402
U6650
CASE-AL1
SPKRAMP_LFE_OUT_P AUDIO:SPEAKER AMP
L6651 C6654 SSM2315 MIN_LINE_WIDTH=0.50 MM OUT 6 63 99
DRAWING NUMBER SIZE
FERR-1000-OHM 0.022UF R6652 99 SSM2315LFE_IN_N C1 IN- WLCSP OUT+ C3 MIN_NECK_WIDTH=0.20 MM
D
59
AUD_LO2_R_P 1 2 SPKRAMP_LFE_IN_L_P 1 2 99 SPKRAMP_LFE_IN_C_P 1
0 2 99 SSM2315LFE_IN_P A1 IN+ OUT_ A3
Apple Inc. REVISION
IN
R
0402 5% CRITICAL
10%
25V
1/16W C2 SD* SPKRAMP_LFE_OUT_N OUT 6 63 99
X7R
MF-LF
402
MIN_LINE_WIDTH=0.50 MM NOTICE OF PROPRIETARY PROPERTY: BRANCH
0402 GND MIN_NECK_WIDTH=0.20 MM
62 AUD_SPKRAMP_WIN_SHDN_L PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
B3
A2

66 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO JACK 1 LO/HP JACK, SPDIF TX MIC CONNECTOR

APN: 518S0520
L6700 CRITICAL
FERR-1000-OHM
AUD_CONNJ1_SLEEVE2 1 2 HS_MIC_HI
L6781 J6780
OUT 64 FERR-1000-OHM 78171-0003
MIN_NECK_WIDTH=0.20MM 0402 M-RT-SM
R6701 99 64 OUT INT_MIC_F_N 1 2
4
10K 0402
AUD_CONNJ1_SLEEVEDET 1 2 AUD_J1_SLEEVEDET_R OUT 64
MIN_NECK_WIDTH=0.20MM 5% 1/16W INT_MIC_N 1
MF-LF 402
D 84 81 74 73 72 L6702
6 INT_MIC_SHIELD
99 6 INT_MIC_P
2
3
D
55 53 52 49 48
28 27 26 25 8 7 6 PP3V3_S0 FERR-1000-OHM L6780
47 42 40 37 34 30
71 70 69 64 63 59
101 99 88 86 85
FERR-1000-OHM
1 2 AUD_J1_PERIPHDET_R
APN: 514-0632 0402
OUT 64
99 64 OUT INT_MIC_F_P 1
0402
2
5
CRITICAL L6703 1
J6700 FERR-1000-OHM R6780
0
SPDIF-TX-K20 AUD_CONNJ1_TIPDET
1 2 AUD_J1_TIPDET_R OUT 64 5%
1/16W
F-RT-TH MIN_NECK_WIDTH=0.20MM 0402 MF-LF
L6704CRITICAL 2 402
MICROPHONE 6 FERR-220-OHM
DETECT FOR PT 5
AUD_CONNJ1_TIP 1 2 AUD_HPAMP_OUTL_R
SWITCH 2 MIN_LINE_WIDTH=0.40MM
BI 61
MIN_NECK_WIDTH=0.20MM 0402
LEFT 1
RIGHT 3 L6705CRITICAL
FERR-220-OHM
GROUND 4
AUD_CONNJ1_RING 1 2 AUD_HPAMP_OUTR_R 61
BI
AUDIO MIN_LINE_WIDTH=0.40MM
A - VIN
7 L6706
B - VCC
8
9
FERR-1000-OHM
1 2 HS_MIC_LO INT_HP_AMP
SPEAKER CONNECTORS
C - GND
OPERATING VOLTAGE 3.3
0402
OUT 64
R6709 APN: 518S0521
0
POF L6707CRITICAL 1 2 AUD_INT_HP_REF 59
FERR-220-OHM-2.5A 5%
10 1/16W CRITICAL
AUD_CONNJ1_SLEEVE 1 2 AUD_LO_GND_R MF-LF
SHELL 11 OUT 61
12
402
J6781
SHIELD 78171-0004
PINS
13 M-RT-SM
5
AUD_SPDIF_OUT
C IN 59
99 62 6 SPKRAMP_FL_OUT_P 1
C
IN
99 62 6 IN SPKRAMP_FL_OUT_N 2
99 62 6 IN SPKRAMP_BL_OUT_P 3
2
CRITICAL 2
CRITICAL 2
CRITICAL SPKRAMP_BL_OUT_N 4
1 C6700 DZ6700 DZ6702 DZ6704 99 62 6 IN
1UF 6.8V-100PF 6.8V-100PF 6.8V-100PF NOSTUFF NOSTUFF
10% 402 402 402 6
10V
2 X5R C6783 1 1 C6784
402 1 1 1 100PF 100PF
5% 5%
50V 50V
CRITICAL 2
CRITICAL 2
CRITICAL 2
NOSTUFF NOSTUFF CERM 2 2 CERM
DZ6701 DZ6703 DZ6705 C6781 1 1 C6782 402 402
6.8V-100PF 6.8V-100PF 6.8V-100PF 100PF 100PF
402 402 402 5% 5%
50V 50V
CERM 2 2 CERM
1 1 1 402 402
GND_CHASSIS_AUDIO_JACK 63
VOLTAGE=0V
AUDIO JACK 2 LINE IN JACK, SPDIF RX APN: 518S0672

101 99 88
69 64 63 59 55 53
PP3V3_S0 CRITICAL
28 27 26 25 8 7 6
52 49 48 47 42 40 37 34 30
86 85 84 81 74 73 72 71 70 J6782
78171-6006
M-RT-SM
APN: 514-0633 7
B CRITICAL
L6751 SPKRAMP_FR_OUT_P 1 B
FERR-1000-OHM 99 62 6 IN
J6750 AUD_CONNJ2_TIPDET 1 2 AUD_J2_TIPDET_R OUT 64

99 62 6 IN SPKRAMP_FR_OUT_N
SPKRAMP_BR_OUT_P
2
SPDIF-RX-K20 0402 99 62 6 IN
SPKRAMP_BR_OUT_N
3
4
F-RT-TH 99 62 6 IN
DETECT FOR PT 5 L6752 99 62 6 IN SPKRAMP_LFE_OUT_P 5
SWITCH 2 FERR-1000-OHM 99 62 6 SPKRAMP_LFE_OUT_N 6
IN
LEFT 1 AUD_CONNJ2_TIP 1 2 AUD_LI_INL BI 60 NOSTUFF NOSTUFF
RIGHT MIN_NECK_WIDTH=0.20MM 0402 C6787 1 1 C6788 8
GROUND 4 L6753 100PF 100PF
5% 5%
AUDIO FERR-1000-OHM 50V 2 50V
CERM 2 CERM
AUD_CONNJ2_RING 1 2 AUD_LI_INR 402 402
6 BI 60 NOSTUFF NOSTUFF NOSTUFF NOSTUFF
A - VDD MIN_LINE_WIDTH=0.40MM
7 MIN_NECK_WIDTH=0.20MM 0402 C6785 1 1 C6786 C6789 1 1 C6790
B - GND L6754 100PF 100PF 100PF 100PF
C - VOUT
8 600-OHM-300MA 5% 5% 5% 5%
50V 50V 50V 50V
CERM 2 2 CERM CERM 2 2 CERM
OPERATING VOLTAGE 3.3 AUD_CONNJ2_SLEEVE 1 2 AUD_LI_GND 60
402 402 402 402
OUT
POF MIN_LINE_WIDTH=0.40MM
9
10
R6755
SHELL AUD_J2_OPT_OUT 10
11 1 2 AUD_SPDIF_IN OUT 59
SHIELD 5%
PINS
12 1/16W
1 C6750 MF-LF
402
1UF
10%
10V
2 X5R
402 CRITICAL 2 2 CRITICAL 2 CRITICAL
DZ6753 DZ6750 DZ6752
ESDALC5-1BM2 ESDALC5-1BM2 6.8V-100PF
SOD882 SOD882 402
A 1 1
CRITICAL
1 SYNC_MASTER=K17_LENGO SYNC_DATE=11/24/2009 A
2 PAGE TITLE
DZ6751 GND_CHASSIS_AUDIO_JACK 63
AUDIO: JACKS
6.8V-100PF
402 DRAWING NUMBER SIZE
Apple Inc. D
1
RETURN FOR HF NOISE R
REVISION
R6750 NOTICE OF PROPRIETARY PROPERTY: BRANCH

1
0 2 THE INFORMATION CONTAINED HEREIN IS THE
5% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1/16W
MF-LF
402
67 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
"MIKEY"/EXTERNAL MICROPHONE
CODEC OUTPUT SIGNAL PATHS
L6880 MIN_LINE_WIDTH=0.15MM
FUNCTION VOLUME/MUTE CONVERTER PIN COMPLEX MAC OS SHDN WIN SHDN DET ASSIGNMENT FERR-1000-OHM VOLTAGE=3.3V
HP/LINE OUT 0X02 (2) 0X02 (2) 0X09 (9,A) N/A N/A 0X09 (A) 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 1 2 PP3V3_S0_HS_RX
74 73 72 71 70 69 64 63 59 55 53 52 49
SPEAKERS BL/BR 0X02 (2) 0X02 (2) 0X09 (9,V23) GPIO_2 N/A N/A 0402
SPEAKERS FL/FR 0X04 (4) 0X04 (4) 0X0B (11) GPIO_2 GPIO_3 N/A R6890 CRITICAL
SPEAKER LFE 0X03 (3) 0X03 (3) 0X0A (10,D) GPIO_2 GPIO_3 N/A SMBUS_PCH_CLK 1
0 2
C6880 1 1 C6881
SPDIF OUT N/A 0X08 (8) 0x10 (16) N/A N/A 0X0D (B)
48 42 34 32 30 28 26 25 17 6
94 49
IN 10UF 0.001UF
5% 20% 10%
1/16W 6.3V 50V
X5R 2 2 CERM
CRITICAL
MF-LF
R6891
3
402 603 402
CODEC INPUT SIGNAL PATHS 0 AVDD
D FUNCTION CONVERTER PIN COMPLEX VREF DET ASSIGNMENT
48 42 34 32 30 28 26 25 17 6
94 49 BI SMBUS_PCH_DATA 1
5%
2
U6800 D
1/16W CD3275
DRC
KEEP DET TRACE AS SHORT AS POSS
LINE IN 0X05 (5) 0X12 (12,C) N/A 0X12 (C) R6892 MF-LF
402
1
SPDIF IN 0X07 (7) 0x0F (15) N/A N/A 0 HS_SCL 6 SCL MICBIAS HS_MIC_BIAS
19 OUT AUD_I2C_INT_L 1 2
INTERNAL MIC 0X06 (6) 0X0D (13,B,RIGHT) MICBIAS (80%) N/A 5% HS_SDA 5 2 HS_SW_DET
SDA DETECT
EXTERNAL MIC 0X06 (6) 0X0D (13,V22,B,LEFT) MIKEY MIKEY 1/16W
MF-LF
HS_INT_L 7 10 HS_RX_BP
402
R6893 INT* BYPASS
0
25 20 IN AUD_IPHS_SWITCH_EN 1 2 HS_RST_L 8 ENABLE
5%
1/16W
GND THM CRITICAL
1 C6882 1
4
C6883
11
MF-LF
PORT A DETECT PORT B DETECT 402 1
R6880 0.01UF 4.7UF
64 59 AUD_SENSE_A (LINE OUT) (SPDIF DELEGATE) 100K
5%
10%
25V
2 X7R
20%
2 6.3V
OUT TANT
1/16W 402
MF-LF 603-HF
2 402
64 PP3V3_S0_AUDIO_F 1
R6806 1
R6805 64 61 60 59 GND_AUDIO_CODEC
39.2K 20.0K 1 1
1 1% 1% NOSTUFF R6881 R6882
R6801 1/16W 1/16W 1 1K 2.2K
270K AUD_OUTJACK_INSERT_L MF-LF
2 402
MF-LF
2 402
R6884 5%
1/16W
5%
1/16W
5% 0 MF-LF MF-LF
1/16W AUD_PORTD_DET_L NC AUD_PORTG_DET_L NC 5% 2 402 2 402
MF-LF D 3 1/16W
2 402 Q6800 MF-LF
SSM6N15FEAPE Q6801 D 3 Q6801 D 6 2 402
SOT563
SSM6N15FEAPE SSM6N15FEAPE
R6802 SOT563 SOT563
AUD_J1_TIPDET_R 1
47K 2 AUD_J1_DET_RC
63 IN
5%
5 G S 4 CRITICAL
1/16W 1 5 G S 4 2 G S 1 C6884 R6885
MF-LF
402
C6801 0.47UF 2.2K 2
0.1UF AUD_MIC_INL_P 1 2 HS_MIC_HI_R HS_MIC_HI
C 2 20% 10V
CERM 402
59 OUT
10%
1
5%
1/16W
IN 63
C
64 61 60 59 GND_AUDIO_CODEC 10V
X5R
MF-LF NOSTUFF
R6803 402 R68831 1 C6886 402
1 C6887
100K 0.0082UF 15PF
100K 2 5%
64 PP3V3_S0_AUDIO_F 1 AUD_J1_SLEEVEDET_INV 1/16W 10% 5%
MF-LF 2 25V
X7R 2 50V
CERM
1 5% CRITICAL 402 2 402 402
R6804 1/16W
MF-LF C6885
220K 402 D 6 0.47UF
5%
1/16W
Q6800 64 63 AUD_J1_SLEEVEDET_R
59 AUD_MIC_INL_N 1 2 HS_MIC_LO 63
MF-LF SSM6N15FEAPE OUT IN
SOT563
2 402 10%
AUD_J1_SLEEVEDET_R 10V
64 63 IN XW6800
SM
X5R
402
1 C6802 2 G S 1 GND_AUDIO_CODEC 1 2
0.01UF 64 61 60 59
10%
2 16V
CERM INTERNAL MICROPHONE
64 61 60 59 GND_AUDIO_CODEC 402
R6855
2.2K 2
59 IN AUD_CODEC_MICBIAS 1 INT_MIC_BIAS
5%
1/16W
CRITICAL
1
PORT C DETECT (LINE IN)
MF-LF
402 C6854
10UF 1
20%
2 16V R6850
64 59 OUT AUD_SENSE_A TANT-POLY 3.40K
2012-LLP 1%
64 61 60 59 GND_AUDIO_CODEC 1/16W
1 MF-LF
R6813 CRITICAL 2 402
64 PP3V3_S0_AUDIO_F 10K C6850
1% 0.47UF
1/16W
MF-LF 59 OUT AUD_MIC_INR_P 1 2 INT_MIC_F_P IN 63 99
402 2
B 1
R6811
270K AUD_INJACK_INSERT_L NC
10%
10V
X5R 1 NOSTUFF
B
5%
1/16W Q6802 402 C6852 1 R6852 1 C6853
MF-LF 0.0082UF 100K 15PF
2 402 SSM3K15FV D 3 10% 5% 5%
SOD-VESM-HF 25V 1/16W 50V
X7R 2 MF-LF 2 CERM
CRITICAL 402 2 402 402
R6812 C6851
AUD_J2_TIPDET_R 1
47K 2 AUD_J2_DET_RC 0.47UF
63 IN
59 OUT AUD_MIC_INR_N 1 2 INT_MIC_F_N IN 63 99
5% 1 1 G S 2
1/16W
MF-LF
402
C6811 10%
10V
0.1UF X5R
2 20% 10V 402 1
CERM 402 R6851
GND_AUDIO_CODEC 3.40K
64 61 60 59 1%
1/16W
EXTRACTION NOTIFICATION CKT MF-LF
2 402
XW6850
SM
64 IN PP3V3_S0_AUDIO_F
64 61 60 59 GND_AUDIO_CODEC 1 2 INT_MIC_RET
1
R6861
220K
5%
1/16W
MF-LF 1
2 402 R6862
100K
5%
1/16W
MF-LF
PLACE L6800/C6800 CLOSE TO Q6800/01/02 2 402
Q6803 D 3 R6863
L6800 SSM6N15FEAPE AUD_PERIPH_DET_R 1
0 2 AUD_IP_PERIPHERAL_DET OUT
FERR-1000-OHM SOT563
19
A 101 99 88 86 85 84 81 74
47 42 40 37 34 30 28 27 26 25 8 7 6
73 72 71 70 69 64 63 59 55 53 52 49 48
PP3V3_S0 1 2 PP3V3_S0_AUDIO_F
VOLTAGE=3.3V
64
5%
1/16W
MF-LF
0402 MIN_LINE_WIDTH=0.20MM Q6803 D 6 402 PAGE TITLE
1 C6800
0.1UF
R6860
5 G S 4 SSM6N15FEAPE
SOT563
AUDIO: JACK TRANSLATORS
10% DRAWING NUMBER SIZE
15K PERIPHDET_FILT
2 16V
X5R 63 AUD_J1_PERIPHDET_R 1 2
Apple Inc. D
402 5% 2 G S 1 REVISION
64 61 60 59 GND_AUDIO_CODEC 1/16W R
MF-LF
402
1 C6860
0.1UF AUD_J1_PERIPHDET_INV NOTICE OF PROPRIETARY PROPERTY: BRANCH
20%
10V
2 CERM THE INFORMATION CONTAINED HEREIN IS THE
402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
64 61 60 59 GND_AUDIO_CODEC
68 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MagSafe DC Power Jack

CRITICAL
F6905
CRITICAL 6 PP18V5_DCIN_FUSE 1
6AMP-24V
2
PPDCIN_G3H 6 7 65 66
1-Wire OverVoltage & ESD Protection
J6900 MIN_LINE_WIDTH=1mm
78048-0573 VOLTAGE=18.5V 1206-1 48 47 46 45 43 23 21 17 7 6
74 66 65 54 51 50 49
PP3V42_G3H
M-RT-SM
1 C6905 D
D PWR
PWR
1
2 20%
0.01UF
C6908 1
3 2 50V
CERM 0.1UF
GND 603 20%
GND 4 U6901 10V
CERM 2
SIG 5 TC7SZ08AFEAPE 5 402
SOT665
A
2 SMC_BC_ACOK IN 46 47 66
3
SMC_BC_ACOK_BUF 4
Y
CRITICAL 1
B
NO STUFF 1
D6900 R6929
1
3
VCC 2.0K
RCLAMP2402B
2
5%
SC-75 1/16W
NC U6900 MF-LF
MAX9940 2 402
SC70-5
6 ADAPTER_SENSE 5 EXT INT 4 SYS_ONEWIRE BI 46 47
CRITICAL
NO STUFF
1
R6900 NC GND
2
3
100K
1%
1/16W
MF-LF NC
2 402
C
3.425V "G3Hot" Supply C
Supply needs to guarantee 3.31V delivered to SMC VRef generator
CRITICAL
L6991
10UH
SDQ25
1 4
L1 L2
1
R6906
P3V42G3H_SENSE 274K 2 3
1% CRITICAL PP3V42_G3H
CRITICAL 1/16W
CRITICAL MF-LF D6906 6 7 17 21 23 43 45 46 47 48 49
50 51 54 65 66 74
D6905 U6991 2 402
C6903
POWERDI-123
Vout = 3.426V
R6905 BAT30CWFILM LTC1871
1 2
SOT-323 4.7UF 350mA max output
66 65 7 6 PPDCIN_G3H 1
47
2 PPDCIN_S5_P3V42G3H 1 10 SENSE
MSOP
RUN 1 P3V42G3H_EN C6902 2 1 P3V42G3H_SW DFLS130
MIN_LINE_WIDTH=0.3 mm 0.0047UF MIN_LINE_WIDTH=0.3 mm
PPVIN_G3H_P3V42G3H 9 VIN MIN_NECK_WIDTH=0.3 mm CRITICAL
1/3W VOLTAGE=18.5V 3 ITH 2 P3V42G3H_ITH 2 1 P3V42G3H_ITH_RC 20% VOLTAGE=3.42V
R6904
MF
805
25V
CERM
SWITCH_NODE=TRUE DIDT=TRUE
191K 2
1 C6906 1
C6907
2
VOLTAGE=18.5V P3V42G3H_INTVCC 8 INTVCC FB 3 P3V42G3H_FB 10% 1206 1 4.7UF 47UF
25V 20% 20%
CERM 1% 2 6.3V 2 6.3V
7 GATE 402 X5R-CERM
FREQ 4 P3V42G3H_FREQ 1/16W POLY
1 C6900 MF-LF 402 CASE-B3-SM1
CRITICAL 10UF MODE/ 5 C6904 402
C6901 <Ra>
6 GND
10% 1 1 1 1 470PF
D6907 25V
2 X5R 4.7UF
SYNC R6901 R6902 R6903 3 2 1
POWERDI-123 805 10% 80.6K 107K 10K
1 2 10V 2 1% 1% 5%
66 65 6 PPVBAT_G3H_CONN 1/16W 1/16W 1/16W
X5R 353S2800 MF-LF MF-LF MF-LF D CRITICAL 5%
805 50V
2 402 2 402 2 402 Q6991
B DFLS120LXG
P3V42G3H_GATE
<Rb> 1 G FDN337N-G
NP0-C0G
402 B
S SOT23
Vout = 1.230V * (1 + Ra / Rb)

2
Battery Connector
CRITICAL
J6950
BIL Connector
GS731301047E7H CRITICAL
M-RT-SM
14 PPVBAT_G3H_CONN 6 65 66
J6995
MIN_LINE_WIDTH=0.6 mm FF18-5A-R11AD-B-3H
MIN_NECK_WIDTH=0.4 mm F-RT-SM
1 VOLTAGE=8.4V PP3V42_G3H 6 7 17 21 23 43 45 46 47 48 49
50 51 54 65 66 74
2
1 C6950 1 C6951 1
3
0.001UF
10%
0.001UF
10% 518S0720 2 SMBUS_SMC_BSA_SDA IN 6 46 49 65 66 97
4 2 50V
CERM
50V
2 CERM 3 SMBUS_SMC_BSA_SCL BI 6 46 49 65 66 97
402 402 4 SMC_BIL_BUTTON_L 6 46 47
5 OUT
5
6 SMBUS_SMC_BSA_SCLIN 6 46 49 65 66 97
7 SMBUS_SMC_BSA_SDA BI
1 C6955 1 C6953
6 46 49 65 66 97
0.001UF 47PF
8 SYSTEM_DETECT_L 10% 5%
9 2 50V
CERM 2 50V
CERM
A 10 CRITICAL
D6950
402 402
1
11 PAGE TITLE
12 RCLAMP2402B Q6910 C6952 1 C6954 1 DC-In & Battery Connectors
SC-75 SSM3K15FV 47PF 0.001UF
13 D 3 1 5% 10%
SOD-VESM-HF R6912 50V
CERM 2
50V
CERM 2
DRAWING NUMBER SIZE
100K 402 402 Apple Inc. D
3
15 PLACE_NEAR=J6950.6:5mm 5%
1/16W REVISION
MF-LF R
2 402
GND NOTICE OF PROPRIETARY PROPERTY:
518S0694 1 G S 2
BRANCH
47 46 IN SMC_BATT_ULP_L PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

69 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Reverse-Current Protection Inrush Limiter

CRITICAL CRITICAL
FROM ADAPTER Q7080 Q7085
HAT1128R01 HAT1128R01
SOI SOI
65 7 6 PPDCIN_G3H
8
D4 3
PPDCIN_G3H_OR_PBUS 3 D4
8 PPDCIN_G3H_INRUSH
D
7
6
D3
S3
S2 2 MIN_LINE_WIDTH=0.6 mm
1VOLTAGE=18.5V
2
S3
S2 D3
7
6
VOLTAGE=18.5V D
5
D2
D1 S1 1
R7080 1 C70851 R7085 1 S1
D2
D1 5
100K 0.1UF 470K
GATE 5% 10% 1% GATE
1/16W 25V
2 X5R 1/16W
4 MF-LF 402 MF-LF 4
2 402 2 402
CHGR_SGATE_DIV CHGR_AGATE_DIV
MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm
1 1
R7081 R7086
CRITICAL 62K 332K
5% 1%
D7005 1/16W
MF-LF
1/16W
MF-LF
BAT30CWFILM 2 402 402 2
SOT-323
1 (CHGR_SGATE) (CHGR_AGATE)
3 R7003 20
(CHGR_DCIN)
CHGR_DCIN_R 5% R7021
2 1/16W
1
10 2
MF-LF
402 CRITICAL
ACIN pin threshold is 3.2V, +/- 50mV 5%
CHGR_CSI_R_P 3 1
1 C7020 1/16W
MF-LF
99
R7020
Divider sets ACIN threshold at 13.55V 0.047UF 402 0.020
0.5%
10% 1W
10V CHGR_CSI_R_N
Input impedance of ~40K meets 2 CERM R7022 99 MF-LF
30mA max load 402 4 2 0612
sparkitecture requirements 1
10 2
PP5V1_CHGR_VDD R7001 PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.2 mm 4.7 5% MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm 1 2 PP5V1_CHGR_VDDP 1/16W MIN_NECK_WIDTH=0.4 mm CRITICAL CRITICAL CRITICAL CRITICAL
VOLTAGE=5.1V MIN_LINE_WIDTH=0.2 mm MF-LF VOLTAGE=18.5V
PP3V42_G3H
5%
1/16W
VOLTAGE=5.1V
402 1
C7030 1
C7031 1
C7032 1
C7033 1 C7035 1 C7036 1 C7037
48 47 46 45 43 23 21 17 7 6
74 65 54 51 50 49 MF-LF 5 22UF 22UF 22UF 22UF 1UF 1UF 0.001UF
402 C7001 1 C7022 1 1 C7021 20%
2 25V
20%
25V
2 POLY-TANT
20%
2 25V
20%
25V
2 POLY-TANT
10%
2 25V
10%
2 25V
10%
2 50V
1UF 0.1UF 0.1UF CRITICAL POLY-TANT POLY-TANT X5R X5R X7R
1 10% 10% 10% CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM 603-1 603-1 402
C R7010
30.1K NO STUFF
1
10V 2
X5R
402
25V 2
X5R
402
2 25V
X5R
402 4
Q7031 C
1%
1/16W R7002 RJK0305DPB
19
20
MF-LF 100K LFPAK-HF
2 402 5%
1/16W 5
MF-LF VDD VDDP
R7000 2 402 12 VHST CRITICAL DCIN 2 CHGR_DCIN CRITICAL
SMC_RESET_L 1
0 2 CHGR_RST_L 13
Max Current = 15A
48 47 46 6 IN SMB_RST_N
SGATE 26 CHGR_SGATE Q7030 1 2 3
5% 49
1/16W97
46 6
65 IN SMBUS_SMC_BSA_SCL 11 SCL U7000
AGATE 1 CHGR_AGATE 1 C7025
4 RJK0305DPB (L7030/L7031 limit)
MF-LF49 SMBUS_SMC_BSA_SDA 10 SDA TQFN 0.22UF LFPAK-HF
402 97
46 6 BI
CSIP 28 CHGR_CSI_P f = 400 kHz
ISL6259HRTZ
65 97
74 IN CHGR_VFRQ 4 VFRQ 10%
CSIN 27 97 CHGR_CSI_N 10V
2 CERM
CHGR_CELL 6 CELL CRITICAL CRITICAL CRITICAL
Float CELL for 1S 25 CHGR_BOOT
402
L7030 L7031 TO SYSTEM
CHGR_ACIN 3 ACIN
BOOT
DIDT=TRUE 1 2 3 2.2UH-20A-5.5M-OHM 2.2UH-20A-5.5M-OHM
F7040
UGATE 24 CHGR_UGATE 8AMP-24V PPBUS_G3H 6 7 8 40 50 67 68 70 71
83 87
GATE_NODE=TRUE DIDT=TRUE
1
CHGR_ICOMP 5 ICOMP PHASE 23 CHGR_PHASE 1 2 CHGR_PHASE_MID 1 2 1 2
R7011 CHGR_VCOMP 7 VCOMP
MIN_NECK_WIDTH=0.2 mm SM MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm SM
9.31K LGATE 21 CHGR_LGATE SWITCH_NODE=TRUE VOLTAGE=8.4V 1206
1% CHGR_VNEG 8 VNEG GATE_NODE=TRUE DIDT=TRUE 5 DIDT=TRUE
1/16W 1 CHGR_CSO_P 18 CSOP 16 CHGR_BGATE NO STUFF CRITICAL
MF-LF
2 402
R7015 97 BGATE
CRITICAL R70391 F7041
220K 97 CHGR_CSO_N 17 CSON 20V/V AMON 9 CHGR_AMON OUT 50
5% Q7036 10 8AMP-24V
THRM_PAD
1/16W 36V/V BMON 15 CHGR_BMON 5%

(AGND)
OUT 50
MF-LF 4 RJK0305DPB 1/10W PPVBAT_G3H_CHGR_REG 1 2
R7013 1
2 402
1 C7050 (OD) ACOK 14 SMC_BC_ACOK OUT 46 47 65
LFPAK-HF MF-LF MIN_LINE_WIDTH=0.6 mm
CRITICAL CRITICAL TO/FROM BATTERY
PGND
1UF 603 2 MIN_NECK_WIDTH=0.4 mm

100 VOLTAGE=8.4V 1206
1%
1/16W
CHGR_VCOMP_R 10%
16V
2 X5R
5 C7040 1
C7041 1 1 C7045 PPVBAT_G3H_CONN
MF-LF 33UF 33UF 0.001UF 6 65
402 CHGR_PHASE_RC 10%
29
22
402 2 353S2392 CRITICAL 20% 20%

C7015 1 DIDT=TRUE 16V
POLY-TANT 2
16V
POLY-TANT 2 2 50V
X7R
470PF
10% 4
Q7035 1 2 3 CASED2E-SM CASED2E-SM 402
50V RJK0305DPB CRITICAL CRITICAL CRITICAL
CERM 2 NO STUFF
402
LFPAK-HF
1 C7039 R7050 Q7055 Q7056
0.005 SI7137DP SI7137DP
0.001UF
B 10%
2 50V
X7R
1%
1W
MF
SO-8 SO-8
B
R70161 XW7000 402
0612
S
1 2 3 2 1 PPVBAT_G3H_CHGR_R
3.01K
2 3
2 3
SM MIN_LINE_WIDTH=0.6 mm
D
1% 4 3 MIN_NECK_WIDTH=0.4 mm PPVBAT_G3H_FET
1/16W 1 2 (GND) VOLTAGE=8.4V
5
MF-LF
PLACE_NEAR=U7000.29:1mm C7055 1 C7056 1 C7057 1
1
402 2
PLACE_NEAR=U7000.22:1mm 1UF 0.1UF 0.01uF
G
CHGR_VNEG_R 10% 10% 10% MIN_LINE_WIDTH=0.6 mm
25V 2 16V 2 16V
CERM 2
4
X5R X5R MIN_NECK_WIDTH=0.4 mm 1
R7051 603-1 402 402 VOLTAGE=8.4V
C7058 1 R7058
1 C7016 (CHGR_CSO_P) 2.2 1 2 99 50
5%
CHGR_CSO_R_P
1/16W MF-LF 402 1UF 1%
1M
470PF 10%
10% (CHGR_CSO_N) R7052 0 1 2 99 50 CHGR_CSO_R_N 10V 2 1/16W
MF-LF
2 50V
CERM 5% 1/16W MF-LF 402 X5R
402 2 402
402
(PPVBAT_G3H_CHGR_R) (PPVBAT_G3H_CHGR_R) BATT_POS_GATE
(CHGR_BGATE) R7092 1K 1 2 CHGR_BGATE_R 1
5% 1/16W MF-LF 402 R7059
20K
1 C7042 C7002 1 C7011 1 1 C7000 C7005 1 C7026 1 5%
0.068UF
10%
1UF
10%
0.01UF
10% 10%
1UF 0.22UF
20%
0.001UF
10%
R7093 220K 1 2 CHGR_OVP_G_C 1/16W
MF-LF
5% 1/16W MF-LF 402
2 10V 10V 2 16V 2 10V 25V 50V 2 402
CERM X5R CERM 2 X5R CERM 2 CERM 2
402 402 402 402-1 805 402 GND
GND_CHGR_AGND 1 2 3
VOLTAGE=0V
PLACE_NEAR=Q7055.4:1mm
CRITICAL
SOT-363
ASMCC0178
U7090
A 6 5 4
CHGR_OVP_A PAGE TITLE
R7094 1K 1 2 CHGR_OVP_B PBus Supply & Battery Charger
5% 1/16W MF-LF 402
DRAWING NUMBER SIZE
1 C7090 1
R7090 D
100PF 20K Apple Inc.
5% 5% REVISION
PLACE_NEAR=U7090.5:1mm 50V
2 CERM 1/16W R
402 MF-LF
70 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
PP5V_S5 7 23 57 73 102
Vout = 5V
100mA MAX OUTPUT
83 71 70
40 8 7 6
PPBUS_G3H
68 66 50
87
CRITICAL CRITICAL CRITICAL CRITICAL

1 C7270 C7240 1 C7242 1 1 C7241 67 51 7 PP5V_S3_ISNS_R
67 P5VP3V3_VREG3 C7280 1 C7282 1 1 C7281 1 C7283
0.001UF 68UF 68UF 1UF 68UF 68UF 1UF 0.001UF
10% 20% 20% 10% 20% 20% 10% 10%
2 50V
X7R 16V
POLY-TANT
2 16V 2
POLY-TANT
2
16V
X5R R7264 16V
POLY-TANT
2 16V 2
POLY-TANT
2
25V
X5R
50V
2 X7R
402 402 1 0 2 P3V3S5_VBST_R 603-1 402
CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM
67 P5VP3V3_VREF2 5% 1/16W 402
MF-LF
23
29
22
13
2
C7201 1
C7203 1 1
C7205
C7200 1
0.22UF 1UF 10UF
5
V5SW
VIN
VREG5
VREG3
VREF2
1UF 10% 10% 20% C7264 1
10% 10V 6.3V 6.3V
2 2 2
CRITICAL 25V
2
CERM CERM X5R 0.1UF 5
D X5R 402 402 603 10%
603-1 50V
F=400KHZ Q7220 G 4
6 SKIPSEL1 X7R 2 D
RJK0332DPB-01 19 SKIPSEL2
CRITICAL 603-1
CRITICAL
67 51 7 PP5V_S3_ISNS_R LFPAK-SM
C7224 14 OCSEL U7201 Q7260 PP3V3_S5_ISNS_R 7 51
C Vout = 5.0V S
1
0.1UF R7245
QFN
EN 12 P5VS5_EN IN 74
4
SIS426DN
PWRPK-12128 Vout = 3.3V C
TPS51980
10%
0 G
CRITICAL 50V
2 X7R P5VS3_VBST_R 1 2P5VS3_VBST 31 VBST1 VBST2 26 P3V3S5_VBST CRITICAL
12A MAX OUTPUT L7220 MIN_LINE_WIDTH=0.6 mm603-1 5% 1/16W 402 MIN_LINE_WIDTH=0.6 mm S
L7260
9A MAX OUTPUT
3 2 1 MIN_NECK_WIDTH=0.2 mm MF-LF
1 DRVH1
4.7UH-13A-22.5MOHM P5VS3_DRVH DRVH2 24 P3V3S5_DRVH 1 2 3 2.2UH-14A
MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE DIDT=TRUE GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm F=400KHZ
1 2 MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
P5VS3_LL 32 SW1 SW2 25 P3V3S5_LL 1 2
PIMB103T4R7MS-SM SWITCH_NODE=TRUE DIDT=TRUE SWITCH_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm

CRITICAL
30 DRVL1
MIN_NECK_WIDTH=0.2 mm NO STUFF
1
IHLP2525CZ-SM1 CRITICAL
C7252 1
2 2
P5VS3_DRVL
DRVL2 27 P3V3S5_DRVL
GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm
5 R7298 2
2
C7290
1
C7292 1 1 C7272
330UF
C7250 1
XW7220 XW7221 MIN_NECK_WIDTH=0.2 mm
P5VS3_CSP1 7 CSP1
MIN_NECK_WIDTH=0.2 mm CRITICAL D 10 XW7261 10UF 330UF 0.001UF
CSP2 18 P3V3S5_CSP2 5% XW7260
20%
6.3V 2
10UF
20%
SM SM
C7218 P5VS3_CSN1 NO STUFF 8 CSN1 CSN2 17 P3V3S5_CSN2 Q7261 1/10W
MF-LF SM
SM
2
20%
6.3V
20%
6.3V 2
10%
2 50V
POLY-TANT 10V
2 1 1 0.1UF R7248 SIS426DN 603 2 1
X5R POLY-TANT X7R
CASE-D3L-SM1 X5R
0 C7288 PLACE_NEAR=L7260.1:3mm
1
603 CASE-D3L-SM1 402
805 PLACE_NEAR=L7220.1:3mm 1 2 67 P5VP3V3_VREG31 2 P5VS3_FUNC 11 MODE RF 3 P3V3S5_RF 0.1UF PWRPK-12128
PLACE_NEAR=L7220.2:3mm 402 X5R 5% 1/16W 402
4 P3V3S5_LL_RC
1 9 VFB1 PLACE_NEAR=L7260.2:3mm
1 C7271 R7299 5 16V
10%
MF-LF P5VS3_VFB1 VFB2 16 P3V3S5_VFB2 1
10% 25V
2
G DIDT=TRUE NO STUFF
0.001UF NO STUFF 5%
1 CRITICAL D P5VS3_COMP1 10 COMP1 COMP2 15 P3V3S5_COMP2 402 X5R S 1 C7298
10% 1/10W Q7225 R7247 0.001UF
2 50V
X7R 2 MF-LF 3.16K P5VS3_EN_R 4 EN1 EN2 21 P3V3S5_EN_R 1 2 3 10%
50V
402 603 2 SIS426DN 1 2 2 X7R 2
XW7222 PWRPK-12128 1%
5 PGOOD1 PGOOD2 20 R7246 402
1.27K
SM P5VS3_LL_RC 4 1/16W
GND THRM_PAD
1 2 XW7262
PLACE_NEAR=L7220.1:3mm NO STUFF G MF-LF 1 1 SM
1
DIDT=TRUE 402 R7236 1 NO STUFF R7238 1 NO STUFF 1%
1 C7299 R7237 R7239
28
S 1/16W
33
6.04K 6.04K 1
P5VS3_VFB1-R
0.0033UF 1% 20.0K 1
XW7200 353S2678 1
R7206 1% 20.0K MF-LF
402 1
10% 3 2 1 1 1/16W 1% R7249 SM
249K
1/16W 1% R7216 PLACE_NEAR=L7260.2:3mm
50V
2 CERM R7256 MF-LF
402
1/16W
MF-LF 0 1 2 1%
MF-LF
402
1/16W
MF-LF 4.02K P3V3S5_VFB2_R
8.87K 2 2
402 402 5% 1/16W 402 1%
1% P5VS3_COMP1_R 2
1/16W MF-LF
2
1/16W
1/16W MF-LF PLACE_NEAR=U7201.28:1mm 2
402 P3V3S5_COMP2_R MF-LF
1
1 MF-LF
C7236 1
C7237 1 2
402
C7238 1
C7239 1 2
402 R7260
R7220 2 402
23.2K
40.2K 0.047UF 100PF 0.047UF 100PF P3V3S5_CSP2_R 1%
10% 5% 10% 5%
1% 16V 50V 16V 50V 1/16W
1/16W X7R 2 CERM 2 X7R 2 CERM 2 MF-LF
MF-LF 402 402 402 402 2 402
2 402 P5VS3_CSP1_R
B 1
67 P5VP3V3_VREF2 67 P5VP3V3_VREF2
1
B
R7221 R7261
10K 10K
1% 74 OUT P5VS3_PGOOD 1%
1/16W 1/16W
MF-LF MF-LF
2 402 74 OUT P3V3S5_PGOOD 2 402
GND_P5VP3V3_SGND
VOLTAGE=0V
1 1
R7251 R7252
0 0
5% PLACE_NEAR=U7201.4:2mm 5% PLACE_NEAR=U7201.21:2mm
1/16W 1/16W
MF-LF MF-LF
402
2 2 402
74 IN P5VS3_EN 74 IN P3V3S5_EN
PAGE TITLE
5V / 3.3V Power Supply

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R
.
72 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
87 83 71 70 67 66 50 40 8 7 6 PPBUS_G3H
73 68 31 30 28 7 PP1V5_S3
CRITICAL CRITICAL ISNS_1V5_S3_P OUT 51 99
C7330 1 C7331 1 1 C7332 1 C7333

1 C7355 100UF 68UF 1UF 0.001UF
20% 20% 10% 10% ISNS_1V5_S3_N
10UF 16V 2 16V 2
25V
2 X5R 50V
2 X7R OUT 51 99
20% TANT POLY-TANT
2 6.3V
X5R D-HF CASE-D2E-SM 603-1 402
603
103 83 73 55 51 47 45 44 43 33 31 7 6 PP5V_S3 R7305

1
4.7 2 PP5V_S3_DDRREG_V5FILT
5% MIN_NECK_WIDTH=0.2 mm 4 3
1/16W VOLTAGE=5V
MF-LF PP1V5_S3 7 28 30 31 68 73
402 2 1
5
CRITICAL
C7300 1 C7305 1 D CRITICAL R7350 Vout = 1.50V
DDRREG_VDDQSNS 0.001 18A MAX OUTPUT
Q7330
15
14
23
4.7UF 1UF 1%
20% 10% (DDRREG_DRVH) 4 G 1W
(Q7335 limit)
6.3V 2 10V 2 MIN_LINE_WIDTH=0.6 mm
CSD58850Q5A MF-1
CERM X5R V5IN V5FILT VLDOIN 0612
603 402 R73101 MIN_NECK_WIDTH=0.2 mm MLP5X6-LFPAK-Q5A f = 400 kHz
6.81K
C 6 COMP
CRITICAL
VDDQSNS 8 1%
1/16W
MF-LF
S
CRITICAL
L7330
C
31 8 IN MEMVTT_EN 10 S3 VTT Enable
MODE 4 402 2
R7325 C7325 1 2 3 1.0UH-20A
DDRREG_EN 0.1UF
74 IN 11 S5 VDDQ/VTTREF Enable 0
VBST 22 DDRREG_VBST 1 2 DDRREG_VBST_R 1 2 1 2 PPDDR_S3_REG_R
74 OUT TP_DDRREG_PGOOD 13 PGOOD VDDQ PGOOD U7300 IHLP4040DZ11-SM MIN_LINE_WIDTH=0.6 mm
5% 10% MIN_NECK_WIDTH=0.2 mm
TPS51116 1/16W VOLTAGE=1.5V
PPVTTDDR_S3 DRVH 21 DDRREG_DRVH MF-LF 50V NO STUFF
32 7 6
10mA max load QFN GATE_NODE=TRUE DIDT=TRUE 402 X7R
603-1 5 1
1 C7345 1 C7346
31 30 28 7 PP0V75_S0_DDRVTT
5 VTTREF
SYM (2 OF 2)
R7370 10UF
20%
0.001UF
10%
Vout = VDDQSNS/2 LL 20 DDRREG_LL (DDRREG_LL) 1 6.3V
24 VTT SWITCH_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm D 5% 2 X5R 2 50V
X7R
MIN_NECK_WIDTH=0.2 mm 1/10W 603 402 2
Vout = VTTREF MF-LF
XW7360
SM
DRVL 19 DDRREG_DRVL
(DDRREG_DRVL)
4 G
2 603 XW7345
MIN_NECK_WIDTH=0.2 mm CRITICAL DIDT=TRUE SM
1 2 DDRREG_VTTSNS 2 VTTSNS Q7335
PLACE_NEAR=C7361.1:3mm CS 16 DDRREG_CS DDRREG_LL_RC 1 PLACE_NEAR=L7330.2:3mm
CRITICAL CRITICAL 7 NC0 CSD58857Q5 S
NO STUFF
NC MLP5X6-LFPAK-Q5
C7360 1 1 C7361 NC 12 NC1 VDDQSET 9 32 DDRREG_FB 1 C7370
22UF 22UF 1 2 3 1000PF
1
C7340 1
C7341
20%
6.3V
20% VTTGND THRM_PAD GND PGND CS_GND 5% 330UF 330UF
X5R-CERM 2 2 6.3V 25V
2 NP0-C0G 20% 20%
X5R-CERM 1 PLACE_NEAR=Q7335.1:3mm XW7335
25
18
17
603 603 402 3 2 2.0V 3 2 2.0V
SM POLY-TANT POLY-TANT
D2T-SM2 D2T-SM2
DDRREG_CSGND (DDRREG_CSGND) 1 2
1
MIN_NECK_WIDTH=0.2 mm R7320
15.0K
353S1491 1%
1/16W
(DDRREG_VDDQSNS) MF-LF
MIN_LINE_WIDTH=0.2 mm 2 402
C7350 1 2
(DDRREG_FB)
<Ra>
0.033UF XW7300
10%
16V 2
SM Vout = 0.75V * (1 + Ra / Rb) 1
R7321
X5R 1 PLACE_NEAR=U7300.25:2mm 15.0K
402 PLACE_NEAR=U7300.3:2mm 1%
1/16W
B MF-LF
2 402 B
GND_DDRREG_SGND <Rb>
VOLTAGE=0V
PAGE TITLE
1.5V DDR3 Supply

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

73 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.5:8mm
PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.7:8mm
50 7 6 PPBUS_CPU_IMVP_ISNS PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.5:8mm PLACE_NEAR=Q7490.7:8mm
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
D C7404 1 C7406 1 C7407 1 C7408 1 C7409 1 C7415 1 C7416 1 C7405 1 C7410 1 C7413 1 1 C7411
10UF
1 C7412
0.001UF
1 C7421
10UF
1 C7422
0.001UF
1 C7425
0.001UF
D
62UF 62UF 62UF 68UF 62UF 62UF 62UF 62UF 68UF 68UF 10% 10% 10% 10% 10%
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
11V 2
ELEC
11V 2
ELEC
11V 2
ELEC
16V 2
POLY-TANT
11V 2
ELEC
11V 2
ELEC
11V 2
ELEC
11V 2
ELEC
16V 2
POLY-TANT
16V 2
POLY-TANT
25V
2 X5R 2 50V
X7R
25V
2 X5R 2 50V
X7R 2 X7R
50V
CASE-B2 CASE-B2 CASE-B2 CASE-D2E-SM CASE-B2 CASE-B2 CASE-B2 CASE-B2 CASE-D2E-SM CASE-D2E-SM 805 402 805 402 402
OMIT
CRITICAL
L7415
0.36UH-20%-40A-0.00075OHM
8 7 1 2
86 85 84 81 74 73 72 71 70
42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 PIMA104E-SM
64 63 59 55 53 52 49 48 47
101 99 88 D CRITICAL
Q7490 2 2
87 73 71 70 55 53 48 42 23 8 7 6 PP5V_S0 2 G IRF6723M2DPBF XW7416 XW7417
102
DIRECTFET-MA SM SM
S
1PLACE_NEAR=L7415.1:4mm 1 PLACE_NEAR=L7415.2:4mm
1
CPUIMVP_PHASE1X CPUIMVP_ISEN1N_R
PP5V_S0_CPUIMVP_V5FILT MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.15 MM MIN_NECK_WIDTH=0.15 MM
VOLTAGE=5V
C7401 1
1 C7400 1
R7416
4.7UF (CPUIMVP_PHASE1) 23.7K
2.2UF 10%
10V NO STUFF 1%
20%
1CRITICAL
10V 2 X5R CPUIMVP_PHASE1_NC 1/16W
X5R-CERM 2 NO STUFF MF-LF
402
805
R7441 1
R7442 1 D7400
SOD523 2 402 R7417
0 0 PMEG2010AEB 1 2 6 7
1
162K 2
5% 5%
1/16W 1/16W 2 D CRITICAL
MF-LF MF-LF NO STUFF R7418 1%
402 2 402 2 1CRITICAL Q7415 0402
1/16W
MF-LF
D7401
SOD523 5 G IRF6795
DIRECTFET-MX
402
R7419
PMEG2010AEB S 2 1 CPUIMVP_ISEN1_NTC 141.2K2
C
38
26
C 2
3 4
BOM: 150K 402
1%
C7403 V5FILT V5IN 1/16W
MF-LF
33PF
1 2
U7400 150KOHM-5% C7420
402
TPS51983 0.022UF
5% 36 TONSEL QFN 22 CPUIMVP_BOOT1 R7414 2 0
1 CPUIMVP_BOOT1_RC C7414 1 2 1UF
CPUIMVP_ISEN1P_R 1 2 48A max current
R7403 50V
CERM
VBST1
21 5% 1/16W MF-LF 402
10% 25V X5R 603-2 MIN_LINE_WIDTH=0.25 MM PPVCORE_S0_CPU
1
5.11K2 402 CPUIMVP_DROOP 39 DRVH1 CPUIMVP_UGATE1 MIN_NECK_WIDTH=0.15 MM 10% 6 7 12
DROOP 23 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE 6 5 15 50
1% 8
353S2942 LL1
24
CPUIMVP_PHASE1
MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE DIDT=TRUE
R74211 16V
CERM-X5R R74221
1/16W 91 12 IN CPU_VCCSENSE_P VSNS DRVL1 CPUIMVP_LGATE1 D CRITICAL 0 402 0
MF-LF 7 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE 5% 5%
402 91 69 12 IN CPU_VCCSENSE_N GNDSNS 29 R7424 2 0 C7424 1 2 1UF Q7490 1/16W 1/16W
VBST2 CPUIMVP_BOOT2 1 CPUIMVP_BOOT2_RC MF-LF MF-LF
40 30 5% 1/16W MF-LF 402 402 2 402 2
CPUIMVP_VREF VREF DRVH2 CPUIMVP_UGATE2 10% 25V X5R 603-2 3 G IRF6723M2DPBF
CRITICAL 28 CPUIMVP_PHASE2
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE S DIRECTFET-MA
CPUIMVP_ISEN1P CPUIMVP_ISEN1N
20 LL2 69 69
8 IN CPUIMVP_VID<0> VID0 27 MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
19 DRVL2 CPUIMVP_LGATE2 MIN_NECK_WIDTH=0.15 MM MIN_NECK_WIDTH=0.15 MM
8 IN CPUIMVP_VID<1> VID1 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE 4
CPUIMVP_VID<2> 18 VID2 33 CPUIMVP_PGOOD OMIT
8 IN PGOOD OUT 27
CPUIMVP_VID<3> 17 34 CPUIMVP_CLK_EN_L CRITICAL

VID3 CLK_EN*
1 C7402
8 IN
CPUIMVP_VID<4> 16 VID4 VR_ON 35 CPUIMVP_VR_ON
OUT 26
L7425
8 IN IN 46 0.36UH-20%-40A-0.00075OHM
0.22UF 8 IN CPUIMVP_VID<5> 15 VID5 DPRSLPVR 12 PM_DPRSLPVR IN 12 15 91
10% (CPUIMVP_PHASE2) 1 2
10V CPUIMVP_VID<6> 14 13 CPU_PSI_L
2 CERM 8 IN VID6 PSI* IN 12 15 91
PIMA104E-SM
402 1 CPUIMVP_PHASE2_NC
37 MODE 2
CPUIMVP_SLEW SLEW 2
6 THERM 9 CPUIMVP_NTC XW7426
SM XW7427
69 CPUIMVP_ISEN1P CSP1 10 R7440 0 SM
5 VR_TT* CPUIMVP_VR_TT_L 2 1 CPU_PROCHOT_L OUT 10 47 91 1 2 6 7
69 CPUIMVP_ISEN1N CSN1 5% 1/16W MF-LF 402 1
1 11 CPUIMVP_IMON
R7400 3
IMON
31
OUT 12 50 91
D CRITICAL PLACE_NEAR=L7425.1:4mm 1 PLACE_NEAR=L7425.2:4mm
249K 69 CPUIMVP_ISEN2P CSP2 TRIPSEL CPUIMVP_TRIPSEL Q7425
1% 4
1
R7450 CPUIMVP_PHASE2X CPUIMVP_ISEN2N_R
1/16W
MF-LF
69 CPUIMVP_ISEN2N CSN2 OSRSEL 32
12.7K
1 C7450 5 G IRF6795 MIN_LINE_WIDTH=0.25 MM
402 2 1% 0.0033UF DIRECTFET-MX
1/16W 10% S
B OMIT OMIT OMIT OMIT
THRM
GND PGND PAD
MF-LF
2 402
50V
2 CERM
402 3 4
1
R7426
23.7K
B
C7440 1 C7441 1 1 C7442 1 C7443 91 69 12 CPU_VCCSENSE_N
BOM: 150K 402
1%
2
25
41
NOSTUFF NOSTUFF NOSTUFF NOSTUFF 1/16W

NONE NONE NONE NONE MF-LF
NONE 2
NONE
NONE 2
NONE 2 NONE
NONE 2 NONE
NONE
R74451 2 402 R7427
402 402 402 402 100K 1
162K 2
5%
1/16W
MF-LF
402 2
1%
1/16W
R7428
MF-LF 0402
XW7400 R7429 402
SM 41.2K2
1 CPUIMVP_ISEN2_NTC 2 1
2 1
1%
1/16W
MF-LF
BOM: 150K 402
402
C7430 150KOHM-5%
0.022UF
CPUIMVP_AGND CPUIMVP_ISEN2P_R 1 2
MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.15 mm MIN_NECK_WIDTH=0.15 MM 10%
VOLTAGE=0V 1 16V
R7430 CERM-X5R
402
R74311
0 0
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2
Loadline = DCR * K * 5.95 / (R7403 * 2uA/mV) CPUIMVP_ISEN2P 69 69 CPUIMVP_ISEN2N

MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
Loadline = 1.83 mohm MIN_NECK_WIDTH=0.15 MM MIN_NECK_WIDTH=0.15 MM
VIMON = Io * DCR * K * 2uA/mV * R7450

50 A = 1.049 V
BOM TABLE
A K = (R7417 || (R7418 + R7419)) / (R7417 || (R7418 + R7419) + R7416) = 0.787 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
SYNC_MASTER=K18_POWER SYNC_DATE=06/29/2009 A
TABLE_5_ITEM PAGE TITLE
CRITICAL
152S1177 2 IND,PWR,0.36uH,1.05MO,12x10x4mm L7415,L7425
CPU IMVP VCore Regulator
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

74 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
87 83 71 68 67 66 50 40 8 7 6 PPBUS_G3H
102 87 73 71 69 55 53 48 42 23 8 7 6 PP5V_S0
C7510 1
2.2UF R7514 1 D7514
CRITICAL CRITICAL
10%
16V 2 5%
0
BAT30CWFILM
1 C7524 C7520 1 C7521 1 1 C7523
X5R
603 C7513 1 1/16W SOT-323 0.001UF 68UF 100UF 1UF
101 99 88 86 85 84 81
PP3V3_S0 GFXIMVP_DROOP MF-LF 10% 20% 20% 10%
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49 2.2UF 402 1 50V
2 CERM 16V 2 16V 2 2 25V
10% 2 POLY-TANT TANT X5R
16V 2 402 CASE-D2E-SM D-HF 603-1
X5R GFXIMVP_VBST_R 3
603 5
21
1
R7512
C 1K
1% C7511 1
1
R7511
1.69K
V5IN
C7514
1UF
1
2
D
CRITICAL C
1/16W
MF-LF 33PF
5% 1% U7500 10%
16V 2 GFXIMVP_UGATE 4 G
Q7530
402 2 50V 1/16W X5R CSD58850Q5A
CERM 2 MF-LF MIN_LINE_WIDTH=0.6 mm
402 2 402
TPS51981 402 MIN_NECK_WIDTH=0.2 mm MLP5X6-LFPAK-Q5A
QFN GATE_NODE=TRUE CRITICAL
DIDT=TRUE
31 DROOP V5FILT 30 PP5V_S0_GFXIMVP_V5FILT
MIN_LINE_WIDTH=0.6 mm VOLTAGE=5V
S
CRITICAL R7540 Vout = VID controlled
GFXIMVP_TONSEL 27 TONSEL CRITICAL MIN_NECK_WIDTH=0.2 mm 0.001 22A max output
VBST 18 GFXIMVP_VBST
1 2 3
L7530 1%
1W f = 350KHz
91 13 GFX_VSENSE_P 5 VSNS DRVH 17 0.47UH-26A MF-1
IN 0612
91 13 GFX_VSENSE_N 4 GNDSNS LL 19 GFXIMVP_PHASE 1 2 PPVCORE_S0_GFX_REG_R 1 2 PPVCORE_S0_GFX 7 13 24 50
IN
20 MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6MM
IHLP2525CZERR47M01 MIN_NECK_WIDTH=0.2MM 3 4
32 DRVL MIN_NECK_WIDTH=0.2 mm
70 GFXIMVP_VREF VREF SWITCH_NODE=TRUE VOLTAGE=1.05V
23 TP_GFXIMVP_PGOOD DIDT=TRUE NO STUFF
16 PGOOD OUT 74
8 IN GFXIMVP_VID<0> VID0 24
1
R7570
15 CLK_EN* NC
8 IN GFXIMVP_VID<1> VID1 25 1
14 VR_ON GFX_VR_EN IN 13 91 CRITICAL 5 5%
8 IN GFXIMVP_VID<2> VID2 9 1/10W
DPRSLPVR GFX_DPRSLPVR Q7535 MF-LF
8 IN GFXIMVP_VID<3> 13 VID3
MODE 22
IN 13 91
D 2 603 C7556 1 1 C7557
8 GFXIMVP_VID<4> 12 VID4
CSD58857Q5 DIDT=TRUE
10UF 0.001UF
IN MLP5X6-LFPAK-Q5 20% 10%
8 IN GFXIMVP_VID<5> 11 VID5 IMONC 28 GFXIMVP_OSRSEL R7510 GFXIMVP_LGATE 4 G GFXIMVP_LL_RC 6.3V 2
X5R
50V
2 CERM
GFXIMVP_VID<6> 10 26 GFXIMVP_TRIPSEL 0 GFXIMVP_VREF 70 MIN_LINE_WIDTH=0.6MM 603 402
R7513 8 IN VID6 TRIPSEL 1 2 MIN_NECK_WIDTH=0.2MM NO STUFF
GATE_NODE=TRUE
1
46.4K2 GFXIMVP_ISLEW 29 ISLEW
IMON 8 GFXIMVP_IMON 5%
1/16W OUT 13 91 DIDT=TRUE
S
1 C7570
VR_TT* 7 MF-LF 1000PF
1% NC 402 5%
1/16W 99 GFXIMVP_CS_P 2 CSP THERM 6GFXIMVP_THERM 25V
2 NP0-C0G
MF-LF 3 1 2 3 402
402 99 GFXIMVP_CS_N CSN
PGND
SIGNAL_MODEL=EMPTY
GND
SIGNAL_MODEL=EMPTY 1
C7512 1 R7516 C7515 1 R7515 R7518
0.22UF 150K 0.0033UF 22.6K 200K
353S2664
1/16W R7517
1
33
10% 1% 10% 1% 1%
1/16W 1/16W
10V
CERM 2 PLACE_NEAR=U7500.1:1mm
XW7500
SM
MF-LF
402
100K
1%
50V
CERM 2 MF-LF MF-LF
402 402 2 402 402
B PLACE_NEAR=U7500.33:1mm 2 1
1/16W
MF-LF
402
B
GND_GFXIMVP_AGND
MIN_LINE_WIDTH=0.6MM (GND_GFXIMVP_AGND)
MIN_NECK_WIDTH=0.2MM 84 85 86 88 99 101
VOLTAGE=0V (GFX_VSENSE_N) PP3V3_S0 6 7 8 25 26 27 28 30 34 37 40 42 47 48 49
52 53 55 59 63 64 69 70 71 72 73 74 81
R7542
1
0 2 99 50 GFXIMVP_CS_R_N
5% 99 50 GFXIMVP_CS_R_P
1/16W
MF-LF
OMIT 402
C7549 1 C7542 1
1 C7517
10PF
5% NOSTUFF
R7541 0.022UF
10%
50V NONE 1
0 2 16V
CERM 2 NONE 2 2 CERM-X5R
402 NONE OMIT 5% 402
402 1/16W
SIGNAL_MODEL=EMPTY C7541 1 MF-LF
402
NOSTUFF
NONE
NONE 2
NONE
402
SIGNAL_MODEL=EMPTY (GND_GFXIMVP_AGND)
Imon = Io x R7540 x 2uA/mV x R7515

Imon = Io x 45.2 mV/A
22A => 995mV
A SYNC_MASTER=T22_MLB SYNC_DATE=03/26/2009 A
PAGE TITLE
GFX IMVP VCore Regulator

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

75 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CPU VTT (1.05V S0) Regulator
NO STUFF
D7631
PP5V_S0 BAT30CWFILM
102 87 73 70 69 55 53 48 42 23 8 7 6 SOT-323
1
Internal 3 ohm path to V5IN 3

PP5V_S0_CPUVTTS0_V5FILT
1 C7601
MIN_NECK_WIDTH=0.2 mm 2.2UF 2
VOLTAGE=5V 10%
C7600 1 2 16V
30
21
X5R
2.2UF 603 CPUVTTS0_BOOT_RC
10% V5FILT V5IN MIN_LINE_WIDTH=0.3 mm
16V 2 MIN_NECK_WIDTH=0.2 mm
X5R CRITICAL
603
74 IN CPUVTTS0_EN 25 EN (SYM-VER3)
CPUVTTS0_VID<0> 16 VID0 U7600 R76311

CPUVTTS0_VID<1> 15 VID1
QFN
0
1 C7631 PPBUS_G3H 6 7 8 40 50 66 67 68 70 83 87
SN0808088
5% 1UF
CPUVTTS0_VID<2> 14 VID2 1/16W 10%
MF-LF
402 2
16V
2 X5R CRITICAL CRITICAL CRITICAL VID2 VID1 VID0 Vout
9 SLP 402 5 1
C7620 1
C7621 1
C7623 1 C7622
CPUVTTS0_VBST 68UF 62UF 100UF 0.001UF 0 0 0 1.1000V
R7619 TP_CPUVTTS0_PG_L 24 PG*
VBST 18
MIN_LINE_WIDTH=0.3 mm 20% 20% 20% 10%
0 MIN_NECK_WIDTH=0.2 mm CRITICAL 2 16V 2 11V 2 16V 2 50V
5%
1/16W
91 10 OUT CPUVTTS0_PGOOD 23 PGOOD
Q7630 POLY-TANT
CASE-D2E-SM
ELEC
CASE-B2
TANT
D-HF
X7R
402 0 0 1 1.0500V
MF-LF DRVH 17 CPUVTTS0_DRVH 4 RJK0305DPB
CPUVTTS0_IMON
C 402 51 OUT
Imon = Io x R7640 x 2uA/mV x R7610

SIGNAL_MODEL=EMPTY
NO STUFF
SIGNAL_MODEL=EMPTY
8 IMON MIN_LINE_WIDTH=0.6 mm
GATE_NODE=TRUE
DIDT=TRUE
LFPAK-HF 0 1 0 1.0625V +1 step C
Imon = Io x 99.8mV/A R76101 1 C7610 0 1 1 1.1125V
49.9K 0.0033UF
30A => 2.994V 1%
1/16W
MF-LF
10%
50V
2 CERM
1 2 3 1 1 0 1.0750V +2 steps
402 2
<Rimon>
402 LL 19 CPUVTTS0_LL
1 1 1 1.1250V
91 12 IN CPU_VTTSENSE_P 5 VSNS MIN_NECK_WIDTH=0.2 mm NO STUFF
SWITCH_NODE=TRUE
91 12 IN CPU_VTTSENSE_N 4 GSNS DIDT=TRUE 5 1
R7670 1 1 0 0 1.0375V -1 step
1 CRITICAL
R7612 28 OSRSEL
CRITICAL
5%
1/10W L7630 1 0 1 1.0875V
1K Q7636 MF-LF 0.6UH-30A-1.5MOHM
101 99 88 86 85 84 81 74 73
47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 1 2 CPUVTTS0_TONSEL 27 TONSEL 603
72 71 70 69 64 63 59 55 53 52 49 48
1%
DRVL 20 CPUVTTS0_DRVL
4 RJK0328DPB2 MPL104-SM R7640
1/16W CPUVTTS0_TRIPSEL 26 TRIPSEL MIN_NECK_WIDTH=0.2 mm LFPAK-HF DIDT=TRUE
0.001
MF-LF GATE_NODE=TRUE CPUVTT_LL_RC 1%
402 DIDT=TRUE NO STUFF 2 1W PPCPUVTT_S0 6 7 10 12 13 15 25 26 40 74 101
CPUVTTS0_ISLEW 29 ISLEW MF-1
1
R7613 1 C7670 PPCPUVTT_S0_REG_R 2
0612
1 Vout = VID controlled
0 1000PF MIN_LINE_WIDTH=0.6 mm
5% 4 3
5%
1/16W C7615 1 2 3
2 25V
NP0-C0G
VOLTAGE=1.05V 26A max output
MF-LF 0.001UF 10 402
2 402 CPUVTTS0_DROOP_RC 2 1 CPUVTTS0_DROOP 31 DROOP
NC NC f = 350 kHz
NC 11
NC
10%
50V 1OMIT NC 13
NC
1 C7647
R76141 1
R7615 CERM
402
R7616 IMONC 12 PP3V3_S0
99 101
84 85 86
6 7 8 25 26 27 28 30 34 37 40 42 47 48 49
10UF
20%
90.9K 4.02K NOSTUFF 52 53 55 59 63 64 69 70 71 72 73 74 81
88 6.3V
1% 1% NONE 2 X5R
1/16W
MF-LF
1/16W
MF-LF
NONE
NONE
C7643 1 C7644 1 603
402 2 0.1UF
2 402 2 402 10% 10PF
<Rdroop> 16V 2 5%
CPUVTTS0_VREF 32 VREF X5R
402
50V
CERM 2
R7641
CPUVTTS0_CS_P 402 0 CPUVTTS0_CS_R_P
1.7V, 250uA max 6 REF CSP 2 99 1 2 99
MIN_NECK_WIDTH=0.2 mm 5% MIN_NECK_WIDTH=0.09 mm
B R7611
1/16W
MF-LF
402 R7642 B
23.7K2 CPUVTTS0_IMON2 7 IMON2 CPUVTTS0_CS_N 0 CPUVTTS0_CS_R_N
1 CSN 3 99 1 2 99
R76171 1
R7618 1%
1/16W GND PGND THRM_PAD
MIN_NECK_WIDTH=0.2 mm OMIT OMIT 5%
1/16W
10K 10K MF-LF C7619 1 C7641 1 1 C7642 MF-LF
1
22
33
1% 1% 402 0.22UF NOSTUFF NOSTUFF 402

1/16W 1/16W 10% 353S2705 NONE NONE
MF-LF MF-LF 6.3V NONE 2
402 2 2 402 CERM-X5R 2 NONE 2 NONE
NONE
402 402 402
GND_CPUVTTS0_AGND
XW7600
SM
VOLTAGE=0V
2 1
A SYNC_MASTER=T22_MLB SYNC_DATE=03/26/2009 A
PAGE TITLE
CPUVTT (1.05V) Power Supply

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

76 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.8V S0 Regulator FW 10V Boost Regulator

101 99 88 86 85 84 81 74 73
42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0
72 71 70 69 64 63 59 55 53 52 49 48 47
R7790 CRITICAL
CRITICAL 0.02
C7720 1
0.5%
1W L7795
1
2
3
PPBUS_FW_FWBOOST MF 4.7UH-10A
22UF 40 7
0612
VIN
VDD
20% 1 2 PFWBOOST_SW 1 2
6.3V
CERM 2 3 4 MIN_LINE_WIDTH=0.5 mm PCMC063T-SM
CRITICAL MIN_NECK_WIDTH=0.25 mm
D
805
U7720 L7720
2.2UH-3.25A C7790 1 PFWBOOST_BOOST
D
ISL8014 PP1V8_S0 6 7 12 16 73 88 101
10UF MIN_NECK_WIDTH=0.25 mm
QFN 10% SWITCH_NODE=TRUE
P1V8S0_EN 5 EN LX 14 1V8S0_SW 1 2 DIDT=TRUE
74 IN
SWITCH_NODE=TRUE Vout = 1.794V 16V 2
5
CRITICAL LX 15 DIDT=TRUE IHLP1616BZ-SM X5R
CRITICAL 1206 CRITICAL
74 OUT P1V8S0_PGOOD 7 PG R77201 C7723 1 1 C7721 Max Current = 2A VIN
D7790
VFB 8 1V8S0_FB 113K
1% 47PF 22UF Freq = 1 MHz U7790 DO222-SM PP10V_FW 7 8 40
4 SYNCH 1/16W 5% 20% PFWBOOST_ITH 1 ITH/RUN SENSE- 4 PFWBOOST_SENSE 1 2
THRM_PAD
16
NC MF-LF
402 2
50V
CERM 2
6.3V
2 CERM
CRITICAL
Vout = 10V
6 402 805 LTC1872 STPS1L30MF NO STUFF
NC NC <Ra> 1
R7797 1
R7795 Max Current = 2A
12 PGND
10 SGND
SOT23-6
13
NC 38.3K 3 VFB
7 C7795 1 1.00M
1% 33PF 1% Freq = 550KHz
CRITICAL 1/16W 5% 1/4W
D 50V
R77211 PFWBOOST_NGATE 4
11
17
MF-LF NGATE 6 CERM 2 MF-LF
90.9K
C7722 1
2 402 GATE_NODE=TRUE
DIDT=TRUE G 402 2 1206
1% 22UF CRITICAL CRITICAL <Ra> 1
C7799
20% PFWBOOST_ITH_R
1/16W
MF-LF 6.3V
CERM 2 GND
Q7790 S
68UF
402 2 805 FDC796NG 20%
16V
2 POLY-TANT
<Rb> SUPERSOT-6 1
R7796
1
2
3
5
6
2
C7797 1 1
C7794 86.6K
CASE-D2E-SM
0.0012UF 1%
Vout = 0.8V * (1 + Ra / Rb) 10% 1UF 1/16W
50V 2 10%
CERM 2 16V MF-LF
402 X5R 2 402
402 <Rb>
PFWBOOST_FB
1.5V S0 Regulator Vout = 0.8V * (1 + Ra / Rb)
49 36 35 34 33 32 31 20 17 7 6 PP3V3_S3
103 102 88 74 72 56 55 54 51 50
CRITICAL
C 1
1 C7750
22UF
C
U7710
ISL8009B
VIN 20%
6.3V
2 CERM
805
CRITICAL
L7770
1.05V S5 LDO
DFN 2.2UH-3.25A PP1V5_S0 Ibex Peak-M requires JTAG pull-ups to be powered at 1.05V in S5.
7 34 42 59 74 99
2 EN Pull-ups (3) must be 51 ohms to support XDP (not required in production).
PP3V3_S0 LX 8 1V5_S0_SW
101 99 88 86 85 84 81 74 73 72 71 1 2
CRITICAL
42 40 37 34 30 28 27 26 25 8 7 6
70 69 64 63 59 55 53 52 49 48 47 IN
MIN_NECK_WIDTH=0.2 mm IHLP1616BZ-SM
Vout = 1.508V 70mA is required to support pull-ups. Alternative is strong voltage
3 POR VFB 6 SWITCH_NODE=TRUE dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
NC DIDT=TRUE
C7776 1
1
R7780 Max Current = 0.8A
4 SKIP RSI 5 100K CRITICAL
47PF 1% Freq = 1.6MHZ
5% 1/16W XDP_PCH
GND THRM_PAD 50V
CERM 2 MF-LF
CRITICAL
7 9 402 2 402
<Ra> 1 C7771 U7740
1V5_S0_FB 22UF TPS720105
99 86 84 74 73 58 51 50 49 35 31 7 6 PP3V3_S5 SON
20%
6.3V
101
4 BIAS
PP1V05_S5 7 17
1 2 CERM
R7781 805 Vout = 1.05V
113K 6 IN OUT 1
1%
1/16W
MF-LF 3 EN NC 2
Max Current = 0.35A
NC
2 402 XDP_PCH XDP_PCH
<Rb> C7740 1 GND
THRM
PAD 1 C7741
1UF 5 7 2.2UF
Vout = 0.8V * (1 + Ra / Rb) 10%
6.3V 2
10%
2 6.3V
CERM X5R
402 402
1.2V ENET Regulator

B 103 102
36 35 34 33 32 31 20 17 7 6
88 74 72 56 55 54 51 50 49
PP3V3_S3 B
CRITICAL
1
1 C7760
VIN 22UF
20%
U7760 6.3V
2 CERM CRITICAL
ISL8009B 805 L7760
DFN 2.2UH-3.25A PP1V2_ENET 7 37 73
PM_ENET_EN 2 EN CRITICAL LX 8 1V2ENET_SW 1 2

74 8 IN
MIN_NECK_WIDTH=0.2 mm IHLP1616BZ-SM Vout = 1.229V
3 POR VFB 6 SWITCH_NODE=TRUE
NC DIDT=TRUE
C7766 1
1
R7760 Max Current = 0.6A
4 SKIP RSI 5 52.3K
47PF 1% Freq = 1.6MHZ
5% 1/16W
GND THRM_PAD 50V
CERM 2 MF-LF
CRITICAL
7 9 402 2 402
1V2ENET_FB <Ra> 1 C7761
22UF
20%
6.3V
1 2 CERM
R7761 805
100K
1%
1/16W
MF-LF
2 402
<Rb>
Vout = 0.8V * (1 + Ra / Rb)
PAGE TITLE
1.05V to 1.0V FW Drop Misc Power Supplies

DRAWING NUMBER SIZE
Apple Inc. D
40 7 6 PP1V0_FW R7700 PPVIN_FW_FWPHY 7 39 40 R
REVISION
1
0.4752
1%
1/16W THE INFORMATION CONTAINED HEREIN IS THE
MF PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
77 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V S3 FET CRITICAL

3.3V S0 FET CRITICAL
Q7830
Q7810 SI7615DN
PWRPK-1212-8
SIA417DJ
85 86 88 99 101
SC70-6L PP3V3_S0 6 7 8 25 26 27 28 30 34 37 40 42 47 48 49
S
99 86 84 74 73 72 58 51 50 49 35 31 7 6 PP3V3_S5 52 53 55 59 63 64 69 70 71 72 74 81 84
PP3V3_S5
2 3
73 72 58 51 50 49 35 31 7 6 101
D
101 99 86 84 74
D
PP3V3_S3_ISNS_R
1
3.3V S0 FET
5
7 102
1
R7832
1
C7831 1
G
R7812
1
C7811 1
D 0.033UF MOSFET SiA417
G
100K
Q7812 D 6 10K 0.033UF 3.3V S3 FET Q7812 D 3 10%
4
5% 16V
10%
5% 16V 1/16W X5R 2
SSM6N15FEAPE SSM6N15FEAPE CHANNEL P-TYPE 8V/5V
3
1/16W X5R 2 MF-LF 402
SOT563 SOT563
MF-LF 402
MOSFET SiA417
402
2 C7830
402
2 C7810 R7830 0.01UF RDS(ON) 23 mOhm @4.5V
R7810 0.01UF 47K
P3V3S3_EN_L
47K
P3V3S3_SS CHANNEL P-TYPE 8V/5V P3V3S0_EN_L 1 2 P3V3S0_SS 1 2
2 G S 1 1 2 1 2
PM_SLP_S3_L_R
5 G S 4 5%
74 73 50 IN
74 47
31 18 IN PM_SLP_S4_L 5%
10%
RDS(ON) 23 mOhm @4.5V 1/16W 10%
16V
46 43 1/16W MF-LF
MF-LF 16V 402 CERM
402 CERM
402
LOADING 2.096 A (EDP) 402
1.5V S3/S0 FET

68 31 30 28 7 PP1V5_S3
102 73 67 57 23 7 PP5V_S5
C7801
0.1UF
1
1.5V S3/S0 FET 3.3V GPU FET CRITICAL
Q7870
1
20%
10V
CERM 2 VCC
5 MOSFET SI7108DN SIA417DJ
402
SC70-6L
U7801 PP3V3_S5
PP3V3_S0GPU 6 7 75 80 81 82 83 85
4 7
SLG5AP020 CHANNEL N-TYPE 86 84 74 73 72 58 51 50 49 35 31 7 6
CRITICAL 101 99
1
D
31 IN P1V5CPU_EN 2 ON
TDFN
CRITICAL
D 5
R7801 Q7801 RDS(ON) 6 mOhm @4.5V 3.3V GPU FET
3 7
0 4 SI7108DN
NO STUFF SHDN* G 1V5S3RS0FET_GATE1 2 G PWRPK-1212-8-HF LOADING 3.2A (EDP) R7872 1 C7871 1
MOSFET SiA417
C
G
C C7802 1
1UF S 6
5%
1/16W
MF-LF
1V5S3RS0FET_GATE_R
S
51K
5%
1UF
10%
10V CHANNEL P-TYPE 8V/5V
3
1/16W X5R 2
10% 402 MF-LF
10V
2 PG 8 1 2 3 376S0651 402
RDS(ON) 23 mOhm @4.5V
X5R 402
2 C7870
402 THRM R7870 0.01UF
GND PAD
P3V3GPU_EN_L 1
1K
2 P3V3GPU_SS 1 2
LOADING 1.1 A (EDP)
4
PP1V5_S3RS0 7 57
Q7872 5%
1/16W 10%
16V
SSM3K15FV D 3 MF-LF
Green FET drives gate to D+4.7V. SOD-VESM-HF
402 CERM
402
TP_P1V5S3RS0_PGOOD
OUT 74
88 74 IN EG_RAIL2_EN
1 G S 2
1.2V S0 FET
72 37 7 PP1V2_ENET
102 73 67 57 23 7 PP5V_S5 1.2V S0 FET
1 MOSFET SI2306BDS-GE3
C7850 CRITICAL
0.1UF CHANNEL N-TYPE 5.0V S0 FET Q7860
1
20%
10V
CERM 2 VCC
CRITICAL RDS(ON) 65 mOhm @4.5V SI7615DN
PWRPK-1212-8
402
3
U7850 LOADING 0.124 A (EDP)
PP5V_S0_ISNS_R 7 102
SLG5AP020
S
D
3
TDFN PP5V_S3
D
74 P1V2GMUX_EN 2 ON D 5 R7850 103 83 68 55 51 47 45 44 43 33 31 7 6
IN
CRITICAL Q7850 5.0V S0 FET
5
0 G
3 SHDN* G 7 1 2 1 SI2306BDS-GE3
1
1V2S0FET_GATE
1V2S0FET_GATE_R SOT23 R7862 1
B S
B
G
S 6
5%
1/16W 47K
C7861 1
MOSFET SI7615DN
MF-LF 0.033UF
4
5%
10%
8
402
2
1/16W
16V
CHANNEL P-TYPE 20V/12V
PG MF-LF 2
THRM
376S0748 402
2
X5R
402 C7860
GND PAD R7860 0.01UF
RDS(ON) 5.5 MOHM @4.5V
47K
4
PP1V2_S0 6 7 88 P5V0S0_EN_L 1 2 P5V0S0_SS 1 2

5%
Green FET drives gate to D+4.7V. 1/16W
MF-LF
10%
16V
CERM
Q7865 402
402
TP_P1V2S0_PGOOD OUT 74 SSM3K15FV D 3

SOD-VESM-HF
1 G S 2
74 73 50 IN PM_SLP_S3_L_R
1.8V GPU_IFPX FET
101 88 72 16 12 7 6 PP1V8_S0
87 71 70 69 55 53 48 42 23 8 7 6 PP5V_S0
102
C7880 1
0.1UF 1.8V GPU_IFPX FET
1
20%
10V
CERM 2 VCC
402 376S0683 MOSFET SI2312BDS
U7880 3
CHANNEL N-TYPE
SLG5AP020 D CRITICAL
EG_RAIL4_EN 2 TDFN
88 87 74 IN ON D 5 Q7880 RDS(ON) 31 mOhm @4.5V
A 3 SHDN*
CRITICAL
G 7 1V8GPUIFPXFET_GATE 1 G SI2312BDS
SOT23
LOADING 0.3 A (EDP) SYNC_MASTER=K17_WFERRY SYNC_DATE=06/09/2009 A
S PAGE TITLE
6
S
8
2 Power FETs
PG PP1V8_GPUIFPX 6 7 82 DRAWING NUMBER SIZE
GND
THRM
PAD Apple Inc. D
4
REVISION
Green FET drives gate to D+4.7V. R

TP_GPUIFPX_PGOOD
OUT 74 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
78 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
State SMC_PM_G2_ENABLE PM_SLP_S4_L PM_SLP_S3_L
3.3V,5V S3 ENABLE
Run (S0) 1 1 1
(PM_S4_STATE_L)
Sleep (S3) 1 1 0 74 73 47 46 43 31 18 IN PM_SLP_S4_L PM_SLP_S4_L OUT 18 31 43 46 47 73 74
MAKE_BASE=TRUE
Soft-Off (S5) 1 0 0 2
R7911 R7912
Battery Off (G3Hot) 0 0 0 5.1K 0
5% 5%
3.3V S5 ENABLE 1/16W 1/16W
1 MF-LF MF-LF
R7902 402 402
100 S5 rail PWRGD PLACE_NEAR=R7251.2:3mm
46 IN SMC_PM_G2_EN 2 1 P3V3S5_EN OUT 67
D
5%
1/16W
MF-LF
NO STUFF 74 67 P5VS3_EN
MAKE_BASE=TRUE
P5VS3_EN OUT 67 74 D
R79581 402 1 C7902 49 48 47 46 45 43 23 21 17 7 6
74 66 65 54 51 50
PP3V42_G3H
74 68 DDRREG_EN DDRREG_EN
0.068UF OUT
100K 10%
MAKE_BASE=TRUE
5% 10V NO STUFF
1/16W 2
MF-LF
402
CERM
402
1
R7940 Unused PGOOD signal PLACE_NEAR=U7300.11:3mm 1 C7910 1 C7912
PLACE_NEAR=U4900.L13:3mm 2 PLACE_NEAR=R7252.2:2mm 100K 0.47UF 0.47UF
5%
1/16W 74 73 TP_P1V2S0_PGOOD TP_P1V2S0_PGOOD IN 73 74 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
MF-LF MAKE_BASE=TRUE 402 402
402
R7941
2 74 73 TP_GPUIFPX_PGOOD TP_GPUIFPX_PGOOD IN 73 74
MAKE_BASE=TRUE
R7901 0
67 IN P3V3S5_PGOOD 1 2 RSMRST_PWRGD 46 74 73 TP_P1V5S3RS0_PGOOD TP_P1V5S3RS0_PGOOD IN 73 74
2
100 1
MAKE_BASE=TRUE
P5VS5_EN OUT 67 5%
1/16W 74 70 TP_GFXIMVP_PGOOD TP_GFXIMVP_PGOOD IN 70 74
5% MF-LF MAKE_BASE=TRUE
1/16W NO STUFF 402
MF-LF OMIT 74 68 TP_DDRREG_PGOOD TP_DDRREG_PGOOD 68 74
402 1 C7901 C7941 1
MAKE_BASE=TRUE
IN
0.068UF
10% NOSTUFF
2
10V
CERM
NONE
NONE
Other S0 RAILS
402 NONE 2
402 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0
74 73 72 71 70 69 64 63 59 55 53 52 49
1
S0 ENABLE R7992
(PM_SLP_S3_L) 10K
R7978 5%
1/16W
PM_SLP_S3_L 100 74 73 50 PM_SLP_S3_L_R MF-LF
86 74 46 31 18 6 IN
1 2 402 2
MAKE_BASE=TRUE
5% PM_SLP_S3_L_R OUT 50 73 74
1/16W
MF-LF
PM_SLP_S4_L 402 2 PM_SLP_S3_L_R
R7979 1 2 R7981 R7985 2 OUT 50 73 74
IN 18 31 43 46 47 73 74
R7986
100K 33K 10K 5.1K PM_SLP_S3_L_R OUT 50 73 74
5% 5% 5%
1/16W 1/16W 1/16W 5%
1
C MF-LF
402 2
MF-LF
402
1 MF-LF
402
1
1/16W
MF-LF
402 PLACE_NEAR=U7720.5:6mm
IG
EG
PM_ALL_GFX_PGOOD
HIGH
PM_ALL_GPU_PGOOD
C
VFRQ_SLPS4 VFRQ_SLPS3 PLACEMENT_NOTE=Near U1800
74 72 P1V8S0_EN P1V8S0_EN OUT 72 74
2
R7933 R7932 MAKE_BASE=TRUE

74 73 P1V2GMUX_EN P1V2GMUX_EN 73 74
0 0 74 MAKE_BASE=TRUE OUT
5% 5% 50214917487 47
6 PP3V42_G3H
1/16W 1/16W
46 45 43 23 74 71 CPUVTTS0_EN CPUVTTS0_EN OUT 71 74
MF-LF MF-LF
66 65 54 51
MAKE_BASE=TRUE
1
402 402
R7995
100 PP3V3_S5
2
R7931 74 S0PGOOD_PWROK 1 2
6 7 31 35 49 50 51 58 72 73
84 86 99 101
10K CHGR VFRQ Generation PLACE_NEAR=U7720.5:6mm

5%
5% PLACE_NEAR=U7600.25:6mm PLACE_NEAR=U7850.1:6mm 1/16W
1/16W MF-LF
MF-LF R7996 402
1
402 1 C7981 1 C7985 1 C7986 72 P1V8S0_PGOOD 1

100
2 R7994 1
1 C7989
CHGR_VFRQ 0.47UF 0.47UF 0.47UF IN 0 0.1UF
OUT 66
10% 10% 10% 5% 20%
6.3V 6.3V 6.3V 5% 10V
Q7931 NO STUFF
2 CERM-X5R
402
2 CERM-X5R
402
2 CERM-X5R
402
1/16W
MF-LF
1/16W
MF-LF
2 CERM
402
SSM3K15FV D 3 101 99 88 86 85 84 81
PP3V3_S0
402
R7997 402
2
2
SOD-VESM-HF R7935 48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49 100
P5VS3_PGOOD 1 2 S0_PWR_PGOOD
0 67 IN
5% 5%
1/16W 1/16W
MF-LF MF-LF
1
402 402 5 TC7SZ08AFEAPE
2
1 G S 2 27MHZ OE EN Generation R7999 NO STUFF 2
A
SOT665
VFRQ Low: Fix Frequency 10K R7991 4 ALL_SYS_PWRGD
5% 100 1
U7980Y OUT 25 27 46 88
VFRQ High: Variable Frequency 1/16W

MF-LF
88 87 83 74 8 PM_ALL_GPU_PGOOD 1 2 ALL_GFX_PGOOD_R B
1
402 5%
VFRQ_EN_GATE 1/16W 3
CK505_27MHZ_EN_L OUT 26 MF-LF
402
ENET Enable Generation 3.3V ENET FET EXT GPU PWRGD Pullup
Q7995
SSM3K15FV
SOD-VESM-HF
D 3
"ENET" = "S0" || ("S3" && "AC" && "WOL_EN") CRITICAL

Q7922
B NOTE: S3 term is guaranteed by source of R7920 & Q7920, MUST BE S3 RAIL. NTR4101P
SOT-23-HF
101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
74 73 72 71 70 69 64 63 59 55 53 52 49
PP3V3_S0
B
49 36 35 34 33 32 31 20 17 7 6 PP3V3_S3 PP3V3_ENET 7 27 37
R7990 1 1 G S 2
103 102 88 72 56 55 54 51 50
2 S D 3 100K
5% 3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT
1/16W
MF-LF
402 2
R7920 1
R7921 1 1 C7921 G
10K 10K 0.033UF 88 87 83 74 8 IN PM_ALL_GPU_PGOOD 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6
PP3V3_S0
5% 5% 10% 1 74 73 72 71 70 69 64 63 59 55 53 52 49
1/16W 1/16W 16V
2 X5R PM_ALL_GPU_PGOOD
88 87 83 74 8 IN RAIL_MON C7971 1 PLACE_NEAR=U7971.7:2mm
MF-LF MF-LF C7922
7
402 PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD
402 2 402 2 R7922 0.01UF
88 87 83 74 8 IN
MAKE_BASE=TRUE
OUT 8 74 83 87 88
VDD VDDA 0.1uF
100K 2 20%
72 8 PM_ENET_EN 1 P3V3ENET_SS 2 1 10V
2
OUT
5% 10%
U7971 CERM
402
1/16W ISL88042IRTJJZ
3 MF-LF 16V TDFN
CERM
C7920 1 D Q7921 402 402 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 3 V2MON MR* 1
NC
0.22UF 2N7002DW-X-G 74 73 72 71 70 69 64 63 59 55 53 52 49
10%
10V
CERM 2
402
S G 5
SOT-363
PM_ENET_EN_L WLAN Enable Generation GPU Rail Sequencing
99 72 59 42 34 7
101 71 40 26 25 15 13 12 10 7 6
PP1V5_S0
PPCPUVTT_S0
5 V3MON CRITICAL
6 V4MON
GND
RST*
THRM_PAD
8 S0PGOOD_PWROK 74
4 6 "WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
9
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal. V2MON THRESHOLD IS 2.866V
GT216 GPU requires rails to come V3MON THRESHOLD IS 0.6V
D Q7921 up in the following order:
V4MON THRESHOLD IS 0.6V
2N7002DW-X-G
SOT-363 1) 1.1V
86 74 46 31 18 6 IN PM_SLP_S3_L 2 G S PM_WLAN_EN_L OUT 33
2) GPU_3.3V
3 1 6 3) GPUVcore
Q7920 D D Q7925 4) GDDR3 1.8V
2N7002DW-X-G 2N7002DW-X-G
SOT-363 SOT-363
20 WOL_EN 5 G S S G 2 AP_PWR_EN 20 33 88 87 74
EG_RAIL1_EN EG_RAIL1_EN 74 87 88
IN IN
A 4 1
88 74 73
MAKE_BASE=TRUE
EG_RAIL2_EN EG_RAIL2_EN 73 74 88
MAKE_BASE=TRUE PAGE TITLE
AC_EN_L (AC_EN_L)
88 83 74
EG_RAIL3_EN EG_RAIL3_EN
74 83 88
Power Control
6 3 MAKE_BASE=TRUE DRAWING NUMBER SIZE
Q7925 EG_RAIL4_EN EG_RAIL4_EN Apple Inc. D
D
Q7920 2N7002DW-X-G
D 88 87 74 73
MAKE_BASE=TRUE
73 74 87 88
REVISION
2N7002DW-X-G SOT-363 R
SOT-363
47 46 18 IN SMC_ADAPTER_EN 2 G S (PM_SLP_S3_L) 5 G S
1 4 THE INFORMATION CONTAINED HEREIN IS THE
79 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
Page Notes U8000
NV-GT216
BGA 0.1uF
- =PP1V2_GPU_PEX_PLLXVDD (1 OF 9) C8055 1 2 PEG_D2R_P<0> OUT 8 9 91
PEG_R2D_C_P<0> C8020 0.1uF 1 2 PEG_R2D_P<0> AP17 AL17 PEG_D2R_C_P<0> 10% 16V X5R 402
- =PP1V2_GPU_PEX_IOVDDQ 91 8 IN 91 PEX_RX0 PEX_TX0 91
10% 16V X5R 40291 PEG_R2D_N<0> PEG_D2R_C_N<0> C8056 0.1uF 1 2 PEG_D2R_N<0>
- =PP1V2_GPU_PEX_IOVDD AN17 PEX_RX0* PEX_TX0* AM17 91
OUT 8 9 91
PEG_R2D_C_N<0> C8021 0.1uF 1 2 10% 16V X5R 402

91 8 IN
10% 16V X5R 402 0.1uF
(NONE)
C8057 1 2 PEG_D2R_P<1> OUT 8 9 91
PEG_R2D_C_P<1> C8022 0.1uF 1 2 PEG_R2D_P<1> PEG_D2R_C_P<1> 10% 16V X5R 402

91 8 IN 91 AN19 PEX_RX1 PEX_TX1 AM18 91
BOM options provided by this page:
AP19 PEX_RX1* PEX_TX1* AM19 91
OUT 8 9 91
(NONE)
PEG_R2D_C_N<1> C8023 0.1uF 1 2 10% 16V X5R 402
91 8
D
IN
10% 16V X5R 402
C8059 0.1uF 1 2 PEG_D2R_P<2> OUT 8 9 91
D
PP1V05_S0GPU PEG_R2D_C_P<2> C8024 0.1uF 1 2 PEG_R2D_P<2> PEG_D2R_C_P<2> 10% 16V X5R 402
82 80 77 75 51 7 6 91 8 IN 91 AR19 PEX_RX2 PEX_TX2 AL19 91
PP1V05_S0GPU 10% 16V X5R 40291 PEG_R2D_N<2> PEG_D2R_C_N<2> C8060 0.1uF 1 2 PEG_D2R_N<2>
82 80 77 75 51 7 6 AR20 PEX_RX2* PEX_TX2* AK19 91
OUT 8 9 91
PP1V05_S0GPU PEG_R2D_C_N<2> C8025 0.1uF 1 2 10% 16V X5R 402

82 80 77 75 51 7 6 91 8 IN
10% 16V X5R 402 0.1uF
C8061 1 2 PEG_D2R_P<3> OUT 8 9 91

91 8 IN 91 AP20 PEX_RX3 PEX_TX3 AL20 91
AN20 PEX_RX3* PEX_TX3* AM20 91
OUT 8 9 91
PEG_R2D_C_N<3> C8027 0.1uF 1 2 10% 16V X5R 402

91 8 IN
10% 16V X5R 402 0.1uF
C8063 1 2 PEG_D2R_P<4> OUT 8 9 91

91 8 IN 91 AN22 PEX_RX4 PEX_TX4 AM21 91

AP22 PEX_RX4* PEX_TX4* AM22 91
OUT 8 9 91
PEG_R2D_C_N<4> C8029 0.1uF 1 2 10% 16V X5R 402

91 8 IN
10% 16V X5R 402 0.1uF
C8065 1 2 PEG_D2R_P<5> OUT 8 9 91

PEX 1.05V Current = 2A 91 8 IN 91 AR22 PEX_RX5 PEX_TX5 AL22 91
10% 16V X5R 40291 PEG_R2D_N<5> AR23 AK22 PEG_D2R_C_N<5> C8066 0.1uF 1 2 PEG_D2R_N<5>
PEX_RX5* PEX_TX5* 91
OUT 8 9 91
PEG_R2D_C_N<5> C8031 0.1uF 1 2 10% 16V X5R 402

250mA 91 8 IN
10% 16V X5R 402 0.1uF
C8067 1 2 PEG_D2R_P<6> OUT 8 9 91

91 AP23 PEX_RX6 PEX_TX6 AL23 91
1 C8002 1 C8001 1 C8000 91 8 IN
10% 16V X5R 40291 PEG_R2D_N<6> AN23 PEX_RX6* PEX_TX6* AM23 91 PEG_D2R_C_N<6> C8068 0.1uF 1 2 PEG_D2R_N<6>
1UF 4.7UF 22UF 0.1uF OUT 8 9 91
10% 20% 20% 91 8 PEG_R2D_C_N<6> C8033 1 2 10% 16V X5R 402
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM-X5R
IN
10% 16V X5R 402
NC_GPU_DFM 402 603 805 C8069 0.1uF 1 2 PEG_D2R_P<7> OUT 8 9 91
NO_TEST=TRUE
OMIT 91 8 IN 91 AN25 PEX_RX7 PEX_TX7 AM24 91
10% 16V X5R 40291 PEG_R2D_N<7> AP25 AM25 PEG_D2R_C_N<7> C8070 0.1uF 1 2 PEG_D2R_N<7>
PEX_RX7* PEX_TX7* 91
OUT 8 9 91
PEG_R2D_C_N<7> C8035 0.1uF 1 2 10% 16V X5R 402

C U8000
NV-GT216
1 C8003
1UF
1 C8004
0.1UF
1 C8005
0.1UF
91 8 IN
10% 16V X5R 402
C8071 0.1uF 1 2 PEG_D2R_P<8> 8 9 91
C
BGA 10% 20% 20% OUT
C8036 0.1uF
(2 OF 9) 2 6.3V
CERM 2 10V
CERM
10V
2 CERM 91 8 IN PEG_R2D_C_P<8> 1 2 91 PEG_R2D_P<8> AR25 PEX_RX8 PEX_TX8 AL25 91 PEG_D2R_C_P<8> 10% 16V X5R 402
H32 402 402 402 10% 16V X5R 40291 PEG_R2D_N<8> PEG_D2R_C_N<8> C8072 0.1uF 1 2 PEG_D2R_N<8>
PEX_IOVDD1 AK16 AR26 PEX_RX8* PEX_TX8* AK25 91
OUT 8 9 91
PEG_R2D_C_N<8> C8037 0.1uF 1 2 10% 16V X5R 402

M7 PEX_IOVDD2 AK17 91 8 IN
10% 16V X5R 402 0.1uF
P6 PEX_IOVDD3 AK21 C8073 1 2 PEG_D2R_P<9> OUT 8 9 91
A5 PEX_IOVDD4 AK24
PEG_R2D_C_P<9> C8038 0.1uF 1 2 PEG_R2D_P<9> AP26 AL26 PEG_D2R_C_P<9> 10% 16V X5R 402
91 8 IN 91 PEX_RX9 PEX_TX9 91
U7 PEX_IOVDD5 AK27 10% 16V X5R 40291 PEG_R2D_N<9> PEG_D2R_C_N<9> C8074 0.1uF 1 2 PEG_D2R_N<9>
1500mA AN26 PEX_RX9* PEX_TX9* AM26 91
OUT 8 9 91
V6
PEG_R2D_C_N<9> C8039 0.1uF 1 2 10% 16V X5R 402
91 8 IN
AB7 10% 16V X5R 402
C8075 0.1uF
AD6 1 C8008 1 C8007 1 C8006 1 C8018 0.1uF
1 2 PEG_D2R_P<10> OUT 8 9 91
AF6 PEX_IOVDDQ1 AG11 1UF

10%
4.7UF
20%
22UF
20%
10UF
20% 91 8 IN PEG_R2D_C_P<10> C8040 1 2 91 PEG_R2D_P<10> AN28 PEX_RX10 PEX_TX10 AM27 91 PEG_D2R_C_P<10> 10% 16V X5R 402
C8076 0.1uF
AG6 PEX_IOVDDQ2 AG12 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM-X5R
6.3V
2 X5R 10% 16V X5R 40291 PEG_R2D_N<10> AP28 PEX_RX10* PEX_TX10* AM28 91 PEG_D2R_C_N<10> 1 2 PEG_D2R_N<10> OUT 8 9 91
402 603 805 603 PEG_R2D_C_N<10> C8041 0.1uF 1 2 10% 16V X5R 402
AJ5 PEX_IOVDDQ3 AG13 91 8 IN
10% 16V X5R 402 0.1uF
AK15 PEX_IOVDDQ4 AG15 C8077 1 2 PEG_D2R_P<11> OUT 8 9 91
AL7 PEX_IOVDDQ5 AG16
PEG_R2D_C_P<11> C8042 0.1uF 1 2 PEG_R2D_P<11> AR28 PEG_D2R_C_P<11> 10% 16V X5R 402
91 8 IN 91 PEX_RX11 PEX_TX11 AL28 91
E7 PEX_IOVDDQ6 AG17 C8078 0.1uF
1 C8009 1 C8010 1 C8011 0.1uF
10% 16V X5R 40291 PEG_R2D_N<11> AR29 PEX_RX11* PEX_TX11* AK28 91 PEG_D2R_C_N<11> 1 2 PEG_D2R_N<11> OUT 8 9 91
A2 PEX_IOVDDQ7 AG18 1UF
10%
0.1UF
20%
0.1UF
20% 91 8 IN PEG_R2D_C_N<11> C8043 1 2 10% 16V X5R 402
A7 PEX_IOVDDQ8 AG22
2 6.3V
CERM 2 10V
CERM
10V
2 CERM 10% 16V X5R 402
C8079 0.1uF 1 2
B7 PEX_IOVDDQ9 AG23 402 402 402 PEG_D2R_P<12> OUT 8 9 91
C5 PEG_R2D_C_P<12> C8044 0.1uF 1 2 PEG_R2D_P<12> PEG_D2R_C_P<12> 10% 16V X5R 402

NC PEX_IOVDDQ10 AG24 91 8 IN 91 AP29 PEX_RX12 PEX_TX12 AK29 91
C7 AG25 10% 16V X5R 40291 PEG_R2D_N<12> AN29 AL29 PEG_D2R_C_N<12> C8080 0.1uF 1 2 PEG_D2R_N<12>
PEX_IOVDDQ11 PEX_RX12* PEX_TX12* 91
OUT 8 9 91
D5 PEG_R2D_C_N<12> C8045 0.1uF 1 2 10% 16V X5R 402

PEX_IOVDDQ12 AG26 91 8 IN
D6 PEX_IOVDDQ13 AJ14 L8015 10% 16V X5R 402
C8081 0.1uF 1 2 PEG_D2R_P<13>
120 mA: GT216 A01 DG v3 01/09 100NH-700MA-0.14OHM 0.1uF OUT 8 9 91
D7 PEX_IOVDDQ14 AJ15
91 8 IN PEG_R2D_C_P<13> C8046 1 2 91 PEG_R2D_P<13> AN31 PEX_RX13 PEX_TX13 AM29 91 PEG_D2R_C_P<13> 10% 16V X5R 402
E5 PEX_IOVDDQ15 AJ19 PP1V05_GPU_PEX_PLLVDD_F 1 2
10% 16V X5R 40291 C8082 0.1uF 1 2
MIN_LINE_WIDTH=0.25 mm PEG_R2D_N<13> AP31 PEX_RX13* PEX_TX13* AM30 91 PEG_D2R_C_N<13> PEG_D2R_N<13> 8 9 91
B F4
G5
PEX_IOVDDQ16
PEX_IOVDDQ17
AJ21
AJ22
VOLTAGE=1.05V 1 C8017 1
0603
C8016 C8015 1 91 8 IN PEG_R2D_C_N<13> C8047 0.1uF 1 2

10% 16V X5R 402
10% 16V X5R 402
OUT
B
J18 1UF 4.7UF 4.7UF C8083 0.1uF 1 2 PEG_D2R_P<14>
PEX_IOVDDQ18 AJ24 10% 20% 20% OUT 8 9 91
6.3V C8048 0.1uF
J19 PEX_IOVDDQ19 AJ25 2 CERM 2 6.3V
CERM
6.3V 2
CERM 91 8 IN PEG_R2D_C_P<14> 1 2 91 PEG_R2D_P<14> AR31 PEX_RX14 PEX_TX14 AM31 91 PEG_D2R_C_P<14> 10% 16V X5R 402
J25 402 603 603 10% 16V X5R 40291 PEG_R2D_N<14> PEG_D2R_C_N<14> C8084 0.1uF 1 2 PEG_D2R_N<14>
PEX_IOVDDQ20 AJ27 AR32 PEX_RX14* PEX_TX14* AM32 91
OUT 8 9 91
PEG_R2D_C_N<14> C8049 0.1uF 1 2 10% 16V X5R 402

J26 PEX_IOVDDQ21 AK18 91 8 IN
10% 16V X5R 402 0.1uF
AA4 PEX_IOVDDQ22 AK20 C8085 1 2 PEG_D2R_P<15> OUT 8 9 91
AB4 PEX_IOVDDQ23 AK23
PEG_R2D_C_P<15> C8050 0.1uF 1 2 PEG_R2D_P<15> AR34 AN32 PEG_D2R_C_P<15> 10% 16V X5R 402
91 8 IN 91 PEX_RX15 PEX_TX15 91
AC5 PEX_IOVDDQ24 AK26 10% 16V X5R 40291 PEG_R2D_N<15> PEG_D2R_C_N<15> C8086 0.1uF 1 2 PEG_D2R_N<15>
AP34 PEX_RX15* PEX_TX15* AP32 91
OUT 8 9 91
Y4 PEX_IOVDDQ25 AL16
PEG_R2D_C_N<15> C8051 0.1uF 1 2 10% 16V X5R 402
91 8 IN
AG20 10% 16V X5R 402
NO STUFF
R8060
D35 200
VDD_SENSE PEX_PLLVDD 94 17 IN PEG_CLK100M_P AR16 PEX_REFCLK PEX_TSTCLK_OUT AJ17 PEX_TSTCLK_P 1 2
P7 AG14
94 17 IN PEG_CLK100M_N AR17 PEX_REFCLK* PEX_TSTCLK_OUT* AJ18 PEX_TSTCLK_N 1%
1/16W
E35 R8050 MF-LF
GND_SENSE VDD_SENSE AD20 GPU_VDD_SENSE 83 R8020 0 2.49K2 402
R7 88 8 IN EG_RESET_L 1 2 GPU_RESET_R_L AM16 PEX_RST* PEX_TERMP AG21 PEX_TERMP_PD 1
GND_SENSE AD19 GPU_GND_SENSE 83 5% 1%
A4 BUFRST* 1/16W 1/16W
MF-LF AR13 PEX_CLKREQ* MF-LF
402 AG19 402
88 8 PEX_CLKREQ_L PEX_SVDD_3V3 F7
BI
1 C8013 1 C8012
4.7UF 0.1UF
10% 10%
NC_GPU_BUFRST_L PP3V3_S0GPU 6.3V 2 16V
OUT 6
85 83 82 81 80 73 7 6
R8021 2 X5R-CERM
603
X5R
402
1
10K 2
5%
A 1/16W
MF-LF
402
NO STUFF SYNC_MASTER=K18_MLB SYNC_DATE=06/29/2009 A
0 2 PAGE TITLE
PP1V05_S0GPU R8012 PP3V3R1V05_GPU_PEX_SVDD
82 80 77 75 51 7 6 1
5% MIN_LINE_WIDTH=0.30MM NV GT216 PCI-E
1/16W MIN_NECK_WIDTH=0.20MM DRAWING NUMBER SIZE
MF-LF VOLTAGE=3.3V
402
Apple Inc. D
R8013 1
0 2
REVISION
R
5%
1/16W
MF-LF
402 THE INFORMATION CONTAINED HEREIN IS THE
80 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page: U8000
- =PPVCORE_GPU U8000 NV-GT216
BGA
- =PP1V8_GPU_FBVDDQ
NV-GT216 (8 OF 9)
BGA
(9 OF 9) B3 V18
Signal aliases required by this page: 83
7 6 PPVCORE_GPU L11 V19 B6 V20
(NONE) 50
L12
OMIT V21 B9 OMIT V22
???A @ ???/???MHz Core/Mem Clk for VDD
BOM options provided by this page: L13 V23 B12 V24
(NONE) L14 V25 B15 V31
1 C8100 1 C8101 1 C8102 L15 W11 B21 Y11
1UF 0.22UF 0.22UF L16 W12 B24 Y13
D
10%
10V
2 X5R
402
10%
6.3V
2 CERM-X5R
402
10%
6.3V
2 CERM-X5R
402
L17 W13 B27 Y15 D
L18 W14 B30 Y17
L19 W15 B33 Y19
L20 W16 C2 Y21
L21 W17 C34 Y23
L22 W18 E6 Y25
L23 W19 E9 AA2
L24 AD24 E12 AA5
1 C8103 1 C8104 1 C8105 1 C8106 1 C8107 L25 W21 E15 AA11
0.1UF 0.047UF 0.047UF 0.047UF 0.022UF
10% 10% 10% 10% 10% M12 W22 E18 AA12
16V 16V 16V 16V 16V
2 X7R-CERM 2 X7R 2 X7R 2 X7R 2 CERM-X5R
402 402 402 402 402 M14 W23 E24 AA13
M16 W24 E27 AA14
M18 W25 E30 AA15
M20 Y12 F2 AA16
1 C8108 1 C8109 1 C8110 1 C8111 1 C8112 M22 Y14 F5 AA17
0.022UF 0.022UF 0.015UF 0.015UF 0.01UF M24 Y16 F31 AA18
10% 10% 10% 10% 10%
16V 16V 16V 16V 25V P11 Y18 F34 AA19
2 CERM-X5R 2 CERM-X5R 2 X7R 2 X7R 2 X7R
402 402 402 402 402 P13 Y20 J2 AA20
P15 Y22 J5 AA21
P17 Y24 J31 AA22
P19 VDD VDD AB11 J34 AA23
1 C8113 1 C8114 1 C8115 1 C8116 1 C8117 P21 AB13 L9 AA24
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
10% 10% 10% 10% 10% P23 AB15 M2 AA25
25V 25V 25V 25V 25V
2 X7R 2 X7R 2 X7R 2 X7R 2 X7R
402 402 402 402 402 P25 AB17 M5 AA34
R11 AB19 M11 AB12
R12 AB21 M13 AB14
C 1 C8118 1 C8119
R13
R14
AB23
AB25
M15
M17
AB16
AB18
C
0.0068UF 0.0047UF R15 AC11 M19 AB20
10% 10%
2 25V
CERM
25V
2 CERM R16 AC12 M21 AB22
402 402 R17 AC13 M23 AB24
R18 AC14 M25 AC9
R19 AC15 M31 AD2
R20 AC16 M34 AD5
R21 AC17 N11 AD11
R22 AC18 N12 AD13
R23 AC19 N13 AD15
R24 AC20 N14 AD17
R25 AC21 N15 AD21
T12 AC22 N16 AD23
T14 AC23 N17 GND GND AD25
T16 AC24 N18 AD31
79 78 77 51 8 7 6 PP1V8_S0GPU_ISNS T18 AC25 N19 AD34
T20 AD12 N20 AE11
T22 AD14 N21 AE12
T24 AD16 N22 AE13
V11 AD18 N23 AE14
Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF
V13 AD22 N24 AE15
V15 W20 N25 AE16
???A @ ???MHz 1.8V GDDR3
V17 P12 AE17
P14 AE18
P16 AE19
C8150 1 P18 AE20
4.7UF
B 20%
6.3V 2
CERM
P20 AE21 B
603 P22 AE22
OMIT P24 AE23
R2 AE24
R5 AE25
C8156 1 C8157 1 C8158 1 C8159 1 C8160 1 U8000 R31 AG2
4.7UF 0.1UF 0.1UF 0.1UF 0.047UF R34 AG5
20% 20% 20% 20% 10% NV-GT216
6.3V 10V 10V 10V 16V BGA T11 AG31
CERM 2 CERM 2 CERM 2 CERM 2 X7R 2
(7 OF 9)
603 402 402 402 402 T13 AG34
B18 J20
T15 AK2
J17 J21
T17 AK5
U27 J22
T19 AP33
C8162 1 C8163 1 C8164 1 C8165 1 C8166 1 AB27 J23
T21 AK31
0.047UF 0.047UF 0.01UF 0.01UF 0.01UF AB29 J24
10% 10% 10% 10% 10% T23 AK34
16V 16V 25V 25V 25V AC27 J29
X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 T25 AL6
402 402 402 402 402 AD27 N27
U11 AL9
AE27 P27
U12 AL12
AJ28 R27
FBVDDQ FBVDDQ U13 AL15
E21 T27
U14 AL18
G8 U29
U15 AL21
G9 V27
U16 AL24
G17 V29
U17 AL27
G18 V34
U18 AL30
G22 W27
U19 AN2
H29 Y27
U20 AN34
J14 AA27
U21 AP3
A J15
J16
AA29
AA31
U22 AP6 SYNC_MASTER=GT216 SYNC_DATE=03/26/2009 A
U23 AP9 PAGE TITLE
U24 AP12 NV GT216 CORE/FB POWER

U25 AP15 DRAWING NUMBER SIZE
V2 AP18
Apple Inc. D
V5 AP21 REVISION
R
V9 AP24
V12 AP27 NOTICE OF PROPRIETARY PROPERTY: BRANCH
V14 AP30 THE INFORMATION CONTAINED HEREIN IS THE
V16 K9 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
AK14 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
81 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP1V2_GPU_FBPLLAVDD
- =PP1V8_GPU_FBIO
OMIT
U8000
(NONE) NV-GT216
BGA
BOM options provided by this page: (4 OF 9)
(NONE) 98 79 BI FB_B_DQ<0> B13 FBC_D00 FBC_CMD0 C17 FB_B_LMA<4> OUT 79 98
98 79 BI FB_B_DQ<1> D13 FBC_D01 FBC_CMD1 B19 FB_B_RAS_L OUT 79 98
OMIT 98 79 FB_B_DQ<2> A13 FBC_D02 FBC_CMD2 D18 FB_B_LMA<5> 79 98
D U8000
98 79
BI
BI FB_B_DQ<3> A14 FBC_D03 FBC_CMD3 F21 FB_B_BA<1>
OUT
OUT 79 98 D
98 79 BI FB_B_DQ<4> C16 FBC_D04 FBC_CMD4 A23 FB_B_UMA<2> OUT 79 98
NV-GT216 98 79 FB_B_DQ<5> B16 FBC_D05 FBC_CMD5 D21 FB_B_UMA<4> 79 98
BGA BI OUT
(3 OF 9) 98 79 BI FB_B_DQ<6> A17 FBC_D06 FBC_CMD6 B23 FB_B_UMA<3> OUT 79 98
98 78 BI FB_A_DQ<0> L32 FBA_D00 FBA_CMD0 V32 FB_A_LMA<4> OUT 78 98 98 79 BI FB_B_DQ<7> D16 FBC_D07 FBC_CMD7 E20 FB_B_UCKE OUT 79 98
98 78 BI FB_A_DQ<1> N33 FBA_D01 FBA_CMD1 W31 FB_A_RAS_L OUT 78 98 98 79 BI FB_B_DQ<8> C13 FBC_D08 FBC_CMD8 G21 FB_B_UCS0_L OUT 79
FB_A_DQ<2> FB_A_LMA<5> FB_B_DQ<9> FB_B_MA<11> 1

98 78 BI L33 FBA_D02 FBA_CMD2 U31 OUT 78 98 98 79 BI B11 FBC_D09 FBC_CMD9 F20 OUT 79 98
R8252
98 78 BI FB_A_DQ<3> N34 FBA_D03 FBA_CMD3 Y32 FB_A_BA<1> OUT 78 98 98 79 BI FB_B_DQ<10> C11 FBC_D10 FBC_CMD10 F19 FB_B_LCAS_L OUT 79 10K
5%
98 78 BI FB_A_DQ<4> N35 FBA_D04 FBA_CMD4 AB35 FB_A_UMA<2> OUT 78 98 98 79 BI FB_B_DQ<11> A11 FBC_D11 FBC_CMD11 F23 FB_B_WE_L OUT 79 98 1/16W
MF-LF
98 78 BI FB_A_DQ<5> P35 FBA_D05 FBA_CMD5 AB34 FB_A_UMA<4> OUT 78 98 98 79 BI FB_B_DQ<12> C10 FBC_D12 FBC_CMD12 A22 FB_B_BA<0> OUT 79 98
2 402
98 78 BI FB_A_DQ<6> P33 FBA_D06 FBA_CMD6 W35 FB_A_UMA<3> OUT 78 98 98 79 BI FB_B_DQ<13> C8 FBC_D13 FBC_CMD13 C22 FB_B_UMA<5> OUT 79 98
98 78 BI FB_A_DQ<7> P34 FBA_D07 FBA_CMD7 W33 FB_A_UCKE OUT 78 98 98 79 BI FB_B_DQ<14> B8 FBC_D14 FBC_CMD14 B17 FB_B_MA<12> OUT 79 98
98 78 BI FB_A_DQ<8> K35 FBA_D08 FBA_CMD8 W30 FB_A_UCS0_L OUT 78 98 79 BI FB_B_DQ<15> A8 FBC_D15 FBC_CMD15 F24 FB_B_DRAM_RST OUT 79 98
FB_A_DQ<9> FB_A_MA<11> 1 FB_B_DQ<16> FB_B_MA<7>

98 78 BI K33 FBA_D09 FBA_CMD9 T34 OUT 78 98
R8203 98 79 BI E8 FBC_D16 FBC_CMD16 C25 OUT 79 98
1
98 78 BI FB_A_DQ<10> K34 FBA_D10 FBA_CMD10 T35 FB_A_LCAS_L OUT 78 10K 98 79 BI FB_B_DQ<17> F8 FBC_D17 FBC_CMD17 E22 FB_B_MA<10> OUT 79 98 R8250
5%
98 78 BI FB_A_DQ<11> H33 FBA_D11 FBA_CMD11 AB31 FB_A_WE_L OUT 78 98 1/16W 98 79 BI FB_B_DQ<18> F10 FBC_D18 FBC_CMD18 C20 FB_B_LCKE OUT 79 98 10K
MF-LF 5%
98 78 BI FB_A_DQ<12> G34 FBA_D12 FBA_CMD12 Y30 FB_A_BA<0> OUT 78 98
2 402 98 79 BI FB_B_DQ<19> F9 FBC_D19 FBC_CMD19 B22 FB_B_MA<0> OUT 79 98 1/16W
1 MF-LF
98 78 BI FB_A_DQ<13> G33 FBA_D13 FBA_CMD13 Y34 FB_A_UMA<5> OUT 78 98 98 79 BI FB_B_DQ<20> F12 FBC_D20 FBC_CMD20 A19 FB_B_MA<9> OUT 79 98
R8251 2 402
98 78 BI FB_A_DQ<14> E34 FBA_D14 FBA_CMD14 W32 FB_A_MA<12> OUT 78 98 98 79 BI FB_B_DQ<21> D8 FBC_D21 FBC_CMD21 D22 FB_B_MA<6> OUT 79 98 10K
5%
98 78 BI FB_A_DQ<15> E33 FBA_D15 FBA_CMD15 AA30 FB_A_DRAM_RST OUT 78 98 98 79 BI FB_B_DQ<22> D11 FBC_D22 FBC_CMD22 D20 FB_B_LMA<2> OUT 79 98 1/16W
MF-LF
98 78 BI FB_A_DQ<16> G31 FBA_D16 FBA_CMD16 AA32 FB_A_MA<7> OUT 78 98 98 79 BI FB_B_DQ<23> E11 FBC_D23 FBC_CMD23 E19 FB_B_MA<8> OUT 79 98
2 402
FB_A_DQ<17> FB_A_MA<10> 1 FB_B_DQ<24> FB_B_LMA<3>
98 78 BI F30 FBA_D17 FBA_CMD17 Y33 OUT 78 98
R8200 98 79 BI D12 FBC_D24 FBC_CMD24 D19 OUT 79 98
98 78 BI FB_A_DQ<18> G30 FBA_D18 FBA_CMD18 U32 FB_A_LCKE OUT 78 98 10K 98 79 BI FB_B_DQ<25> E13 FBC_D25 FBC_CMD25 F18 FB_B_MA<1> OUT 79 98
5%
98 78 BI FB_A_DQ<19> G32 FBA_D19 FBA_CMD19 Y31 FB_A_MA<0> OUT 78 98 1/16W 98 79 BI FB_B_DQ<26> F13 FBC_D26 FBC_CMD26 C19 NC_FBB_MA<13> OUT 81
1 MF-LF
98 78 BI FB_A_DQ<20> K30 FBA_D20 FBA_CMD20 U34 FB_A_MA<9> OUT 78 98
R8201 2 402 98 79 BI FB_B_DQ<27> F14 FBC_D27 FBC_CMD27 F22 FB_B_BA<2> OUT 79 98
98 78 BI FB_A_DQ<21> K32 FBA_D21 FBA_CMD21 Y35 FB_A_MA<6> OUT 78 98 10K 98 79 BI FB_B_DQ<28> F15 FBC_D28 FBC_CMD28 C23 NC_FB_B_UCS1_L 81
5%
FB_A_DQ<22> FB_A_LMA<2> FB_B_DQ<29> FB_B_LCS0_L
C 98 78
98 78
BI
BI FB_A_DQ<23>
H30
K31
FBA_D22
FBA_D23
FBA_CMD22
FBA_CMD23
W34
V30 FB_A_MA<8>
OUT
OUT
78 98
78 98
1/16W
MF-LF
2 402
98 79
98 79
BI
BI FB_B_DQ<30>
E16
F16
FBC_D29
FBC_D30
FBC_CMD29
FBC_CMD30
B20
A20
79 98
NC_FB_B_LCS1_L 81 C
98 78 BI FB_A_DQ<24> L31 FBA_D24 FBA_CMD24 U35 FB_A_LMA<3> OUT 78 98 98 79 BI FB_B_DQ<31> F17 FBC_D31
FBC_CLK0 E17 FB_B_CLK_P<0> OUT 79 98
98 78 BI FB_A_DQ<25> L30 FBA_D25 FBA_CMD25 U30 FB_A_MA<1> OUT 78 98 98 79 BI FB_B_DQ<32> D29 FBC_D32
FBC_CLK0* D17 FB_B_CLK_N<0> OUT 79 98
98 78 BI FB_A_DQ<26> M32 FBA_D26 FBA_CMD26 U33 NC_FBA_MA<13> OUT 81 98 79 BI FB_B_DQ<33> F27 FBC_D33
FBC_CLK1 D23 FB_B_CLK_P<1> OUT 79 98
98 78 BI FB_A_DQ<27> N30 FBA_D27 FBA_CMD27 AB30 FB_A_BA<2> OUT 78 98 98 79 BI FB_B_DQ<34> F28 FBC_D34
FBC_CLK1* E23 FB_B_CLK_N<1> OUT 79 98
98 78 BI FB_A_DQ<28> M30 FBA_D28 FBA_CMD28 AB33 NC_FB_A_UCS1_L 81 98 79 BI FB_B_DQ<35> E28 FBC_D35
98 78 BI FB_A_DQ<29> P31 FBA_D29 FBA_CMD29 T33 FB_A_LCS0_L 78 98 98 79 BI FB_B_DQ<36> D26 FBC_D36
FBC_DQM0 A16 FB_B_DQM_L<0> BI 79 98
98 78 BI FB_A_DQ<30> R32 FBA_D30 FBA_CMD30 W29 NC_FB_A_LCS1_L 81 98 79 BI FB_B_DQ<37> F25 FBC_D37
FBC_DQM1 D10 FB_B_DQM_L<1> BI 79 98
98 78 BI FB_A_DQ<31> R30 FBA_D31 98 79 BI FB_B_DQ<38> D24 FBC_D38
FBA_CLK0 T32 FB_A_CLK_P<0> OUT 78 98 FBC_DQM2 F11 FB_B_DQM_L<2> BI 79 98
98 78 BI FB_A_DQ<32> AG30 FBA_D32 98 79 BI FB_B_DQ<39> E25 FBC_D39
FBA_CLK0* T31 FB_A_CLK_N<0> OUT 78 98 FBC_DQM3 D15 FB_B_DQM_L<3> BI 79 98
98 78 BI FB_A_DQ<33> AG32 FBA_D33 98 79 BI FB_B_DQ<40> E32 FBC_D40
FBA_CLK1 AC31 FB_A_CLK_P<1> OUT 78 98 FBC_DQM4 D27 FB_B_DQM_L<4> BI 79 98
98 78 BI FB_A_DQ<34> AH31 FBA_D34 98 79 BI FB_B_DQ<41> F32 FBC_D41
FBA_CLK1* AC30 FB_A_CLK_N<1> OUT 78 98 FBC_DQM5 D34 FB_B_DQM_L<5> BI 79 98
98 78 BI FB_A_DQ<35> AF31 FBA_D35 98 79 BI FB_B_DQ<42> D33 FBC_D42
FBC_DQM6 A34 FB_B_DQM_L<6> BI 79 98
98 78 BI FB_A_DQ<36> AF30 FBA_D36 98 79 BI FB_B_DQ<43> E31 FBC_D43
FBA_DQM0 P32 FB_A_DQM_L<0> BI 78 98 FBC_DQM7 D28 FB_B_DQM_L<7> BI 79 98
98 78 BI FB_A_DQ<37> AE30 FBA_D37 98 79 BI FB_B_DQ<44> C33 FBC_D44
FBA_DQM1 H34 FB_A_DQM_L<1> BI 78 98
98 78 BI FB_A_DQ<38> AC32 FBA_D38 98 79 BI FB_B_DQ<45> F29 FBC_D45
FBA_DQM2 J30 FB_A_DQM_L<2> BI 78 98 FBC_DQS_RN0 B14 FB_B_RDQS<0> IN 79 98
98 78 BI FB_A_DQ<39> AD30 FBA_D39 98 79 BI FB_B_DQ<46> D30 FBC_D46
FBA_DQM3 P30 FB_A_DQM_L<3> BI 78 98 FBC_DQS_RN1 B10 FB_B_RDQS<1> IN 79 98
98 78 BI FB_A_DQ<40> AN33 FBA_D40 98 79 BI FB_B_DQ<47> E29 FBC_D47
FBA_DQM4 AF32 FB_A_DQM_L<4> BI 78 98 FBC_DQS_RN2 D9 FB_B_RDQS<2> IN 79 98
98 78 BI FB_A_DQ<41> AL31 FBA_D41 98 79 BI FB_B_DQ<48> B29 FBC_D48
FBA_DQM5 AL32 FB_A_DQM_L<5> BI 78 98 FBC_DQS_RN3 E14 FB_B_RDQS<3> IN 79 98
98 78 BI FB_A_DQ<42> AM33 FBA_D42 98 79 BI FB_B_DQ<49> C31 FBC_D49
FBA_DQM6 AL34 FB_A_DQM_L<6> BI 78 98 FBC_DQS_RN4 F26 FB_B_RDQS<4> IN 79 98
98 78 BI FB_A_DQ<43> AL33 FBA_D43 98 79 BI FB_B_DQ<50> C29 FBC_D50
FBA_DQM7 AF35 FB_A_DQM_L<7> BI 78 98 FBC_DQS_RN5 D31 FB_B_RDQS<5> IN 79 98
98 78 BI FB_A_DQ<44> AK30 FBA_D44 98 79 BI FB_B_DQ<51> B31 FBC_D51
FBC_DQS_RN6 A31 FB_B_RDQS<6> IN 79 98
98 78 BI FB_A_DQ<45> AK32 FBA_D45 98 79 BI FB_B_DQ<52> C32 FBC_D52
FBA_DQS_RN0 L35 FB_A_RDQS<0> IN 78 98 FBC_DQS_RN7 A26 FB_B_RDQS<7> IN 79 98
98 78 BI FB_A_DQ<46> AJ30 FBA_D46 98 79 BI FB_B_DQ<53> B32 FBC_D53
FBA_DQS_RN1 G35 FB_A_RDQS<1> IN 78 98
98 78 BI FB_A_DQ<47> AH30 FBA_D47 98 79 BI FB_B_DQ<54> B35 FBC_D54
FBA_DQS_RN2 H31 FB_A_RDQS<2> IN 78 98 FBC_DQS_WP0 C14 FB_B_WDQS<0> OUT 79 98
98 78 FB_A_DQ<48> AH33 FBA_D48 98 79 FB_B_DQ<55> B34 FBC_D55
B 98 78
BI
BI FB_A_DQ<49> AH35 FBA_D49
FBA_DQS_RN3
FBA_DQS_RN4
N32
AD32
FB_A_RDQS<3>
FB_A_RDQS<4>
IN
IN
78 98
78 98
98 79
BI
BI FB_B_DQ<56> A29 FBC_D56
FBC_DQS_WP1
FBC_DQS_WP2
A10
E10
FB_B_WDQS<1>
FB_B_WDQS<2>
OUT
OUT
79 98
79 98
B
98 78 BI FB_A_DQ<50> AH34 FBA_D50 82 80 75 51 7 6 PP1V05_S0GPU 98 79 BI FB_B_DQ<57> B28 FBC_D57
FBA_DQS_RN5 AJ31 FB_A_RDQS<5> IN 78 98 FBC_DQS_WP3 D14 FB_B_WDQS<3> OUT 79 98
FB_A_DQ<51> AH32 FBA_D51 FB_B_DQ<58> A28 FBC_D58
98 78 BI
FB_A_DQ<52> AJ33 FBA_D52
FBA_DQS_RN6 AJ35 FB_A_RDQS<6> IN 78 98 L8200 98 79 BI
FB_B_DQ<59> C28 FBC_D59
FBC_DQS_WP4 E26 FB_B_WDQS<4> OUT 79 98
98 78 BI
FBA_DQS_RN7 AC34 FB_A_RDQS<7> 78 98
FERR-220-OHM-2.5A 98 79 BI
FBC_DQS_WP5 D32 FB_B_WDQS<5> 79 98 51 8 7 6 PP1V8_S0GPU_ISNS
FB_A_DQ<53> IN FB_B_DQ<60> OUT
98 78 BI AL35 FBA_D53 98 79 BI C26 FBC_D60 79 78 77 76
1 2 FBC_DQS_WP6 A32 FB_B_WDQS<6> OUT 79 98
98 78 BI FB_A_DQ<54> AM34 FBA_D54 98 79 BI FB_B_DQ<61> D25 FBC_D61
98 78 BI FB_A_DQ<55> AM35 FBA_D55
FBA_DQS_WP0 L34 FB_A_WDQS<0> OUT 78 98
0603
98 79 BI FB_B_DQ<62> B25 FBC_D62
FBC_DQS_WP7 B26 FB_B_WDQS<7> OUT 79 98
R82951
FBA_DQS_WP1 H35 FB_A_WDQS<1> 1.07K
98 78 BI FB_A_DQ<56> AF33 FBA_D56
FBA_DQS_WP2 J32 FB_A_WDQS<2>
OUT 78 98
1 C8202 1 C8200 1 C8201 98 79 BI FB_B_DQ<63> A25 FBC_D63 1%
1/16W
98 78 BI FB_A_DQ<57> AE32 FBA_D57
OUT 78 98
1UF 4.7UF 4.7UF MF-LF
N31 FB_A_WDQS<3> 10% 10% 10%
98 78 BI FB_A_DQ<58> AF34 FBA_D58
FBA_DQS_WP3 OUT 78 98
2 6.3V 2 6.3V 2 6.3V NCG11 402 2
AE31 FB_A_WDQS<4> CERM X5R-CERM X5R-CERM FB_B_UCAS_L
98 78 BI FB_A_DQ<59> AE35 FBA_D59
FBA_DQS_WP4 OUT 78 98 402 603 603 NCG12 FBC_DEBUG G19 OUT 79
FBA_DQS_WP5 AJ32 FB_A_WDQS<5> OUT 78 98

NCG14
98 78 BI FB_A_DQ<60> AE34 FBA_D60 FB_VREF J27 GPU_FB_VREF
FBA_DQS_WP6 AJ34 FB_A_WDQS<6> OUT 78 98 79 78 77 76 51 8 7 6 PP1V8_S0GPU_ISNS NCG15
98 78 BI FB_A_DQ<61> AE33 FBA_D61 NC
FBA_DQS_WP7 AC33 FB_A_WDQS<7> OUT 78 98
NCG24 NO STUFF NO STUFF
98 78 BI FB_A_DQ<62> AB32 FBA_D62
R82901 NCG25 C8296 1 R82971 R82961
98 78 BI FB_A_DQ<63> AC35 FBA_D63 FB_DLLAVDD AG27 PP1V05_GPU_FBPLLAVDD_F MIN_LINE_WIDTH=0.2 MM 0.1uF 1.02K 2.49K
MIN_NECK_WIDTH=0.2 MM 56.2 NCG27 10% 1% 1%
FB_PLLAVDD AF27 VOLTAGE=1.05V 1% 16V 2 1/16W 1/16W
NCP29 1/16W
MF-LF NCG28 X5R MF-LF
402 2
MF-LF
402 2
FB_A_UCAS_L 402
NCR29 FBA_DEBUG T30 OUT 78 402 2
NCL29 FB_CAL_PD_VDDQ K27 FBCAL_PD_VDDQ

NCM29 L27 FBCAL_PU_GND PLACE_NEAR=U8000.K27:3mm NO STUFF GPU_FB_VREF_UNTERM_L
NC FB_CAL_PU_GND MIN_LINE_WIDTH=0.25 mm
AD29
NC D 6 MIN_NECK_WIDTH=0.25 mm
AE29
FB_CAL_TERM_GND M27 FBCAL_TERM_GND Q8295
NC R82911 SSM6N15FEAPE
AG29
NC R82921 31.6
SOT563
AH29
NC 40.2 1% PLACE_NEAR=U8000.L27:3mm
1% 1/16W
1/16W MF-LF
MF-LF 402 2 2 G S 1
402 2
FB_VREF_UNTERM
A PLACE_NEAR=U8000.M27:3mm 81 80 79 78 IN
PAGE TITLE
NO STUFF NC
NV GT216 FRAME BUFFER I/F
DRAWING NUMBER SIZE
Q8295 D 3
Apple Inc. D
SSM6N15FEAPE REVISION
SOT563 R

5 G S 4 THE INFORMATION CONTAINED HEREIN IS THE
NC NC I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
82 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
Page Notes
PP1V8_S0GPU_ISNS CRITICAL PP1V8_S0GPU_ISNS CRITICAL
78 77 76 51 8 7 6 79 78 77 76 51 8 7 6 Power aliases required by this page:
79
A2 VDD0 VSS0 A3 A2 VDD0 VSS0 A3 - =PP1V8_S0_FB_VDD
A11 VDD1
U8400 VSS1 A10 A11 VDD1
U8450 VSS1 A10 - =PP1V8_S0_FB_VREFA
BGA BGA
C8400 1 1 C8401 1 C8402 1 C8403 1 C8404 F1 VDD2 (2 OF 2) VSS2 G1 C8450 1 1 C8451 1 C8452 1 C8453 1 C8454 F1 VDD2 (2 OF 2) VSS2 G1
10UF 0.1uF 0.1uF 0.1uF 0.1uF 10UF 0.1uF 0.1uF 0.1uF 0.1uF Signal aliases required by this page:
K4J10324QD-HC11
K4J10324QD-HC11
F12 VSS3 G12 F12 VSS3 G12
32MX32-900MHZ-MFH
32MX32-900MHZ-MFH
20% 10% 10% 10% 10% VDD3 20% 10% 10% 10% 10% VDD3
6.3V 2 (NONE)
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
M1 VDD4 VSS4 L1 6.3V 2
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
M1 VDD4 VSS4 L1
603 402 402 402 402 M12 VDD5 VSS5 L12 603 402 402 402 402 M12 VDD5 VSS5 L12 BOM options provided by this page:
V2 VDD6 VSS6 V3 V2 VDD6 VSS6 V3 VRAM4
V11 VDD7 VSS7 V10 V11 VDD7 VSS7 V10
D
K1 VDDA0
K12 VDDA1
VSSA0 J1
VSSA1 J12
K1 VDDA0
K12 VDDA1
VSSA0 J1
VSSA1 J12
D
A1 VDDQ0 VSSQ0 B1 A1 VDDQ0 VSSQ0 B1
1 C8410 1 C8415 A12 VDDQ1 VSSQ1 B4
1 C8460 1 C8465 A12 VDDQ1 VSSQ1 B4
0.1uF 0.1uF 0.1uF 0.1uF
10% 10% C1 VDDQ2 VSSQ2 B9 10% 10% C1 VDDQ2 VSSQ2 B9
2 16V
X5R 2 16V
X5R B12 2 16V
X5R 2 16V
X5R B12
402 402 C4 VDDQ3 VSSQ3 402 402 C4 VDDQ3 VSSQ3
U8400.J1 U8400.J12 C9 VDDQ4 VSSQ4 D1 U8400.J1 U8400.J12 C9 VDDQ4 VSSQ4 D1
Connect to designated pin, then GND Connect to designated pin, then GND
C12 VDDQ5 VSSQ5 D4 C12 VDDQ5 VSSQ5 D4
E1 VDDQ6 VSSQ6 D9 E1 VDDQ6 VSSQ6 D9
78 77 76 51 8 7 6 PP1V8_S0GPU_ISNS D12 79 78 77 76 51 8 7 6 PP1V8_S0GPU_ISNS D12
79 E4 VDDQ7 VSSQ7 E4 VDDQ7 VSSQ7
E9 VDDQ8 VSSQ8 G2 E9 VDDQ8 VSSQ8 G2
C8420 1 1 C8421 1 C8422 1 C8423 1 C8424 1 C8425 1 C8426 J4 VDDQ10 VSSQ10 L2 C8470 1 1 C8471 1 C8472 1 C8473 1 C8474 1 C8475 1 C8476 J4 VDDQ10 VSSQ10 L2
10UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
20% 10% 10% 10% 10% 10% 10% J9 VDDQ11 VSSQ11 L11 20% 10% 10% 10% 10% 10% 10% J9 VDDQ11 VSSQ11 L11
6.3V 2 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 6.3V 2 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V
X5R X5R X5R X5R X5R X5R X5R N1 VDDQ12 VSSQ12 P1 X5R X5R X5R X5R X5R X5R X5R N1 VDDQ12 VSSQ12 P1
603 402 402 402 402 402 402 603 402 402 402 402 402 402
N4 VDDQ13 VSSQ13 P4 N4 VDDQ13 VSSQ13 P4
78 32 8 GPU_FB_A_VREF_DIV N12 VDDQ15 VSSQ15 P12 78 32 8 GPU_FB_A_VREF_DIV N12 VDDQ15 VSSQ15 P12
R1 VDDQ16 VSSQ16 T1 R1 VDDQ16 VSSQ16 T1
1 1
R8430 R8433 R4 VDDQ17 VSSQ17 T4
R84801 R84831 R4 VDDQ17 VSSQ17 T4
549 549 R9 VDDQ18 VSSQ18 T9 549 549 R9 VDDQ18 VSSQ18 T9
1% 1% R12 T12 1% 1% R12 T12
1/16W 1/16W VDDQ19 VSSQ19 1/16W 1/16W VDDQ19 VSSQ19
MF-LF MF-LF V1 MF-LF MF-LF V1
402 2 402 2 VDDQ20 402 2 402 2 VDDQ20
V12 VDDQ21 V12 VDDQ21
FB_A0_VREF H1 VREF0 FB_A1_VREF H1 VREF0

FB_A2_VREF H12 VREF1 FB_A3_VREF H12 VREF1
C C8431 R84341 C8432 C8481 R84841 C8482
C
R84311 R84321 1
0.01UF
R84351 1
0.01UF
R84811 R84821 1
0.01uF
R84851 1
0.01uF
1.33K 931 10% 1.33K 931 10% 1.33K 931 10% 1.33K 931 10%
1% 1% 16V 1% 1% 1% 1% 1% 1%
1/16W 1/16W 2 CERM 1/16W 1/16W 2 16V
CERM 1/16W 1/16W 16V
2 CERM 1/16W 1/16W 2 16V
CERM
MF-LF MF-LF 402 MF-LF MF-LF 402 MF-LF MF-LF 402 MF-LF MF-LF 402
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2
FB_A2_VREF_UNTERM_L FB_A3_VREF_UNTERM_L
FB_A0_VREF_UNTERM_L FB_A1_VREF_UNTERM_L
FB_A_CLK0_TERM FB_A_CLK1_TERM
VOLTAGE=0.9V D 6 D 3 VOLTAGE=0.9V D 6 D 3
VRAM4 VRAM4 Q8400 Q8400 VRAM4 VRAM4 Q8450 Q8450
R8440 1
R8442 1
R8444 1
R8446 1 SSM6N15FEAPE SSM6N15FEAPE R8490 1
R8492 1
R8494 1
R8496 1 C8496 1 SSM6N15FEAPE SSM6N15FEAPE
1K 121 121 243 C8446 1 SOT563 SOT563
1K 121 121 243 0.01UF SOT563 SOT563
5% 1% 1% 1% 0.01UF 79 78 77 FB_VREF_UNTERM 5% 1% 1% 1% 10% 79 78 77 FB_VREF_UNTERM
1/16W 1/16W 1/16W 1/16W 10% IN
1/16W 1/16W 1/16W 1/16W 16V IN
MF-LF MF-LF MF-LF MF-LF 16V 81 80
CERM 2 81 80
402 2 402 2 402 2 402 2 CERM 2 2 G 5 G

MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
MF-LF
402 2 402 2 G 5 G
402 S 1 S 4 S 1 S 4
VRAM4 VRAM4 VRAM4 VRAM4
1 1 1 1 1 1
R8443 R8445 R8447 R8493 R8495 R8497
121 121 243 OMIT 121 121 243 OMIT
1% 1% 1% 1% 1% 1%
1/16W 1/16W 1/16W CRITICAL 1/16W 1/16W 1/16W CRITICAL
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402 2 402 2 402
98 78 77 IN FB_A_MA<0> K9 A0 U8400 DM0 E3 FB_A_DQM_L<1> IN 77 98 98 78 77 IN FB_A_MA<0> K9 A0 U8450 DM0 E3 FB_A_DQM_L<6> IN 77 98
98 78 77 IN FB_A_MA<1> H11 A1 BGA DM1 E10 FB_A_DQM_L<2> IN 77 98 98 78 77 IN FB_A_MA<1> H11 A1 BGA DM1 E10 FB_A_DQM_L<7> IN 77 98
98 77 IN FB_A_LMA<2> K10 A2 (1 OF 2) DM2 N10 FB_A_DQM_L<3> IN 77 98 98 77 IN FB_A_UMA<2> K10 A2 (1 OF 2) DM2 N10 FB_A_DQM_L<5> IN 77 98
32MX32-900MHZ-MFH
K4J10324QD-HC11
32MX32-900MHZ-MFH
K4J10324QD-HC11
98 77 IN FB_A_LMA<3> M9 A3 DM3 N3 FB_A_DQM_L<0> IN 77 98 98 77 IN FB_A_UMA<3> M9 A3 DM3 N3 FB_A_DQM_L<4> IN 77 98
MFHIGH
MFHIGH
98 77 IN FB_A_LMA<4> K4 A4 98 77 IN FB_A_UMA<4> K4 A4
DQ0 B2 FB_A_DQ<11> BI 77 98 DQ0 B2 FB_A_DQ<48> BI 77 98
98 77 IN FB_A_LMA<5> H2 A5 98 77 IN FB_A_UMA<5> H2 A5
DQ1 B3 FB_A_DQ<14> 77 98 DQ1 B3 FB_A_DQ<51> 77 98
B 98 78 77
98 78 77
IN
IN
FB_A_MA<6>
FB_A_MA<7>
K3
L4
A6
A7
DQ2 C2 FB_A_DQ<15>
BI
BI 77 98
98 78 77
98 78 77
IN
IN
FB_A_MA<6>
FB_A_MA<7>
K3
L4
A6
A7
DQ2 C2 FB_A_DQ<55>
BI
BI 77 98 B
DQ3 C3 FB_A_DQ<13> BI 77 98 DQ3 C3 FB_A_DQ<54> BI 77 98
98 78 77 IN FB_A_MA<8> K2 A8/AP 98 78 77 IN FB_A_MA<8> K2 A8/AP
DQ4 E2 FB_A_DQ<10> BI 77 98 DQ4 E2 FB_A_DQ<52> BI 77 98
98 78 77 IN FB_A_MA<9> M4 A9 98 78 77 IN FB_A_MA<9> M4 A9
DQ5 F3 FB_A_DQ<12> BI 77 98 DQ5 F3 FB_A_DQ<50> BI 77 98
98 78 77 IN FB_A_MA<10> K11 A10 98 78 77 IN FB_A_MA<10> K11 A10
DQ6 F2 FB_A_DQ<8> BI 77 98 DQ6 F2 FB_A_DQ<53> BI 77 98
98 78 77 IN FB_A_MA<11> L9 A11 98 78 77 IN FB_A_MA<11> L9 A11
DQ7 G3 FB_A_DQ<9> BI 77 98 DQ7 G3 FB_A_DQ<49> BI 77 98
98 77 IN FB_A_LCKE H9 CKE 98 77 IN FB_A_UCKE H9 CKE
98 78 77 IN FB_A_MA<12> J3 A12/CS1* 98 78 77 IN FB_A_MA<12> J3 A12/CS1*
98 77 IN FB_A_CLK_P<0> J11 CK DQ10 C11 FB_A_DQ<19> BI 77 98 98 77 IN FB_A_CLK_P<1> J11 CK DQ10 C11 FB_A_DQ<63> BI 77 98
98 77 IN FB_A_CLK_N<0> J10 CK* DQ11 C10 FB_A_DQ<22> BI 77 98 98 77 IN FB_A_CLK_N<1> J10 CK* DQ11 C10 FB_A_DQ<60> BI 77 98
98 77 IN FB_A_LCS0_L F4 CS0* DQ12 E11 FB_A_DQ<18> BI 77 98 77 IN FB_A_UCS0_L F4 CS0* DQ12 E11 FB_A_DQ<58> BI 77 98
MFHIGH
MFHIGH
98 78 77 IN FB_A_WE_L H4 WE* DQ13 F10 FB_A_DQ<20> BI 77 98 98 78 77 IN FB_A_WE_L H4 WE* DQ13 F10 FB_A_DQ<56> BI 77 98
77 IN FB_A_LCAS_L F9 CAS* DQ14 F11 FB_A_DQ<23> BI 77 98 77 IN FB_A_UCAS_L F9 CAS* DQ14 F11 FB_A_DQ<59> BI 77 98
98 78 77 IN FB_A_RAS_L H10 RAS* DQ15 G10 FB_A_DQ<21> BI 77 98 98 78 77 IN FB_A_RAS_L H10 RAS* DQ15 G10 FB_A_DQ<61> BI 77 98
FB_A0_ZQ A4 ZQ DQ16 M11 FB_A_DQ<26> BI 77 98 FB_A1_ZQ A4 ZQ DQ16 M11 FB_A_DQ<46> BI 77 98
FB_A0_MF A9 MF DQ17 L10 FB_A_DQ<24> BI 77 98 FB_A1_MF A9 MF DQ17 L10 FB_A_DQ<47> BI 77 98
FB_A0_SEN V4 SEN DQ18 N11 FB_A_DQ<28> BI 77 98 FB_A1_SEN V4 SEN DQ18 N11 FB_A_DQ<44> BI 77 98
98 78 77 IN FB_A_DRAM_RST V9 RESET DQ19 M10 FB_A_DQ<25> BI 77 98 98 78 77 IN FB_A_DRAM_RST V9 RESET DQ19 M10 FB_A_DQ<41> BI 77 98
DQ20 R11 FB_A_DQ<29> BI 77 98 DQ20 R11 FB_A_DQ<45> BI 77 98

98 77 OUT FB_A_RDQS<1> D3 RDQS0 98 77 OUT FB_A_RDQS<6> D3 RDQS0
DQ21 R10 FB_A_DQ<27> BI 77 98 DQ21 R10 FB_A_DQ<42> BI 77 98
98 77 OUT FB_A_RDQS<2> D10 RDQS1 98 77 OUT FB_A_RDQS<7> D10 RDQS1
DQ22 T11 FB_A_DQ<30> BI 77 98 DQ22 T11 FB_A_DQ<43> BI 77 98
98 77 OUT FB_A_RDQS<3> P10 RDQS2 98 77 OUT FB_A_RDQS<5> P10 RDQS2
DQ23 T10 FB_A_DQ<31> BI 77 98 DQ23 T10 FB_A_DQ<40> BI 77 98
98 77 OUT FB_A_RDQS<0> P3 RDQS3 98 77 OUT FB_A_RDQS<4> P3 RDQS3
DQ24 M2 FB_A_DQ<2> BI 77 98 DQ24 M2 FB_A_DQ<35> BI 77 98
98 77 IN FB_A_WDQS<1> D2 WDQS0 DQ25 L3 FB_A_DQ<3> BI 77 98 98 77 IN FB_A_WDQS<6> D2 WDQS0 DQ25 L3 FB_A_DQ<34> BI 77 98
98 77 IN FB_A_WDQS<2> D11 WDQS1 DQ26 N2 FB_A_DQ<0> BI 77 98 98 77 IN FB_A_WDQS<7> D11 WDQS1 DQ26 N2 FB_A_DQ<33> BI 77 98
FB_A_WDQS<3> P11 M3 FB_A_DQ<4> FB_A_WDQS<5> P11 M3 FB_A_DQ<32>

A 98 77
98 77
IN
IN FB_A_WDQS<0> P2
WDQS2
WDQS3
DQ27
DQ28 R2 FB_A_DQ<1>
BI
BI
77 98
77 98
98 77
98 77
IN
IN FB_A_WDQS<4> P2
WDQS2
WDQS3
DQ27
DQ28 R2 FB_A_DQ<39>
BI
BI
77 98
77
98
SYNC_MASTER=GT216 SYNC_DATE=03/26/2009 A
DQ29 R3 FB_A_DQ<5> BI 77 98 DQ29 R3 FB_A_DQ<36> BI
PAGE TITLE
FB_A_BA<0> FB_A_BA<0>
G9 BA0 G9 BA0
GDDR3 Frame Buffer A (Top)
MFHIGH
MFHIGH
98 78 77 IN 98 78 77 IN
DQ30 T2 FB_A_DQ<6> BI 77 98 DQ30 T2 FB_A_DQ<38> BI
98 78 77 IN FB_A_BA<1> G4 BA1 98 78 77 IN FB_A_BA<1> G4 BA1
DQ31 T3 FB_A_DQ<7> BI 77 98 DQ31 T3 FB_A_DQ<37> BI 77 DRAWING NUMBER SIZE
FB_A_BA<2> H3 BA2 FB_A_BA<2> H3 BA2 98
98 78 77 IN 98 78 77 IN
Apple Inc. D
J2 RFU J2 RFU REVISION
NC NC R
R84481 1
R8449 NOTICE OF PROPRIETARY PROPERTY: BRANCH
243
1%
100
5% R84981 1
R8499 THE INFORMATION CONTAINED HEREIN IS THE
1/16W 1/16W 243 100 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MF-LF MF-LF 1% 5% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 2 2 402 1/16W 1/16W
MF-LF
402 2
MF-LF I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 84 OF 132
2 402 II NOT TO REPRODUCE OR COPY IT
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
Page Notes
PP1V8_S0GPU_ISNS CRITICAL PP1V8_S0GPU_ISNS CRITICAL
78 77 76 51 8 7 6 79 78 77 76 51 8 7 6 Power aliases required by this page:
79
A2 VDD0 VSS0 A3 A2 VDD0 VSS0 A3 - =PP1V8_S0_FB_VDD
A11 VDD1
U8500 VSS1 A10 A11 VDD1
U8550 VSS1 A10 - =PP1V8_S0_FB_VREF_B
BGA BGA
C8500 1 1 C8501 1 C8502 1 C8503 1 C8504 F1 VDD2 (2 OF 2) VSS2 G1 C8550 1 1 C8551 1 C8552 1 C8553 1 C8554 F1 VDD2 (2 OF 2) VSS2 G1
10UF 0.1uF 0.1uF 0.1uF 0.1uF 10UF 0.1uF 0.1uF 0.1uF 0.1uF Signal aliases required by this page:
K4J10324QD-HC11
K4J10324QD-HC11
F12 VSS3 G12 F12 VSS3 G12
32MX32-900MHZ-MFH
32MX32-900MHZ-MFH
20% 10% 10% 10% 10% VDD3 20% 10% 10% 10% 10% VDD3
6.3V 2 (NONE)
X5R 2 16V
X5R
16V
2 X5R 2 16V
X5R 2 16V
X5R
M1 VDD4 VSS4 L1 6.3V 2
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
M1 VDD4 VSS4 L1
603 402 402 402 402 M12 VDD5 VSS5 L12 603 402 402 402 402 M12 VDD5 VSS5 L12 BOM options provided by this page:
V2 VDD6 VSS6 V3 V2 VDD6 VSS6 V3 VRAM4
V11 VDD7 VSS7 V10 V11 VDD7 VSS7 V10
D
K1 VDDA0
K12 VDDA1
VSSA0 J1
VSSA1 J12
K1 VDDA0
K12 VDDA1
VSSA0 J1
VSSA1 J12
D
A1 VDDQ0 VSSQ0 B1 A1 VDDQ0 VSSQ0 B1
1 C8510 1 C8515 A12 VDDQ1 VSSQ1 B4
1 C8560 1 C8565 A12 VDDQ1 VSSQ1 B4
0.1uF 0.1uF 0.1uF 0.1uF
10% 10% C1 VDDQ2 VSSQ2 B9 10% 10% C1 VDDQ2 VSSQ2 B9
2 16V
X5R 2 16V
X5R B12 2 16V
X5R 2 16V
X5R B12
402 402 C4 VDDQ3 VSSQ3 402 402 C4 VDDQ3 VSSQ3
U8500.J1 U8500.J12 C9 VDDQ4 VSSQ4 D1 U8500.J1 U8500.J12 C9 VDDQ4 VSSQ4 D1
Connect to designated pin, then GND Connect to designated pin, then GND
C12 VDDQ5 VSSQ5 D4 C12 VDDQ5 VSSQ5 D4
E1 VDDQ6 VSSQ6 D9 E1 VDDQ6 VSSQ6 D9
78 77 76 51 8 7 6 PP1V8_S0GPU_ISNS D12 79 78 77 76 51 8 7 6 PP1V8_S0GPU_ISNS D12
79 E4 VDDQ7 VSSQ7 E4 VDDQ7 VSSQ7
C8520 1 1 C8521 1 C8522 1 C8523 1 C8524 1 C8525 1 C8526 J4 VDDQ10 VSSQ10 L2 C8570 1 1 C8571 1 C8572 1 C8573 1 C8574 1 C8575 1 C8576 J4 VDDQ10 VSSQ10 L2
10UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10UF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
20% 10% 10% 10% 10% 10% 10% J9 VDDQ11 VSSQ11 L11 20% 10% 10% 10% 10% 10% 10% J9 VDDQ11 VSSQ11 L11
6.3V 2 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V 6.3V 2 2 16V 2 16V 2 16V 2 16V 2 16V 2 16V
X5R X5R X5R X5R X5R X5R X5R N1 VDDQ12 VSSQ12 P1 X5R X5R X5R X5R X5R X5R X5R N1 VDDQ12 VSSQ12 P1
603 402 402 402 402 402 402 603 402 402 402 402 402 402
79 32 8 GPU_FB_B_VREF_DIV N12 VDDQ15 VSSQ15 P12 79 32 8 GPU_FB_B_VREF_DIV N12 VDDQ15 VSSQ15 P12
R1 VDDQ16 VSSQ16 T1 R1 VDDQ16 VSSQ16 T1
1
R8530 R4 VDDQ17 VSSQ17 T4
R85801 R4 VDDQ17 VSSQ17 T4
549
1% R85331 R9 VDDQ18 VSSQ18 T9 549
1% R85831 R9 VDDQ18 VSSQ18 T9
1/16W 549 R12 VDDQ19 VSSQ19 T12 1/16W 549 R12 VDDQ19 VSSQ19 T12
MF-LF 1% V1 MF-LF 1% V1
402 2 1/16W VDDQ20 402 2 1/16W VDDQ20
MF-LF V12 MF-LF V12
402 2 VDDQ21 402 2 VDDQ21
FB_B0_VREF H1 VREF0 FB_B1_VREF H1 VREF0

FB_B2_VREF H12 VREF1 FB_B3_VREF H12 VREF1
C C8531 R85341 C8532 C8581 R85841 C8582
C
R85311 R85321 1
0.01uF
R85351 1
0.01uF
R85811 R85821 1
0.01uF
R85851 1
0.01uF
1.33K 931 10% 1.33K 931 10% 1.33K 931 10% 1.33K 931 10%
1% 1% 1% 1% 1% 1% 1% 1%
1/16W 1/16W 2 16V
CERM 1/16W 1/16W 2 16V
CERM 1/16W 1/16W 16V
2 CERM 1/16W 1/16W 16V
2 CERM
MF-LF MF-LF 402 MF-LF MF-LF 402 MF-LF MF-LF 402 MF-LF MF-LF 402
402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2
FB_B2_VREF_UNTERM_L FB_B3_VREF_UNTERM_L
FB_B0_VREF_UNTERM_L FB_B1_VREF_UNTERM_L
FB_B_CLK0_TERM FB_B_CLK1_TERM
VOLTAGE=0.9V D 6 D 3 VOLTAGE=0.9V D 6 D 3
VRAM4 VRAM4 Q8500 Q8500 VRAM4 VRAM4 Q8550 Q8550
R8540 1
R8542 1
R8544 1
R8546 1 C8546 1 SSM6N15FEAPE SSM6N15FEAPE R8590 1
R8592 1
R8594 1
R8596 1 C8596 1 SSM6N15FEAPE SSM6N15FEAPE
SOT563 SOT563 SOT563 SOT563
1K 121 121 243 0.01UF 1K 121 121 243 0.01UF
5% 1% 1% 1% 10% 79 78 77 FB_VREF_UNTERM 5% 1% 1% 1% 10% 79 78 77 FB_VREF_UNTERM
1/16W 1/16W 1/16W 1/16W 16V IN 16V IN
MF-LF MF-LF MF-LF MF-LF CERM 2 81 80 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF CERM 2 81 80
402 2 402 2 402 2 402 2 402 2 G 5 G 402 2 402 2 402 2 402 2 402 2 G 5 G
S 1 S 4 S 1 S 4
VRAM4 VRAM4 VRAM4 VRAM4
1 1 1 1 1 1
R8543 R8545 R8547 R8593 R8595 R8597
121 121 243 OMIT 121 121 243 OMIT
1% 1% 1% 1% 1% 1%
1/16W 1/16W 1/16W CRITICAL 1/16W 1/16W 1/16W CRITICAL
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402 2 402 2 402
98 79 77 IN FB_B_MA<0> K9 A0 U8500 DM0 E3 FB_B_DQM_L<1> IN 77 98 98 79 77 IN FB_B_MA<0> K9 A0 U8550 DM0 E3 FB_B_DQM_L<5> IN 77 98
98 79 77 IN FB_B_MA<1> H11 A1 BGA DM1 E10 FB_B_DQM_L<2> IN 77 98 98 79 77 IN FB_B_MA<1> H11 A1 BGA DM1 E10 FB_B_DQM_L<7> IN 77 98
98 77 IN FB_B_LMA<2> K10 A2 (1 OF 2) DM2 N10 FB_B_DQM_L<3> IN 77 98 98 77 IN FB_B_UMA<2> K10 A2 (1 OF 2) DM2 N10 FB_B_DQM_L<4> IN 77 98
32MX32-900MHZ-MFH
K4J10324QD-HC11
32MX32-900MHZ-MFH
K4J10324QD-HC11
98 77 IN FB_B_LMA<3> M9 A3 DM3 N3 FB_B_DQM_L<0> IN 77 98 98 77 IN FB_B_UMA<3> M9 A3 DM3 N3 FB_B_DQM_L<6> IN 77 98
MFHIGH
MFHIGH
98 77 IN FB_B_LMA<4> K4 A4 98 77 IN FB_B_UMA<4> K4 A4
DQ0 B2 FB_B_DQ<15> BI 77 98 DQ0 B2 FB_B_DQ<45> BI 77 98
98 77 IN FB_B_LMA<5> H2 A5 98 77 IN FB_B_UMA<5> H2 A5
DQ1 B3 FB_B_DQ<9> 77 98 DQ1 B3 FB_B_DQ<46> 77 98
B 98 79 77
98 79 77
IN
IN
FB_B_MA<6>
FB_B_MA<7>
K3
L4
A6
A7
DQ2 C2 FB_B_DQ<14>
BI
BI 77 98
98 79 77
98 79 77
IN
IN
FB_B_MA<6>
FB_B_MA<7>
K3
L4
A6
A7
DQ2 C2 FB_B_DQ<47>
BI
BI 77 98 B
DQ3 C3 FB_B_DQ<11> BI 77 98 DQ3 C3 FB_B_DQ<43> BI 77 98
98 79 77 IN FB_B_MA<8> K2 A8/AP 98 79 77 IN FB_B_MA<8> K2 A8/AP
DQ4 E2 FB_B_DQ<13> BI 77 98 DQ4 E2 FB_B_DQ<42> BI 77 98
98 79 77 IN FB_B_MA<9> M4 A9 98 79 77 IN FB_B_MA<9> M4 A9
DQ5 F3 FB_B_DQ<12> BI 77 98 DQ5 F3 FB_B_DQ<40> BI 77 98
98 79 77 IN FB_B_MA<10> K11 A10 98 79 77 IN FB_B_MA<10> K11 A10
DQ6 F2 FB_B_DQ<10> BI 77 98 DQ6 F2 FB_B_DQ<41> BI 77 98
98 79 77 IN FB_B_MA<11> L9 A11 98 79 77 IN FB_B_MA<11> L9 A11
DQ7 G3 FB_B_DQ<8> BI 77 98 DQ7 G3 FB_B_DQ<44> BI 77 98
98 77 IN FB_B_LCKE H9 CKE 98 77 IN FB_B_UCKE H9 CKE
98 79 77 IN FB_B_MA<12> J3 A12/CS1* 98 79 77 IN FB_B_MA<12> J3 A12/CS1*
98 77 IN FB_B_CLK_P<0> J11 CK DQ10 C11 FB_B_DQ<21> BI 77 98 98 77 IN FB_B_CLK_P<1> J11 CK DQ10 C11 FB_B_DQ<60> BI 77 98
98 77 IN FB_B_CLK_N<0> J10 CK* DQ11 C10 FB_B_DQ<17> BI 77 98 98 77 IN FB_B_CLK_N<1> J10 CK* DQ11 C10 FB_B_DQ<61> BI 77 98
98 77 IN FB_B_LCS0_L F4 CS0* DQ12 E11 FB_B_DQ<22> BI 77 98 77 IN FB_B_UCS0_L F4 CS0* DQ12 E11 FB_B_DQ<62> BI 77 98
MFHIGH
MFHIGH
98 79 77 IN FB_B_WE_L H4 WE* DQ13 F10 FB_B_DQ<18> BI 77 98 98 79 77 IN FB_B_WE_L H4 WE* DQ13 F10 FB_B_DQ<57> BI 77 98
77 IN FB_B_LCAS_L F9 CAS* DQ14 F11 FB_B_DQ<23> BI 77 98 77 IN FB_B_UCAS_L F9 CAS* DQ14 F11 FB_B_DQ<63> BI 77 98
98 79 77 IN FB_B_RAS_L H10 RAS* DQ15 G10 FB_B_DQ<20> BI 77 98 98 79 77 IN FB_B_RAS_L H10 RAS* DQ15 G10 FB_B_DQ<58> BI 77 98
FB_B0_ZQ A4 ZQ DQ16 M11 FB_B_DQ<29> BI 77 98 FB_B1_ZQ A4 ZQ DQ16 M11 FB_B_DQ<36> BI 77 98
FB_B0_MF A9 MF DQ17 L10 FB_B_DQ<27> BI 77 98 FB_B1_MF A9 MF DQ17 L10 FB_B_DQ<38> BI 77 98
FB_B0_SEN V4 SEN DQ18 N11 FB_B_DQ<24> BI 77 98 FB_B1_SEN V4 SEN DQ18 N11 FB_B_DQ<37> BI 77 98
98 79 77 IN FB_B_DRAM_RST V9 RESET DQ19 M10 FB_B_DQ<25> BI 77 98 98 79 77 IN FB_B_DRAM_RST V9 RESET DQ19 M10 FB_B_DQ<39> BI 77 98
DQ20 R11 FB_B_DQ<30> BI 77 98 DQ20 R11 FB_B_DQ<35> BI 77 98

98 77 OUT FB_B_RDQS<1> D3 RDQS0 98 77 OUT FB_B_RDQS<5> D3 RDQS0
DQ21 R10 FB_B_DQ<28> BI 77 98 DQ21 R10 FB_B_DQ<34> BI 77 98
98 77 OUT FB_B_RDQS<2> D10 RDQS1 98 77 OUT FB_B_RDQS<7> D10 RDQS1
DQ22 T11 FB_B_DQ<31> BI 77 98 DQ22 T11 FB_B_DQ<32> BI 77 98
98 77 OUT FB_B_RDQS<3> P10 RDQS2 98 77 OUT FB_B_RDQS<4> P10 RDQS2
DQ23 T10 FB_B_DQ<26> BI 77 98 DQ23 T10 FB_B_DQ<33> BI 77 98
98 77 OUT FB_B_RDQS<0> P3 RDQS3 98 77 OUT FB_B_RDQS<6> P3 RDQS3
DQ24 M2 FB_B_DQ<4> BI 77 98 DQ24 M2 FB_B_DQ<48> BI 77 98
98 77 IN FB_B_WDQS<1> D2 WDQS0 DQ25 L3 FB_B_DQ<3> BI 77 98 98 77 IN FB_B_WDQS<5> D2 WDQS0 DQ25 L3 FB_B_DQ<50> BI 77 98
98 77 IN FB_B_WDQS<2> D11 WDQS1 DQ26 N2 FB_B_DQ<0> BI 77 98 98 77 IN FB_B_WDQS<7> D11 WDQS1 DQ26 N2 FB_B_DQ<54> BI 77 98
FB_B_WDQS<3> P11 M3 FB_B_DQ<2> FB_B_WDQS<4> P11 M3 FB_B_DQ<49>

A 98 77
98 77
IN
IN FB_B_WDQS<0> P2
WDQS2
WDQS3
DQ27
DQ28 R2 FB_B_DQ<1>
BI
BI
77 98
77 98
98 77
98 77
IN
IN FB_B_WDQS<6> P2
WDQS2
WDQS3
DQ27
DQ28 R2 FB_B_DQ<51>
BI
BI
77 98
77 98 SYNC_MASTER=GT216 SYNC_DATE=03/26/2009 A
DQ29 R3 FB_B_DQ<6> BI 77 98 DQ29 R3 FB_B_DQ<55> BI
PAGE TITLE
FB_B_BA<0> FB_B_BA<0>
G9 BA0 G9 BA0
GDDR3 Frame Buffer B (Top)
MFHIGH
MFHIGH
98 79 77 IN 98 79 77 IN
DQ30 T2 FB_B_DQ<7> BI 77 98 DQ30 T2 FB_B_DQ<52> BI
98 79 77 IN FB_B_BA<1> G4 BA1 98 79 77 IN FB_B_BA<1> G4 BA1
DQ31 T3 FB_B_DQ<5> BI 77 98 DQ31 T3 FB_B_DQ<53> BI 77 98 DRAWING NUMBER SIZE
FB_B_BA<2> H3 BA2 FB_B_BA<2> H3 BA2
98 79 77 IN 98 79 77 IN
Apple Inc. D
J2 RFU J2 RFU REVISION
NC NC R
R85481 1
R8549 R85981 1
R8599
243 100 1% 5%
1% 5% 1/16W 1/16W THE INFORMATION CONTAINED HEREIN IS THE
1/16W 1/16W MF-LF MF-LF PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
MF-LF MF-LF 402 2 2 402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 2 2 402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
85 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes 110mA OMIT
- =PP3V3_GPU_VDD33 U8000
- =PP3V3_GPI_MIO
NV-GT216
BGA
- =PP1V2_GPU_PLLVDD (6 OF 9)
- =PP1V2_GPU_H_PLLVDD 85 83 82 81 80 75 73 7 6 PP3V3_S0GPU J9 GPIO0 K1 GPU_VCORE_VID3 BI 81 83
- =PP1V2_GPU_VID_PLLVDD J10 GPIO1 K2 DP_EG_HPD BI 81 85
J11 GPIO2 K3 GPU_VCORE_VID4

Signal aliases required by this page: 1 C8694 1 C8696 1 C8698 J12
VDD33
GPIO3 H3 EG_LCD_PWR_EN
BI 81 83
(NONE) 0.1UF 1UF 4.7UF BI 81 88

20% 10% 20% J13 GPIO4 H2 EG_BKLT_EN 81 88
2 10V
CERM
6.3V
2 X5R 6.3V
2 X5R-CERM1
BI
BOM options provided by this page: GPIO5 H1 GPU_VCORE_VID0 81 83
D (NONE)
402 402 402
GPIO6 H4 GPU_VCORE_VID1
BI
BI 81 83 D
GPIO7 H5 GPU_VCORE_VID2 BI 81 83
GPIO8 H6 SMC_GFX_OVERTEMP_R_L
BI 81
GPIO9 J7 TP_GPU_GSTATE<0> BI 6 81
GPIO10 K4 FB_VREF_UNTERM BI 77 78 79 81
GPIO11 K5 GPU_GPIO_11 BI 81
GPIO12 H7 SMC_GFX_THROTTLE_R_L
BI 81
GPIO13 J4 FBVDD_ALTVO BI 81 87
GPIO14 J6 NC_GPU_GPIO_14 BI 81
GPIO15 L1 NC_GPU_GPIO_15 BI 81
81 NC_GPU_ROM_CS_L C3 ROM_CS* GPIO16 L2 GPU_GPIO_16 BI 81
81 GPU_ROM_SCLK D4 ROM_SCLK GPIO17 L4 NC_GPU_GPIO_17 BI 81
81 GPU_ROM_SI D3 ROM_SI GPIO18 M4 NC_GPU_GPIO_18 BI 81
81 GPU_ROM_SO C4 ROM_SO GPIO19 L7 NC_GPU_GPIO_19 BI 81
GPIO20 L5 NC_GPU_GPIO_20 BI 81
1 1 NC_GPU_GPIO_21
R8696 R8697 GPIO21 K6 BI 81
40.2K 40.2K GPIO22 L6 NC_GPU_GPIO_22 BI 81

1% 1%
1/16W 1/16W GPIO23 M6 NC_GPU_GPIO_23 BI 81
MF-LF MF-LF
2 402 2 402 GPU_STRAP_REF_3V3_PDN9 MULTI_STRAP_REF0_GND
GPU_STRAP_REF_MIOB_PD
M9 MULTI_STRAP_REF1_GND
85 83 82 81 80 75 73 7 6 PP3V3_S0GPU
P9 MIOA_VDDQ_1
85 83 82 81 80 75 73 7 6 PP3V3_S0GPU
R9 MIOA_VDDQ_2
C8610 1 C8611 1 T9 MIOA_VDDQ_3
1UF 1UF U9 MIOA_VDDQ_4
R86201 1
R8621 10%
6.3V 2
10%
6.3V 2
C 49.9
1%
1/16W
49.9
1%
1/16W
CERM
402
CERM
402 AA9 MIOB_VDDQ_1
C
MF-LF MF-LF AB9 MIOB_VDDQ_2
402 2 2 402 R86161 1
R8618 W9 MIOB_VDDQ_3 JTAG_TCK AP14 TP_GPU_JTAG_TCK IN 81
10K 10K
GPU_MIOA_PD_VDDQ 80 5% 5% Y9 MIOB_VDDQ_4 JTAG_TDI AN14 TP_GPU_JTAG_TDI IN 81
1/16W 1/16W
GPU_MIOB_PD_VDDQ 80 MF-LF MF-LF JTAG_TDO AN16 TP_GPU_JTAG_TDO OUT 81
402 2 2 402 GPU_TESTMODE_PD AP35 TESTMODE
JTAG_TMS AR14 TP_GPU_JTAG_TMS IN 81
GPU_MIOA_PU_GND 80
GPU_MIOA_VREF N5 MIOA_VREF JTAG_TRST* AP16 TP_GPU_JTAG_TRST_L IN 81
GPU_MIOB_PU_GND 80
GPU_MIOB_VREF AF1 MIOB_VREF
MIOA_CLKIN N4 NC_GPU_MIOA_CLKIN IN 81
R86221 1
R8623 R86171 1
1
C8617 R8619 1 GPU_MIOA_PD_VDDQ MIOA_CLKOUT R4 NC_GPU_MIOA_CLKOUTPBI 81
49.9
1%
49.9
1%
10K
5% 0.1uF 10K
5%
1 C8619 R8660
10K
80
GPU_MIOA_PU_GND
U5
T5
MIOA_CAL_PD_VDDQ
MIOA_CAL_PU_GND
MIOA_CLKOUT* T4 NC_GPU_MIOA_CLKOUTNBI 81
1/16W 1/16W 1/16W 10% 1/16W 0.1uF 5%

80
MIOA_CTL3 P5 NC_GPU_MIOA_CTL3
2 16V
BI 81
MF-LF MF-LF MF-LF MF-LF 10% 1/16W
402 2 X5R 2 16V N2 TP_GPU_MIOA_DE
2 402 402 2 402 2 402 X5R MF-LF
GPU_MIOB_PD_VDDQ AA7 MIOB_CAL_PD_VDDQ
MIOA_DE BI 6 81
402 2 402 80
MIOA_D0 N1 TP_GPU_MIOA_D<0> 6 81
GPU_MIOB_PU_GND BI
80 AA6 MIOB_CAL_PU_GND
MIOA_D1 P4 TP_GPU_MIOA_D<1> BI 6 81
AF9 SP_PLLVDD MIOA_D5 T3 TP_GPU_MIOA_D<5> BI 6 81
65mA MIOA_D6 T2 TP_GPU_MIOA_D<6> BI 6 81

AE9 PLLVDD
MIOA_D7 T1 TP_GPU_MIOA_D<7> BI 6 81
AD9 VID_PLLVDD MIOA_D8 U4 TP_GPU_MIOA_D<8> BI 6 81
MIOA_D9 U1 TP_GPU_MIOA_D<9> BI 6 81
MIOA_D10 U2 GPU_MIOA_D<10> BI 81
MIOA_D11 U3 GPU_MIOA_D<11> BI 81
MIOA_D12 R6 GPU_MIOA_D<12> BI 81
B MIOA_D13
MIOA_D14
T6
N6
GPU_MIOA_D<13>
GPU_MIOA_D<14>
BI 81
B
L8635 MIOA_HSYNC N3
BI
NC_GPU_MIOA_HSYNC BI
81
82 80 77 75 51 7 6 PP1V05_S0GPU 100NH-700MA-0.14OHM 98 81 27 GPU_CLK27M B1 XTAL_IN

81
IN NC_GPU_MIOA_VSYNC BI
25mA MIOA_VSYNC L3 81
1 2 PP1V05_GPU_H_PLLVDD_F 8 OUT NC_GPU_XTALOUT B2 XTAL_OUT
0603 MIN_NECK_WIDTH=0.2 mm MIOB_CLKIN AE1 NC_GPU_MIOB_CLKIN IN 81
VOLTAGE=1.05V
C8637 1 C8635 1 1 C8636 MIOB_CLKOUT V4 NC_GPU_MIOB_CLKOUTPBI 81
4.7UF 4.7UF 1UF 81 OUT GPU_XTALOUTBUFF D1 XTAL_OUTBUFF MIOB_CLKOUT* W4 NC_GPU_MIOB_CLKOUTNBI 81
20% 20% 10%
6.3V 6.3V 6.3V W3 NC_GPU_MIOB_CTL3
CERM 2 CERM 2 2 X5R
98 81 GPU_CLK27M_SS D2 XTAL_SSIN
MIOB_CTL3 BI 81
603 603 402 IN NC_GPU_MIOB_DE
MIOB_DE Y5 BI 81
MIOB_D0 Y1 NC_GPU_MIOB_D<0> BI 81
L8640 MIOB_D1 Y2 NC_GPU_MIOB_D<1> BI 81
82 80 77 75 51 7 6 PP1V05_S0GPU 100NH-700MA-0.14OHM MIOB_D2 Y3 NC_GPU_MIOB_D<2> 81

BI
50mA
1 2 PP1V05_GPU_VID_PLLVDD_F MIOB_D3 AB3 NC_GPU_MIOB_D<3> BI 81
0603 MIN_NECK_WIDTH=0.2 mm MIOB_D4 AB2 NC_GPU_MIOB_D<4> BI 81
VOLTAGE=1.05V
C8643 1 C8640 1 1 C8641 1 C8631 MIOB_D5 AB1 NC_GPU_MIOB_D<5> BI 81
4.7UF 4.7UF 1UF 0.1uF MIOB_D6 AC4 NC_GPU_MIOB_D<6> BI 81
20% 20% 10% 10%
6.3V 2 6.3V 2 6.3V
2 X5R 2 16V MIOB_D7 AC1 NC_GPU_MIOB_D<7>
CERM CERM X5R BI 81
603 603 402 402 MIOB_D8 AC2 NC_GPU_MIOB_D<8> 81
BI
MIOB_D9 AC3 NC_GPU_MIOB_D<9> BI 81
MIOB_D10 AE3 NC_GPU_MIOB_D<10> BI 81
MIOB_D11 AE2 NC_GPU_MIOB_D<11> BI 81
MIOB_D12 U6 NC_GPU_MIOB_D<12> BI 81
MIOB_D13 W6 NC_GPU_MIOB_D<13> BI 81
MIOB_D14 Y6 NC_GPU_MIOB_D<14> BI 81
81 BI GPU_STRAP<0> W5 STRAP0
GPU_STRAP<1> W7
A 81
81
BI
BI GPU_STRAP<2> V7
STRAP1
STRAP2 SYNC_MASTER=K18_MLB SYNC_DATE=06/29/2009 A
MIOB_HSYNC W1 NC_GPU_MIOB_HSYNC BI 81
PAGE TITLE
MIOB_VSYNC W2 NC_GPU_MIOB_VSYNC BI 81 NV GT216 GPIO/MIO/MISC

DRAWING NUMBER SIZE
THERMDP B5 GPU_TDIODE_P
THERMDN B4 GPU_TDIODE_N
IN 52 81 99
52 81 99 Apple Inc. D
OUT
REVISION
R

86 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Renamed signals Unused signals
Native Func Native Func 81 80 TP_GPU_JTAG_TCK TP_GPU_JTAG_TCK 80 81
GPIOs GPIOs MAKE_BASE=TRUE
GP HPDE 81 80 TP_GPU_JTAG_TDI TP_GPU_JTAG_TDI 80 81
83
80 GPU_VCORE_VID3 GPU_VCORE_VID3 OUT 80 81 83 81 80 NC_GPU_GPIO_15 NC_GPU_GPIO_15 80 81 98 81 80 27 GPU_CLK27M GPU_CLK27M 27 80 81 98 MAKE_BASE=TRUE
81 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE
HPDC DVI_MODE0 81 80 TP_GPU_JTAG_TDO TP_GPU_JTAG_TDO 80 81
85
80 DP_EG_HPD DP_EG_HPD IN 80 81 85 80 GPU_GPIO_16 EG_DP_CA_DET 81 98 81 80 GPU_CLK27M_SS GPU_CLK27M_SS 80 81 98 MAKE_BASE=TRUE
81 MAKE_BASE=TRUE MAKE_BASE=TRUE
LCD0_BL_PWM HDMI_DETECT0 81 80 TP_GPU_JTAG_TMS TP_GPU_JTAG_TMS 80 81
83
80 GPU_VCORE_VID4 GPU_VCORE_VID4 OUT 80 81 83 81 80 NC_GPU_GPIO_17 NC_GPU_GPIO_17 80 81 99 81 80 52 GPU_TDIODE_P GPU_TDIODE_P 52 80 81 99 MAKE_BASE=TRUE
LCD0_VDD DVI_MODE1 81 80 TP_GPU_JTAG_TRST_L TP_GPU_JTAG_TRST_L 80 81
88
80 EG_LCD_PWR_EN EG_LCD_PWR_EN 80 81 88 81 80 NC_GPU_GPIO_18 NC_GPU_GPIO_18 80 81 99 81 80 52 GPU_TDIODE_N GPU_TDIODE_N 52 80 81 99 MAKE_BASE=TRUE
LCD0_BL_EN HDMI_DETECT1
88
80 EG_BKLT_EN EG_BKLT_EN 80 81 88 81 80 NC_GPU_GPIO_19 NC_GPU_GPIO_19 80 81
81 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
VID0 HPDD
83
80 GPU_VCORE_VID0 GPU_VCORE_VID0 80 81 83 81 80 NC_GPU_GPIO_20 NC_GPU_GPIO_20 80 81 85 82 81 LVDS_EG_DDC_CLK LVDS_EG_DDC_CLK 81 82 85 NC_FBA_MA<13> NC_FBA_MA<13> 77 81
D
81
83
80 GPU_VCORE_VID1 VID1
MAKE_BASE=TRUE
GPU_VCORE_VID1
OUT
OUT 80 81 83 81 80 NC_GPU_GPIO_21 HPDF

NC_GPU_GPIO_21 80 81 85 82 81
MAKE_BASE=TRUE
LVDS_EG_DDC_DATA LVDS_EG_DDC_DATA 81 82 85
MAKE_BASE=TRUE
NC_FBB_MA<13>
NO_TEST=TRUE
NC_FBB_MA<13> 77 81
D
81 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
VID2/MEM_VID SWAPRDY_A
83
80 GPU_VCORE_VID2 GPU_VCORE_VID2 OUT 80 81 83 81 80 NC_GPU_GPIO_22 NC_GPU_GPIO_22 80 81 85 82 81 DP_EG_DDC_CLK DP_EG_DDC_CLK 81 82 85
GP
81 80 NC_GPU_GPIO_23 NC_GPU_GPIO_23 80 81 85 82 81 DP_EG_DDC_DATA DP_EG_DDC_DATA 81 82 85
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE
THERM
80 SMC_GFX_OVERTEMP_R_L SMC_GFX_OVERTEMP_R_L 80 81
81 MAKE_BASE=TRUE Unused I2C Buses
FAN_PWM
81 80 6 TP_GPU_GSTATE<0> TP_GPU_GSTATE<0> 6 80 81 81 77 NC_FB_B_UCS1_L NC_FB_B_UCS1_L 77 81
81
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
MEM_VREF
79
77 FB_VREF_UNTERM FB_VREF_UNTERM 77 78 79 80 81 82 81 NC_GPU_I2CC_SCL NC_GPU_I2CC_SCL 81 82
78
80
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
SLI_SYNC
80 GPU_GPIO_11 TP_GPU_GSTATE<1> OUT 6 82 81 NC_GPU_I2CC_SDA NC_GPU_I2CC_SDA 81 82 77 NC_FB_B_LCS1_L NC_FB_B_LCS1_L 77 81
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE 81 MAKE_BASE=TRUE NO_TEST=TRUE
AC_DET
80 SMC_GFX_THROTTLE_R_L SMC_GFX_THROTTLE_R_L OUT 80 81 81 80 NC_GPU_ROM_CS_L NC_GPU_ROM_CS_L 80 81
PWR_CTL0
87
80 FBVDD_ALTVO FBVDD_ALTVO OUT 80 81 87 81 77 NC_FB_A_UCS1_L NC_FB_A_UCS1_L 77 81
PWR_CTL1
80 NC_GPU_GPIO_14 NC_GPU_GPIO_14 80 81 81 77 NC_FB_A_LCS1_L NC_FB_A_LCS1_L 77 81
81 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
Config Straps
Physical 82 81 NC_GPU_I2CH_SCL NC_GPU_I2CH_SCL 81 82
Strapping Pin Strapping Bit 3 Strapping Bit 2 Strapping Bit 1 Strapping Bit 0
82 81 NC_GPU_I2CH_SDA NC_GPU_I2CH_SDA 81 82 81 6 TP_LVDS_EG_B_CLK_P TP_LVDS_EG_B_CLK_P 6 81 82
MAKE_BASE=TRUE NO_TEST=TRUE 82 MAKE_BASE=TRUE
85 83 82 81 80 75 73 7 6 PP3V3_S0GPU ROM_SO XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
82 81 6 TP_LVDS_EG_B_CLK_N TP_LVDS_EG_B_CLK_N 6 81 82
I2CS ties into SMBus connection page MAKE_BASE=TRUE
ROM_SCLK PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
OMIT NO STUFF NO STUFF (I2CS requires pullups even if not used) 98 82 81 NC_LVDS_EG_A_DATA_P<3> NC_LVDS_EG_A_DATA_P<3> 81 82 98
R87071 R8709 1
R87111 ROM_SI RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]
98 82 81 NC_LVDS_EG_A_DATA_N<3> NC_LVDS_EG_A_DATA_N<3> 81 82 98
2.0K 4.99K 15.0K MAKE_BASE=TRUE NO_TEST=TRUE
5% 1% 1% STRAP 2 PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
1/16W 1/16W 1/16W 98 82 81 NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_P<3> 81 82 98
MF-LF MF-LF MF-LF MAKE_BASE=TRUE NO_TEST=TRUE
402 2 402 2 402 2 STRAP 1 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
NC_LVDS_EG_B_DATA_N<3> NC_LVDS_EG_B_DATA_N<3>
C 80 GPU_ROM_SI STRAP 0 USER[3] USER[2] USER[1] USER[0]
98 82 81
81 82
98
C
OUT
80 IN GPU_ROM_SO
80 IN GPU_ROM_SCLK
G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.
Strap S1/S2 Bit[3:0] PU/PD Rval Strap S1/S2 Bit[3:0] PU/PD Rval PCI_DEVID[4:0]=0x14
OMIT
1 1 1 0 0000 PD 5k 8 1000 PU 5k 81 80 NC_GPU_MIOA_CLKOUTP NC_GPU_MIOA_CLKOUTP 80 81
R8708 R8710 R8712 1 0001 PD 10k 9 1001 PU 10k
45.3K 10K 15.0K 81 80 NC_GPU_MIOA_CLKOUTN NC_GPU_MIOA_CLKOUTN 80 81
1% 1% 1% 2 0010 PD 15k A 1010 PU 15k MAKE_BASE=TRUE NO_TEST=TRUE
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 3 0011 PD 20k B 1011 PU 20k 81 80 NC_GPU_MIOA_CTL3 NC_GPU_MIOA_CTL3 80 81
402 2 402 2 402 2 MAKE_BASE=TRUE NO_TEST=TRUE
4 0100 PD 25k C 1100 PU 25k
81 80 6 TP_GPU_MIOA_DE TP_GPU_MIOA_DE 6 80 81
5 0101 PD 30k D 1101 PU 30k MAKE_BASE=TRUE
6 0110 PD 35k E 1110 PU 35k 80 6 TP_GPU_MIOA_D<9..0> GPU_MIOA_D<9..0>
MAKE_BASE=TRUE
7 0111 PD 45k F 1111 PU 45k
81 80 NC_GPU_MIOA_CLKIN NC_GPU_MIOA_CLKIN 80 81
85 83 82 81 80 75 73 7 6 PP3V3_S0GPU
NC_GPU_MIOA_D<14..10> GPU_MIOA_D<14..10> 80
81 80 NC_GPU_MIOA_HSYNC NC_GPU_MIOA_HSYNC 80 81
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION MAKE_BASE=TRUE NO_TEST=TRUE
R87011 R87031 R87051 81 80 NC_GPU_MIOA_VSYNC NC_GPU_MIOA_VSYNC 80 81
45.3K 34.8K 10K 114S0353 1 RES,MTL FILM,1/16W,24.9K,1,0402,SMD,LF R8708 VRAM_512_SAMSUNG MAKE_BASE=TRUE NO_TEST=TRUE
1% 1% 1%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 114S0368 1 RES,MTL FILM,1/16W,35.7K,1,0402,SMD,LF R8708 VRAM_512_HYNIX 81 80 NC_GPU_MIOB_CLKIN NC_GPU_MIOB_CLKIN 80 81
81 80 NC_GPU_MIOB_CLKOUTP NC_GPU_MIOB_CLKOUTP 80 81
80 BI GPU_STRAP<0>
81 80 NC_GPU_MIOB_CLKOUTN NC_GPU_MIOB_CLKOUTN 80 81
80 BI GPU_STRAP<1>
81 80 NC_GPU_MIOB_CTL3 NC_GPU_MIOB_CTL3 80 81
80 GPU_STRAP<2>
B BI
NO STUFF NO STUFF NO STUFF

81 80 NC_GPU_MIOB_DE
NC_GPU_MIOB_DE 80 81
B
1 1 1 80 NC_GPU_MIOB_D<14..0> NO_TEST=TRUE GPU_MIOB_D<14..0>
R8702 R8704 R8706 MAKE_BASE=TRUE
2.0K 10K 24.9K 81 80 NC_GPU_MIOB_VSYNC NC_GPU_MIOB_VSYNC 80 81
5% 1% 1%
101 99 88 86 85 84
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 MAKE_BASE=TRUE NO_TEST=TRUE
1/16W 1/16W 1/16W 74 73 72 71 70 69 64 63 59 55 53 52 49
MF-LF MF-LF MF-LF 81 80 NC_GPU_MIOB_HSYNC NC_GPU_MIOB_HSYNC 80 81
85 83 82 81 80 75 73 7 6 PP3V3_S0GPU
R87501 R87511 R87521 R87531 Unused Clocks

2.2K 2.2K 4.7K 4.7K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 98 81 80 GPU_CLK27M_SS
402 2 402 2 402 402 85 83 82 81 80 75 73 7 6 PP3V3_S0GPU 80 GPU_XTALOUTBUFF
2 2 GPU_SS_INT
1 1
R8796 R8797 R87801 R87811
85 82 81 IN DP_EG_DDC_CLK 2.2K 2.2K 10K 10K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
85 82 81 BI DP_EG_DDC_DATA MF-LF MF-LF MF-LF MF-LF
402 402 402 2 402 2
85 83 82 81 80 75 73 7 6 PP3V3_S0GPU 2 2
85 18 8 IN DP_IG_DDC_CLK NO STUFF
DP_CA_DET_EG_FET SMC_GFX_OVERTEMP_R_L R8798 0 1 2 SMC_GFX_OVERTEMP_L
81 80 OUT 46
DP_CA_DET_EG_FET Q8742 85 18 8 BI DP_IG_DDC_DATA 5% 1/16W MF-LF 402
R87421 SOD-VESM-HF 81 80 SMC_GFX_THROTTLE_R_L R8799 0 1 2 SMC_GFX_THROTTLE_L
OUT 46
5% 1/16W MF-LF 402
100K SSM3K15FV
1
1% EG_LCD_PWR_EN OUT 80 81 88
1/16W
G
MF-LF
402 2 EG_BKLT_EN OUT 80 81 88
S
81 EG_DP_CA_DET DP_CA_DET IN 85 86 88 FBVDD_ALTVO OUT 80 81 87
A
3
A
2
FB_VREF_UNTERM OUT 77 78 79 80
81
SYNC_MASTER=K18_MLB SYNC_DATE=07/01/2009
PAGE TITLE
R8743
0
1
R8792 R8793R8794 R8795 1 1 NO STUFF
1 GT216 GPIOS & STRAPS
1 2 DP_CA_DET_EG IN 88 10K 10K 10K 10K DRAWING NUMBER SIZE
5% 5% 5% 5%
5%
1/16W
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF Apple Inc. D
MF-LF 402 402 402 402 REVISION
402 2 2 2 2 R
DP_CA_DET_EG_PLD
Isolation FETs for DP MUX inputs THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
87 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Sum of peak currents: 240mA
L8800
- =PP1V8_GPU_IFPX 73 7 6 PP1V8_GPUIFPX FERR-220-OHM-2.5A ?mA peak per diff pair
?mA peak for all pairs

- =PP3V3_GPU_IFPCD_IOVDD
1 2 PP1V8_GPU_IFPAB_IOVDD_F
0603
VOLTAGE=1.8V
C8800 1 C8801 1 C8803 1
OMIT
4.7UF 0.1UF 0.1UF
(NONE)
20% 20% 20%
6.3V 10V 10V
CERM 2
603
CERM 2
402
CERM 2
402
U8000
BOM options provided by this page: NV-GT216
(NONE) BGA
80 77 75 51 7 6 PP1V05_S0GPU Place at AG9 Place at AG10 (5 OF 9)
D
82
AG9 IFPA_IOVDD IFPA_TXC AM11 LVDS_EG_A_CLK_P OUT 88 98 D
AG10 IFPB_IOVDD IFPA_TXC* AM12 LVDS_EG_A_CLK_N OUT 88 98
GPU_IFPEF_RSET 82 L8805 82 PP1V05_GPU_IFPCD_IOVDD_F AJ8 IFPC_IOVDD

IFPA_TXD0 AM8 LVDS_EG_A_DATA_P<0>
180-OHM-1.5A AK8 IFPD_IOVDD OUT 88 98
GPU_IFPC_RSET 82 80mA peak IFPA_TXD0* AL8 LVDS_EG_A_DATA_N<0> OUT 88 98

1 2 PP1V05_GPU_IFPAB_PLLVDD_F 82 PP1V05_GPU_IFPEF_IOVDD_F AE7 IFPE_IOVDD
GPU_IFPAB_RSET 82 0603 MIN_LINE_WIDTH=0.3 mm IFPA_TXD1 AM10 LVDS_EG_A_DATA_P<1> OUT 88 98
MIN_NECK_WIDTH=0.2 mm AD7 IFPF_IOVDD
GPU_IFPD_RSET 82 VOLTAGE=1.05V IFPA_TXD1* AM9 LVDS_EG_A_DATA_N<1>
C8805 1 C8806 1 AK9 IFPAB_PLLVDD IFPA_TXD2 AK10 LVDS_EG_A_DATA_P<2>
OUT 88 98
4.7UF 1UF OUT 88 98

20% 10% 82 GPU_IFPAB_RSET AJ11 IFPAB_RSET IFPA_TXD2* AL10 LVDS_EG_A_DATA_N<2> 88 98
6.3V 2 6.3V 2 OUT
CERM CERM IFPA_TXD3 AK11 NC_LVDS_EG_A_DATA_P<3>OUT 81 98
603 402 82 PP3V3_GPU_IFPC_PLLVDD_F AJ9 IFPC_PLLVDD
1 1 1 1 NC_LVDS_EG_A_DATA_N<3>OUT
R8855 R8850 R8851 R8858 82 GPU_IFPC_RSET AK7 IFPC_RSET
IFPA_TXD3* AL11 81 98
1K 1K 1K 1K
1% 1% 1% 1% IFPB_TXC AP13 TP_LVDS_EG_B_CLK_P OUT 6 81
1/16W 1/16W 1/16W 1/16W 82 PP1V8_GPU_IFPEF_PLLVDD_F AJ6 IFPEF_PLLVDD
MF-LF MF-LF MF-LF MF-LF IFPB_TXC* AN13 TP_LVDS_EG_B_CLK_N OUT 6 81
2 402 2 402 2 402 2 402 82 GPU_IFPEF_RSET AL1 IFPEF_RSET
IFPB_TXD4 AN8 LVDS_EG_B_DATA_P<0> OUT 88 98
L8810 IFPB_TXD4* AP8 LVDS_EG_B_DATA_N<0> OUT 88 98

180-OHM-1.5A ?mA peak per diff pair
IFPB_TXD5 AP10 LVDS_EG_B_DATA_P<1> 88 98
OUT
?mA peak for all pairs
82 80 77 75 51 7 6 PP1V05_S0GPU 1 2 PP1V05_GPU_IFPCD_IOVDD_F 82 IFPB_TXD5* AN10 LVDS_EG_B_DATA_N<1> OUT 88 98
0603 MIN_NECK_WIDTH=0.1 mm IFPB_TXD6 AR11 LVDS_EG_B_DATA_P<2> OUT 88 98
VOLTAGE=1.05V
C8810 1 C8811 1 C8813 1 85 81 BI LVDS_EG_DDC_CLK G1 I2CA_SCL IFPB_TXD6* AR10 LVDS_EG_B_DATA_N<2> OUT 88 98
4.7UF 0.1UF 0.1UF 85 81 BI LVDS_EG_DDC_DATA G4 I2CA_SDA IFPB_TXD7 AN11 NC_LVDS_EG_B_DATA_P<3>OUT 81 98
20% 20% 20%
6.3V 2 10V 10V AP11 NC_LVDS_EG_B_DATA_N<3>OUT
CERM CERM 2 CERM 2 IFPB_TXD7* 81 98
603 402 402
IFPC_AUX_I2CW_SCL AP2 DP_EG_AUX_CH_P OUT 85 98
Place at AJ8 Place at AK8 IFPC_AUX_I2CW_SDA* AN3 DP_EG_AUX_CH_N OUT 85 98
81 BI NC_GPU_I2CC_SCL E3 I2CC_SCL
I2CS must be pulled up if not used IFPC_L0 AM7 DP_EG_ML_P<0> OUT 85 98
81 BI NC_GPU_I2CC_SDA E4 I2CC_SDA NO STUFF NO STUFF
IFPC_L0* AM6 DP_EG_ML_N<0>
L8815 I2CS addr fixed at 0x9E,0x9F OUT 85 98
R88611 1
C FERR-220-OHM-2.5A
160mA peak
IFPC_L1
IFPC_L1*
AL5
AM5
DP_EG_ML_P<1>
DP_EG_ML_N<1>
OUT 85 98
85 98
1K
5%
R8860
1K
5%
C
PP3V3_S0GPU 1 2 PP3V3_GPU_IFPC_PLLVDD_F OUT
85 83 81 80 75 73 7 6 82 1/16W 1/16W
0603 MIN_LINE_WIDTH=0.3 mm IFPC_L2 AM3 DP_EG_ML_P<2> OUT 85 98 MF-LF MF-LF
MIN_NECK_WIDTH=0.2 mm 402 2 2 402
VOLTAGE=3.3V 52 49 46 SMBUS_SMC_0_S5_SCL E2 I2CS_SCL IFPC_L2* AM4 DP_EG_ML_N<2> 85 98
C8815 1 C8816 1 BI
SMBUS_SMC_0_S5_SDA E1 I2CS_SDA IFPC_L3 AP1 DP_EG_ML_P<3>
OUT
4.7UF 1UF 52 49 46 BI OUT 85 98
20% 10% IFPC_L3* AR2 DP_EG_ML_N<3>
6.3V 2 6.3V 2 I2CS must be pulled up if not used. OUT 85 98
CERM CERM
603 402 I2CS addr fixed at 0x9E,0x9F IFPD_AUX_I2CX_SCL AP4NC
IFPD_AUX_I2CX_SDA* AN4NC
81 BI NC_GPU_I2CH_SDA F6 I2CH_SCL
IFPD_L0 AR8NC
81 BI NC_GPU_I2CH_SCL G6 I2CH_SDA
IFPD_L0* AR7NC
IFPD_L1 AP7NC
IFPD_L1* AN7NC
IFPD_L2 AN5NC
85 81 BI DP_EG_DDC_CLK G3 I2CB_SCL
PP1V05_GPU_IFPEF_IOVDD_F 82 IFPD_L2* AP5NC
MIN_LINE_WIDTH=0.4 mm 85 81 BI DP_EG_DDC_DATA G2 I2CB_SDA
MIN_NECK_WIDTH=0.1 mm IFPD_L3 AR5NC
VOLTAGE=1.05V
IFPD_L3* AR4NC
PP1V8_GPU_IFPEF_PLLVDD_F 82 IFPE_AUX_I2CY_SCL AE4NC

MIN_NECK_WIDTH=0.1 mm IFPE_AUX_I2CY_SDA* AD4NC
VOLTAGE=1.8V
Power inputs must be pulled down if not used
IFPE_L0 AH6NC
1 IFPE_L0* AH5NC
R8856 1R8857 IFPE_L1 AH4NC
10K 10K
5% 5% IFPE_L1* AG4NC
1/16W 1/16W
MF-LF MF-LF IFPE_L2 AF4NC
2 402 2 402 IFPE_L2* AF5NC
B IFPE_L3
IFPE_L3*
AE6NC
AE5NC
B
IFPF_AUX_I2CZ_SCL AF3NC
IFPF_AUX_I2CZ_SDA* AF2NC
IFPF_L0 AL2NC
IFPF_L0* AL3NC
IFPF_L1 AJ3NC
IFPF_L1* AJ2NC
IFPF_L2 AJ1NC
IFPF_L2* AH1NC
IFPF_L3 AH2NC
IFPF_L3* AH3NC
AJ12 DACA_VDD DACA_RED AM15

NC
DACA_GREEN AM14
NC
DACA_BLUE AL14
NC
AK12 DACA_VREF
NC DACA_HSYNC AM13
NC
AK13 DACA_RSET
NC DACA_VSYNC AL13
NC
GPU_DACA_VDD AG7 DACB_VDD DACB_RED AK4NC

GPU_DACB_VDD DACB_GREEN AL4NC
PP1V8_GPU_IFPD_PLLVDD DACB_BLUE AJ4NC
MIN_NECK_WIDTH=0.1 mm NCAK6 DACB_VREF
1 VOLTAGE=1.8V NCAH7 DACB_RSET CEC AB5NC
A R8852 1R8853 1R8854
10K
5%
10K
5%
10K
5% AC6 IFPD_PLLVDD
SYNC_MASTER=K18_MLB
PAGE TITLE
1/16W 1/16W 1/16W
MF-LF
2 402
MF-LF
2 402
MF-LF
2 402 NV GT216 VIDEO INTERFACES
DRAWING NUMBER SIZE
DACB_HSYNC AM1NC
Apple Inc. D
82 GPU_IFPD_RSET AB6 IFPD_RSET DACB_VSYNC AM2NC REVISION
R

88 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU VCore Regulator
103
51 47 45
31 7 6 PP5V_S3 R8911
44 43 33 1
73 68 55 1 2 PP5V_S5_GFXIMVP6_PVCC
5% MIN_NECK_WIDTH=0.2MM
1/16W VOLTAGE=5V
MF-LF
402
C8902 1 1 C8903
4.7UF 0.01uF 87 71 70 68 67 66 50 40 8 7 6 PPBUS_G3H
20% 10%
6.3V 2 16V
X5R-CERM 2 CERM CRITICAL CRITICAL
402 402
C8931 1 C8930 1 1 C8932 C8933 1 1 C8934
68UF 68UF 1UF 1UF 0.001UF
20% 20% 10% 10% 10%
R8904 16V 16V
POLY-TANT 2 POLY-TANT 2 2 25V
X5R
25V 2
X5R 2 50V
X7R
10
D
1
1%
2 PP5V_S5_GFXIMVP6_VDD
CASE-D2E-SM CASE-D2E-SM 603-1 603-1 402
D
1/16W VOLTAGE=5V
MF-LF
402 1 C8901
1uF
16
22
10%
2 10V
X5R
R89301 CRITICAL
402 VDD PVCC
1K Q8950
5% IRF6710
1/16W S1
R8905 CRITICAL
MF-LF
402 2 1
150K 1 D
2 GFXIMVP6_RBIAS 1 RBIAS U8900 VIN 14 GFXIMVP6_VIN 2
MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM 5
1% MIN_NECK_WIDTH=0.2MM QFN MIN_NECK_WIDTH=0.2MM
1/16W C8904
MF-LF ISL6263C UGATE 18 GFXIMVP6_UGATE 4 G 6
402 0.033UF MIN_LINE_WIDTH=0.6MM
2 1 MIN_NECK_WIDTH=0.2MM S
GFXIMVP6_SOFT 2 SOFT GATE_NODE=TRUE DIDT=TRUE 3
10% MIN_NECK_WIDTH=0.2MM BOOT 17 GFXIMVP6_BOOT
16V MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM CRITICAL
X5R
402 DIDT=TRUE C8956 1 R8940
GFXIMVP6_IMON 28 IMON 0.22UF CRITICAL Vout = 0.80V - 0.98V
51 OUT 10% 0.001
PM_ALL_GPU_PGOOD PGOOD
16V 2
X7R L8920 1%
1W
88 87 74 8 OUT 31
603 0.6UH-30A-1.5MOHM MF-1
85 83
80 75 73 7 6 PP3V3_S0GPU 83 GFXIMVP6_VID0 23 VID0 0612
82 81 PHASE 19 GFXIMVP6_PHASE 1 2 PPVCORE_GPU_REG_R 2 1 PPVCORE_GPU 6 7 50 76 83
83 GFXIMVP6_VID1 24 VID1 MIN_LINE_WIDTH=0.6MM MIN_LINE_WIDTH=0.6MM
R89071 1
R8910 83 GFXIMVP6_VID2 25 VID2
SWITCH_NODE=TRUE
MPL104-SM MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
4 3
C8966 1 CRITICAL 30A max output
10K 10K DIDT=TRUE 10UF
PPVCORE_GPU 5%
1/16W
5%
1/16W
83 GFXIMVP6_VID3 26 VID3 1 2 6 7
C8969 1 C8968 1 20% C8942 1 (L8920 limit)
83 76 50 7 6
MF-LF MF-LF GFXIMVP6_VID4 27 VID4 10UF 6.3V 2 330UF
402 2
83
D CRITICAL 0.001UF 20% X5R 20%
2 402 EG_RAIL3_EN 10% 6.3V 2 603
1
88 74 IN 29 VR_ON
LGATE 21 GFXIMVP6_LGATE Q8951 50V
X7R 2
X5R
603
2.0V
POLY-TANT 2 3
R8924 GFXIMVP6_AF_EN 30 AF_EN MIN_LINE_WIDTH=0.6MM IRF6795 D2T-SM2
100 GFXIMVP6_FDE 32 FDE
GATE_NODE=TRUE
5 G DIRECTFET-MX
402 1 C8965 CRITICAL
1% DIDT=TRUE S 1 C8967 10UF
20% 1
1/16W
MF-LF MIN_LINE_WIDTH=0.3MM 3 4
4.7UF 2 6.3V
X5R
C8943
10% 330UF
C PLACE_NEAR=U8900.8:7mm
402 2
99
GFXIMVP6_VSEN_P 8 VSEN
6.3V
2 X5R-CERM
603
603 20%
3 2 2.0V
POLY-TANT
C
R8920 99 GFXIMVP6_VSEN_N 9 RTN D2T-SM2
GPU_VDD_SENSE 1
20 2 MIN_LINE_WIDTH=0.3MM
75 MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.25V
5%
1/16W 1 C8920
1 C8923 C8921 1
MF-LF 0.001UF 0.001UF
402 0.001UF 10%
50V
10%
50V
10% 2 CERM GFXIMVP6_PHASE_VSUM
2 50V CERM 2 1 C8953 MIN_LINE_WIDTH=0.3MM
CERM 402 402
R8908 402 (GFXIMVP6_AGND) 680pF
10%
R89031 MIN_NECK_WIDTH=0.3MM
20 SIGNAL_MODEL=EMPTY 1K
75 GPU_GND_SENSE 1 2 2 50V
CERM 1%
MIN_NECK_WIDTH=0.20 mm GFXIMVP6_VW 4 VW 402 1/16W
MIN_LINE_WIDTH=0.25 mm 5% MIN_LINE_WIDTH=0.3MM MF-LF
VOLTAGE=0V 1/16W MIN_NECK_WIDTH=0.2MM 402 2
MF-LF 1
402 R8909 1 C8922
7.15K
1
PLACE_NEAR=U8900.9:7mm 0.001UF
1% 10%
R8925 C8950
1/16W
MF-LF 2 50V
X7R
100 402 2 402
1% 330PF
1/16W 2 1
MF-LF GFXIMVP6_COMP_RC GFXIMVP6_COMP 5 COMP
402 MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM VO 12 GFXIMVP6_VO
MIN_NECK_WIDTH=0.3MM 10% MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM
2
1 50V
R8950 CERM 1 C8952 R8900
150K
1%
402
10%
330PF OCSET 3 GFXIMVP6_OCSET 1
7.32K2 GPU VCore Setpoints
1/16W 50V MIN_LINE_WIDTH=0.3MM
MF-LF 2 CERM MIN_NECK_WIDTH=0.2MM 1%
1/16W VID4 VID3 VID2 VID1 VID0 Max Batt Balanced Max perf
2 402 402 MF-LF
Voltage
GFXIMVP6_VSUM 402
GFXIMVP6_FB 6 FB MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 1 0 1 0 1 0.74675V K17 -
MIN_NECK_WIDTH=0.2MM ISP 13 C8906 1
1 GFXIMVP6_DFB 330PF
1
R8951 R8953 ISN 11
MIN_LINE_WIDTH=0.3MM 5%
50V 2
1 0 0 1 0 0.82400V - K17 -
3.01K MIN_NECK_WIDTH=0.2MM COG
150 1% 402 0 1 1 1 1 0.90125V - - K17
1% 1/16W
B 1/16W
MF-LF
402 0.0068UF
C8951 2
MF-LF
402 R8902 2 1
R8901 Other VID states may not be valid..
B
2
GFXIMVP6_VDIFF_RC 1 2 GFXIMVP6_VDIFF 7
ICOMP 10 9.76K 9.09K (PPVCORE_GPU_REG)
VDIFF 1% 1%
MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM 1/16W 1/16W
25V
PGND VSS THRM_PAD
MF-LF
402 C8971 MF-LF
2 402
CERM
1
68PF
402 GFXIMVP6_DROOP 1 2
20
15
33
353S2289 5%
50V C8972 1
CERM 0.001UF
402-1 10%
50V
CERM 2
GND_GFXIMVP6_AGND 402
VOLTAGE=0V
XW8900
SM
85 83 82 81 80 75 73 7 6 PP3V3_S0GPU
1 2
R8986 PLACE_NEAR=U8900.33:2mm
K17 Default Vcore Setpoints
0 TABLE_BOMGROUP_HEAD
81 80 IN GPU_VCORE_VID0 2 1 BOM GROUP BOM OPTIONS

5% TABLE_BOMGROUP_ITEM
1/16W GPUVID_0P75V GPUVID4_1,GPUVID3_0,GPUVID2_1,GPUVID1_0,GPUVID0_1

MF-LF GPUVID0_1 GPUVID1_1 GPUVID2_1 GPUVID3_1 GPUVID4_1
402 TABLE_BOMGROUP_ITEM
R8990 R89871 R89841 R89821 R89951 R89911 GPUVID_0P82V GPUVID4_1,GPUVID3_0,GPUVID2_0,GPUVID1_1,GPUVID0_0

2.2K 2.2K 2.2K 2.2K 2.2K TABLE_BOMGROUP_ITEM
0 5% 5% 5% 5% 5% GPUVID_0P90V GPUVID4_0,GPUVID3_1,GPUVID2_1,GPUVID1_1,GPUVID0_1
81 80 IN GPU_VCORE_VID1 1 2 1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF
5% 402 2 402 2 402 2 402 2 402 2
1/16W
MF-LF GFXIMVP6_VID0 83
402
GFXIMVP6_VID1 83
R8993 GFXIMVP6_VID2 83
0 GFXIMVP6_VID3
A 81 80 IN GPU_VCORE_VID2 1
5%
2
GFXIMVP6_VID4
83
1/16W PAGE TITLE
MF-LF
402
GPUVID0_0 GPUVID1_0 GPUVID2_0 GPUVID3_0 GPUVID4_0
GPU (GT216) CORE SUPPLY
R8994 R89881 R89851 R89831 R89961 R89921
DRAWING NUMBER SIZE
81 80 GPU_VCORE_VID3 1
0 2 2.2K 2.2K 2.2K 2.2K 2.2K Apple Inc. D
IN
5% 5% 5% 5% 5% REVISION
5% 1/16W 1/16W 1/16W 1/16W 1/16W R
1/16W MF-LF MF-LF MF-LF MF-LF MF-LF
MF-LF 402 2 402 2 402 2 402 2 402 2
402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R8998 THE INFORMATION CONTAINED HEREIN IS THE

0 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
GPU_VCORE_VID4 1 2
81 80 IN
5%
89 OF 132
1/16W III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
MF-LF
402 IV ALL RIGHTS RESERVED 83 OF 103
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
88 IN LCD_PWR_EN
R90941
10K
5%
1/16W
MF-LF
402 2
LCD (LVDS) INTERFACE
CRITICAL
U9000
FPF1009
1 ON MFET-2X2 CRITICAL
L9000
99 86 74 73 72 58 51 50 49 35 31 7 6 PP3V3_S5 2 VIN_1 VOUT_1 4 PP3V3_SW_LCD_UF FERR-250-OHM
1 2
3 VIN_2 VOUT_2 5 VOLTAGE=3.3V
SM
GND THRM C9001 1 C9002 1
1 C9009 PAD 1 C9011 1 C9012 0.1UF 0.001UF

6 7 0.1UF 10UF 10% 10%
0.1UF 10% 20% 16V
2
50V
2
10%
16V 2 16V
X5R 2 6.3V
X5R
X5R
402
X7R
402
2 X5R 402 603
402 CRITICAL
J9000
20474-040E-11
F-RT-SM
41
101 99 88 86 85 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0
74 73 72 71 70 69 64 63 59 55 53 52 49 42
C 1
C
R9010 1
1
100K pull-ups are for R9011 6 PP3V3_SW_LCD 2
100K 100K MIN_LINE_WIDTH=0.5 mm
3
no-panel case (development). 5% 5% MIN_NECK_WIDTH=0.25 mm
1/16W 1/16W VOLTAGE=3.3V
Panel has 2K pull-ups MF-LF MF-LF
4
402 402
2 2
8 6 LVDS_CONN_BKL_SYNC 5
85 6 LVDS_DDC_CLK 6
85 6 LVDS_DDC_DATA 7
98 85 6 LVDS_CONN_A_DATA_N<0> 8
C9010 1
98 85 6 LVDS_CONN_A_DATA_P<0> 9
0.001UF 10
10%
50V
2 98 85 6 LVDS_CONN_A_DATA_N<1> 11
X7R
402
CRITICAL 13
L9010 14
90-OHM-100MA 98 85 6 LVDS_CONN_A_DATA_N<2>
DLP11S
SYM_VER-1
98 85 LVDS_CONN_A_CLK_N 4 3 16
98 6 LVDS_CONN_A_CLK_F_N 17
98 6 LVDS_CONN_A_CLK_F_P 18
98 85 LVDS_CONN_A_CLK_P 1 2
19
Place close to the connector 98 85 6 LVDS_CONN_B_DATA_N<0> 20

98 85 6 LVDS_CONN_B_DATA_P<0> 21
22
98 85 6 LVDS_CONN_B_DATA_N<1> 23
98 85 6 LVDS_CONN_B_DATA_P<1> 24
CRITICAL 25
L9011
B 90-OHM-100MA
DLP11S
SYM_VER-1
98 85 6
98 85 6
LVDS_CONN_B_DATA_N<2>
LVDS_CONN_B_DATA_P<2>
26
27
B
98 85 LVDS_CONN_B_CLK_N 4 3 28
LVDS_CONN_B_CLK_F_N
98 6 29
LVDS_CONN_B_CLK_F_P
98 6 30
98 85 LVDS_CONN_B_CLK_P 1 2
31
89 6 LED_RETURN_1
Place close to the connector 89 6 LED_RETURN_2 32
89 6 LED_RETURN_3 33
89 6 LED_RETURN_4 34
LED_RETURN_5 35
89 6
89 6 LED_RETURN_6 36 518S0651
37
NC
38
39
89 57 6 PPVOUT_S0_LCDBKLT 40
1 C9008 43
1000PF 44
10%
100V
2 X7R
603
PAGE TITLE
LVDS Display Connector

DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

90 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DisplayPort Mux
101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0
74 73 72 71 70 69 64 63 59 55 53 52 49
LVDS Transmitter Termination
A2
J4
1 C9320 1 C9321
0.1UF 0.1UF
93 8 DP_IG_ML_P<0> B4 DIN1_0+ VDD 20% 20%
IN
All emulated LVDS outputs require this termination 2 10V
CERM 2 10V
CERM
93 8 IN DP_IG_ML_N<0> A4 DIN1_0- 402 402
D PLACE_NEAR=U9600.A6:7mm
R9320
93 8 IN DP_IG_ML_P<1> B5 DIN1_1+ U9320
CBTL06141EE
D
93 8 IN DP_IG_ML_N<1> A5 DIN1_1-
357 BGA
98 88 IN LVDS_A_CLK_P 1 2 LVDS_CONN_A_CLK_P OUT 84 98
93 8 IN DP_IG_ML_P<2> B6 DIN1_2+ CRITICAL
1%
1/16W 93 8 IN DP_IG_ML_N<2> A6 DIN1_2-
MF-LF
402
93 8 IN DP_IG_ML_P<3> A8 DIN1_3+ DOUT_0+ B2 DP_ML_P<0> OUT 86 98
93 8 DP_IG_ML_N<3> A9 DIN1_3- DOUT_0- B1 DP_ML_N<0> 86 98

IN OUT
PLACE_NEAR=U9600.A7:7mm C9330 1 2 99 DP_IG_AUX_CH_C_P
R9322 93 18 8 BI DP_IG_AUX_CH_P 10% 16V X5R 402 H9 DAUX1+
357 0.1uF
LVDS_A_CLK_N 1 2 LVDS_CONN_A_CLK_N DP_IG_AUX_CH_N J9 DAUX1-
98 88 IN
1%
OUT 84 98 93 18 8 BI C9331 1 2 99 DP_IG_AUX_CH_C_N
10% 16V X5R 402
DOUT_1+ D2 DP_ML_P<1> OUT 86 98
1/16W 81 18 8 IN DP_IG_DDC_CLK 0.1uF H8 DDC_CLK1 DOUT_1- D1 DP_ML_N<1> OUT 86 98

MF-LF
402 R9325 81 18 8 BI DP_IG_DDC_DATA J8 DDC_DAT1
LVDS_A_DATA_P<0> 1
357 2 LVDS_CONN_A_DATA_P<0>
98 88 IN OUT 6 84 98
18 8 DP_IG_HPD J2 HPD_1
1% OUT E2 DP_ML_P<2>
PLACE_NEAR=U9600.A8:7mm DOUT_2+ OUT 86 98
1/16W
MF-LF DOUT_2- E1 DP_ML_N<2> 86 98
402 OUT
98 82 IN DP_EG_ML_P<0> B8 DIN2_0+
R93041 98 82 IN DP_EG_ML_N<0> B9 DIN2_0-
100K F2
PLACE_NEAR=U9600.B9:7mm R9327 5% DOUT_3+ DP_ML_P<3> OUT 86 98
1/16W 98 82 IN DP_EG_ML_P<1> D8 DIN2_1+
357 MF-LF D9 DOUT_3- F1 DP_ML_N<3> OUT 86 98
98 88 IN LVDS_A_DATA_N<0> 1 2 LVDS_CONN_A_DATA_N<0> OUT 6 84 98 402 2 98 82 IN DP_EG_ML_N<1> DIN2_1-
1%
1/16W 98 82 DP_EG_ML_P<2> E8 DIN2_2+
IN
R9330 MF-LF
402 98 82 IN DP_EG_ML_N<2> E9 DIN2_2- AUX+ H2 DP_AUX_CH_C_P BI 86 98
357
98 88 IN LVDS_A_DATA_P<1> 1 2 LVDS_CONN_A_DATA_P<1> OUT 6 84 98 AUX- H1 DP_AUX_CH_C_N BI 86 98
98 82 IN DP_EG_ML_P<3> F8 DIN2_3+
1%
PLACE_NEAR=U9600.A9:7mm 1/16W DP_EG_ML_N<3> F9 DIN2_3-
MF-LF
98 82 IN PLACE_NEAR=U9320.J1:3mm
402
DP_EG_AUX_CH_P
C9335 1 2 98 DP_EG_AUX_CH_C_P
H6
98 82 BI 10% 16V X5R 402 DAUX2+
0.1uF R9307
DP_EG_AUX_CH_N J6
C PLACE_NEAR=U9600.C10:7mm R9332
98 82
82 81
BI
DP_EG_DDC_CLK
C9336
0.1uF
1 2 98 DP_EG_AUX_CH_C_N
10% 16V X5R 402 H5
DAUX2-
DDC_CLK2
HPDIN J1 DP_HPD_R 1
1K 2 DP_HOTPLUG_DET
IN 85 86 88
C
IN
357 5%
98 88 IN LVDS_A_DATA_N<1> 1 2 LVDS_CONN_A_DATA_N<1> OUT 6 84 98 82 81 BI DP_EG_DDC_DATA J5 DDC_DAT2 1/16W
MF-LF
1% 402
1/16W 81 80 OUT DP_EG_HPD H3 HPD_2
MF-LF
402 R9335 LO=PORT1 LO=AUX_CH
357 HI=PORT2 HI=DDC
98 88 IN LVDS_A_DATA_P<2> 1 2 LVDS_CONN_A_DATA_P<2> OUT 6 84 98
R9305 1 88 IN DP_MUX_SEL_EG A1 GPU_SEL DDC_AUX_SEL C2 DP_CA_DET IN 81 86 88
1%
PLACE_NEAR=U9600.B10:7mm 1/16W
MF-LF
100K DP_MUX_XSD_L B7 G2
5% XSD* TST0
402 1/16W GND
MF-LF
84 81 74 73 72 71 70 69 64
37 34 30 28 27 26 25 8 7 6
63 59 55 53 52 49 48 47 42 40
PP3V3_S0 DPMUX_EN_HPD DPMUX_EN_HPD
402 2 101 99 88 86 85
R93011 1 C9301
B3
C8
G8
H4
H7
DPMUX_EN_S0&DPMUX_EN_PLD 1UF
PLACE_NEAR=U9600.A10:7mm R9337 10K
357 R93021 1%
1/16W
10%
6.3V
2 CERM-X5R
98 88 IN LVDS_A_DATA_N<2> 1 2 LVDS_CONN_A_DATA_N<2> OUT 6 84 98 10K MF-LF 402
1% 402 2
1% 1/16W
1/16W DPMUX_EN_PLD MF-LF
DP_HOTPLUG_DET
R9340 MF-LF
402
R9303
402 2 88 86 85 OUT
MAKE_BASE=TRUE
LVDS_B_CLK_P 357 LVDS_CONN_B_CLK_P
98 88 IN
1 2 OUT 84 98 0
88 IN DP_MUX_EN 1 2
1%
1/16W 5%
PLACE_NEAR=U9600.C8:7mm MF-LF 1/16W
402 MF-LF
402
PLACE_NEAR=U9600.C9:7mm R9342
LVDS_B_CLK_N 1
357 2 LVDS_CONN_B_CLK_N
98 88 IN OUT 84 98
1%
1/16W
MF-LF
402 R9345
LVDS_B_DATA_P<0> 357
98 88 1 2 LVDS_CONN_B_DATA_P<0> 6 84 98
B IN OUT
B
PLACE_NEAR=U9600.A2:7mm
1%
1/16W
MF-LF
402
LVDS DDC MUX
83 82 81 80 75 73 7 6 PP3V3_S0GPU
PLACE_NEAR=U9600.A3:7mm R9347
357
98 88 IN LVDS_B_DATA_N<0> 1 2 LVDS_CONN_B_DATA_N<0> OUT 6 84 98
1%
1/16W R93701 1
R9371
R9350 MF-LF 20K 20K
402 101 99 88 86 85 84 81
48 47 42 40 37 34 30 28 27 26 25 8 7 6 PP3V3_S0 5% 5%
357 74 73 72 71 70 69 64 63 59 55 53 52 49 1/16W 1/16W
98 88 IN LVDS_B_DATA_P<1> 1 2 LVDS_CONN_B_DATA_P<1> OUT 6 84 98 MF-LF MF-LF
402 2 2 402
1%
PLACE_NEAR=U9600.A1:7mm 1/16W
MF-LF
402 C9370 1 R93721 1
R9373
0.1UF 20K 20K
20% 14 5% 5%
10V 1/16W 1/16W
CERM 2 VCC MF-LF MF-LF
PLACE_NEAR=U9600.B3:7mm R9352 402
U9370 402 2 2 402
LVDS_B_DATA_N<1> 1
357 2 LVDS_CONN_B_DATA_N<1> LVDS_DDC_SEL_EG 13 QFN1 1 LVDS_EG_DDC_CLK
98 88 6 84 98 88 81 82
IN OUT IN C1 A1 2 IN
SN74LV4066A
1%
1/16W B1
MF-LF
402 R9355 88 IN LVDS_DDC_SEL_IG 5
C2 A2 3
4 LVDS_IG_DDC_CLK IN 18
LVDS_B_DATA_P<2> 1
357 2 LVDS_CONN_B_DATA_P<2> LVDS_DDC_CLK
98 88 6 84 98 6 84
IN OUT B2 OUT
1%
PLACE_NEAR=U9600.C5:7mm 1/16W 6 8 LVDS_EG_DDC_DATA 81 82
MF-LF C3 A3 BI
402 9
B3
12
C4 A4
11 LVDS_IG_DDC_DATA BI 18
R9357 B4 10 LVDS_DDC_DATA BI 6 84
357 GND THRM

A 98 88 IN LVDS_B_DATA_N<2> 1
1%
2 LVDS_CONN_B_DATA_N<2> OUT 6 84 98
7 15 SYNC_MASTER=K17_REF SYNC_DATE=06/17/2009 A
1/16W PAGE TITLE
PLACE_NEAR=U9600.A5:7mm MF-LF
402 Muxed Graphics Support
DRAWING NUMBER SIZE
Apple Inc. D
REVISION
R

93 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Port Power Switch

DP_ESD
DP_ESD
CRITICAL
CRITICAL
D CRITICAL
D9410 D9410
RCLAMP0524P
D
RCLAMP0524P
U9480
TPS2051B
L9400
FERR-120-OHM-3A SLP2510P8
SLP2510P8
SOT23
99 84 74 73 72 58 51 50 49 35 31 7 6 PP3V3_S5 5 IN OUT 1 PP3V3_S0_DPILIM 1 2 PP3V3_S0_DPPWR
101 MIN_LINE_WIDTH=0.38 MM MIN_LINE_WIDTH=0.38 MM 2 IO IO 1
MIN_NECK_WIDTH=0.20 MM 0603 MIN_NECK_WIDTH=0.20 MM 5 IO IO 4
PM_SLP_S3_L 4 EN OC* 3 TP_DPPWR_OC_L VOLTAGE=3.3V VOLTAGE=3.3V 9 NC NC 10
74 46 31 18 6 IN
GND
1 C9400 6 NC NC 7
0.01UF
GND
2
GND
20%
2 50V
CERM
603 3
3
CRITICAL CRITICAL
C9480 1 1 C9481 C9485 1 1 C9486 1
10UF 0.1UF
0.1UF 22UF C9487
20%
6.3V 2
20%
10V 20% 20% 100UF
X5R 2 CERM 10V 6.3V 20%
603 402 CERM 2
402
2 X5R-CERM
603
2 6.3V
POLY-TANT R94201
CASE-B2-SM 100K
5%
1/16W
MF-LF
402 2 NO STUFF
R9400 0 1 2
5% 1/16W MF-LF 402
NO STUFF
NO STUFF R9430 0 1 2
R9401 0 1 2
5% 1/16W MF-LF 402
ESD_HOT=TRUE 5% 1/16W MF-LF 402
HDMI_CEC CRITICAL NO STUFF
J9400 R9431 0 1 2
5% 1/16W MF-LF 402
NO STUFF DSPLYPRT-M97-1 CRITICAL
R9403 0 1 2 F-RT-THSM FL9400
5% 1/16W MF-LF 402 12-OHM-100MA
NO STUFF
C R9413 0 1 2
5% 1/16W MF-LF 402
BOT ROW TOP ROW 98 DP_ML_CONN_P<0> 1
TCM1210-4SM
SYM_VER-2 4
98 DP_ML_C_P<0> C9410 1 2 DP_ML_P<0>
C
1 TH PINS SM PINS IN 85 98
R9425 CRITICAL 2 1 98 DP_ML_CONN_N<0> 10% 16V X5R 402
HOT_PLUG_DETECT GND 0.1uF
1M
5%
FL9403
12-OHM-100MA
4 CONFIG1
3 FL9401
12-OHM-100MA
2 3 98 DP_ML_C_N<0> C9411 1 2 DP_ML_N<0> IN 85 98
1/16W ML_LANE0P 10% 16V X5R 402
MF-LF TCM1210-4SM 6 CONFIG2
5 TCM1210-4SM 0.1uF
4 SYM_VER-2 1 ML_LANE0N DP_ML_CONN_P<1> 1 SYM_VER-2 4
2 402 C9414 C9412 1
98
98 85 IN DP_ML_P<3> 1 2 98 DP_ML_C_P<3> 98 DP_ML_CONN_P<3> 8 GND
7 98 DP_ML_C_P<1> 2 DP_ML_P<1> IN 85 98
10% 16V X5R 402 GND 10% 16V X5R 402
0.1uF 10 ML_LANE3P 9 0.1uF
ML_LANE1P FL9402
98 85 IN DP_ML_N<3> C9415 1 2 98 DP_ML_C_N<3>
10% 16V X5R 402
3 2 98 DP_ML_CONN_N<3> 12 ML_LANE3N ML_LANE1N
11 98 DP_ML_CONN_N<1> 2 3
12-OHM-100MA 98 DP_ML_C_N<1> C9413 1 2 DP_ML_N<1>
10% 16V X5R 402 IN 85 98
0.1uF 14 GND
13 CRITICAL TCM1210-4SM 0.1uF
GND 1 SYM_VER-2 4
98 85 BI DP_AUX_CH_C_P 16 AUX_CHP ML_LANE2P
15 98 DP_ML_CONN_P<2> 98 DP_ML_C_P<2> C9416 1 2 DP_ML_P<2> IN 85 98
18 17 10% 16V X5R 402
AUX_CHN ML_LANE2N
0.1uF
98 85 BI DP_AUX_CH_C_N 20 DP_PWR RETURN
19 98 DP_ML_CONN_N<2> 2 3 98 DP_ML_C_N<2> C9417 1 2 DP_ML_N<2>
10% 16V X5R 402
IN 85 98
101 DP_ESD CRITICAL 0.1uF
72 71 70 69 64 63 59 55
34 30 28 27 26 25 8 7 6 PP3V3_S0
53 52 49 48 47 42 40 37
99 88 86 85 84 81 74 73
CRITICAL SHIELD PINS
R94431 R94421 D9411 22 21 NO STUFF
100K RCLAMP0524P R9402 0
5% 100K SLP2510P8 514-0637 1 2
1/16W
MF-LF
5%
1/16W
R94211 NO STUFF
5% 1/16W MF-LF 402
402 2 MF-LF 100K R9432 0 1 2
402 2 5%
88 85 81 OUT DP_CA_DET 1/16W 2 IO 5% 1/16W MF-LF 402
MF-LF IO 1
6 402 2
9 NC NC 10
Q9440 D
GND
2N7002DW-X-G DP_ESD
SOT-363
S G 2 DP_CA_DET_L_Q CRITICAL DP_ESD
3
3
D9400 CRITICAL
1 RCLAMP0504F
SC70-6-1
D9411
Q9440 D RCLAMP0524P
B DP_CA_DET_Q
2N7002DW-X-G
SOT-363
S G 5 1
6
SLP2510P8
B
DP to DVI/HDMI 5 IO IO 4
4
R94221 Cable Adapter 2 5
6 NC NC 7
1M (CA) has 100k
5%
GND
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm 1/16W pull-up to DP_PWR. 4
MF-LF 3
402 2
3
101 99 88 86 85
69 64 63 59 55 53 52
30 28 27 26 25 8 7 6 PP3V3_S0
49 48 47 42 40 37 34
84 81 74 73 72 71 70
R9445 1
10K R9444 1
5% 10K
1/16W 5%
MF-LF 1/16W
402 MF-LF
2
402
88 85 OUT DP_HOTPLUG_DET 2
D
Q9441
2N7002DW-X-G
SOT-363
S G 2 DP_HPD_L_Q
3
1
Q9441 D
2N7002DW-X-G
SOT-363
S G 5 DP_HPD_Q
A 4 DP Source must pull SYNC_MASTER=K20A_MLB SYNC_DATE=03/26/2009 A
R9423 1 down HPD input with PAGE TITLE
100K
5%
1/16W
greater than or equal DisplayPort Connector
MF-LF to 100K (DPv1.1a). DRAWING NUMBER SIZE
402
2
Apple Inc. D
REVISION
R

94 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
83 71 70 68 67 66 50 40 8 7 6
PPBUS_G3H
CRITICAL
C9540 1 1 C9545 CRITICAL
62UF 1UF C9590 1 1 C9595
20% 10%
11V 2 2 25V 62UF 1UF
ELEC X5R
603-1
R9500 20% 10%
25V
CASE-B2 4.7 11V
ELEC 2 2 X5R
2 1 PVIN_S0GPU_P1V05 603-1
CASE-B2
5%
1/16W
MF-LF
402
CRITICAL 7 3 2
Q9510 PP5V_S0
SIZ700DT C9500 1 6 7 8 23 42 48 53 55 69 70 71 73 102
POWERPAIR-6X3.7 10UF C9501 1

10%
1 P1V05GPU_DRVH 25V 2
X5R
1UF
MIN_LINE_WIDTH=0.6MM 10%
MIN_NECK_WIDTH=0.2MM 805 10V 2
8 GATE_NODE=TRUE X5R (Internal 10-ohm path 5
DIDT=TRUE
402-1
from PVCC to VCC) D
PP5V_S0GPU_P1V05P1V8_VCC CRITICAL
6 P1V05GPU_DRVL
VOLTAGE=5V
Q9560
MIN_NECK_WIDTH=0.2MM SIS426DN
GATE_NODE=TRUE PP5V_S0GPU_VREF P1V8FB_DRVH 4
PWRPK-12128
DIDT=TRUE MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.6MM G
C9503 1 C
C 5 4
VOLTAGE=5V
C95041 1UF
10%
GATE_NODE=TRUE
DIDT=TRUE
S
CRITICAL PP1V8_S0GPU_ISNS_R 6 7 51
19
1UF 10V L9560 Vout = 1.8V
5
1 2 3
10% X5R 2
PP1V05_S0GPU_ISNS_R 10V 2 402-1 1.0UH-13A-5.6MOHM
PVCC VCC VREF3
51 7
X5R
402-1 1 2 8A MAX OUTPUT
Vout = 1.05V C9530 1 CRITICAL LDO 7 NC 5 PCMB065T-SM CRITICAL (Q9560 limit?)
CRITICAL 0.1UF 6 VIN LDOREFIN 8 (SGND)
3.5A MAX OUTPUT L9510
10%
50V 2 P1V05GPU_VBST 17 BOOT1 BOOT2 24 P1V8FB_VBST D C9560 1 F = 500 KHZ
(Q9510 limit?) 2.2UH-8.0A
X7R
603-1 MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM 15 UGATE1
U9500 UGATE2 26
DIDT=TRUE MIN_LINE_WIDTH=0.6MM
CRITICAL 20%
220UF
DIDT=TRUE QFN2 Q9561 2.5V 2 1 C9565
1 2 P1V05GPU_LL POLY-TANT
ISL6236
16 PHASE1 PHASE2 25 10UF
f = 400 kHz MIN_LINE_WIDTH=0.6MM SIS426DN CASE-B2-SM2
20%
1 CRITICAL PCMB065T-SM MIN_NECK_WIDTH=0.2MM 18 LGATE1 LGATE2 23 P1V8FB_DRVL 4
PWRPK-12128 6.3V
C9510 SWITCH_NODE=TRUE
DIDT=TRUE 10 OUT1 OUT2 30 (=PP1V8FB_S0_REG)
G 2 X5R
XW9515
SM
330UF
20% 14 EN1 EN2 27
GATE_NODE=TRUE
DIDT=TRUE
S 603
2 2.0V
1 2 POLY-TANT
B2-SM
9 BYP 1 C9580 1 2 3
P1V05GPU_VFB 11 FB1 REFIN2 32 GPU_P1V8_REFIN 0.1UF
10%

LB# 820-2849 Schematic Diagram PDF

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8 7 6 5 4 3 2 1

SCHEMATIC,"ANGEL ISLAND",MLB 2009-05-19

Table of Contents K20_MLB SMC K17_WFERRY CPU Constraints K17_WFERRY

Revision History K20A_MLB SMC Support K17_REF Memory Constraints K17_WFERRY

Power Aliases (MASTER) Thermal Sensors K17_CHENGD SMC Constraints K17_WFERRY

PCH Grounds T22_MLB 5V / 3.3V Power Supply K20A_MLB

PCH Non-GFX Decoupling K17_WFERRY 1.5V DDR3 Supply K17_REF

CPU/PCH GFX Decoupling K17_WFERRY CPU IMVP VCore Regulator K18_POWER

Clock (CK505) K17_REF CPUVTT (1.05V) Power Supply T22_MLB

Chipset Support K17_REF Misc Power Supplies K17_WFERRY

DDR3 SO-DIMM Connector A K17_REF Power FETs K17_WFERRY

DDR3 Byte/Bit Swaps K18_MLB Power Control K17_WFERRY

PROJECT SPECIFIC CONNS K20A_MLB LCD Backlight Driver (MC34845) K17_VEMURI

Schematic / PCB #’s Apple Inc.

051-8503 1 SCHEM,ANGEL_ISLAND,MLB,K17 SCH CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH

GPIO FDI DMI RTC

Mini PCI-E E-NET E-NET J6780,6781,6782,6700,6750

POWER SYSTEM ARCHITECTURE SMC PWRGD

SMC_BATT_ISENSE GPUVCORE_EN GPUVCORE_PGOOD (PAGE 69)

1.103V(L/H) R5413 VOUT2 PPVTT_S0_DDR_LDO SM_DRAMPWROK

VIN P5VS0_EN P1V2GMUX_EN

U1800 LCD_BKLT_EN APP001 (PAGE 70)

NOTICE OF PROPRIETARY PROPERTY: BRANCH

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

639-0973 PCBA,2.53GHZ,512SAM_VRAM,K17 K17_COMMON,CPU_2_53GHZ,FB_512_SAMSUNG,EEEE_DCMV,K17_PVT 138S0603 138S0602 ALL Murata alt to Samsung

D 516S0806 516S0805 ALL FOXCONN ALT TO MOLEX

353S2805 353S2603 ALL Fairchild 8 in alt to 6 in wafer

127S0111 127S0060 ALL Rohm alt to Kemet

128S0299 128S0218 ALL NEC/TOKIN alt to Sanyo

337S3808 337S3839 ALL GT216 A02 alt to A03 part

376S0887 376S0749 ALL Fairchild alt to Vishay

K17 BOM GROUPS TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

C BOM GROUP BOM OPTIONS

Bar Code Labels / EEEE #’s

341T0229 1 IC,SMC,K17 U4900 CRITICAL SMC_PROG

335S0610 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_BLANK

341T0244 1 IC,EFI ROM,K17 U6100 CRITICAL BOOTROM_PROG

341S2384 1 IR,ENCORE II, CY7C63833-LFXC U4800 CRITICAL

336S0025 1 IC,XP2-5,HF,CPLD,BLANK U9600 CRITICAL GMUX_5K_BLANK

A 341S2568 1 IC,CPLD,LATTICE,132CSBGA,K17MLB U9600 CRITICAL GMUX_PROG

333S0535 4 IC,SDRAM,GDDR3,32MX32,900MHZ,TIVA,HF U8400,U8450,U8500,U8550 CRITICAL VRAM_512_HYNIX

SPKRAMP_LFE_OUT_P 62 63 99 I1063 TRUE SMBUS_SMC_A_S3_SCL 6 33 46 49 55 97 MAKE_BASE=TRUE

SPKRAMP_FR_OUT_N 62 63 99 I1066 TRUE CONN_USB2_BT_P 33 99

SPKRAMP_BR_OUT_P 62 63 99 I1065 TRUE CONN_USB2_BT_N 33 99 MAKE_BASE=TRUE

C J9000 (LVDS CONN) J3500 (EXPRESS CARD CONN)

MAKE_BASE=TRUE NC_PCH_NC5 TRUE NC_PCH_NC5

MAKE_BASE=TRUE NC_PCH_TP19 TRUE NC_PCH_TP19

MAKE_BASE=TRUE NC_PCH_TP18 TRUE NC_PCH_TP18

TRUE PPCPUVTT_S0 7 10 12 13 15 25 26 40 71 74 101 MAKE_BASE=TRUE NC_PCH_TP17 TRUE NC_PCH_TP17

B I1019 TRUE LED_RETURN_3

MAKE_BASE=TRUE 20 6 NC_PCH_TP14 TRUE NC_PCH_TP14 6 20

GND J6900 (DC POWER CONN) 17 6 TRUE

GND MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY: BRANCH

STDOFF-4.5OD.98H-1.1-3.48-TH 1 91 13 GFX_VID<0..6> GFXIMVP_VID<0..6> 70

D Left CPU Right CPU Bottom Left GPU ZT0930

ZT0915 GPU signals MAKE_BASE=TRUE NO_TEST=TRUE

3R2P5 1.4DIA-SHORT-EMI-MLB-M97-M98 1 88 18 8 LVDS_IG_PANEL_PWR LVDS_IG_PANEL_PWR 8 18 88

ZT0971 1.4DIA-SHORT-EMI-MLB-M97-M98 88 75 8 PEX_CLKREQ_L PEX_CLKREQ_L 8 75 88 5%