16-Bit PCM Audio DAC: Data Sheet
16-Bit PCM Audio DAC: Data Sheet
16-Bit PCM Audio DAC: Data Sheet
00759-001
CONVERSION
Compact disc players CLK LE DATA
GENERAL DESCRIPTION
The AD1856 is a monolithic, 16-bit pulse code modulation (PCM) The AD1856 can operate with ±5 V to ±12 V power supplies,
audio DAC. The device provides a voltage output amplifier, 16-bit making it suitable for both the portable and home-use markets.
DAC, 16-bit serial-to-parallel input register, and voltage reference. The digital supplies, +VL and −VL, can be separated from the
The digital portion of the AD1856 is fabricated with CMOS logic analog supplies, +VS and −VS, for reduced digital crosstalk.
elements that are provided by the Analog Devices, Inc., BiMOS II Separate analog and digital ground pins are also provided.
process. The analog portion of the AD1856 is fabricated with Power dissipation is 110 mW (typical) with ±5 V supplies and
bipolar and MOS devices, as well as thin film resistors. 135 mW (typical) when ±12 V supplies are used.
This combination of circuit elements, as well as careful design and The AD1856 is packaged in a 16-lead plastic SOIC package
layout techniques, results in high performance audio playback. and incorporates the industry-standard pinout. Operation is
Laser trimming of the linearity error affords extremely low total guaranteed over the temperature range of −25°C to +70°C and
harmonic distortion. An optional linearity trim pin is provided over the voltage supply range of ±4.75 V to ±13.2 V.
to allow residual differential linearity error at midscale to be
eliminated. This feature is particularly valuable for low distortion PRODUCT HIGHLIGHTS
reconstructions of low amplitude signals. Output glitch is also 1. Total harmonic distortion is 100% tested.
small, contributing to the overall high level of performance. The 2. MSB trim feature allows superlinear operation.
output amplifier achieves fast settling and high slew rates, providing 3. The AD1856 operates with ±5 V to ±12 V supplies.
a full ±3 V signal at load currents of up to ±8 mA. The output 4. Serial interface is compatible with digital filter chips.
amplifier is short-circuit protected and can withstand indefinite 5. 1.5 μs settling time permits 2×, 4×, and 8× oversampling.
shorts to ground. 6. No external components are required.
The serial input interface consists of the clock, data, and latch 7. 96 dB dynamic range.
enable pins. The serial twos complement data-word is clocked 8. ±3 V or ±8 mA output capability.
into the DAC, MSB first, by the external data clock. The latch 9. 16-bit resolution.
enable signal transfers the input word from the internal serial input 10. Twos complement serial input words.
register to the parallel DAC input register. The input clock can 11. Low cost.
support a 10 MHz clock rate. The serial input port is compatible 12. 16-lead plastic SOIC package.
with popular digital filter chips used in consumer audio products.
These filters operate at oversampling rates of 2×, 4×, and 8× the
sampling frequency.
TABLE OF CONTENTS
Features .............................................................................................. 1 Power Supplies and Decoupling ..................................................9
Applications ....................................................................................... 1 Total Harmonic Distortion ..........................................................9
Functional Block Diagram .............................................................. 1 Optional MSB Adjustment........................................................ 10
General Description ......................................................................... 1 Digital Circuit Considerations...................................................... 11
Product Highlights ........................................................................... 1 Input Data ................................................................................... 11
Revision History ............................................................................... 2 Applications of the AD1856 PCM Audio DAC .......................... 12
Specifications..................................................................................... 3 One DAC per System ................................................................. 12
Absolute Maximum Ratings ............................................................ 5 One DAC per Channel .............................................................. 12
ESD Caution .................................................................................. 5 Two DACs per Channel (Four-DAC System) ........................ 13
Pin Configuration and Function Descriptions ............................. 6 Digital Filtering and Oversampling ............................................. 14
Terminology ...................................................................................... 7 Achieving 8× fS Oversampling with Two AD1856 Devices
Theory of Operation ........................................................................ 8 and the Yamaha YM3414 .......................................................... 14
REVISION HISTORY
2/13—Rev. B to Rev. C Changes to Table 2.............................................................................5
Updated Format .................................................................. Universal Changes to Figure 2 and Table 3......................................................6
Deleted 16-Lead DIP (N) Package ................................... Universal Deleted Figure 14 and Dual DAC, 4× fS Oversampling
Reorganized Layout ............................................................ Universal Architecture Section..........................................................................7
Changes to Features Section, General Description Changes to Grounding Recommendations Section,
Section, and Product Highlights Section ...................................... 1 Power Supplies and Decoupling Section, and Figure 3 ................9
Changes to Total Harmonic Distortion Parameter Changes to Input Data Section ..................................................... 11
and Power Supply Parameter, Table 1 ............................................ 3 Changes to Digital Filtering and Oversampling Section .......... 14
Changes to Power Dissipation Parameter, Table 1 ....................... 4 Updated Outline Dimensions ....................................................... 15
Deleted Figure 1; Renumbered Sequentially................................. 4 Changes to Ordering Guide .......................................................... 15
Rev. C | Page 2 of 16
Data Sheet AD1856
SPECIFICATIONS
Typical values at TA = 25°C, VL = ±5 V, and VS = ±5 V, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 1 16 Bits
DIGITAL INPUTS
Input Voltage High, VIH 2.4 +VL V
Input Voltage Low, VIL 0 0.8 V
Input Current High, IIH1 VIH = +VL 1.0 µA
Input Current Low, IIL1 VIL = 0.4 V −10 µA
Clock Input Frequency1 10 MHz
ACCURACY
Gain Error ±2.0 %
Bipolar Zero Error ±30 mV
Differential Linearity Error ±0.001 % of FSR
Noise at Bipolar Zero RMS, 20 Hz to 20 kHz 6 µV
TOTAL HARMONIC DISTORTION 990.5 Hz
0 dB AD1856RZ-K 0.002 0.00251 %
AD1856RZ 0.002 0.0081 %
−20 dB AD1856RZ-K 0.018 0.0201 %
AD1856RZ 0.018 0.0401 %
−60 dB AD1856RZ-K 1.8 2.01 %
AD1856RZ 1.8 4.01 %
MONOTONICITY 15 Bits
DRIFT 0°C to 70°C
Total Drift ±25 ppm of FSR/°C
Bipolar Zero Drift ±4 ppm of FSR/°C
SETTLING TIME To ±0.006% of FSR
Voltage Output 6 V step 1.5 µs
1 LSB step 1.0 µs
Slew Rate 9 V/µs
Current Output 1 mA step, 10 Ω to 100 Ω load 350 ns
1 kΩ load 350 ns
WARM-UP TIME 1 Minute
OUTPUT
Voltage Output Configuration
Bipolar Range ±3 V
Output Current ±8 mA
Output Impedance 0.1 Ω
Short-Circuit Duration Indefinite to ground
Current Output Configuration
Bipolar Range (±30%) ±1.0 mA
Output Impedance (±30%) 1.7 kΩ
POWER SUPPLY
Voltage, +VL and +VS +VS ≥ +VL for operation 4.75 5 13.2 V
Voltage, −VL and −VS −VL ≥ −VS for operation −13.2 −5 −4.75 V
Current, +I +VL and +VS = 5 V, 10 MHz clock 10 151 mA
+VL and +VS = 12 V, 10 MHz clock 12 mA
Current, −I −VL and −VS = −5 V, 10 MHz clock −12 −151 mA
−VL and −VS = −12 V, 10 MHz clock −15 mA
Rev. C | Page 3 of 16
AD1856 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
POWER DISSIPATION 10 MHz clock
±VS and ±VL = ±5 V 110 1501 mW
±VS and ±VL = ±12 V 135 mW
TEMPERATURE RANGE
Specification 0 +70 °C
Operational −25 +70 °C
Storage −60 +100 °C
1
Tested on all production units at final test.
Rev. C | Page 4 of 16
Data Sheet AD1856
Rev. C | Page 5 of 16
AD1856 Data Sheet
SERIAL
+VL 3 14 MSB ADJ
INPUT
REGISTER
NC 4 IOUT 13 IOUT
CLK 5 12 AGND
CONTROL
LE 6 LOGIC 11 SJ
DATA 7 10 RF
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NC = NO CONNECT
Rev. C | Page 6 of 16
Data Sheet AD1856
TERMINOLOGY
Total Harmonic Distortion The theoretical dynamic range of an n-bit converter is approx-
Total harmonic distortion (THD) is defined as the ratio of the imately (6 × n) dB. In the case of the 16-bit AD1856, that is
square root of the sum of the squares of the harmonic values to 96 dB. The actual dynamic range of a converter is less than the
the value of the fundamental input frequency. THD is expressed theoretical value due to limitations imposed by noise, quantiza-
in percent (%) or decibels (dB). tion error, and other errors.
THD is a measure of the magnitude and distribution of linearity Bipolar Zero Error
error and differential linearity error. The distribution of these Bipolar zero error is the deviation in the actual analog output
errors may be different, depending on the amplitude of the output from the ideal output (0 V) when the twos complement input
signal. Therefore, to be most useful, THD should be specified for code representing half scale (all 0s) is loaded into the input
both large and small signal amplitudes. register.
Settling Time Differential Linearity Error
Settling time is the time required for the output to reach and Differential linearity error is the measure of the variation in
remain within a specified error band about its final value, mea- analog value, normalized to full scale, associated with a 1 LSB
sured from the digital input transition. Settling time is the primary change in the digital input. Monotonic behavior requires that
measure of dynamic performance. the differential linearity error not exceed 1 LSB in the negative
Dynamic Range direction.
The dynamic range specification indicates the ratio of the small- Monotonicity
est signal that the converter can resolve to the largest signal it is A digital-to-analog converter is monotonic if the output either
able to produce. As a ratio, it is usually expressed in decibels (dB). increases or remains constant as the digital input increases.
Rev. C | Page 7 of 16
AD1856 Data Sheet
THEORY OF OPERATION
The AD1856 is a complete, monolithic, 16-bit PCM audio DAC. The resistors that form the ladder structure are fabricated with
No additional external components are required for operation. silicon-chromium thin film. Laser trimming of these resistors
As shown in the block diagram in Figure 1, each chip contains further reduces linearity error, resulting in low output distortion.
a voltage reference, an output amplifier, a 16-bit DAC, a 16-bit The output amplifier uses both MOS and bipolar devices to
input latch, and a 16-bit serial-to-parallel input register. produce low offset, high slew rate, and optimum settling time.
The voltage reference consists of a band gap circuit and buffer When combined with the on-board feedback resistor, the output
amplifier. This circuitry produces an output voltage that is stable op amp can convert the output current of the AD1856 to a
over time and temperature changes. voltage output.
The 16-bit digital-to-analog converter uses a combination of a
segmented decoder and R-2R architectures to achieve consistent
linearity and differential linearity.
Rev. C | Page 8 of 16
Data Sheet AD1856
ground (AGND and DGND). The analog ground pin is the high AD1856
quality ground reference point for the analog portion of the 2 8 1 12
DGND –VL –VS AGND
device. The digital ground pin returns ground current from the
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digital logic portions of the AD1856 circuitry. Both pins should GROUND
components should be placed around the AD1856 so that analog Figure 3. Alternate Recommended Schematic
and digital return currents do not cross each other. A single solid Given that these two supplies are within the range of ±5 V to
ground plane with good parts placement and trace routing yields ±12 V, they can be used to power the AD1856. In this case, the
the quietest design with the best signal integrity and EMI/EMC positive logic and positive analog supplies can both be connected
specifications. to the single positive supply. The negative logic and negative analog
POWER SUPPLIES AND DECOUPLING supplies can both be connected to the single negative supply.
Performance benefits from a measure of isolation between the
The AD1856 has four power supply input pins. +VS and −VS
supplies, introduced by using simple low-pass filters in the
provide the supply voltages to operate the linear portions of the
individual power supply leads.
DAC, including the voltage reference, output amplifier, and
control amplifier. The +VS and −VS supplies are designed to As with most linear circuits, changes in the power supplies affect
operate from ±5 V to ±12 V. the output of the DAC. Analog Devices recommends that well-
regulated power supplies with less than 1% ripple be incorporated
The +VL and −VL pins supply power to the digital portions of
into the design of any system using these devices.
the chip, including the input shift register and the input latching
circuitry. The +VL and −VL supplies are also designed to operate TOTAL HARMONIC DISTORTION
from ±5 V to ±12 V, subject only to the limitation that +VL cannot The THD figure of an audio DAC represents the amount of
be more positive than +VS, and −VL cannot be more negative undesirable signal produced during reconstruction and play-
than −VS. back of an audio waveform. The THD specification, therefore,
Decoupling capacitors should be used on all power supply pins. provides a direct method for classifying and choosing an audio
Furthermore, good engineering practice suggests that these DAC for a desired level of performance.
capacitors be placed as close as possible to the package pins. The Analog Devices tests and grades all AD1856 devices on the
decoupling for both the bipolar logic supply, ±VL, and the bipolar basis of THD performance. A block diagram of the test setup
analog supply, ±VS, should be returned to the closest ground pins. is shown in Figure 4. In this test setup, a digital data stream,
The use of four separate power supplies reduces feedthrough representing a 0 dB, −20 dB, or −60 dB sine wave, is sent to the
from the digital portion of the system to the linear portions of device under test. The frequency of this waveform is 990.5 Hz.
the system, thus contributing to good performance. However, Input data is sent to the AD1856 at a 4× fS rate (176.4 kHz). The
four separate voltage supplies are not necessary for good circuit AD1856 under test produces an analog output signal with the
performance. For example, Figure 3 illustrates a system where on-board op amp.
only a single positive and a single negative supply are available.
23 CYCLES
4× fS
DATA
RATE AD1856 ±3V
16-BIT DATA
DIGITAL VOUT
WAVEFORM LE
GENERATOR CLK
990.5Hz 30kHz
NOTCH LOW-PASS
0 1 0 0 0 1 FILTER FILTER
OUTPUT 1 1 1 1 1 0
1 1 0 1 0 1
4096 PT. . . . . . .
FFT . . . . . . DIGITIZER
ANALYZER . . . . . .
1 1 0 0 1 0
1 0 1 0 1 1
0 0 1 1 1 0
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4096
SAMPLES
Rev. C | Page 9 of 16
AD1856 Data Sheet
0.100
The automatic test equipment digitizes 4096 samples of the
output test waveform, incorporating 23 complete cycles of the 0.050
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of the AD1856 for various amplitudes of a 1 kHz output signal.
As shown in Figure 5, the AD1856 offers excellent performance, 0.001
1 100 1k 10k
even at amplitudes as low as −60 dB. Figure 6 shows the typical FREQUENCY (Hz)
THD vs. frequency performance. Figure 6. Typical THD vs. Frequency
10.0
OPTIONAL MSB ADJUSTMENT
Use of an optional adjustment circuit allows residual differential
TOTAL HARMONIC DISTORTION (%)
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Figure 5. Typical Unadjusted THD vs. Amplitude
MSB ADJ 14
Rev. C | Page 10 of 16
Data Sheet AD1856
M L
DATA S S
B B
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LE
>100ns
>30ns >30ns
CLK
>15ns
>60ns
>40ns >40ns
LATCH
ENABLE (LE)
>50ns
INTERNAL DAC INPUT REGISTER
>15ns >15ns UPDATED WITH 16 MOST RECENT BITS
Rev. C | Page 11 of 16
AD1856 Data Sheet
Figure 10 shows a circuit using one AD1856 per system to repro- AD1856
duce both stereo channels of a typical first-generation digital DATA VOUT
CLK
audio system. The input data is fed to the AD1856 in a format LE
that alternates between left channel data and right channel data. LOW-
RIGHT
The output of the AD1856 is switched between the left channel SHA PASS
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SAMPLE OUTPUT
FILTER
and right channel output sample-and-hold amplifiers (SHAs). RIGHT
The SHAs demultiplex and deglitch the output of the AD1856. Figure 12. Third SHA Eliminates Phase Delay
The timing diagram for the control signals for this circuit is
shown in Figure 11.
ONE DAC PER CHANNEL
Another approach used to eliminate phase delay between left and
right channels uses one DAC per channel. In this architecture, the
LOW-
PASS
LEFT input data bit streams for the left channel and the right channel
SAMPLE
1/2
FILTER
OUTPUT
are simultaneously sent and latched into each DAC. This second-
LEFT
AD712
generation approach, shown in Figure 13, is suitable for higher
AD1856
DATA VOUT performance digital audio playback units.
CLK
LE AD1856
LOW- LEFT DATA VOUT
RIGHT DATA CLK
PASS
OUTPUT
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SAMPLE FILTER LE
RIGHT 1/2
AD712 LOW-
LEFT
PASS
OUTPUT
Figure 10. AD1856 in a One DAC per System Architecture 1/2
FILTER
AD712
AD1856
RIGHT DATA VOUT
CLK DATA CLK
LE
LOW-
RIGHT
PASS 00759-014
OUTPUT
FILTER
1/2
DATA AD712
LE
DAC
OUT
SAMPLE
RIGHT
00759-012
SAMPLE
LEFT
Rev. C | Page 12 of 16
Data Sheet AD1856
TWO DACs PER CHANNEL (FOUR-DAC SYSTEM) AD1856
DATA VOUT
Another architecture uses two DACs per channel. In this CLK
LE LOW-
scheme, shown in Figure 14, each DAC reproduces one half of SHA PASS
LEFT
OUTPUT
the output waveform. The advantage obtained is that midscale AD1856 1/2
FILTER
DATA VOUT
differential linearity error no longer affects the zero-crossing CLK
AD712
LE
points of the waveforms. These effects are shifted to the points
where the output waveform crosses ±3/4 full scale. The result
AD1856
is that THD performance for low amplitude signals is greatly DATA VOUT
improved. Not shown in Figure 14 is a VLSI circuit, which is CLK
LE LOW-
required to separate the incoming data into the appropriate SHA PASS
RIGHT
OUTPUT
AD1856 FILTER
form required by each DAC. DATA
1/2
VOUT
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AD712
CLK
LE
Rev. C | Page 13 of 16
AD1856 Data Sheet
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DEGLITCH
SIGNALS
Rev. C | Page 14 of 16
Data Sheet AD1856
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16 9
7.60 (0.2992)
7.40 (0.2913)
1 10.65 (0.4193)
8
10.00 (0.3937)
03-27-2007-B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
ORDERING GUIDE
Model 1 Temperature Range THD at Full-Scale Output Package Description Package Option
AD1856RZ −25°C to +70°C 0.008% 16-Lead SOIC_W RW-16
AD1856RZ-REEL −25°C to +70°C 0.008% 16-Lead SOIC_W RW-16
AD1856RZ-REEL7 −25°C to +70°C 0.008% 16-Lead SOIC_W RW-16
AD1856RZ-K −25°C to +70°C 0.0025% 16-Lead SOIC_W RW-16
AD1856RZ-K-REEL7 −25°C to +70°C 0.0025% 16-Lead SOIC_W RW-16
1
Z = RoHS Compliant Part.
Rev. C | Page 15 of 16
AD1856 Data Sheet
NOTES
Rev. C | Page 16 of 16
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