16-Bit PCM Audio DAC: Data Sheet

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16-Bit PCM Audio DAC

Data Sheet AD1856


FEATURES FUNCTIONAL BLOCK DIAGRAM
RF
0.0025% THD
Fast settling permits 2×, 4×, and 8× oversampling
16-BIT
±3 V output REFERENCE IOUT DAC
Optional trim allows superlinear performance AUDIO
OUTPUT
±5 V to ±12 V operation
16-BIT INPUT LATCH
16-lead plastic SOIC package
Serial input

APPLICATIONS 16-BIT SERIAL-TO-PARALLEL

00759-001
CONVERSION
Compact disc players CLK LE DATA

Digital audio amplifiers Figure 1.


DAT recorders and players
Synthesizers and keyboards

GENERAL DESCRIPTION
The AD1856 is a monolithic, 16-bit pulse code modulation (PCM) The AD1856 can operate with ±5 V to ±12 V power supplies,
audio DAC. The device provides a voltage output amplifier, 16-bit making it suitable for both the portable and home-use markets.
DAC, 16-bit serial-to-parallel input register, and voltage reference. The digital supplies, +VL and −VL, can be separated from the
The digital portion of the AD1856 is fabricated with CMOS logic analog supplies, +VS and −VS, for reduced digital crosstalk.
elements that are provided by the Analog Devices, Inc., BiMOS II Separate analog and digital ground pins are also provided.
process. The analog portion of the AD1856 is fabricated with Power dissipation is 110 mW (typical) with ±5 V supplies and
bipolar and MOS devices, as well as thin film resistors. 135 mW (typical) when ±12 V supplies are used.
This combination of circuit elements, as well as careful design and The AD1856 is packaged in a 16-lead plastic SOIC package
layout techniques, results in high performance audio playback. and incorporates the industry-standard pinout. Operation is
Laser trimming of the linearity error affords extremely low total guaranteed over the temperature range of −25°C to +70°C and
harmonic distortion. An optional linearity trim pin is provided over the voltage supply range of ±4.75 V to ±13.2 V.
to allow residual differential linearity error at midscale to be
eliminated. This feature is particularly valuable for low distortion PRODUCT HIGHLIGHTS
reconstructions of low amplitude signals. Output glitch is also 1. Total harmonic distortion is 100% tested.
small, contributing to the overall high level of performance. The 2. MSB trim feature allows superlinear operation.
output amplifier achieves fast settling and high slew rates, providing 3. The AD1856 operates with ±5 V to ±12 V supplies.
a full ±3 V signal at load currents of up to ±8 mA. The output 4. Serial interface is compatible with digital filter chips.
amplifier is short-circuit protected and can withstand indefinite 5. 1.5 μs settling time permits 2×, 4×, and 8× oversampling.
shorts to ground. 6. No external components are required.
The serial input interface consists of the clock, data, and latch 7. 96 dB dynamic range.
enable pins. The serial twos complement data-word is clocked 8. ±3 V or ±8 mA output capability.
into the DAC, MSB first, by the external data clock. The latch 9. 16-bit resolution.
enable signal transfers the input word from the internal serial input 10. Twos complement serial input words.
register to the parallel DAC input register. The input clock can 11. Low cost.
support a 10 MHz clock rate. The serial input port is compatible 12. 16-lead plastic SOIC package.
with popular digital filter chips used in consumer audio products.
These filters operate at oversampling rates of 2×, 4×, and 8× the
sampling frequency.

Rev. C Document Feedback


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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD1856 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Power Supplies and Decoupling ..................................................9
Applications ....................................................................................... 1 Total Harmonic Distortion ..........................................................9
Functional Block Diagram .............................................................. 1 Optional MSB Adjustment........................................................ 10
General Description ......................................................................... 1 Digital Circuit Considerations...................................................... 11
Product Highlights ........................................................................... 1 Input Data ................................................................................... 11
Revision History ............................................................................... 2 Applications of the AD1856 PCM Audio DAC .......................... 12
Specifications..................................................................................... 3 One DAC per System ................................................................. 12
Absolute Maximum Ratings ............................................................ 5 One DAC per Channel .............................................................. 12
ESD Caution .................................................................................. 5 Two DACs per Channel (Four-DAC System) ........................ 13
Pin Configuration and Function Descriptions ............................. 6 Digital Filtering and Oversampling ............................................. 14
Terminology ...................................................................................... 7 Achieving 8× fS Oversampling with Two AD1856 Devices
Theory of Operation ........................................................................ 8 and the Yamaha YM3414 .......................................................... 14

Analog Circuit Considerations ....................................................... 9 Outline Dimensions ....................................................................... 15

Grounding Recommendations ................................................... 9 Ordering Guide .......................................................................... 15

REVISION HISTORY
2/13—Rev. B to Rev. C Changes to Table 2.............................................................................5
Updated Format .................................................................. Universal Changes to Figure 2 and Table 3......................................................6
Deleted 16-Lead DIP (N) Package ................................... Universal Deleted Figure 14 and Dual DAC, 4× fS Oversampling
Reorganized Layout ............................................................ Universal Architecture Section..........................................................................7
Changes to Features Section, General Description Changes to Grounding Recommendations Section,
Section, and Product Highlights Section ...................................... 1 Power Supplies and Decoupling Section, and Figure 3 ................9
Changes to Total Harmonic Distortion Parameter Changes to Input Data Section ..................................................... 11
and Power Supply Parameter, Table 1 ............................................ 3 Changes to Digital Filtering and Oversampling Section .......... 14
Changes to Power Dissipation Parameter, Table 1 ....................... 4 Updated Outline Dimensions ....................................................... 15
Deleted Figure 1; Renumbered Sequentially................................. 4 Changes to Ordering Guide .......................................................... 15

Rev. C | Page 2 of 16
Data Sheet AD1856

SPECIFICATIONS
Typical values at TA = 25°C, VL = ±5 V, and VS = ±5 V, unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 1 16 Bits
DIGITAL INPUTS
Input Voltage High, VIH 2.4 +VL V
Input Voltage Low, VIL 0 0.8 V
Input Current High, IIH1 VIH = +VL 1.0 µA
Input Current Low, IIL1 VIL = 0.4 V −10 µA
Clock Input Frequency1 10 MHz
ACCURACY
Gain Error ±2.0 %
Bipolar Zero Error ±30 mV
Differential Linearity Error ±0.001 % of FSR
Noise at Bipolar Zero RMS, 20 Hz to 20 kHz 6 µV
TOTAL HARMONIC DISTORTION 990.5 Hz
0 dB AD1856RZ-K 0.002 0.00251 %
AD1856RZ 0.002 0.0081 %
−20 dB AD1856RZ-K 0.018 0.0201 %
AD1856RZ 0.018 0.0401 %
−60 dB AD1856RZ-K 1.8 2.01 %
AD1856RZ 1.8 4.01 %
MONOTONICITY 15 Bits
DRIFT 0°C to 70°C
Total Drift ±25 ppm of FSR/°C
Bipolar Zero Drift ±4 ppm of FSR/°C
SETTLING TIME To ±0.006% of FSR
Voltage Output 6 V step 1.5 µs
1 LSB step 1.0 µs
Slew Rate 9 V/µs
Current Output 1 mA step, 10 Ω to 100 Ω load 350 ns
1 kΩ load 350 ns
WARM-UP TIME 1 Minute
OUTPUT
Voltage Output Configuration
Bipolar Range ±3 V
Output Current ±8 mA
Output Impedance 0.1 Ω
Short-Circuit Duration Indefinite to ground
Current Output Configuration
Bipolar Range (±30%) ±1.0 mA
Output Impedance (±30%) 1.7 kΩ
POWER SUPPLY
Voltage, +VL and +VS +VS ≥ +VL for operation 4.75 5 13.2 V
Voltage, −VL and −VS −VL ≥ −VS for operation −13.2 −5 −4.75 V
Current, +I +VL and +VS = 5 V, 10 MHz clock 10 151 mA
+VL and +VS = 12 V, 10 MHz clock 12 mA
Current, −I −VL and −VS = −5 V, 10 MHz clock −12 −151 mA
−VL and −VS = −12 V, 10 MHz clock −15 mA

Rev. C | Page 3 of 16
AD1856 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
POWER DISSIPATION 10 MHz clock
±VS and ±VL = ±5 V 110 1501 mW
±VS and ±VL = ±12 V 135 mW
TEMPERATURE RANGE
Specification 0 +70 °C
Operational −25 +70 °C
Storage −60 +100 °C
1
Tested on all production units at final test.

Rev. C | Page 4 of 16
Data Sheet AD1856

ABSOLUTE MAXIMUM RATINGS


Table 2. Stresses above those listed under Absolute Maximum Ratings
Parameter Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
+VL to DGND 0 V to 13.2 V
other conditions above those indicated in the operational
+VS to AGND 0 V to 13.2 V
section of this specification is not implied. Exposure to absolute
−VL to DGND −13.2 V to 0 V
maximum rating conditions for extended periods may affect
−VS to AGND −13.2 V to 0 V
device reliability.
Digital Inputs to DGND −0.3 V to +VL
AGND to DGND ±0.3 V ESD CAUTION
Short-Circuit Protection Indefinite short to ground
Soldering, 10 sec 300°C
Storage Temperature Range −60°C to +100°C

Rev. C | Page 5 of 16
AD1856 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS


–VS 1 16-BIT 16-BIT 16 +VS
LATCH DAC
DGND 2 15 TRIM

SERIAL
+VL 3 14 MSB ADJ
INPUT
REGISTER
NC 4 IOUT 13 IOUT

CLK 5 12 AGND
CONTROL
LE 6 LOGIC 11 SJ

DATA 7 10 RF

–VL 8 AD1856 9 VOUT

00759-002
NC = NO CONNECT

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions


Pin No. Mnemonic Description
1 −VS Analog Power Supply, Negative
2 DGND Digital Ground
3 +VL Logic Power Supply, Positive
4 NC No Connection
5 CLK Data Clock Input
6 LE Latch Enable Input
7 DATA Serial Data Input
8 −VL Logic Power Supply, Negative
9 VOUT Voltage Output
10 RF Feedback Resistor
11 SJ Summing Junction
12 AGND Analog Ground
13 IOUT Current Output
14 MSB ADJ MSB Adjustment Terminal
15 TRIM MSB Trimming Potentiometer Terminal
16 +VS Analog Power Supply, Positive

Rev. C | Page 6 of 16
Data Sheet AD1856

TERMINOLOGY
Total Harmonic Distortion The theoretical dynamic range of an n-bit converter is approx-
Total harmonic distortion (THD) is defined as the ratio of the imately (6 × n) dB. In the case of the 16-bit AD1856, that is
square root of the sum of the squares of the harmonic values to 96 dB. The actual dynamic range of a converter is less than the
the value of the fundamental input frequency. THD is expressed theoretical value due to limitations imposed by noise, quantiza-
in percent (%) or decibels (dB). tion error, and other errors.
THD is a measure of the magnitude and distribution of linearity Bipolar Zero Error
error and differential linearity error. The distribution of these Bipolar zero error is the deviation in the actual analog output
errors may be different, depending on the amplitude of the output from the ideal output (0 V) when the twos complement input
signal. Therefore, to be most useful, THD should be specified for code representing half scale (all 0s) is loaded into the input
both large and small signal amplitudes. register.
Settling Time Differential Linearity Error
Settling time is the time required for the output to reach and Differential linearity error is the measure of the variation in
remain within a specified error band about its final value, mea- analog value, normalized to full scale, associated with a 1 LSB
sured from the digital input transition. Settling time is the primary change in the digital input. Monotonic behavior requires that
measure of dynamic performance. the differential linearity error not exceed 1 LSB in the negative
Dynamic Range direction.
The dynamic range specification indicates the ratio of the small- Monotonicity
est signal that the converter can resolve to the largest signal it is A digital-to-analog converter is monotonic if the output either
able to produce. As a ratio, it is usually expressed in decibels (dB). increases or remains constant as the digital input increases.

Rev. C | Page 7 of 16
AD1856 Data Sheet

THEORY OF OPERATION
The AD1856 is a complete, monolithic, 16-bit PCM audio DAC. The resistors that form the ladder structure are fabricated with
No additional external components are required for operation. silicon-chromium thin film. Laser trimming of these resistors
As shown in the block diagram in Figure 1, each chip contains further reduces linearity error, resulting in low output distortion.
a voltage reference, an output amplifier, a 16-bit DAC, a 16-bit The output amplifier uses both MOS and bipolar devices to
input latch, and a 16-bit serial-to-parallel input register. produce low offset, high slew rate, and optimum settling time.
The voltage reference consists of a band gap circuit and buffer When combined with the on-board feedback resistor, the output
amplifier. This circuitry produces an output voltage that is stable op amp can convert the output current of the AD1856 to a
over time and temperature changes. voltage output.
The 16-bit digital-to-analog converter uses a combination of a
segmented decoder and R-2R architectures to achieve consistent
linearity and differential linearity.

Rev. C | Page 8 of 16
Data Sheet AD1856

ANALOG CIRCUIT CONSIDERATIONS


+5V
GROUNDING RECOMMENDATIONS
+VL +VS
The AD1856 has two ground pins, designated analog and digital 3 16

ground (AGND and DGND). The analog ground pin is the high AD1856
quality ground reference point for the analog portion of the 2 8 1 12
DGND –VL –VS AGND
device. The digital ground pin returns ground current from the

00759-004
digital logic portions of the AD1856 circuitry. Both pins should GROUND

be connected directly to a single solid ground plane, and the –5V

components should be placed around the AD1856 so that analog Figure 3. Alternate Recommended Schematic
and digital return currents do not cross each other. A single solid Given that these two supplies are within the range of ±5 V to
ground plane with good parts placement and trace routing yields ±12 V, they can be used to power the AD1856. In this case, the
the quietest design with the best signal integrity and EMI/EMC positive logic and positive analog supplies can both be connected
specifications. to the single positive supply. The negative logic and negative analog
POWER SUPPLIES AND DECOUPLING supplies can both be connected to the single negative supply.
Performance benefits from a measure of isolation between the
The AD1856 has four power supply input pins. +VS and −VS
supplies, introduced by using simple low-pass filters in the
provide the supply voltages to operate the linear portions of the
individual power supply leads.
DAC, including the voltage reference, output amplifier, and
control amplifier. The +VS and −VS supplies are designed to As with most linear circuits, changes in the power supplies affect
operate from ±5 V to ±12 V. the output of the DAC. Analog Devices recommends that well-
regulated power supplies with less than 1% ripple be incorporated
The +VL and −VL pins supply power to the digital portions of
into the design of any system using these devices.
the chip, including the input shift register and the input latching
circuitry. The +VL and −VL supplies are also designed to operate TOTAL HARMONIC DISTORTION
from ±5 V to ±12 V, subject only to the limitation that +VL cannot The THD figure of an audio DAC represents the amount of
be more positive than +VS, and −VL cannot be more negative undesirable signal produced during reconstruction and play-
than −VS. back of an audio waveform. The THD specification, therefore,
Decoupling capacitors should be used on all power supply pins. provides a direct method for classifying and choosing an audio
Furthermore, good engineering practice suggests that these DAC for a desired level of performance.
capacitors be placed as close as possible to the package pins. The Analog Devices tests and grades all AD1856 devices on the
decoupling for both the bipolar logic supply, ±VL, and the bipolar basis of THD performance. A block diagram of the test setup
analog supply, ±VS, should be returned to the closest ground pins. is shown in Figure 4. In this test setup, a digital data stream,
The use of four separate power supplies reduces feedthrough representing a 0 dB, −20 dB, or −60 dB sine wave, is sent to the
from the digital portion of the system to the linear portions of device under test. The frequency of this waveform is 990.5 Hz.
the system, thus contributing to good performance. However, Input data is sent to the AD1856 at a 4× fS rate (176.4 kHz). The
four separate voltage supplies are not necessary for good circuit AD1856 under test produces an analog output signal with the
performance. For example, Figure 3 illustrates a system where on-board op amp.
only a single positive and a single negative supply are available.

23 CYCLES
4× fS
DATA
RATE AD1856 ±3V
16-BIT DATA
DIGITAL VOUT
WAVEFORM LE
GENERATOR CLK
990.5Hz 30kHz
NOTCH LOW-PASS
0 1 0 0 0 1 FILTER FILTER
OUTPUT 1 1 1 1 1 0
1 1 0 1 0 1
4096 PT. . . . . . .
FFT . . . . . . DIGITIZER
ANALYZER . . . . . .
1 1 0 0 1 0
1 0 1 0 1 1
0 0 1 1 1 0
00759-005

4096
SAMPLES

Figure 4. Block Diagram of Distortion Test Circuit

Rev. C | Page 9 of 16
AD1856 Data Sheet
0.100
The automatic test equipment digitizes 4096 samples of the
output test waveform, incorporating 23 complete cycles of the 0.050

TOTAL HARMONIC DISTORTION (%)


sine wave. A 4096-point FFT is performed on the results of the
test. Based on the first nine harmonics of the fundamental
0.020
990.5 Hz output wave, the total harmonic distortion of the –20dB
device is calculated. Neither a deglitcher nor an MSB trim is
0.010
used during the THD test.
The circuit design, layout, and manufacturing techniques used 0.005

in the production of the AD1856 result in excellent THD perfor-


FULL SCALE
mance. Figure 5 shows the typical unadjusted THD performance 0.002

00759-007
of the AD1856 for various amplitudes of a 1 kHz output signal.
As shown in Figure 5, the AD1856 offers excellent performance, 0.001
1 100 1k 10k
even at amplitudes as low as −60 dB. Figure 6 shows the typical FREQUENCY (Hz)
THD vs. frequency performance. Figure 6. Typical THD vs. Frequency
10.0
OPTIONAL MSB ADJUSTMENT
Use of an optional adjustment circuit allows residual differential
TOTAL HARMONIC DISTORTION (%)

1.0 linearity errors around midscale to be eliminated. These errors


are especially important when low amplitude signals are being
reproduced. In these cases, as the signal amplitude decreases,
0.1 the ratio of the midscale differential linearity error to the signal
amplitude increases and THD increases.
16 BITS Therefore, for best performance at low output levels, the optional
0.01
MSB adjustment circuitry shown in Figure 7 can be used. This
circuit allows the differential linearity error at midscale to be
00759-006

zeroed out. However, no adjustments are required to meet data


0.001
–60 –50 –40 –30 –20 –10 0 10 sheet specifications.
AMPLITUDE (dB)
470kΩ 100kΩ 200kΩ
TRIM 15 1 –VS

00759-008
Figure 5. Typical Unadjusted THD vs. Amplitude
MSB ADJ 14

Figure 7. Optional MSB Adjustment Circuit

Rev. C | Page 10 of 16
Data Sheet AD1856

DIGITAL CIRCUIT CONSIDERATIONS


INPUT DATA Figure 9 provides the specific timing requirements that must be
Data is transmitted to the AD1856 in a bit stream composed met for the data transfer to be accomplished properly.
of 16-bit words with a serial, MSB first format. Three signals The input pins of the AD1856 are both TTL and 5 V CMOS
must be present to achieve proper operation: the data, clock, compatible, independent of the power supply voltages used.
and latch enable signals. Input data bits are clocked into the The input requirements illustrated in Figure 8 and Figure 9
input register on the rising edge of the clock signal. The LSB is are compatible with the data outputs provided by popular DSP
clocked in on the 16th clock pulse. When all data bits are loaded, filter chips used in digital audio playback systems. The AD1856
a low-going latch enable pulse updates the DAC input. Figure 8 input clock can run at a 10 MHz rate. This clock rate allows data
illustrates the general signal requirements for data transfer for transfer rates for 2×, 4×, or 8× oversampling reconstruction. The
the AD1856. Applications of the AD1856 PCM Audio DAC section provides
additional guidelines for using the AD1856 with various DSP
CLK
filter chips.

M L
DATA S S
B B
00759-009

LE

Figure 8. Signal Requirements of the AD1856

>100ns

>30ns >30ns

CLK
>15ns
>60ns

>40ns >40ns

LATCH
ENABLE (LE)
>50ns
INTERNAL DAC INPUT REGISTER
>15ns >15ns UPDATED WITH 16 MOST RECENT BITS

MSB LSB NEXT


DATA 1ST BIT 2ND BIT 16TH BIT WORD
00759-010
BITS CLOCKED INTO
SHIFT REGISTER

Figure 9. Timing Relationships of Input Signals

Rev. C | Page 11 of 16
AD1856 Data Sheet

APPLICATIONS OF THE AD1856 PCM AUDIO DAC


The AD1856 is a versatile digital-to-analog converter designed The architecture illustrated in Figure 10 is suitable for low-end
for applications in consumer digital audio equipment. Portable, home or portable systems. However, its usefulness in mid-quality
car, and home compact disc players, digital audio amplifiers, and or high-quality digital audio reproduction is limited by the phase
DAT systems can all use the AD1856. Popular circuit architectures delay that is introduced in the multiplexed output. This phase delay
in these systems include stereo playback sections featuring one is due to the fact that the information contained in the input bit
DAC per system, one DAC per audio channel (left/right), or even stream represents left and right channel audio sampled simulta-
multiple DACs per channel. Furthermore, these architectures use neously but reconstructed alternately. One solution to this problem
different output reconstruction rates to accomplish these functions, is to incorporate a third, noninverting SHA to delay the output
including reproduction at the sample rate (1 × fS), at twice the of one channel so that it can catch up to the other channel. This
sample rate (2 × fS), at four times the sample rate (4 × fS), and solution eliminates the phase shift by restoring simultaneous
even at eight times the sample rate (8 × fS). For CD applications, reproduction. This solution is illustrated in Figure 12.
fS is 44.1 kHz; for DAT applications, fS is 48 kHz.
SAMPLE LOW-
LEFT
ONE DAC PER SYSTEM LEFT SHA SHA PASS
FILTER
OUTPUT

Figure 10 shows a circuit using one AD1856 per system to repro- AD1856
duce both stereo channels of a typical first-generation digital DATA VOUT
CLK
audio system. The input data is fed to the AD1856 in a format LE

that alternates between left channel data and right channel data. LOW-
RIGHT
The output of the AD1856 is switched between the left channel SHA PASS

00759-013
SAMPLE OUTPUT
FILTER
and right channel output sample-and-hold amplifiers (SHAs). RIGHT

The SHAs demultiplex and deglitch the output of the AD1856. Figure 12. Third SHA Eliminates Phase Delay
The timing diagram for the control signals for this circuit is
shown in Figure 11.
ONE DAC PER CHANNEL
Another approach used to eliminate phase delay between left and
right channels uses one DAC per channel. In this architecture, the
LOW-
PASS
LEFT input data bit streams for the left channel and the right channel
SAMPLE
1/2
FILTER
OUTPUT
are simultaneously sent and latched into each DAC. This second-
LEFT
AD712
generation approach, shown in Figure 13, is suitable for higher
AD1856
DATA VOUT performance digital audio playback units.
CLK
LE AD1856
LOW- LEFT DATA VOUT
RIGHT DATA CLK
PASS
OUTPUT
00759-011

SAMPLE FILTER LE
RIGHT 1/2
AD712 LOW-
LEFT
PASS
OUTPUT
Figure 10. AD1856 in a One DAC per System Architecture 1/2
FILTER
AD712
AD1856
RIGHT DATA VOUT
CLK DATA CLK
LE
LOW-
RIGHT
PASS 00759-014
OUTPUT
FILTER
1/2
DATA AD712

Figure 13. One DAC per Channel Architecture


LEFT WORD RIGHT WORD

LE

1.5µs MIN 1.5µs MIN

DAC
OUT

SAMPLE
RIGHT
00759-012

SAMPLE
LEFT

Figure 11. Control Signals for One DAC Circuit

Rev. C | Page 12 of 16
Data Sheet AD1856
TWO DACs PER CHANNEL (FOUR-DAC SYSTEM) AD1856
DATA VOUT
Another architecture uses two DACs per channel. In this CLK
LE LOW-
scheme, shown in Figure 14, each DAC reproduces one half of SHA PASS
LEFT
OUTPUT
the output waveform. The advantage obtained is that midscale AD1856 1/2
FILTER
DATA VOUT
differential linearity error no longer affects the zero-crossing CLK
AD712
LE
points of the waveforms. These effects are shifted to the points
where the output waveform crosses ±3/4 full scale. The result
AD1856
is that THD performance for low amplitude signals is greatly DATA VOUT
improved. Not shown in Figure 14 is a VLSI circuit, which is CLK
LE LOW-
required to separate the incoming data into the appropriate SHA PASS
RIGHT
OUTPUT
AD1856 FILTER
form required by each DAC. DATA
1/2
VOUT

00759-015
AD712
CLK
LE

Figure 14. Two DACs per Channel Eliminate Midscale Distortion


from the Zero-Crossing Points

Rev. C | Page 13 of 16
AD1856 Data Sheet

DIGITAL FILTERING AND OVERSAMPLING


Oversampling is a term that refers to playback techniques in Oversampling techniques require that the serial input data
which the reconstruction frequency used is an integral (2 or stream run at the same integral multiple of the original data rate.
more) multiple of the original quantized data rate. For example, Therefore, although the constraints on the output low-pass filter
in compact disc stereo digital audio playback units, the original are eased, the constraints on the serial digital input port and the
quantized data sample rate is 44.1 kHz. Popular oversampling settling time of the output stage are not.
rates are 2× fS or 4× fS, yielding reconstruction rates of 88.2 kHz The actual oversampling operation takes place in the digital filter
and 176.4 kHz, respectively. chip, which is located upstream from the DAC. The digital filter
Oversampling is used to ease the performance constraints of accepts data from the media and adds the additional reconstruction
the low-pass filters that usually follow the reconstruction DAC. points according to the algorithm and coefficients stored in the
In any signal reconstructed from sampled data, undesired filter chip. Because the digital filters actually interpolate these
frequency components are introduced in the output spectrum; additional reconstruction points, they are called interpolation
these components are centered at the reconstruction frequency. filters.
When a 44.1 kHz reconstruction frequency is used, the actual ACHIEVING 8× fS OVERSAMPLING WITH TWO
frequency band of interest is 20 Hz to 20 kHz. However, a AD1856 DEVICES AND THE YAMAHA YM3414
band of undesired image frequency components extends from
Figure 15 illustrates the combination of a Yamaha YM3414
approximately 24 kHz to 44.1 kHz; there is additional undesired
digital filter chip and two AD1856 audio DACs. In this scheme,
component energy between 44.1 kHz and 64 kHz. These undesired
the use of a 16.9344 MHz clock allows an 8× oversampling rate
components must be removed with a low-pass filter of very high
for extremely high performance. In addition, a lower order low-
order. First-generation digital audio systems often use low-pass
pass filter can be used without sacrificing performance. The DAC
filters of 9, 11, and even 13 poles. Linear implementations of these
input data is simultaneously transmitted to the input registers of
filters are expensive, difficult to manufacture, and can produce
the DACs through dedicated left and right channel output pins on
distortion due to varying group delay characteristics.
the YM3414. Optional sample-and-hold signals are also provided.
When a 2× reconstruction frequency (88.2 kHz) is used, the 16.9344MHz
lowest undesired frequency components extend down to approx- +5V
CLK LOW-
imately 68 kHz. A 4× rate (176.4 kHz) has undesired components LE VOUT PASS
LEFT
OUTPUT
TD FILTER
extending down to approximately 156 kHz. The filter response WCO DATA
DLO
required to remove these frequency components can be less steep. YM3414
BCO
AD1856
This means that a lower order filter can be used, resulting in less DRO
SHR SHL
distortion at lower cost. Linear filters with three or five poles are DATA
LE VOUT
LOW-
PASS
RIGHT
OUTPUT
adequate and are quite common in digital audio products that use CLK FILTER

oversampling techniques. OPTIONAL


AD1856

00759-017
DEGLITCH
SIGNALS

Figure 15. Yamaha YM3414 and AD1856 Interface

Rev. C | Page 14 of 16
Data Sheet AD1856

OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)


BSC 45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)

0.10 (0.0039) 0°
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

03-27-2007-B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 16. 16-Lead Standard Small Outline Package [SOIC_W]


Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model 1 Temperature Range THD at Full-Scale Output Package Description Package Option
AD1856RZ −25°C to +70°C 0.008% 16-Lead SOIC_W RW-16
AD1856RZ-REEL −25°C to +70°C 0.008% 16-Lead SOIC_W RW-16
AD1856RZ-REEL7 −25°C to +70°C 0.008% 16-Lead SOIC_W RW-16
AD1856RZ-K −25°C to +70°C 0.0025% 16-Lead SOIC_W RW-16
AD1856RZ-K-REEL7 −25°C to +70°C 0.0025% 16-Lead SOIC_W RW-16
1
Z = RoHS Compliant Part.

Rev. C | Page 15 of 16
AD1856 Data Sheet

NOTES

©1988–2013 Analog Devices, Inc. All rights reserved. Trademarks and


registered trademarks are the property of their respective owners.
D00759-0-2/13(C)

Rev. C | Page 16 of 16

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