SSP7N60B/SSS7N60B

SSP7N60B/SSS7N60B
600V N-Channel MOSFET

General Description Features

These N-Channel enhancement mode power field effect • 7.0A, 600V, RDS(on) = 1.2Ω @VGS = 10 V
transistors are produced using Fairchild’s proprietary, • Low gate charge ( typical 38 nC)
planar, DMOS technology. • Low Crss ( typical 23 pF)
This advanced technology has been especially tailored to • Fast switching
minimize on-state resistance, provide superior switching • 100% avalanche tested
performance, and withstand high energy pulse in the • Improved dv/dt capability
avalanche and commutation mode. These devices are well • TO-220F package isolation = 4.0kV (Note 6)
suited for high efficiency switch mode power supplies.

G
TO-220 TO-220F
G DS GD S
SSP Series SSS Series
S

Absolute Maximum Ratings TC = 25°C unless otherwise noted

Symbol Parameter SSP7N60B SSS7N60B Units

VDSS Drain-Source Voltage 600 V
ID Drain Current - Continuous (TC = 25°C) 7.0 7.0 * A
- Continuous (TC = 100°C) 4.4 4.4 * A
IDM Drain Current - Pulsed (Note 1) 28 28 * A
VGSS Gate-Source Voltage ± 30 V
EAS Single Pulsed Avalanche Energy (Note 2) 420 mJ
IAR Avalanche Current (Note 1) 7.0 A
EAR Repetitive Avalanche Energy (Note 1) 14.7 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 5.5 V/ns
PD Power Dissipation (TC = 25°C) 147 48 W
- Derate above 25°C 1.18 0.38 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
Maximum lead temperature for soldering purposes,
TL 300 °C
1/8" from case for 5 seconds
* Drain current limited by maximum junction temperature

Thermal Characteristics
Symbol Parameter SSP7N60B SSS7N60B Units
RθJC Thermal Resistance, Junction-to-Case Max. 0.85 2.6 °C/W
RθCS Thermal Resistance, Case-to-Sink Typ. 0.5 -- °C/W
RθJA Thermal Resistance, Junction-to-Ambient Max. 62.5 62.5 °C/W

©2002 Fairchild Semiconductor Corporation Rev. B, June 2002

 SSP7N60B/SSS7N60B
Electrical Characteristics TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 600 -- -- V
∆BVDSS Breakdown Voltage Temperature
ID = 250 µA, Referenced to 25°C -- 0.65 -- V/°C
/ ∆TJ Coefficient
IDSS VDS = 600 V, VGS = 0 V -- -- 10 µA
Zero Gate Voltage Drain Current
VDS = 480 V, TC = 125°C -- -- 100 µA
IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA

On Characteristics
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 2.0 -- 4.0 V
RDS(on) Static Drain-Source
VGS = 10 V, ID = 3.5 A -- 1.0 1.2 Ω
On-Resistance
gFS Forward Transconductance VDS = 40 V, ID = 3.5 A (Note 4) -- 8.2 -- S

Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, VGS = 0 V, -- 1380 1800 pF
Coss Output Capacitance f = 1.0 MHz -- 115 150 pF
Crss Reverse Transfer Capacitance -- 23 30 pF

Switching Characteristics
td(on) Turn-On Delay Time -- 30 70 ns
VDD = 300 V, ID = 7.0 A,
tr Turn-On Rise Time -- 80 170 ns
RG = 25 Ω
td(off) Turn-Off Delay Time -- 125 260 ns
tf Turn-Off Fall Time (Note 4, 5) -- 85 180 ns
Qg Total Gate Charge VDS = 480 V, ID = 7.0 A, -- 38 50 nC
Qgs Gate-Source Charge VGS = 10 V -- 6.4 -- nC
Qgd Gate-Drain Charge (Note 4, 5) -- 15 -- nC

Drain-Source Diode Characteristics and Maximum Ratings

IS Maximum Continuous Drain-Source Diode Forward Current -- -- 7.0 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 28 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 7.0 A -- -- 1.4 V
trr Reverse Recovery Time VGS = 0 V, IS = 7.0 A, -- 415 -- ns
Qrr Reverse Recovery Charge dIF / dt = 100 A/µs (Note 4) -- 4.6 -- µC

Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 15.7mH, IAS = 7.0A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD ≤ 7.0A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
6. Only for back side in Viso = 4.0kV and t = 0.3s

©2002 Fairchild Semiconductor Corporation Rev. B, June 2002

 SSP7N60B/SSS7N60B
Typical Characteristics

VGS
Top : 15.0 V
10.0 V
1 8.0 V
10 10
1
7.0 V
6.5 V
6.0 V
5.5 V
Bottom : 5.0 V

ID, Drain Current [A]

ID, Drain Current [A]

o
150 C
0
10
0
10
o
25 C
o
※ Notes :
-55 C ※ Notes :
1. 250μ s Pulse Test 1. VDS = 40V
-1 2. 250μ s Pulse Test
10 2. TC = 25℃

-1
10
10
-1
10
0
10
1 2 4 6 8 10

VDS, Drain-Source Voltage [V] VGS, Gate-Source Voltage [V]

Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics

1
4 10
VGS = 10V
Drain-Source On-Resistance

IDR, Reverse Drain Current [A]

RDS(ON) [Ω ],

3
VGS = 20V

0
2 10

150℃ 25℃
1 ※ Notes :
1. VGS = 0V
※ Note : TJ = 25℃ 2. 250μ s Pulse Test

0 10
-1

0 5 10 15 20 25 0.2 0.4 0.6 0.8 1.0 1.2 1.4

ID, Drain Current [A] VSD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs Figure 4. Body Diode Forward Voltage

Drain Current and Gate Voltage Variation with Source Current
and Temperature

3000 12
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
2500 10 VDS = 120V

VDS = 300V
VGS, Gate-Source Voltage [V]

2000 8 VDS = 480V

Ciss
Capacitance [pF]

1500 6

1000 Coss 4
※ Notes :
1. VGS = 0 V
500 Crss 2. f = 1 MHz 2
※ Note : ID = 7.0 A

0 0
10
-1
10
0
10
1 0 5 10 15 20 25 30 35 40

VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC]

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics

©2002 Fairchild Semiconductor Corporation Rev. B, June 2002

 SSP7N60B/SSS7N60B
Typical Characteristics (Continued)

1.2 3.0

2.5
Drain-Source Breakdown Voltage

1.1

Drain-Source On-Resistance
BV DSS , (Normalized)

RDS(ON) , (Normalized)
2.0

1.0 1.5

1.0

0.9 ※ Notes :
1. VGS = 0 V
※ Notes :
2. ID = 250 μ A 0.5 1. VGS = 10 V
2. ID = 3.5 A

0.8 0.0
-100 -50 0 50 100 150 200 -100 -50 0 50 100 150 200
o o
TJ, Junction Temperature [ C] TJ, Junction Temperature [ C]

Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation

vs Temperature

2
10
2
10 Operation in This Area Operation in This Area
is Limited by R DS(on) is Limited by R DS(on)

100 µs
100 µs10 µs
1
10
1
10 1 ms
1 ms
10 ms
ID, Drain Current [A]
ID, Drain Current [A]

10 ms
100 ms
DC 0
0
10 DC
10

-1
-1 10 ※ Notes :
10 ※ Notes :
o o
1. TC = 25 C 1. TC = 25 C
o o
2. TJ = 150 C 2. TJ = 150 C
3. Single Pulse 3. Single Pulse
-2 -2
10 10
0 1 2 3 0 1 2 3
10 10 10 10 10 10 10 10

VDS, Drain-Source Voltage [V] VDS, Drain-Source Voltage [V]

Figure 9-1. Maximum Safe Operating Area Figure 9-2. Maximum Safe Operating Area
for SSP7N60B for SSS7N60B

6
ID, Drain Current [A]

0
25 50 75 100 125 150
TC, Case Temperature [℃]

Figure 10. Maximum Drain Current

vs Case Temperature

©2002 Fairchild Semiconductor Corporation Rev. B, June 2002

 SSP7N60B/SSS7N60B
Typical Characteristics (Continued)

(t), T h e r m a l R e s p o n s e
10

D = 0 .5
※ N o te s :
1 . Z θ J C (t) = 0 .8 5 ℃ /W M a x .
2 . D u ty F a c to r, D = t 1 /t 2
0 .2 3 . T J M - T C = P D M * Z θ J C (t)
-1
10 0 .1

0 .0 5

0 .0 2 PDM
θ JC

0 .0 1 t1
s in g le p u ls e
Z

t2
-2
10

-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11-1. Transient Thermal Response Curve for SSP7N60B

(t), T h e rm a l R e s p o n s e

D = 0 .5
0
10

0 .2 ※ N o te s :
1 . Z θ J C (t) = 2 .6 ℃ /W M a x .
0 .1 2 . D u ty F a c to r, D = t 1 /t 2
3 . T J M - T C = P D M * Z θ J C (t)
0 .0 5
-1
10
0 .0 2
PDM
0 .0 1
θ JC

t1
Z

t2
s in g le p u ls e
-2
10

-5 -4 -3 -2 -1 0 1
10 10 10 10 10 10 10
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11-2. Transient Thermal Response Curve for SSS7N60B

©2002 Fairchild Semiconductor Corporation Rev. B, June 2002

 SSP7N60B/SSS7N60B
Gate Charge Test Circuit & Waveform

VGS
Same Type
50KΩ
as DUT Qg
12V 200nF
300nF 10V
VDS
VGS Qgs Qgd

DUT
3mA

Charge

Resistive Switching Test Circuit & Waveforms

RL VDS
VDS 90%

VGS VDD
RG

10%
VGS
10V DUT
td(on) tr td(off)
tf
t on t off

Unclamped Inductive Switching Test Circuit & Waveforms

L BVDSS
1
VDS EAS = ---- L IAS2 --------------------
2 BVDSS - VDD
BVDSS
ID
IAS
RG
VDD ID (t)

10V DUT VDD VDS (t)

tp
tp Time

©2002 Fairchild Semiconductor Corporation Rev. B, June 2002

 SSP7N60B/SSS7N60B
Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT +

VDS

I SD
L

Driver
RG
Same Type
as DUT VDD

VGS • dv/dt controlled by RG

• ISD controlled by pulse period

Gate Pulse Width

VGS D = --------------------------
Gate Pulse Period 10V
( Driver )

IFM , Body Diode Forward Current

I SD
( DUT ) di/dt

IRM

Body Diode Reverse Current

VDS
( DUT ) Body Diode Recovery dv/dt

VSD VDD

Body Diode
Forward Voltage Drop

©2002 Fairchild Semiconductor Corporation Rev. B, June 2002

 SSP7N60B/SSS7N60B
Package Dimensions

TO-220
9.90 ±0.20 4.50 ±0.20
1.30 ±0.10

(8.70)

2.80 ±0.10
(1.70)

+0.10
ø3.60 ±0.10 1.30 –0.05

18.95MAX.
(3.70)

15.90 ±0.20
9.20 ±0.20

(1.46)

(3.00)
(45°
)
(1.00)
13.08 ±0.20

10.08 ±0.30

1.27 ±0.10 1.52 ±0.10

0.80 ±0.10 +0.10

0.50 –0.05 2.40 ±0.20
2.54TYP 2.54TYP
[2.54 ±0.20] [2.54 ±0.20]

10.00 ±0.20

Dimensions in Millimeters

©2002 Fairchild Semiconductor Corporation Rev. B, June 2002

 SSP7N60B/SSS7N60B
Package Dimensions (Continued)

3.30 ±0.10
TO-220F
10.16 ±0.20 ø3.18 ±0.10 2.54 ±0.20
(7.00) (0.70)

6.68 ±0.20

15.87 ±0.20
15.80 ±0.20

(1.00x45°)

MAX1.47
9.75 ±0.30

0.80 ±0.10
(3
0°
)

#1
0.35 ±0.10 +0.10
0.50 –0.05 2.76 ±0.20
2.54TYP 2.54TYP
[2.54 ±0.20] [2.54 ±0.20]
4.70 ±0.20

9.40 ±0.20

Dimensions in Millimeters

©2002 Fairchild Semiconductor Corporation Rev. B, June 2002

 TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.

ACEx™ FASTr™ OPTOLOGIC® SMART START™ UltraFET®

Bottomless™ FRFET™ OPTOPLANAR™ SPM™ VCX™
CoolFET™ GlobalOptoisolator™ PACMAN™ STAR*POWER™
CROSSVOLT™ GTO™ POP™ Stealth™
DOME™ HiSeC™ Power247™ SuperSOT™-3
EcoSPARK™ I2C™ PowerTrench® SuperSOT™-6
E2CMOS™ ISOPLANAR™ QFET™ SuperSOT™-8
EnSigna™ LittleFET™ QS™ SyncFET™
FACT™ MicroFET™ QT Optoelectronics™ TinyLogic™
FACT Quiet series™ MicroPak™ Quiet Series™ TruTranslation™
FAST® MICROWIRE™ SLIENT SWITCHER® UHC™
STAR*POWER is used under license

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury to the user.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In This datasheet contains the design specifications for
Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

©2002 Fairchild Semiconductor Corporation Rev. H6

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™ FASTr™ OPTOLOGIC  SMART START™ VCX™
Bottomless™ FRFET™ OPTOPLANAR™ SPM™
CoolFET™ GlobalOptoisolator™ PACMAN™ Stealth™
CROSSVOLT™ GTO™ POP™ SuperSOT™-3
DOME™ HiSeC™ Power247™ SuperSOT™-6
EcoSPARK™ I2C™ PowerTrench  SuperSOT™-8
E2CMOSTM ISOPLANAR™ QFET™ SyncFET™
EnSignaTM LittleFET™ QS™ TinyLogic™
FACT™ MicroFET™ QT Optoelectronics™ TruTranslation™
FACT Quiet Series™ MicroPak™ Quiet Series™ UHC™
FAST  MICROWIRE™ SILENT SWITCHER  UltraFET 

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H7
This datasheet has been download from:

www.datasheetcatalog.com

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