1st International Conference on Electrical & Electronic Engineering (ICEEE)

04-06 November 2015, RUET, Rajshahi, Bangladesh

Optimized Design of Full-Subtractor Using New SRG

Reversible Logic Gates and VHDL Simulation
Md. Samiur Rahman Sajjad Waheed, Ali Newaz Bahar
Dept. of Information and Communications Technology Dept. of Information and Communications Technology
Mawlana Bhashani Science and Technology University Mawlana Bhashani Science and Technology University
Tangail, Dhaka Tangail, Dhaka
samiur.rahman.mbstu@gmail.com swaheed.iu@gmail.com, alinewazbahar@gmail.com

Abstract—Reversible logic has comprehensive applications in circuits are constructed using reversible logic gates. These
communications, quantum computing, low power VLSI design, reversible circuits not only produce unique output vector from
computer graphics, cryptography, nanotechnology and optical each input vector but also the input can be reconstructed from
computing. It has received significant attention in low power the outputs. A reversible circuit should be designed using a
dissipating circuit design in the past few years. While several minimum number of reversible gates. Fan-out and loops are
researchers have inspected the design of reversible logic units, not allowed in reversible logic circuits [3]. However fan-out
there is not much reported works on reversible subtractors. In and feedback can be achieved by using additional gates. The
this paper we proposed the quantum equivalent circuit for SRG synthesis of a reversible logic circuit should have the
(SRG refers to Samiur Rahman Gate) gate and we have
following optimization parameters [4], [5], [6], [7], [8], [9],
computed the quantum cost of SRG gate. We also showed that
how SRG gate can work singly as a Full-subtractor circuit. It is [10], [11], [12], [13].
being tried to design the circuit optimal in terms of number of
reversible gates, number of garbage outputs, number of constant • Minimum number of gates
inputs and quantum cost with compared to the existing circuits. • Minimum number of garbage outputs
All the designs have nanometric scales. • Minimum number of constant inputs
• Minimum number of quantum costs
Keywords—reversible logic; reversible gate; quantum
computing; quantum cost; nanotechnology based systems;
Decimal addition plays an important role in various
microprocessors and other future computing circuits.
I. INTRODUCTION Therefore circuits designed to perform decimal addition using
binary methods must be fast and must incorporate the required
Reversible logic has received great attention in the recent correction to produce accurate decimal sum. The present paper
years due to its ability to reduce the power dissipation. proposes an optimized design of a full-subtractor using new
Quantum arithmetic components need reversible logic circuits reversible logic gates. The proposed full-subtractor is
for their construction. Reversible logic circuits find wide constructed using a minimum number of reversible logic gates
application in low power digital design, quantum computing and it produces the least number of garbage outputs, minimum
and nanotechnology. In 1960 R.Landauer demonstrated that number quantum cost compared to other existing circuits and
high technology circuits and systems constructed using therefore it can be used to build up more complex arithmetic
irreversible hardware results in energy dissipation due to circuits using reversible logic gates. This paper is organized as
information loss. According to Landauer’s principle, the loss follows: Section II gives the brief introduction to some of the
of one bit of information dissipates kTln2 joules of energy important basic reversible logic. In section III the new gates
where k is the Boltzmann’s constant and T is the absolute used in the proposed design of full-subtractor circuits are
temperature at which the operation is performed [1]. Later explained. In section IV, the conventional full-subtractor
Bennett, in 1973, showed that in order to avoid kTln2 joules circuit and its implementation described. Section V gives the
of energy dissipation in a circuit it must be built up from reversible logic implementation of the proposed designs of
reversible circuits [2]. this full-subtractor also the comparison of proposed design
with other existing circuits. Finally section VI concludes with
A reversible logic gate is an n-input, n-output logic device a scope for further research.
with one-to-one mapping. Reversible

978-1-4673-7819-2/15/$31.00©2015 IEEE
 II. REVERSIBLE LOGIC III. PROPOSED REVERSIBLE GATES

At present there are many 3x3 reversible logic gates such Fig.3 and Fig.4 show a SRG (SRG refers to Samiur
as Fredkin gate, Toffoli gate, Double Feynman gate, Peres Rahman Gate) gate. The input vector is I (A, B, C, D) and the
gate [3], [4], [5], [6], [7], [8]. The quantum cost of each
output vector is O (P, Q, R, S).P =A⊕C, Q =A⊕B, R
reversible logic gate is an important optimization parameter
[7].The quantum cost of a 1x1 reversible gate is assumed to be =A’B⊕A’C⊕BC and S=A⊕B⊕C⊕D. The full-subtractor
zero. The quantum cost of a 2x2 reversible logic gate is taken using SRG is obtained with D=0 and its quantum cost is equal
as unity. The quantum cost of other reversible gates is to 7. Let
calculated by counting the number of V, V+ and CNOT gates
present in their quantum circuit. V is the square root of NOT B ⊕ ⊕ Q=A⊕C
(SNR) gate and V+ is its Hermitian. The V and V+ quantum
gates have the following properties: A ⊕ P=A⊕B
V * V = NOT (1) C1 C2 C3
V * V+ = V + * V = 1 (2) C V V+ V R=A’B⊕A’C⊕B
V+* V+ = NOT (3)
D ⊕ ⊕ S=A⊕B⊕C⊕D
SRN and (Hermitian Matrix of SRN) and EX-OR gate on the
same line generates symmetric gate pattern has a cost of 1. Fig. 3. Quantum implementation of SRG gate
The synthesis of a reversible logic circuit should have the
following important reversible logic [6], [7], [8], [9], [10], B Q=A⊕C
[11], [12], [13]:
A P=A⊕B
• Equal number of input states and output states SRG
• Preserves an unique mapping between input and output C R=A’B⊕A’C⊕BC
vectors for any reversible circuit
• One or more operations can be united called reversible D S=A⊕B⊕C⊕D
gate
Fig. 4. SRG gate
• (N x N) Reversible gate has N number of inputs and N
number of outputs where N= {1, 2, 3, …}
TABLE I. TRUTH TABLE OF PROPOSED REVERSIBLE SRG
GATE
Encoded data is represented by qubits rather than bits Din A B C D P Q R S Dout
which can perform certain calculations exponentially faster 0 0 0 0 0 0 0 0 0 0
than conventional computing. Quantum computation uses 1 0 0 0 1 0 0 0 1 1
matrix multiplication rather than conventional Boolean 2 0 0 1 0 0 1 1 1 7
operations and the information measurement is realized by 3 0 0 1 1 0 1 1 0 6
4 0 1 0 0 1 0 1 1 11
calculating the state of qubits.The matrix operations over 5 0 1 0 1 1 0 1 0 10
qubits are simply specified by using quantum primitives in 6 0 1 1 0 1 1 1 0 14
Fig.1 and Fig.2. 7 0 1 1 1 1 1 1 1 15
8 1 0 0 0 1 1 0 1 13
A A 9 1 0 0 1 1 1 0 0 12
10 1 0 1 0 1 0 0 0 8
11 1 0 1 1 1 0 0 1 9
B ⊕ A⊕B 12 1 1 0 0 0 1 0 0 4
13 1 1 0 1 0 1 0 1 5
Fig. 1. Quantum XOR Operation 14 1 1 1 0 0 0 1 1 3
15 1 1 1 1 0 0 1 0 2
1000
0100 A. Functional Verification of The Quantum Implementation
UCN= 0001 of The SRG Gate
0010
We have functionally verified the working of the
proposed quantum implementation of the SRG gate. The
Fig. 2. Equivalent matrix for XOR
output P of the SRG gate is equal to A⊕B, the output Q is

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 equal to A⊕C, the output R is equal A’B⊕A’C⊕BC and the
output S is equal to A⊕B⊕C⊕D thus the functionality of the D=Xi-Yi-Bin (4)
outputs P, Q and S is easy to verify. The path of the outputs R Bout = 1 If Xi <(Yi + Bin) (5)
And logic equations are,
consists of V + and V gates thus cannot be directly verified
D = A⊕B⊕C (6)
and the path of the outputs P consists of V gates thus cannot Bout = A’B⊕A’C⊕BC (7)
be directly verified. In order to verify the output R, we use the
truth table of the SRG gate which is shown in Table I, and
compare the expected output with the output produced. For
the path from input C to output R, the controlled signals of V +
and V gates are labeled as C1, C2 and C3 as shown in Fig.3.
A small illustration of the verification of the output R is
shown below for two input combinations in which the
inversion and identity properties of V and V + gates will be Fig. 6. Full-subtractor
utilized (the properties of V and V + gates working as an NOT
gate. V. RESULTS AND DISCUSSION

A. Reversible Logic Implementation of Full-Subtractor

B. Reversible Mapping
Circuit
Reversible are circuits (gates) that have one-to-one
In Fig. 4 a novel design of full-subtractor using only one
mapping between vectors of inputs and outputs; thus the
SRG gate is shown. As you see, if input vector is (A, B, C, 0)
vector of input states can be always reconstructed from the
then the output vector will be (A, B, Diff, Borr) shows in Fig.
vector of output states. In truth table of proposed reversible
8. Constructing the above circuit requires one gate that
SRG gate, here input vector I (A, B, C, D) and output vector
generates only one garbage output. According to the previous
O (P, Q, R, S) and decimal input set {0,1, 2, 3, 4, 5, 6, 7, 8, 9,
section, the quantum cost of SRG is only 7, so the quantum
10, 11, 12, 13, 14, 15} is equal to output set {0, 1, 7, 6, 11,
cost of the proposed full-subtractor circuit is only 7 showing
10, 14, 15, 13, 12, 8, 9, 4, 5, 3, 2}. There are four reversible
in Fig.7. Table II is the truth table of proposed full-subtractor
sets {2, 7, 15}, {3, 6, 14}, {4, 11, 9, 12} and {5, 10, 8, 13}
circuit. Full-Subtractor circuit:
shows in Table I and Fig. 5.
Diff = A⊕B⊕C (8)
2 3 Borr = A’B⊕A’C⊕BC (9)

B P=A⊕C
6
7 14 A Q=A⊕B
15 SRG
4 5
C R=A’B⊕A’C⊕BC

0 S=A⊕B⊕C
12 13 10
11
Fig. 7. Proposed reversible full-subtractor circuit

TABLE II. TRUTH TABLE OF FULL-SUBTRACTOR

8
9
A B C D=0 P Q Borr Diff
Fig. 5. Reversible mapping 0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 1
IV. CONVENTIONAL FULL-SUBTRACTOR CIRCUIT 0 1 0 0 0 1 1 1
0 1 1 0 1 1 1 0
1 0 0 0 1 1 0 1
Fig.6 show a full-subtractor is a combinational 1 0 1 0 0 1 0 0
circuit which is used to perform subtraction of three bits. It 1 1 0 0 1 0 0 0
has three inputs, Xi (minuend) and Yi(subtrahend) and Bin 1 1 1 0 0 0 1 1
(subtrahend) and two outputs D (difference) and Bout (borrow).

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 VI. CONCLUSIONS
B. VHDL Implementation
In this research, we implemented the quantum
LIBRARY ieee ; representation of the SRG gate for the first time and we
USE ieee.std_logic_1164.all ; utilized it in constructing a new reversible full-subtractor
ENTITY Subtractor IS Port(A, B, C, D: in std_logic; circuit. We showed that the proposed reversible circuit is
P, Q, R,S : out std_logic); better than the existing circuits in literature. Furthermore, we
END Subtractor ; synthesized a novel reversible full-subtractor circuit. This
ARCHITECTURE ckt OF Subtractor IS proposed work can be used for designing large reversible
BEGIN systems which is the necessary requirement of
P<= A xor C; nanotechnology based systems and quantum computers. All
Q<= A xor B; the scales are in the nanometric area.
R<= (not A and B) xor (not A and C) xor (B and C);
S<= A xor B xor C; REFERENCES
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Existing circuit [15] 3 2 1 8
Proposed Design 1 2 1 7

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