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Summary of Lecture 2 (Week 3) : OH DD in DD OL OH OL

The document discusses a lecture on the electronic analysis of inverters made of NMOS and PMOS transistors. It explains that for DC analysis, the input voltage is slowly varied to measure the output, while transient analysis assumes a time-varying input voltage. It then analyzes the behavior of NMOS and PMOS transistors at different input voltages to determine the output voltage levels and explain the logic levels. Threshold voltages and saturation regions of the transistors are also analyzed to determine the voltage level at which both transistors operate in saturation, which is defined as the midpoint voltage.

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Hammad Satti
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29 views

Summary of Lecture 2 (Week 3) : OH DD in DD OL OH OL

The document discusses a lecture on the electronic analysis of inverters made of NMOS and PMOS transistors. It explains that for DC analysis, the input voltage is slowly varied to measure the output, while transient analysis assumes a time-varying input voltage. It then analyzes the behavior of NMOS and PMOS transistors at different input voltages to determine the output voltage levels and explain the logic levels. Threshold voltages and saturation regions of the transistors are also analyzed to determine the voltage level at which both transistors operate in saturation, which is defined as the midpoint voltage.

Uploaded by

Hammad Satti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Sir I am not feeling well due to vomiting and severe headache I may not be able to take session if I will

not be able to take it then I am sorry.

SUMMARY OF LECTURE 2 (WEEK


3)
In this lecture we have learnt about the electronic analysis of inverter (made up of nmos and
pmos) so in case of DC analysis we have to take input slowly but for output it is not measured
immediately whether it is measure when the input is stabilized but for transient analysis the
scenario is different we have to assume a function of a time for input, hence output changes
respectively. For Dc analysis consider a low voltage for input then Vin will be zero hence nmos
will be off while pmos will be conducting current so output (V OH=VDD). While when the input
voltage is high (Vin= VDD) then it will be opposite to the case of low voltage for input hence the
VOL will be zero. While logic swing output will be the difference btw V OH and VOL . Hence we can
say that:
VGSN = Vin
VSGp = VDD - Vin
The nmos remains in cut off region until following condition is met V in <= VTH hence the pmos will
be the conducting so the output voltage will be equal to V DD. As Vin increases the nFet is on while
the Pfet is still conducting hence we will see decrease in V SGp hence the efficiency of the device
decreases. The pmos remain in cut off region if V in = VDD - |VTp| then output voltage will be zero,
hence it is high logic. To make sure that input voltage does not overlap the output voltage then
we use voltage noise margins
1. VNMH= VOH – VlH
2. VNMHL= VIL - VOL
These noise margins tell us about the stability of inputs and lesser the Nosie margin is better
will be the efficiency of the device.

If the input voltage is greater than the voltage at the mid-point then it is considered as the logic
high side and vice versa. If we say that mid-point voltage, input voltage, output voltage is same
then all transistor have equal drain currents. In order to calculate the mid-point voltage we have
to find the mode of operation of the Mosfets.

Consider a Nmos then


Vsat= VGSn - VTH
VGSn= Vin =VM
So,
Vsat= VM - VTH
And
VDSn= Vout = VM
So, for checking saturation region
Vsat< VDSn
So by putting equations of Vsat and VDSn we get:
VM> VM - VTH
Its true, hence the condition is satisfied so we can say that the nmos is in saturation region.

Consider Pmos then


Vsat= VSDp - |VTp|= VDD - Vin - |VTp|
VSDp= VDD – Vout = VM – Vout
And
Vsat <= VSDp
Put euqations of Vsat and VSDp then we get

- |VTp|<= 0

The condition is satisfied hence the pmos is in the saturation region.

As
IDN =IDP
Hence bu putting values and re-arranging them we get final result as
Bn/Bp =[ Kn* *(W/L)n]/[ Kp* *(W/L)p]

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