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Summary of Lecture 2 (Week 4) : 1. Fall Time

This lecture discusses rise time and fall time calculations for digital circuits. Rise time is defined as the time required for a signal to rise from 10% to 90% of its final value, while fall time is the time to fall from 90% to 10%. The lecture derives equations to calculate rise time and fall time for an inverter circuit based on its output capacitance and the resistances of the NMOS and PMOS transistors. It is shown that the fall time and rise time are both approximately 2.2 times the RC time constant of the inverter. The minimum period and maximum operating frequency of the inverter are also defined in terms of rise and fall times.

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31 views

Summary of Lecture 2 (Week 4) : 1. Fall Time

This lecture discusses rise time and fall time calculations for digital circuits. Rise time is defined as the time required for a signal to rise from 10% to 90% of its final value, while fall time is the time to fall from 90% to 10%. The lecture derives equations to calculate rise time and fall time for an inverter circuit based on its output capacitance and the resistances of the NMOS and PMOS transistors. It is shown that the fall time and rise time are both approximately 2.2 times the RC time constant of the inverter. The minimum period and maximum operating frequency of the inverter are also defined in terms of rise and fall times.

Uploaded by

Hammad Satti
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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SUMMARY OF LECTURE 2(WEEK

4)
In this lecture we have studied about the concept of rise and fall time and how to calculate it. As rise
time is the time required for a signal to rise from zero and vice versa for the fall time.

For

1. FALL TIME
Let’s assume that the Vin is zero as well as VDD at time equal to zero so initially at output we will get:

Vout (0) = VDD

When we switch on our inverter then we will see that nmos is in the active region while the pmos
will be in cutoff region.

i = - Cout (dVout)/dt

From Ohms Law we can say that:

I = Vout/Rn

So,

(Vout/Rn )= - Cout (dVout)/dt

(dVout /Vout) = - dt /(Cout* Rn)

Integrate both sides with limits V out(0) to Vout(t) then will get,

ln [Vout(t)] – ln[Vout(0)] = - t /(Cout* Rn)

As Vout (0) = VDD so,

ln [Vout(t)/VDD] = - t /(Cout* Rn)

Now take antilog of the above equation then we will get,

(Vout(t)/VDD) = e- t /(Cout* Rn)

As (Cout* Rn) is equal to Tn hence,

(Vout(t)/VDD) = e- t / Tn

From the graph shown on the right side we can say that:

1. V1 is approx. 90% if VDD


2. V0 is approx. 10% if VDD

The time equation is as follows:


t = Tn * ln [VDD/Vout(t)]

As we can see that tf = ty – tx, so

tf = Tn * {ln [VDD/(0.1 *VDD)] - ln [VDD/(0.9 *VDD)]}

Hence,

tf = 2.2*Tn

2. RISE TIME
Let’s assume that the V is zero as well as V at time equal to zero so initially at output we will get:

Vout (0) = V

Hence the nmos will be off so current will be,

i = - Cout (dVout)/dt

As,

I = (VDD –Vout)/Rp

[(VDD –Vout)/Rp ]=- Cout (dVout)/dt

(dVout /(VDD –Vout)) = - dt /(Cout* Rp)

Integrate both sides with limits V out(0) to Vout(t) then will get,

ln [(VDD –Vout)/VDD] = - t /(Cout* Rp)

As tp = (Cout* Rp)

So,

Vout(t) = VDD [ 1 – e-t/tp]

As from the graph we can see that,

tr = T v – T u

tr = Tp * {ln [VDD/VDD-(0.9 *VDD)] - ln [VDD/VDD-(0.1 *VDD)]}

tr = 2.2 Tp
Hence,

Tmin = tf + tr

So,

Maximum freq. = F = 1/ Tmin = 1/( tf + tr)

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