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SAE TECHNICAL
PAPER SERIES 2000-01-3603

Design and Implementation of a Digital

Controller for DC-to-DC Power Converters
John Sustersic, John R. (Jack) Zeller and Zhiqiang Gao
The Advanced Engineering Research Laboratory, Cleveland State University

Robert Button
NASA Glenn Research Center

Reprinted From: Proceedings of the SAE Power

Systems Conference 2000
(P-359)

SAE Power Systems Conference

San Diego, California
October 31 - November 2, 2000

400 Commonwealth Drive, Warrendale, PA 15096-0001 U.S.A. Tel: (724) 776-4841 Fax: (724) 776-5760
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2000-01-3603

Design and Implementation of a Digital Controller For DC-to-

DC Power Converters
John Sustersic, John R. (Jack) Zeller and Zhiqiang Gao
The Advanced Engineering Research Laboratory, Cleveland State University

Robert Button
NASA Glenn Research Center

ABSTRACT OBJECTIVE

A digital signal processor (DSP) solution is proposed to The principle goal of this effort is to demonstrate the
control an H-bridge DC-DC isolated output power following device-level improvements in an open-ended,
converter. The multiple mode digital controller is digital configuration that will easily allow for the
evaluated with an existing Westinghouse 1-kW power development and implementation of a number of system-
stage. The digital controller was developed using the level objectives.
dSPACE [1] rapid prototype development system and
MATLAB/Simulink. It is evaluated using a real-time DEVICE LEVEL IMPROVEMENTS -
digital control development platform that included the
actual Westinghouse converter power stage. Preliminary 1. Real-time optimization and adaptive compensation of
digital controller performance is presented that warrants the converter for varying load and/or line conditions.
continued investigation and development of this 2. Digital control to provide active compensation for
application of digital control and supports the use of the mismatched FETs and/or aging components in the
DSP as a viable component in Power Management and converter bridge.
Distribution (PMAD) applications. 3. Software implementation of under voltage protection,
thereby eliminating inefficient hardware protection
INTRODUCTION methods.
4. Greatly improved portability to other converters.
The burgeoning interest in digitally controlled DC-DC 5. Possibility of implementing optimized active filter
power conversion is represented by the growing volume technology.
of literature on the subject [2-12]. The interest is strong in
the aerospace industry, especially at NASA, for several SYSTEM LEVEL IMPROVEMENTS - A digital control
reasons. First, efficient DC-DC power conversion is system architecture will include features to improve fault-
critically important in all space platforms, especially tolerance and improve overall system performance.
manned spacecraft. Second, all space borne systems Such an architecture might involve a single DSP device
require extensive telemetry data from all elements of the controlling several DC-DC converters, with several such
system. These requirements increase the cost and the systems operating concurrently. Each DSP would be
complexity of all elements of the space system and responsible for its assigned converters in addition to the
further increase the expenditures of time and money monitoring of other devices. This architecture would
required for sophisticated systems integration. Third, the allow for the following system capabilities or
high costs associated with the deployment of space improvements:
systems constantly point research toward new
technologies that promise to reduce the size and weight 1. Optimization of parallel converters under widely
of system components while increasing overall system varying load conditions.
reliability and lowering integration costs. As outlined in 2. Controller redundancy to maintain converter
the following work, digitally controlled DC-DC power operation in case of a DSP failure.
conversion promises advantages in all of these areas. 3. Independent verification of each converter’s
operation by secondary controllers.
4. Improved scalability.
5. Active load balancing.
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6. Improved telemetric capabilities. converter is maintained through two phase-locked PWM

7. In situ frequency-domain analysis (FFT) of converter signals.
operations.
8. Early identification of potential device failures.
9. Improvement in overall system reliability and
stability.
10. Active impedance control.

DIGITAL CONTROLLER DEVELOPMENT

The approach selected to develop this digital control

architecture includes several key steps. First, a simple Figure 2 – Bi-Phase PWM Signal Definition, 2*tc = T,
mathematical model of the system was developed as the PWM Phase 1 duty cycle = ta/tc, PWM Phase 2 duty cycle
initial basis of the controller design. Second, the digital = tb/tc. All units in seconds.
control development platform was interfaced to the
power converter. Third, the preliminary controller The converter requires alternating assertions of these
resulting from the simulation analysis was further PWM signals to drive an AC current through the
developed using the digital control development platform transformer primary. Each PWM signal switches a high-
and dSPACE’s extensions to Simulink, the Real-Time side FET and the opposing low-side FET in the H-bridge.
Workshop (RTW). Finally, the control algorithm Asserting a particular PWM signal activates that set of
developed in this environment was programmed in native FETs, allowing current to flow in one direction through
C code to avoid limitations of the Simulink/RTW the transformer. Asserting the opposite PWM signal
environment and thereby improve overall controller allows current to flow in the opposite direction. The duty
performance. cycle of each PWM signal is directly proportional to the
time current is flowing through the transformer during
MODELING AND SIMULATION each half-cycle. Ideally, both PWM signals would be
balanced. However, the transconductance of the FETs
The modeling of DC-DC converters has resulted in may vary by a factor of two nominally, and this
several linearized [15-18] and quasi-linearized [19] imbalance may result in a DC current component
solutions. These solutions generally consider only buck- through the transformer primary. Since this current may
boost class converters that require only a single Pulse saturate the transformer core and limit it’s ability to
Width Modulation (PWM) input. However, the converter transmit power, the duty cycles of the driving PWM
system to be studied in this research is significantly more signals must be adjusted to compensate. Figure 2
complicated. Its model will include a series of linear and illustrates an exaggerated case of current imbalance to
non-linear blocks. The non-linear blocks can be quite completely define these two control signals. The top
complicated, especially the H-bridge block and the step- waveform of figure 2 is a uniform square wave of period
down isolation transformer block. However, since an T and 50% duty cycle. The middle waveform is one
objective of this investigation is a real-time digital control PWM channel and the lower waveform is the second
development platform that uses the actual converter, it is channel. Time tc exactly equals 0.5T. The duty cycle of
not necessary to precisely model the plant. Instead, a channel one is define as ta/tc. The duty cycle of channel
simple model was used to roughly test the proposed two is defined as tb/tc. Both of these quantities are strictly
control system. limited to the range 0 ≤ t ≤ 1 . However, the FETs exhibit
a finite turn-off time, and it is possible that duty cycles
CONTROLLER DESIGN near 1 may result in a shoot-through condition where
FETs on one side of the H-bridge may momentarily be
conducting simultaneously. These effects may damage
or destroy converter components and must be avoided.
Therefore, conventional designs implement a dead-band
between the PWM phases. The dead-band used in this
application is 5%. Therefore, the actual range of PWM
duty cycles in this application is 0 ≤ t ≤ 0.95 .

Implementing the current mode control begins with

calculating the current mode error. This is done by
sensing the current through the transformer and
Figure 1 – Controller Block Diagram integrating it to determine the average (DC) transformer
primary current. A PI current loop controller is then used.
A two-loop PI controller (Figure 1) was developed for the The controller output is limited to restrict its control
initial testing of the digital controller. Control of the authority, and then differentially combined with the
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voltage loop controller output to determine the two PWM addition to the three aforementioned feed back variables,
duty cycles. the input and output currents are also sensed. These
currents will be used for further control development and
The outer voltage loop is again a PI controller with feed for real-time input and output power measurements.
forward of the converter input voltage. In this application,
the error signal drives a PI controller with a proportional HP 6050A DC-DC DCS150-20
gain near zero and an integral gain between 50 and 500. DC Electronic Power
The output of the traditional PI control is then normalized 120 VDC
Load Converter
by dividing it by the converter input voltage. This result is 1 kW 40 Amp
hard-limited to the range of +/- 1, then linearly scaled into
the range between zero and one. This is the PWM duty
cycle output of the voltage loop controller, and is then CPLD
dSPACE PC host
combined with the output of the current mode controller TMS320C DSP & ADCs
to form the two bi-phase PWM signals.

Additionally, all integration operations in the control Figure 4 – Real-Time Digital Control Development
implementation provide mechanisms that limit the Platform Block Diagram
integration and prevent integrator run-up. All limits in the
controller are implemented by checking the limited This research utilizes a dSPACE DSP rapid-prototype
variable against a programmed maximum (or minimum) development system based on the TMS320C40 DSP by
value and assigning the maximum (or minimum, Texas Instruments that provides 60 Mflops performance.
respectively) value if the variable exceeds the limit. The dSPACE system includes the DS1003 Modular DSP
board, the DS2001 High Resolution ADC board, the
Finally, the controller implementation uses limited DS2102 high-Resolution DAC board, and the DS4002
Boolean logic to shut down the converter under adverse Timing and Digital I/O board. This configuration provides
input line conditions. the following capabilities:

DIGITAL DC-DC CONVERTER ARCHITECTURE AND • Five ADC channels with 16-bit resolution and a
dSPACE SYSTEM TESTBED (FIGURES 3 &4) sampling time of 6.2 microseconds.
• Six DAC channels with 16-bit resolution and a
The H-bridge DC-DC galvanically isolated power settling time of 2.0 microseconds.
converter uses four FET switches to modulate filtered • Single and/or three-phase PWM generation and
input power through a transformer. measurement.
• Eight programmable digital I/O lines with 200ns
resolution.
• Thirty-two additional digital I/O lines.

A Sorenson [13] Model DCS150-20 provides the nominal

120 VDC, 10 amps required by the Westinghouse
converter. The testbed employs a Hewlett-Packard [14]
Model 6050A DC Electronic load with the appropriate
Current Isolation load modules. GPIB interfaced oscilloscopes with
Gate Drivers sensor amplifier isolated probes and other GPIB instrumentation round
and out the testbed.

CPLD PWM integrator ADC In interfacing the converter to the digital control
Generation ADC development platform, a minimum of signal processing
circuitry was used to scale and condition the measured
variables for digitization and use in the controller. The
DSP
circuitry was developed using Analog Devices AD210
Figure 3 - Basic H-Bridge and Conceptual Diagram Isolation Amplifiers. Two pole Butterworth filters are used
on the voltage feedback channels to eliminate aliasing.
To adapt this system to digital control, it is necessary to
digitize both the output voltage and to sense and digitize The Hall effect devices that measure the current signals
the transformer current. These voltages are galvanically provide the necessary electrical isolation. For the current
isolated from the digitization circuitry to avoid ground loop feedback path, an F. W. Bell CLN-100 Hall effect
loops. Additionally, the transformer primary current must current-mode sensor is employed, providing a bandwidth
be sensed to allow current-mode control. As outlined in of 160 KHz. An analog integrator is used to determine
the previous section, it is actually the DC value of the the DC offset current in the transformer primary. For the
primary current that is used in the control algorithm. In
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input and output current measurements, F. W. Bell model power conversion. Furthermore, the CPLD approach
BB-100 Hall-Effect current sensors are employed. provides hardware-guaranteed phase lock between the
two PWM signals; a software-based generation algorithm
DIGITAL PWM GENERATION could be corrupted by an operating system failure in a
multi-processing controller. Finally, the CPLD based
In preparing the converter and the dSPACE system for PWM generator relieves the DSP of potentially significant
the hardware-in-the-loop simulation, it was discovered processor bandwidth demands, freeing the DSP for
that there was no direct way to maintain the phase lock advanced control computations, and other system-level
between the two PWM channels that are required in the distributed PMAD functions such as communication.
H-bridge. Using the dSPACE DSP hardware to
accomplish this would involve writing a low-level driver to The digital PWM signal generation circuit was fabricated
guarantee that the two PWM signals were never using an Altera 7000S family device and the CSU printed
simultaneously asserted. circuit board prototyping capabilities. The final device
offers quartz-crystal accuracy in PWM signal generation
50 MHz Clock with a resolution of less than 20 nanoseconds.
Phase
1 PRELIMINARY RESULTS
DSP Four Control Output
Data 8-bit Logic and Drivers The Simulink/RTW–based control algorithm proved
Register PWM state Phase useful as a proof-of-concept study and was effective in
machine 2 controlling the system under low power (<100 watts)
CPLD conditions. However, technical restrictions on the
language of the environment resulted in an inefficient
Figure 5 – PWM Generation algorithm that was limited to a 2 kHz update frequency.
This limitation required that the controller be
It was decided that a better solution would involve implemented with smaller PI gains, effectively reducing
developing an Hardware Definition Language (HDL) the controller bandwidth. Subsequently, the control
program with which to program a complex programmable algorithm was manually coded into a native C program
logic device (CPLD) that would interface to a digital and downloaded directly into dSPACE’s DSP processor.
output from dSPACE’s DSP and generate the The native C controller executed easily at 25 kHz,
appropriate PWM signals. This novel CPLD architectural utilizing only 33% of the CPU bandwidth, and ensured
approach was designed to offer software-selectable that the controller would provide an updated PWM duty
switching frequencies and a PWM resolution of eight bits ratio for each switching cycle. In addition to providing all
per PWM channel. Furthermore, the device was the functionality of the Simulink/RTW–based controller,
designed with the flexibility to allow for future the C control also provided programmable running
improvements. Figure 5 shows the functional block averaging on all feedback variables. After a cursory
diagram of the PWM generation circuitry. The PWM investigation of the effects of varying the number of
generation is controlled via four 8-bit registers as samples, the researchers selected a three sample
indicated in figure 5. Two registers hold the PWM duty running average for this digital control application.
cycle for each of the two phase-locked channels. The
third register holds the divisor for the modulo-n clock The resultant digital controller demonstrated an average
generator circuit. The fourth register is reserved for output regulation better than 0.2% throughout the full
future expansion and may be used in part to increase the power range of the converter. Controller performance in
PWM resolution. Using the 50 MHz clock in this three fundamental measures of power regulation was
implementation, the maximum attainable PWM frequency measured and is documented in the following
of the phase-locked PWM outputs is 100 kHz. paragraphs. Each of these performance
Additionally, the phase is generated with quartz-crystal characterizations is presented for identical digital
accuracy. The granularity of this implementation is better controllers using two distinct integral gains in the voltage
than 20 nanoseconds. PI controller. The values used are Ki =25 and Ki = 100.
The current-mode control, switching frequency, sampling
The additional expense of utilizing a CPLD in this rate, and sampling average is identical in all cases as
application is easy to justify. Most importantly, the documented previously. The HP Infinium oscilloscope
architecture of the CPLD-based PWM generator ensures used for these characterizations is set to utilize its built-in
that the PWM signals continue in the event of a DSP bandwidth-limiting filter to clearly show controller
software failure. Under this condition, the PWM duty response. The vertical scale of all graphs is 5 volts per
cycles will not change significantly and the converter will division.
continue to provide a voltage output near the specified
value. This allows the DSP time to restart and regain
regulation of the converter without necessarily disrupting
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STEADY STATE CONTROLLER RESPONSE on decreasing load transients. However, the faster time-
constant of the higher bandwidth controller is clearly
The digital controller demonstrates good steady-state evident by comparing the recovery time of the two
performance under the indicated conditions for both controllers. The faster controller requires only 25
controller implementations. The results are shown milliseconds to recover from the decreasing load and 50
graphically in figures 6(a) and 6(b). Both controllers
indicate an average output value of 27.86 volts.
Interestingly, the standard deviation in the output voltage
for the lower-bandwidth controller (Ki = 25) is only 10
millivolts, compared to the 23.9 millivolts of the higher-
bandwidth controller (Ki = 100).

Figure 7a – Load Transient Response, Vset = 28 volts Iload

= 2 to 10 amps, Ki = 100.

milliseconds for the increasing load. The slower

controller requires approximately 125 milliseconds to
recover from both transient cases. Again, the average
Figure 6a – Steady-state controller response, Vset = 28 output voltage of both controllers is the same.
volts Iload = 10 amps, Ki = 100.

Figure 7b – Load Transient Response, Vset = 28 volts Iload

Figure 6b – Steady-state controller response, Vset = 28 = 2 to 10 amps, Ki = 25.
volts Iload = 10 amps, Ki = 25.
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
Line transient response was determined using the
Load transient response was determined using the Sorenson DC power supply’s period transient generator.
HP6050A electronic load and its periodic transient This produced line transients from 100 volts to 125 volts.
generator. As shown in figures 7(a) and 7(b), the digital The results are shown in figures 8(a) and (b). As in the
controller exhibits good response to load transients. Both load transient cases studied, the effect of the different
controllers have similar output voltage fall-off on controller bandwidth is clearly evident. However, the
increasing load transients and similar voltage over-shoot magnitudes of the output voltage transients are different
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for the two controllers. The higher bandwidth controller These data clearly indicate that the feed forward control
shows output transients of one volt in magnitude in implementation used in this controller improves the
response to the 25% input transients. The lower magnitude of the input line voltage induced output
bandwidth controller exhibits output transients of voltage transient by approximately 50% and reduces the
approximately 3 volts in response to the same input duration of the disturbance by 25% to 50%.
transients.

Figure 8a – Line Transient Response, Vset = 28 volts Iload =

10 amps, Vin = 100 volts to 125 volts, Ki = 100. Figure 9 – Line Transient Response With and Without
Feed Forward Control, Vset = 28 volts Iload = 10 amps, Vin =
100 volts to 125 volts, Ki = 100.

CONCLUDING REMARKS

This paper documents the elements of a research

program to develop a DSP-based digital controller for a
high power DC-to-DC converter. The controller
developed features a novel architecture in which a CPLD
device is used for PWM generation. Separating this
converter function from the control DSP eases the DSP’s
computational load and provides a level of system fault
tolerance. Evaluations of the initial selected control
strategies show fast transient recovery for load and line
disturbances and the potential for stable, tight steady-
state output voltage regulation.

The results obtained thus far have identified several key

Figure 8b – Line Transient Response, Vset = 28 volts Iload = issues that require further investigation. First, the current
10 amps, Vin = 100 volts to 125 volts, Ki = 25. mode controller’s structure and command authority must
be thoroughly studied and refined. Second, the current
Recall that the digital controller developed for this controller’s sensitivity to integral gain seems to indicate
application uses feed forward control on the input voltage that either better noise filtering is needed in the data
to improve line transient response. To test the acquisition or a lead-lag compensator may be required to
effectiveness of this control approach, the line transient increase the system’s phase margin. Third, there are
test was repeated for the high bandwidth controller with indications that the 8-bit resolution per PWM channel
the feed forward control removed. may be near the minimum required in this application.
Fourth, the effect of varying the switching frequency on
Figure 9 illustrates the effectiveness of the feed forward converter input and output impedance should be
control. The bottom trace indicates the identical result analyzed to determine if the switching frequency might
displayed in figure 8(a). The top trace is the performance serve as a viable and useful control handle for the
of the controller without the feed forward control regulating system. Finally, nonlinear control techniques
component using identical test parameters. Both traces should be evaluated to determine the best controller for
are displayed using identical time and voltage scales. this application.
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The digital controller and test bed developed in this 10. C.P. Henze and N. Mohan, “A Digitally Controlled
research is ideally suited to resolve these issues and to AC-DC Power Conditioner That Draws Sinusoidal
help define the hardware and software requirements for Current,” IEEE Power Electronics Specialists
the next generation of digital power conversion Conference, June 1986, pp. 531-540.
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employing powerful DSPs and fast network “Digital Control of DC-DC Converters: Microcontroller
communication, may indeed form the basis of modular, Implementation Issues,” Combined Proceedings of
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Electronics Technology, Powersystems World’96.
ACKNOWLEGMENTS September 1996, pp. 168-180.
12. C.L. Phillips and H.T. Nagle, Digital Control Analysis
The work discussed in this paper is sponsored by the and Design, Prentice-Hall, New Jersey, 1995.
NASA Glenn Research Center under grant #NCC3-699 13. Sorensen, A division of Elgar 9250 Brown Deer
and by Cleveland State University. The work is Road San Diego, CA 92121
conducted in CSU’s Fenn College of Engineering 14. Hewlett-Packard, Palo Alto, CA.
Advanced Engineering Research Laboratory (AERL). 15. R.D. Middlebrook and S. Cuk, “A General Unified
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AERL team including Charles Alexander, Marcelo IEEE Power Electronics Specialists Conference
Gonzales, and Tom Stimac for their help in the Rec., 1976, pp. 18-34.
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Switching Power Stages in Discontinuous
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