Microprocessor and Microcontroller MCQ 6

Microprocessor and microcontroller online test 5
Class: III ECE B
Date:07.06.20
MCQ
1. The instruction, MOV AX, 0005H belongs to the address mode

a) register
b) direct
c) immediate
d) register relative
2. The instruction, MOV AX, 1234H is an example of

a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
3. The instruction, MOV AX,[BX] is an example of

a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
4.The addressing mode that is used in unconditional branch instructions is

a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
5. If a number of instructions are repeating through the main program, then to reduce the
length of the program, __________ is used.
a) procedure
b) subroutine
c) macro
d) none of the mentioned
6. A macro within a macro is called

a) macro-within-macro
b) nested macro
c) macro-in-macro
7. The end of a macro can be represented by the directive.

a) END
b) ENDS
c) ENDM
d) ENDD
8. The instruction, “INC” increases the contents of the specified register or memory location
by
a) 2
b) 0
c) 1
d) 3
9. The instruction that enables subtraction with borrow is

a) DEC
b) SUB
c) SBB
d) None of the mentioned
10. The instruction that is used to convert the result of the addition of two packed BCD
numbers to a valid BCD number is
a) DAA
b) DAS
c) AAA
d) AAS
11) f an interrupt is generated from outside the processor then it is an

a) internal interrupt
b) external interrupt
c) interrupt
12. Example of an external interrupt is

a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
13. The interrupt request that is independent of IF flag is

a) NMI
b) TRAP
c) Divide by zero
d) All of the mentioned
14. During the execution of an interrupt, the data pushed into the stack is the content of
a) IP
b) CS
c) PSW
15. At the end of ISR, the instruction should be

a) END
b) ENDS
c) IRET
d) INTR
16. n the I/O mode, the 8255 ports work as

a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
17. In BSR mode, only port C can be used to

a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
18. The feature of mode 0 is

a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
19. The feature of mode 2 of 8255 is

a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
20. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
21. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
22. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
23. The registers that store the keyboard and display modes and operations programmed by
CPU are
a) I/O control and data buffers
b) Control and timing registers
c) Return buffers
d) Display address registers
24. The sensor RAM acts as 8-byte first-in-first-out RAM in

a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
25. When a key is pressed, a debounce logic comes into operation in

a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
26. The processors used in the multi-microprocessor are

a) coprocessors
b) independent processors
c) coprocessors or independent processors
27. The processor that asks for bus access or may itself fetch the instructions and execute
them is
a) microprocessor
b) coprocessor
c) independent processor
d) coprocessor and independent processor
28. The bus arbitration is handled by an external circuit in

a) loosely coupled system
b) tightly coupled system
c) tightly and loosely coupled system
29 The register that may be used as an operand register is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
30. The architecture of 8051 consists of

a) 4 latches
b) 2 timer registers
c) 4 on-chip I/O ports
31. he register that provides control and status information about counters is
a) IP
b) TMOD
c) TSCON
d) PCON
32. Which of the following is not an addressing mode of 8051?

a) register instructions
b) register specific instructions
c) indexed addressing
d) none
33. The address register for storing the 16-bit addresses can only be
a) stack pointer
b) data pointer
c) instruction register
d) accumulator
34. The instruction, RLA performs

a) rotation of address register to left
b) rotation of accumulator to left
c) rotation of address register to right
d) rotation of accumulator to right
35. The serial communication is

a) cheaper communication
b) requires less number of conductors
c) slow process of communication
36. The number of bits transmitted or received per second is defined as

a) transmission rate
b) reception rate
c) transceiver rate
d) baud rate
37. The bits that control the external interrupts are
a) ET0 and ET1
b) ET1 and ET2
c) EX0 and EX1
d) EX1 and EX2
38. The number of priority levels that each interrupt of 8051 have is
a) 1
b) 2
c) 3
d) 4
39. Which of the following is not one of the SFR addresses of the ports of 8051?
a) 80H
b) 90H
c) A0H
d) NONE
40. The pin that is grounded for interfacing external EPROM is

a) EA(active low)
b) PSEN(active low)
c) OE(active low)

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Microprocessor and microcontroller online test 5

Class: III ECE B

1. The instruction, MOV AX, 0005H belongs to the address mode

2. The instruction, MOV AX, 1234H is an example of

3. The instruction, MOV AX,[BX] is an example of

4.The addressing mode that is used in unconditional branch instructions is

6. A macro within a macro is called

7. The end of a macro can be represented by the directive.

9. The instruction that enables subtraction with borrow is

11) f an interrupt is generated from outside the processor then it is an

12. Example of an external interrupt is

13. The interrupt request that is independent of IF flag is

15. At the end of ISR, the instruction should be

16. n the I/O mode, the 8255 ports work as

17. In BSR mode, only port C can be used to

18. The feature of mode 0 is

19. The feature of mode 2 of 8255 is

24. The sensor RAM acts as 8-byte first-in-first-out RAM in

25. When a key is pressed, a debounce logic comes into operation in

26. The processors used in the multi-microprocessor are

28. The bus arbitration is handled by an external circuit in

30. The architecture of 8051 consists of

32. Which of the following is not an addressing mode of 8051?

34. The instruction, RLA performs

35. The serial communication is

36. The number of bits transmitted or received per second is defined as

40. The pin that is grounded for interfacing external EPROM is

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