lOMoARcPSD|13055590

Mcq Of Computer Organization & Architecture-3340705

Computer Organization And Architecture (Gujarat Technological University)

StuDocu is not sponsored or endorsed by any college or university

Downloaded by Suraj Ingale (svingale2001@gmail.com)
 lOMoARcPSD|13055590

COA IMP Questions Bank

Multiple Choice Questions

Subject: COA
1. CPU has built-in ability to execute a particular set of machine instructions, called as

a. Instruction Set
b. Registers

c. Sequence Set
d. User instructions

2. Opcode indicates the operations to be performed.

a. True

b. False

3. The length of a register is called

a. word limit
b. word size

c. register limit
d. register size

4. The holds the contents of the accessed memory word.

a. MAR

b. MBR
c. PC

d. IR

5. Which of the following is not a visible register?

a. General Purpose Registers
b. Address Register

c. Status Register
d. MAR

6. Which of the following is a data transfer instruction?

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

a. STA 16-bit address

b. ADD A, B

c. MUL C, D
d. RET

7. What is correct instruction if you want the control to go to the location 2000h?
a. MOV 2000h

b. MOV A, 2000h
c. JMP 2000h

d. RET 2000h

8. What kind of a flag is the sign flag?

a. General Purpose
b. Status

c. Address
d. Instruction

9. Brain of computer is
a. Control unit

b. Arithmetic and Logic unit

c. Central Processing Unit

d. Memory

10. Control Unit acts as the central nervous system of the computer.
a. True
b. False

11. What does MBR stand for?

a. Main Buffer Register
b. Memory Buffer Routine
c. Main Buffer Routine
d. Memory Buffer Register

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

12. In the instruction ADD A, B, the answer gets stored in

a. B

b. A
c. C

d. Buffer

13. What does PC stand for?

a. Program Changer
b. Program Counter

c. Performance Counter
d. Performance Changer

14. Which of the following holds the last instruction fetched?

a. PC
b. MAR
c. MBR

d. IR

15. The portion of the processor which contains the hardware required to fetch the operations
is
a. Datapath

b. Processor
c. Control

d. Output unit

16. Causing the CPU to step through a series of micro operations is called
a. Execution
b. Runtime
c. Sequencing
d. Pipelining

17. The functions of execution and sequencing are performed by using

a. Input Signals

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

b. Output Signals
c. Control Signals

d. CPU

18. What does D in the D-flip flop stand for?

a. Digital
b. Direct

c. Delay
d. Durable

19. A is a circuit with only one output but can have multiple inputs.
a. Logic gate

b. Truth table
c. Binary circuit
d. Boolean circuit

20. There are 5 universal gates.

a. True
b. False

21. The Output is LOW if any one of the inputs is HIGH in case of a gate.
a. NOR

b. NAND
c. OR

d. AND

22. Number of outputs in a half adder _

a. 1
b. 2

c. 3
d. 0

23. The gate is an OR gate followed by a NOT gate.

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

a. NAND
b. EXOR

c. NOR
d. EXNOR

24. What is the high speed memory between the main memory and the CPU called?
a. Register Memory

b. Cache Memory
c. Storage Memory

d. Virtual Memory

25. Cache Memory is implemented using the DRAM chips.

a. True
b. False

26. Whenever the data is found in the cache memory it is called as

a. HIT

b. MISS
c. FOUND

d. ERROR

27. LRU stands for

a. Low Rate Usage
b. Least Rate Usage

c. Least Recently Used

d. Low Required Usage

28. When the data at a location in cache is different from the data located in the main
memory, the cache is called
a. Unique
b. Inconsistent
c. Variable

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

d. Fault

29. Which of the following is not a write policy to avoid Cache Coherence?
a. Write through
b. Write within

c. Write back
d. Buffered write

30. Which of the following is an efficient method of cache updating?

a. Snoopy writes

b. Write through
c. Write within
d. Buffered write

31. In mapping, the data can be mapped anywhere in the Cache Memory.
a. Associative
b. Direct

c. Set Associative
d. Indirect

32. The transfer between CPU and Cache is

a. Block transfer

b. Word transfer
c. Set transfer

d. Associative transfer

33. Computer has a built-in system clock that emits millions of regularly spaced electric
pulses per called clock cycles.
a. Second

b. Millisecond
c. Microsecond
d. Minute

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

34. It takes one clock cycle to perform a basic operation.

a. True

b. False

35. The operation that does not involves clock cycles is

a. Installation of a device
b. Execute

c. Fetch
d. Decode

36. The number of clock cycles per second is referred as

a. Clock speed

b. Clock frequency
c. Clock rate
d. Clock timing

37. CISC stands for

a. Complex Information Sensed CPU
b. Complex Instruction Set Computer

c. Complex Intelligence Sensed CPU

d. Complex Instruction Set CPU

38. Which of the following processor has a fixed length of instructions?

a. CISC

b. RISC
c. EPIC

d. Multi-core

39. MAR stands for

a. Memory address register
b. Main address register
c. Main accessible register

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

d. Memory accessible register

40. A circuitry that processes that responds to and processes the basic instructions that are
required to drive a computer system is
a. Memory

b. ALU
c. CU

d. Processor

41. Any electronic holding place where data can be stored and retrieved later whenever
required is _
a. Memory

b. Drive
c. Disk

d. Circuit

42. Cache memory is the onboard storage.

a. True
b. False

43. Which of the following is the fastest means of memory access for CPU?
a. Registers

b. Cache
c. Main memory

d. Virtual Memory

44. The memory implemented using the semiconductor chips is

a. Cache
b. Main

c. Secondary
d. Registers

45. Size of the memory mainly depends on the size of the address bus.
a. Main

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

b. Virtual
c. Secondary

d. Cache

46. Which of the following is independent of the address bus?

a. Secondary memory
b. Main memory

c. Onboard memory
d. Cache memory

47. What is the location of the internal registers of CPU?

a. Internal
b. On-chip
c. External

d. Motherboard

48. is also called auxiliary storage.

a. secondary memory
b. tertiary memory

c. primary memory
d. cache memory

49. Secondary storage virtually has an unlimited capacity because the cost per bit is very low.
a. True

b. False

50. Magnetic tape is a type of access device.

a. Sequential
b. Direct access

c. Step
d. Indirect

51. The magnetic tape is generally a plastic ribbon coated with

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

a. Magnesium oxide
b. Chromium dioxide

c. Zinc oxide
d. Copper oxide

52. The dots on the magnetic tape represent

a. Binary digits

b. Decimal digits
c. Hex digits

d. Oct digits

53. Which of the following is the correct representation for a storage capacity of a tape?
a. Data recording density = Storage capacity
b. Length = Storage capacity
c. Storage capacity= Length * data recording density
d. Storage capacity= Length + data recording density

54. is the amount of data that can be stored on a given length of tape.
a. Storage capacity

b. Length
c. Data recording density

d. Tape density

55. 8. The number of characters/second that can be transmitted to the memory from the tape
is denoted by the term.
a. Data transfer rate

b. Transmission mode
c. Transmission rate

d. Data mode

56. Tape drive is connected to and controlled by

a. Interpreter

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

b. Tape controller
c. CPU

d. Processor

57. is used for writing/reading of data to/from a magnetic ribbon.

a. Magnetic disk
b. Magnetic tape

c. Magnetic frames
d. Magnetic Ribbon

58. Magnetic disk is a sequential access device.

a. True
b. False

59. The disk’s surface is divided into a number of invisible concentric circles called:
a. Drives
b. Tracks

c. Slits
d. References

60. The number of sectors per track on a magnetic disk

a. less than 5

b. 10 or more
c. 8 or more

d. less than 7

61. Generally there are bytes in a sector.

a. 64
b. 128

c. 256
d. 512

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

62. The interval between the instant a computer makes a request for the transfer of data from
a disk system to the primary storage and the instance this operation is completed is called

a. Disk arrival time

b. Disk access time

c. Drive utilization time

d. Disk utilization time

63. Disk access time does not depends on which of the following factors
a. Seek time
b. Latency

c. Transfer rate
d. Arrival rate

64. A Stack-organised Computer uses instruction of

a. Indirect addressing

b. Two-addressing
c. Zero addressing

d. Index addressing

65. PSW is saved in stack when there is a

a. interrupt recognized
b. execution of RST instruction

c. Execution of CALL instruction

d. All of these

66. MIMD stands for

a. Multiple instruction multiple data

b. Multiple instruction memory data

c. Memory instruction multiple data

d. Multiple information memory data

67. A group of bits that tell the computer to perform a specific operation is known as

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

a. Instruction code
b. Micro-operation

c. Accumulator
d. Register

68. The operation executed on data stored in registers is called

a. Macro-operation

b. Micro-operation
c. Bit-operation

d. Byte-operation

69. Status bit is also called

a. Binary bit
b. Flag bit

c. Signed bit
d. Unsigned bit

70. An address in main memory is called

a. Physical address

b. Logical address
c. Memory address

d. Word address

71. A register capable of shifting its binary information either to the right or the left is called
a. parallel register
b. serial register

c. shift register
d. storage register

72. What is the content of Stack Pointer (SP)?

a. Address of the current instruction
b. Address of the next instruction

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

c. Address of the top element of the stack

d. Size of the stack

73. Which of the following interrupt is non maskable

a. INTR

b. RST 7.5
c. RST 6.5

d. TRAP

74. Which of the following is a main memory

a. Secondary Memory
b. Auxiliary Memory

c. Cache Memory
d. Virtual Memory

75. The memory unit that communicates directly with the CPU is called the
a. Main Memory

b. Secondary Memory
c. Shared Memory

d. Auxiliary Memory

76. The addressing mode used in an instruction of the form ADD X Y, is

a. Absolute
b. Indirect

c. Index
d. None of these

77. In a program using subroutine call instruction, it is necessary

a. Initialize program counter
b. Clear the accumulator
c. Reset the microprocessor
d. Clear the instruction register

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

78. The BSA instruction is

a. Branch and Store Accumulator
b. Branch and save return address
c. Branch and shift address

d. Branch and show Accumulator

79. The load instruction is mostly used to designate a transfer from memory to a processor
register known as
a. Accumulator

b. Instruction Register
c. Program counter
d. Memory address Register

80. In case of, Zero-address instruction method the operands are stored in _.
a. Registers
b. Accumulators

c. Push down stack

d. Cache

81. The addressing mode which makes use of in-direction pointers is .

a. Indirect addressing mode

b. Index addressing mode

c. Relative addressing mode

d. Offset addressing mode

82. The addressing mode/s, which uses the PC instead of a general purpose register is
a. Indexed with offset
b. Relative

c. Direct
d. Both A and C

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

83. When we use auto increment or auto decrement, which of the following is/are true
1) In both, the address is used to retrieve the operand and then the address gets altered.
2) In auto increment the operand is retrieved first and then the address altered.
3) Both of them can be used on general purpose registers as well as memory locations.
a. 1,2,3
b. 2

c. 1,3
d. 2,3

84. The addressing mode, where you directly specify the operand value is .
a. Immediate

b. Direct
c. Definite

d. Relative

85. addressing mode is most suitable to change the normal sequence of execution of
instructions.
a. Relative

b. Indirect
c. Index with Offset

d. Immediate

86. The Load instruction does the following operation/s,

a. Loads the contents of a disc onto a memory location
b. Loads the contents of a location onto the accumulators

c. Load the contents of the PCB onto the register

d. Both a and c

87. In a system, which has 32 registers the register id is long

a. 16 bits

b. 8 bits
c. 5 bits

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

d. 6 bits

88. The two phases of executing an instruction are

a. Instruction decoding and storage
b. Instruction fetch and instruction execution

c. Instruction execution and storage

d. Instruction fetch and Instruction processing

89. The Instruction fetch phase ends with

a. Placing the data from the address in MAR into MDR

b. Placing the address of the data into MAR

c. Completing the execution of the data and placing its storage address into MAR
d. Decoding the data in MDR and placing it in IR

90. The condition flag Z is set to 1 to indicate

a. The operation has resulted in an error
b. The operation requires an interrupt call

c. The result is zero

d. There is no empty register available

91. The return address of the Sub-routine is pointed to by .

a. IR

b. PC
c. MAR

d. Special Memory Registers

92. Subroutine nesting means,

a. Having multiple subroutines in a program
b. Using a linking nest statement to put many sub routines under the same name
c. Having one routine call the other
d. None of the above

93. In case of nested subroutines the return addresses are stored in .

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

a. System heap
b. Special memory buffers
c. Processor stack
d. Registers

94. The appropriate return addresses is obtained by the help of in case of nested
routines.
a. MAR
b. MDR

c. Buffers
d. Stack-Pointers

95. When, parameters are being passed on to the subroutines they are stored in .
a. Registers

b. Memory locations
c. Processor stacks

d. All of the above

96. register keeps track of the instructions stored in program stored in memory.
a. AR (Address Register)
b. XR (Index Register)
c. PC (Program Counter)
d. AC (Accumulator)

97. Operation calculating NOT of the OR can be represented as

a. NOT

b. OR
c. NAND
d. NOR

98. RTL stands for:

a. Random transfer language

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

b. Register transfer language

c. Arithmetic transfer language

d. All of these

99. Which operations are used for addition, subtraction, increment, decrement and
complement function:
a. Bus

b. Memory Transfer
c. Arithmetic operation

d. All of these

100. Which language is termed as the symbolic depiction used for indicating the series:
a. Random transfer language
b. Register transfer language

c. Arithmetic transfer language

d. All of these

101. The method of writing symbol to indicate a provided computational process is called
as a:
a. Programming language
b. Random transfer language

c. Register transfer language

d. Arithmetic transfer language

102. In which transfer the computer register are indicated in capital letters for depicting its
function:
a. Memory transfer
b. Register transfer

c. Bus transfer
d. None of these

103. The register that includes the address of the memory unit is termed as the :
a. MAR

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

b. PC
c. IR
d. None of these

104. The register for the program counter is signified as :

a. MAR
b. PC

c. IR
d. None of these

105. How many types of micro operations:

a. 2
b. 4
c. 6

d. 8

106. Which micro operations carry information from one register to another:
a. Register transfer
b. Arithmetic

c. Logical
d. None of these

107. Micro operation is shown as:

a. R1->R2

b. R1<-R2
c. Both

d. None

108. In memory transfer location address is supplied by that puts this on address bus:
a. ALU
b. CPU
c. MAR

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

d. MDR

109. How many types of memory transfer operation:

a. 1
b. 2

c. 3
d. 4

110. Operation of memory transfer are:

a. Read

b. Write
c. Both

d. None

111. Which operation puts memory address in memory address register and data in DR:
a. Memory read
b. Memory write

c. Both
d. None

112. Which operation are implemented using a binary counter or combinational circuit:
a. Register transfer
b. Arithmetic
c. Logical

d. All of these

113. Which operation are binary type, and are performed on bits string that is placed in
register:
a. Logical micro operation

b. Arithmetic micro operation

c. Both
d. None

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

114. In 3 state gate third position termed as high impedance state which acts as:
a. Open circuit

b. Close circuit
c. None of these

d. All of above

115. Arithmetic left shift is used to multiply a signed number by_ :

a. One
b. Two

c. Three
d. All of these

116. In which shift is used to divide a signed number by two:

a. Logical right-shift
b. Arithmetic right shift
c. Logical left shift

d. Arithmetic left shift

117. Two important fields of an instruction are:

a. Opcode
b. Operand

c. Only a
d. Both a & b

118. is the sequence of operations performed by CPU in processing an instruction:

a. Execute cycle

b. Fetch cycle
c. Decode

d. Instruction cycle

119. is the step during which a new instruction is read from the memory:
a. Decode

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

b. Fetch
c. Execute

d. None of these

120. The contents of the program counter is the of the instruction to be run:
a. Data
b. Address

c. Counter
d. None of these

121. ISR stand for:

a. Interrupt save routine
b. Interrupt service routine
c. Input stages routine

d. All of these

122. The OPR field has how many bits:

a. 2
b. 3

c. 4
d. 5

123. RPN stands for

a. Reverse polish notation

b. Read polish notation

c. Random polish notation

d. None of these

124. Which is data manipulation types are:

a. Arithmetic instruction
b. Shift instruction
c. Logical and bit manipulation instructions

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

d. All of these

125. Which is a method of decomposing a sequential process into sub operations:

a. Pipeline
b. CISC

c. RISC
d. Database

126. Asynchronous means:

a. Not in step with the elapse of address

b. Not in step with the elapse of control

c. Not in step with the elapse of data
d. Not in step with the elapse of time

127. is a single control line that informs destination unit that a valid is available
on the bus:
a. Strobe
a. Handshaking
b. Synchronous

c. Asynchronous

128. What is disadvantage of strobe scheme:

a. No surety that destination received data before source removes it
b. Destination unit transfer without knowing whether source placed data on data bus

c. Can’t said
d. Both a & b

129. In technique has 1 or more control signal for acknowledgement that is used
for intimation:
a. Handshaking
b. Strobe

c. Both a & b
d. None of these

Downloaded by Suraj Ingale (svingale2001@gmail.com)

 lOMoARcPSD|13055590

COA IMP Questions Bank

130. In transfer each bit is sent one after the another in a sequence of event and
requires just one line:
a. Serial
b. Parallel

c. Both a & b
d. None of these

131. Modes of transfer b/w computer and I/O device are:

a. Programmed I/O

b. Interrupt-initiated I/O
c. DMA
d. All of these

132. operations are the results of I/O operations that are written in the computer
program:
a. Programmed I/O

b. DMA
c. Handshaking

d. Strobe

133. is a dedicated processor that combines interface unit and DMA as one unit:
a. Input-Output Processor
b. Only input processor

c. Only output processor

d. None of these

134. SIMD stands for:

a. System instruction multiple data

b. Single instruction multiple data

c. Symmetric instruction multiple data

d. Scale instruction multiple data

Downloaded by Suraj Ingale (svingale2001@gmail.com)