2009 Third International Symposium on Intelligent Information Technology Application

Analysis on Capacitor Mismatch and Parasitic Capacitors Effect of Improved

Segmented-Capacitor Array in SAR ADC

Sun Lei, Dai Qinyuan, Qiao Gaoshuai Lee Chuangchuan

Thin Film and Micro fabrication Technology of School of Microelectronics,
Ministry of Education; National Key Laboratory of Shanghai Jiao Tong University,
Nano/Micro Fabrication Technology, Shanghai, China
Shanghai Jiao Tong University, E-mail: lizhangquan@sjtu.edu.cn
Shanghai, China
E-mail: lei.sun@sjtu.edu.cn, qydai@sjtu.edu.cn

Abstract—This paper presents an analysis on capacitor capacitor array avoiding the non-binary- weighted capacitor
mismatch and parasitic capacitors effect of the improved [4]. However, the parasitic capacitors on each side of the
segmented-capacitor array to alleviate the limitation of coupling capacitor and the mismatching of binary
mismatching performance and avoid a non-binary-weighted
weighted-capacitor network have great influence on the
coupling capacitor. Both the matching of binary-weighted
capacitor network and parasitic capacitors on both sides of the attainable resolution which has not yet been analyzed in
coupling capacitor have great influence on the resolution of precise theory. This paper gives a precise analysis on the
ADC system. The relationship among the mismatching of influence which can be provided for circuit designers to
binary-weighted-capacitor network and the parasitic choose process, layout, circuit structure, and capacitor size
capacitors and the attainable resolution of ADC is analyzed by in their design of SAR ADC.
giving precise theoretical demonstration. Therefore, a
theoretical basis is provided for designers to choose process, II. IMPROVED SEGMENTED-CAPACITOR ARRAY SAR ADC
layout, circuit structure, and capacitor size in their design of
The successive approximation ADC usually consists of
SAR ADC.
a sample and hold stage, a digital-to-analog converter
(DAC), a comparator and a successive approximation
register, and it basically implements a binary search
Keywords-Successive Approximation Register (SAR) ADC, algorithm. The principle schematic of the improved
System-on-chip(SOC), Charge Redistribution, Capacitor segmented-capacitor array SAR ADC is shown in Fig.1.
Segmentation. The capacitor array is divided into two parts. In the MSB
part, we add a dummy capacitor C0 parallel with M binary
weighted capacitors. The LSB part only contains L
I. INTRODUCTION capacitors (M=L=n/2, n is the resolution). The coupling
For the comprehensive advantages of SAR ADC in capacitor now is using the unit capacitor C0 . The capacitor
accuracy, speed, power and cost, the increasing equation is as follows:
sophistication of System-on-chip architecture comes an Cmsb = 2M C0 , Cc = C0 (1)
increasing need for SAR ADC. In particular, the CR
(charge-Redistribution) SAR (Successive Approximation L

Register) is widely used in today’s SOC solutions, especially C lsb = ∑C

i =1
i = (2 M − 1) C 0 (2)
as a suitable candidate (in terms of speed, resolution and
circuit complexity) to be integrated to monolithically form
highly sensitive, reliable and intelligent measurement
devices [1]. It is well known that the resolution of the CR
SAR ADC is mainly limited by the matching performance of
its capacitor array [2]. Although this problem may be
mitigated through the adoption of providing high accuracy
capacitors (e.g. poly-to-poly capacitor), it’s normally not
optimized for implementation of such expensive capacitors.
Meanwhile, segmented-capacitor structure is also introduced
to alleviate this problem while introducing a non-binary
coupling capacitor [3]. This non-binary capacitor causes
some bottlenecks on layout and mismatch performance. Figure 1. Block diagram of improved segmented-capacitor array SAR
Thus, it’s significant to introduce an improved segmented- ADC.

978-0-7695-3859-4/09 $26.00 © 2009 IEEE 281

280
DOI 10.1109/IITA.2009.193
 Each conversion is accomplished by a sequence of two C c = C 0 (1 + ε 0 ), C MSB = 2 n /2 C 0 ,
operations: sample and hold mode.
A. Sample Mode
All the capacitors in MSB array are charged to Vin CLSB = 2n/2 C0 − C0 (1 + ε 0 ) (7)
while the comparator is reset to its threshold voltage Vcm
and capacitors in LSB array are ground.
Qx = −Cmsbi(Vin − Vcm) (3)
B. Hold Mode
CMSB C LSB
The dummy capacitor in the MSB array is connected CPL CPR
to ground. The S1and S2 are switched off. The digital codes
are determined by binary searching arithmetic circularly to
control the switches bn-1、b n、…b2、b1 and b0.
n −1
bi
Vx = K i(Vcm − Vin + ∑ Vref ) (4)
i =0 2i
Where,
2n Figure 2. Simplified Structure of the improved segmented-capacitor array
K = (5)
2 + 2 n/2 − 1
n
Due to the charge redistribution procedure is different
The coefficient K has no effect on the linearity of the between MSB and LSB array, we analyze the principle
analog to digital conversion and approximates to 1 as the separately. Firstly, we assume that the comparator threshold
resolution increased. Thus, we can implement 16 bits voltage Vcm is zero which has no effect on our analysis.
resolution by only using two segmented capacitor array for For the MSB capacitor array, the voltage Vx can be
example. The maximum capacitor is 256 C0 which calculated as follow:
alleviates the limitation of capacitor mismatch without M
1
introducing non-binary capacitor. C MSB i{∑ b iVref (1 + ε i )}
i i
i =1 2
III. THE INFLUENCE OF CAPACITOR MISMATCHING AND THE V xMSB =
(C LSB + C PR ) ⋅ C 0 (1 + ε 0 )
PARASITIC CAPACITORS ON EACH SIDE OF THE COUPING C MSB + C PR +
CAPACITOR
C LSB + C PL + C 0 (1 + ε 0 )
M
1
A. Theoretical Analysis = K ` × ( −Vin + ∑2
i=0
i
bi iVref )
We assume that the structure can be simplified as the (8)
M
1
Fig.2 shows. C P l and C P R are the parasitic capacitances + K × (∑
`
bi iε i iVref )
on each side of the coupling capacitor including the parasitic i=0 2i
capacitors on both sides of the coupling capacitor and the
parasitic capacitors on the top plate of the binary-weighted Where,
capacitor array. Obviously, the parasitic capacitors on the
bottom plate of the binary-weighted capacitor array never 2n/2 C0
K `=
have effect on the linearity because they do not contribute {2 C0 − C0 (1 + ε 0 ) + CPL }iC0 (1 + ε 0 )
n /2
(9)
2n/2 C0 + CPR +
charge during the process of charge redistribution. 2n/2 C0 + CPL
Therefore, we only analyze the effect of the parasitic
capacitors on the top plate of the binary-weighted capacitor For the LSB capacitor array, we assume that the
array. As the capacitance is much smaller than each total reference voltage and the input voltage set to 0 due to the
capacitance of MSB and LSB array, we use a smaller principle of superposition in order to simplify our analysis,
capacitor symbol to represent. Suppose that each weighted even though, the voltage Vx is a little complicated.
capacitor C i in MSB and LSB array has a normalized
ratio of (1 + ε i ) relative to the ideal value due to
process variations:
C i = 2 i −1 C 0 (1 + ε i ) , i = 1, 2,...n （6）
Where the unit capacitor C 0 is defined as the total
n/2
capacitance divided by 2 .

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 M
1 2N
CMSB i{∑ i bi iVref (1 + ε i )} δ< (17)
C0 (1 + ε 0 ) i=1 2 2 2N
− 2N − 1
VxLSB = ⋅
CLSB + CPL + C0 (1 + ε 0 ) (C + CPR ) ⋅ C0 (1 + ε 0 )
CMSB + CPR + LSB When the N is becoming larger, the expression can be
CLSB + CPL + C0 (1 + ε 0 )
M M written as (18). In the structure of our improved
1 1 1 1
= × K ` × ∑ i bi iVref + n/2 × K ` × ∑ i bi iε i iVref − segmented-capacitor array, the resolution N is equivalent to
2n/2 i =0 2 2 i =0 2
n/2. Therefore, the limitation of mismatch of capacitors to
CPL M
1 M
1 implementing high resolution has been greatly alleviated.
n/2 n/2
× K `{∑ i bi iVref + ∑ i bi iεi iVref } +
2 C0 ⋅ (2 C0 + CPL ) i =0 2 i=0 2
2N 1
C0 ⋅ ε 0 M
1 M
1 δ< ≈ (18)
× K ` (∑ i bi iVref + ∑ i bi iεi iVref )
2N
(10) 2 − 2N − 1 2N
n/2
2 C0 + CPL i=0 2 i=0 2
E (4) and E (5) is obviously negligible because they are
Therefore, the whole voltage Vx is obtained by adding proportion to result of multiplying relative error and
these contributions from the MSB and LSB capacitor array mismatching ratio, and exponentially inverse proportion to
together, n. E (2) and E (3) is proportion to the reference voltage, so
the total residual voltage is shown. E (2) is the result of the
n−1 parasitic capacitor on the left side of coupling capacitor. E
1
Vx = K`(−Vin + ∑ i bi ⋅Vref ) + E(1) + E(2) + E(3) + E(4) + E(5) (11) (3) is the result of the mismatch of the coupling capacitor.
i=0 2
2n/2C0ε0 − CPL M
1 1
E(2) + E(3) = n/2 n/2
2 C0 ⋅ (2 C0 + CPL )
× K`
∑
i=0 2
b iV
i i ref
2
LSB (19)
Error voltages are shown as follow:
Assume the worst case that all the bits are assigned to 1
M
1 1 M
1 so that the maximum error caused by E(2) and E(3) is
E (1) = K ∑ i bi iVref + n/2 × K ` ∑ i bi iε i iVref
`
(12) required to meet an inequality as (20). Meanwhile, the
i =0 2 2 i =0 2
parasitic capacitors on the right hand of coupling capacitor
have no effect on the linearity.
CPL M
1
E (2) = n /2 n /2
2 C0 ⋅ (2 C0 + CPL )
× K `
∑
i =0 2
b iVref
i i (13) (2 n / 2 − 1) C 0 ε 0 − C P L
C0
(20)
2K `

C0 ⋅ ε 0 M
1 IV. Conclusions
E (3) = n /2
× K ` ∑ i bi iVref (14)
2 C0 + CPL i =0 2 An improved segmented-capacitor array SAR ADC
architecture has been analyzed which can be used to
implement higher resolution. We took a precise analysis on
C0 ⋅ ε 0 M
1
E (4) = n /2
× K ' ∑ i bi iε i iVref (15) the mismatching between binary-weighted capacitors and
2 C0 + CPL i =0 2 the parasitic capacitors on both sides of the coupling
capacitor. The parasitic capacitors on the right hand of the
CPL M
1 coupling capacitor have no effect on the linearity. The
E (5) = n /2 n /2
2 C0 ⋅ (2 C0 + CPL )
× K `
∑
i =0 2
b iε i iVref
i i (16) parasitic capacitors on the left hand have certain effect on
the linearity of the ADC system. This paper presents a
precise and useful analysis on the relationship among the
B. Error Analysis attainable resolution and several usual factors such as:
`
The coefficient K has no effect on the linearity and capacitor mismatching, parasitic capacitors which is very
can be considered as 1 approximately as the resolution useful for circuit designers to choose process, layout, circuit
increased. The resolution of the ADC is mainly determined structure, and capacitor size in the design of SAR ADC.
by exact ratios of any two capacitors in the array according REFERENCES
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