Compare These Arm Architectures: ARM7TDMI and ARM9TDMI. Answer

EC 306 EMBEDDED SYSTEMS NAME : SATINDER SINGH
Assignment No: 02 ROLL NUMBER: 2K17/EC/150
1. Compare these arm architectures: ARM7TDMI and ARM9TDMI.

ANSWER:
ARM7TDMI ARM9TDMI.
* The ARM7TDMI-S processor has a Von- * It follows the Harvard architecture .
Neumann architecture.
* It has a single 32-bit data bus carrying both * It has separate data and instruction buses .
instructions and data.
* It has three stage pipeline. * It has five stage pipeline architecture.
* Its Operational Frequency is 80 MHz. * Its Operational Frequency is 150 MHz.
2. List down and explain various enhancements in ARM9E.

ANSWER:
 To increase performance, the pipeline of the ARM9TDMI core was re-engineered from the three stage
system used by the ARM7TDMI family to five stages. Operations previously performed in the execute
stage of ARM7 are spread across four stages in the ARM9 pipeline: decode, execute, memory, and write.
The reorganization and removal of these critical paths resulted in a much higher clock frequency.
 Another performance improvement is the reduced cycles per instruction rating of the processor. This is
due to improved load and store instruction cycle counts. Single load and store instructions are now single-
cycle operations. This is an enhancement over the ARM7 operation, which used the execute stage three
times: first, to calculate the address; second, to access the memory and cache; and third, to write the data
to the register bank. On ARM9, each step has a separate pipeline stage requiring only one cycle, avoiding
pipeline stalls.
3. Explain with example (+ diagram) a simple ARM based System.

ANSWER:
The Arm architecture is the best-known Arm specification, but it is not the only one. Arm has
similar specifications for many of the components that make up a modern System-on-Chip (SoC).
The system-on-chip (SoC) architecture

A system-on-chip (SoC) is an integrated circuit which packs multiple peripherals of an electronic system
(memory, connectivity, analog, and digital peripherals) on a single substrate with a processor at its heart.
The processor can be a microcontroller, microprocessor, or DSP core. SoCs are becoming popular because
of their smaller size, reduced power consumption, and reduced assembly costs compared to traditional
microcontroller architectures..
Figure 1 shows a standard SoC with multiple peripherals connected by a data bus.
FIGURE 1
Now let’s look at the details of hardware components of SoC shown above. On the hardware side, an SoC
can be thought of as a Lego board. It is easy to utilize the blocks which are required in the application and
leave the other blocks. The hardware portion of a SoC consists of components like:
Core Processor This is the most important component of the SoC as it controls all other peripherals on the
SoC apart from general processor tasks.
System Memory This is divided into Flash memory for code storage, RAM for data, ROM for boot-code of
the device, EEPROM, and an External Memory Interface (EMIF). The ARM architecture provides easy
method for mapping memory and peripherals, leading to a reduction in SoC design time.
Digital peripherals Generally, SoCs are integrated with digital peripherals like counters, PWM, Timer,
digital filters, etc. Some SoC also provide basic logic gates, flip-flops, multiplexers, and de-multiplexers,
etc.
Analog peripherals Along with digital peripherals, SoCs also come with a lone list of analog components
to provide mixed signal capabilities. Analog peripherals like ADCs, op-amps (comparator, amplifier, TIA,
mixer, etc), current and voltage sources, etc. generally form the analog portion of the SoC.
Communication peripherals SoC are fitted with multiple communication interfaces like USB, UART, I2C,
I2S, Ethernet, SPI, CAN, Bluetooth, etc. SoCs use these interfaces to communicate with external devices
like another SoC, a base station, or a server.
Special I/O systems Some SoC also provide special I/O systems like capacitive touch detection and LCD
and LED drivers.
Direct Memory Access Controller (DMA) To improve data access performance, DMA is also included in
the list of peripherals. DMA frees the CPU from data-related tasks and hence improves overall data
throughput of the SoC. DMA controllers can be configured for single/burst data transfer requests,
interrupt signal on completion of data transfer, etc. Transfers of data can take place between:
 Memory to peripheral
 Memory to memory
 Peripheral to memory
 Peripheral to peripheral
Programmable Digital Blocks For applications that require digital capabilities that cannot be built using
the components that exist in the SoC, some SoC vendors provide the option to build your own digital
application using configurable PLDs and ALU to offload tasks from the CPU. With this functionality, the
developer can make his/her own custom digital application suiting his requirement. Programmable digital
blocks are known as Universal Digital Blocks (UDBs) in the Cypress’ PSoC architecture . Each UDB is made
up of two PLDs, status and control logic, and a datapath module. The datapath module is capable of
performing simple arithmetic functions. Developers can describe their digital block in Verilog and have the
PSoC Creator tool compile, synthesize, place-and-route, and automatically build it as part of the system.
Programmable Analog Blocks Vendors provide analog programmability using Switched Capacitor blocks.
These blocks follow mimic resistance using a capacitor. Different op-amp configurations like inverting
amplifier, non-inverting amplifier, filter, integrator, and differentiator can be created using a single op-
amp by varying the input and feedback configurations using switched capacitances.
System Resources The system resources block is the controller block which deals with:
 Clocking sub-system
 Power and Operational modes
 Power supply and monitoring sub-system
 Watchdog timer, etc.
These blocks are connected to each other by a data bus which can be vendor proprietary or using the
industry standard ARM’s Advance Microcontroller Bus Architecture which includes the Advanced High
Performance bus (AHB), Advanced Peripheral Bus (APB), etc. This bus architecture promotes modular
system design, provides higher performance, and reduces power dissipation in on-chip communication.
The peripherals mentioned above are highly configurable and their properties can be modified easily to
suit the needs of the application. This can be done using firmware by writing to peripheral registers or
using a vendor’s proprietary software GUI to modify the configuration settings of the peripherals. For
example, PSoC Creator Software Suite allows developers to configure these components while designing
an application using PSoC.
4. Explain ARM v5TEJ.

ANSWER:
ARMv5TEJ is an advanced RISC based ARM architecture with the Trivial Jazelle extension implemented.
It is a combined superset of the previous ARM architecture versions, which include
ARMv4T, ARMv5T, ARMv5TE.
Below are the general and the special features of this architecture.
The general features of the ARMv5TEJ include:
(a) Load-Store architecture, where data-processing operations only operate on register contents, not directly
on memory contents.
(b) 31 general-purpose 32-bit registers, out of which 16 are visible at any one time. Out of these 16 registers,
3 have special roles, which are STACK
POINTER, PROGRAM COUNTER, and LINK REGISTER.
(c) ARM supports 7 exceptions and a privileged processing mode for each. The seven types of exception are:
• reset
• attempted execution of an Undefined instruction
• software interrupt (SWI) instructions, used to make a call to the OS.
• Prefetch Abort, an instruction fetch memory abort
• Data Abort, a data access memory abort
• IRQ, normal interrupt
• FIQ, fast interrupt.
(d) All processor state other than the general-purpose register contents is held in status registers.
(e) Saturation instructions
The Jazelle Extension enables architectural support for hardware acceleration of opcode execution by Java
Virtual Machines (JVMs).
(f) It has a 32-bit ARM and 16-bit Thumb instruction set.
The special features of the ARMv5TEJ are:
* Extra instructions added for changing state between ARM and Thumb instructions.
* Enhanced multiplication instructions.
* Extra DSP-type instructions.
* Faster multiply accumulates.
5. Elaborate on ARM v6 Architecture and how is it different other ARM families.

ANSWER:
ARM11 Microarchitecture
First implementation of ARMv6 architecture
8-stage pipeline
64-bit data paths
Frequency: up to 750 MHz, 350 – 500+ MHz worst case. 400 – 1,200 Dhrystone MIPS
Power: 0.4 mW/MHz worst case: 0.13µm 1.2V
Media support: SIMD extensions
Improved interrupt latency
ISA extensions THUMB, DSP, Jazelle
100% backwards compatibility to ARMv5
Key ARMv6 Improvements
In developing the ARMv6 architecture, effort has been focused on five key areas:
Memory Management
System design and performance is heavily affected by the way that memory is managed. The memory
management architectural enhancements improve the overall processor performance significantly –
especially for platform-type applications where operating systems need to manage frequent task changes.
With the changes in ARMv6, average instruction fetch and data latency is greatly reduced; the processor
has to spend less time waiting for instructions or data cache misses to be loaded. The memory
management improvements will provide a boost in overall system performance by as much as 30%.
In addition, the memory management enhancements will enable more efficient bus usage. Less bus
activity will yield significant power savings as a result of reduced memory access.
Multiprocessing
Application convergence is driving system implementations towards the need for multiprocessor systems.
Wireless platforms, especially for 2.5G and 3G, are typical applications that demand integration between
ARM processors, ARM and DSPs, or other application accelerators.
Multiprocessor systems share data efficiently by sharing memory. New ARMv6 capabilities in data sharing
and synchronization will make it easier to implement multiprocessor systems, as well as improving their
performance. New instructions enable more complex synchronization schemes, greatly improving system
efficiency.
Multimedia Support
Single Instruction Multiple Data (SIMD) capabilities enable more efficient software implementation of
high-performance media applications such as audio and video encoders. Over sixty SIMD instructions are
added to the ARMv6 Instruction Set Architecture (ISA).
Adding the SIMD instructions will provide performance improvements of between 2x and 4x, depending
on the multimedia application. The SIMD capabilities will enable developers to implement high-end
features such as video codecs, speaker-independent voice recognition and 3D graphics, especially relevant
for next generation wireless applications.
6. Explain Intel’s ARM Derivative with the help o5bf a diagram.

ANSWER:
Intel’s ARM derivatives are Intel XScale and StrongArm.
● XScale is a microarchitecture for central processing units initially designed by Intel implementing the ARM
architecture (version 5) instruction set. XScale comprises several distinct families: IXP,IXC,IOP,XA, CE.
● All the generations of XScale are 32-bit ARMv5TE processors.
Fig. INTEL X-SCALE ARCHITECTURE.
● The Intel XScale core implements the integer instruction set architecture of ARMv5 but does not provide
hardware support of the floating-point instructions. The Intel XScale core provides the Thumb instruction
set (ARMv5T) and the ARM V5E DSP extensions.
● The Intel XScale core comes with either a 16K or 32K byte instruction cache. The instruction cache is 32-
way set associative and has a line size of 32 bytes. All requests that “miss” the instruction cache generate
a 32-byte read request to external memory.
● The Intel XScale core supports software debugging through two instruction address breakpoint registers,
one data-address breakpoint register, one data-address/mask breakpoint register, and a trace buffer.
● The Intel XScale core made a few extensions to the ARM Version 5TE architecture to meet the needs of
various markets and design requirements.
The following is a list of the extensions:
A DSP coprocessor (CP0) has been added that contains a 40-bit accumulator and eight new instructions.
○ New page attributes were added to the page table descriptors. The C and B page attribute encoding was
extended by one more bit to allow for more encodings: write allocate and mini-data cache.
○ Additional functionality has been added to coprocessor 15.
Coprocessor 14 was also created.
○ Enhancements were made to the Event Architecture, which includes instruction cache and data cache
parity error exceptions, breakpoint events, and imprecise external data aborts.

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EC 306 EMBEDDED SYSTEMS NAME : SATINDER SINGH

Assignment No: 02 ROLL NUMBER: 2K17/EC/150

1. Compare these arm architectures: ARM7TDMI and ARM9TDMI.

2. List down and explain various enhancements in ARM9E.

3. Explain with example (+ diagram) a simple ARM based System.

The system-on-chip (SoC) architecture

4. Explain ARM v5TEJ.

5. Elaborate on ARM v6 Architecture and how is it different other ARM families.

6. Explain Intel’s ARM Derivative with the help o5bf a diagram.

Fig. INTEL X-SCALE ARCHITECTURE.

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