Introduction to ARM

ARM – stands for “Advanced RISC Machine” , ARM based microcontrollers are very
popular in 32 bit embedded market, occupying the major share of the market. ARM7 was
the first commercial success, used extensively in products like PDAs, IPods, hard disks, set-
top boxex, mobile phones etc.

ARM is RISC type of machine, hence :

a) instructions are of same size (32bits)
b) most of the instructions are executed in one cycle
c) only load and store instructions access memory, other data processing instructions use
only registers as operands (upto 3 register operands), hence capable of completing the
instructions in one cycle.
d) Less Hardware complexity & Die size (less number of transistors are used compared to
the CISC processor of comparable computational power) and hence consumes less power.

ARM Supports Data bus width of 32bits, supporting very high data bandwidth, so reading
and writing 32 bit data in one cycle.

The ARM Microcontroller / ARM SoC

It is the chip which has in-built cpu core (some version of ARMcore, like ARM7/9/11) and
the necessary large set of peripherals and memory to perform as a system. Hence, it is
referred as System On chip (SoC) .

ARM SoC – Core with Peripherals

ARM has defined the details of architecture, registers, instructions set, memory map, and
timing of the ARM CPU and holds the copyright to it. The Various design houses like
NXP,TI and semiconductor manufacturers license the IP for the CPU and add their own
peripherals (like memory,ports,timers etc) as they please. It is up to the licensee to define the
details of peripherals such as I/O ports, serial port UART, timer, ADC, SPI,DAC,I2C and so
on. As a result while the CPU instructions and architecture are same across the entire ARM
chip made by different vendors, their peripherals are not compatible. That means if you write
a program for the serial port of an ARM chip made by TI, the program might not necessarily
run on an ARM chip sold by NXP.
Features of ARM Architecture/Core
1. ARM is RISC type of machine, hence : a) instructions are of same size (32bits) b)
most of the instructions are executed in one cycle c) only load and store instructions
access memory, other data processing instructions use only registers as operands
(upto 3 register operands), hence capable of completing the instructions in one cycle.
D) Less Hardware complexity & Die size (less number of transistors are used
compared to the CISC processor of comparable computational power) and hence
consumes less power.
2. Supports Data bus width of 32bits, supporting very high data bandwidth, so reading
and writing 32 bit data in one cycle.
3. Pipelining: ARM7 has 3stage pipeline(Fetch,Decode,Execute), ARM 9 has five stage
pipeline, while ARM10 has 6 stages
4. THUMB: A new 16-bit instruction set called ‘Thumb instruction set’ is also
supported, used when the application is very light, and do not need full power of 32-
bit ARM instructions. The advantage is, it occupies less memory, as every instruction
takes less number of memory bytes (say 2 instead of 4 while representing the
machine code in memory), hence achieving high code density. There is also facility
for mixing ARM and THUMB instructions, referred as ‘ARM THUMB
interworking’.
5. MMU & MPU: some versions of ARM core, which supports both Memory
management Unit and Memory Protection Unit and others support one or neither of
them
6. Cache: All the latest ARM cores supports good amount of cache, ARM7 has 8KB
cache.
7. Debug interface - JTAG( stands for Joint Test Application Group) defines a set of
standards for testing the functionality of hardware. Most of the ARM microcontrollers
provide JTAG debug interface, using that one can trace the program using single
stepping, dump the memory/registers by interfacing to host computer.
8. Fast multiplier: Provides fast multiplier unit
9. Enhanced Instructions: Some cores provide DSP (digital signal processing) unit
10. Jazelle DBX (Direct Bytecode eXecution): allows some ARM processors to execute
Java bytecode in hardware. This is useful to increase the execution speed of games
and applications. ARM claims that such Java applications get run in hardware (rather
than software) so that more speed is achieved, Jazelle mode is used to run Java Byte code
in Jazelle mode on an ARM9 processor.
11. Vector floating point unit: This implies hardware support for floating point
computation.
12. Synthesizable: If an ARM processor is synthesizable, it means that its RTL code is
available with the licensee, using which extensions and modifications are possible to
the basic core.
 To specify what features are available with a particular ARM core, naming
conventions are used, like,

ARM7TDMI-S , it is based on ARM 7 core, and has features like Thumb instructions
set (T), JTAG debugger (D), fast multiplier (M) and the embedded ICE (I) [ICE- in
circuit emulator, useful while debugging hardware & software], S – synthesizable

ARM Architecture ( Instruction Set Architecture – ISA)

The term ISA implies, the users i.e. the programmers view of the processor, which
constitute the instruction set, addressing modes, registers, etc. This study is very
important for assembly programmers, since we are programming using embedded C , we
are restricting our study to few basic concepts of ARM 7 architecture only. ( these basic
concepts holds good even for higher versions of ARM core)

Operating Modes : ARM has seven operating modes, i.e it exists in any one of these
modes when the processor is running,

i) User mode: simplest mode with least privileges (or also referred as Unprivileged
mode), this is the mode under which most applications run, User mode is used for
the execution of programs and applications.
ii) FIQ Mode (Fast interrupt request): Entered this mode on request from FIQ
interrupts
iii) IRQ Mode (Interrupt Request): Entered this mode on IRQ request
iv) Supervisor: Entered on Reset and when a software interrupt instruction (SWI) is
executed, and is generally the mode in which the operating system kernel
operates in.
v) Abort: Used to handle memory access violations, Abort is entered after a failed
memory access
vi) Undef: Used to handle undefined instructions, Undefined is entered if the
instruction is not defined (invalid opcodes)
vii) System: This is highly privileged mode used by operating systems to manipulate
and control the activities of the processor, System mode is a special version of
user mode that allows full read write access to the CPSR
Register Set: ARM has 37 registers of size 32bits each, they are

i) PC - 1 dedicated program counter

ii) CPSR – 1 dedicated program status register, (like flag register of 8086)
iii) 5 dedicated saved program status registers (SPSR)
iv) 30 general purpose registers
General purpose registers - even though 30 are there, they are distributed among different
modes, ex: in user & system mode following registers only are available;

R0-R12 - general purpose registers, used for holding both data and address
R13 - Stack pointer (SP)
R14 - Link register (LR)
R15 - Program counter

R14 i.e link register, a special register, used to hold the contents of PC when branching
due to procedural call or interrupts occur. On return PC is loaded back with the contents
of link register. This avoids the overhead of using the stack, i.e basically memory access
(as memory located outside the ARM core)

But not all registers are seen at once. The processor state and operating mode decide
which registers are available to the programmer, At any time only 16 of the 31 general
purpose registers are available to the programmer.

Mode Switching: When the processor switches the mode, say from the user mode to FIQ
mode (on receiving the FIQ interrupt) some of the user mode registers are replaced by
another set of registers, here R8 to R14 are replaced by another set of registers, and names
of these registers are suffixed by FIQ, like R14_FIQ,R12_FIQ and so on.

Why is it that FIQ uses another set of Registers? Note that this mode is entered on a ‘fast
interrupt’ which means it requires fast action. One action during interrupts would be to
save the contents of the currently used registers. This saving takes some time. To ensure
fast operation, in the case of being switched to the FIQ mode, new registers are used. No
time is spent on saving the contents of register R8 to R14 of the user mode. Once the FIQ
mode is entered, those registers are just swapped out, and replaced by a set of new
registers. Not all registers are swapped out. In IRQ mode, only R13 and R14 are replaced
by new registers. In the IRQ mode response need not to be as fast as in the FIQ mode,
there is sufficient time to save contents of most of the registers before mode switching is
done. This also applies to modes ‘undef, supervisor and abort’ , here also only two
registers are swapped out and replaced with the new once.

CPSR – Current Program Status Register, is a very important register, and there is only
one such register for the processor. The CPSR contains the information about the current
state of the processor. It has bits which specify the mode, control bits to enable or disable
FIQ/IRQ interrupts ,THUMB/ARM mode in use and the conditional flags
(Sign,Overflow,Carry,Zero – meaning is same as that of 8086/8051).
[ Bit allocation and Definition of CPSR register

C, CY flag – This flag is set whenever there is a carry out from the D31 bit. This flag bit is affected after a
32 bit addition or subtraction
Z, Zero Flag – The zero flag reflects the result of arithmetic or logic operation. If the result is zero, then
Z=1. (Z=0 , if the result is not zero).
N, Negative flag (Sign flag): Signed numbers uses D31 as the sign bit. The negative flag reflects the result
of an arithmetic operation. If the D31 bit of the result is zero, then N=0 and result is positive. If the D31 bit
is ‘1’ , then N=1, the result is negative.
V,Overflow Flag – This flag is set whenever the result of a signed number operation is too large, causing
the high order bit to overflow into the sign bit.
The V and N flags are used for signed number arithmetic operations.
T – The T flag is used to indicate the ARM is in Thumb state.
I - Used to enable / disable IRQ interrupt.
F – Used to enable / disable FIQ interrupt
M4-M0 – Indicate CPU operating Mode
]
It also provides Sticky overflow flag, this flag indicates overflow itself, but it is ‘sticky’
in the sense that it remains set until explicitly cleared. The contents of this register can be
modifiable only in system mode.

SPSR –Saved Program Status Register: There are five saved program status registers,
that is, one for each of the exception modes of operation. When an exception, that is, an
interrupt occurs, the corresponding SPSR saves the current CPSR value into it (so as to be
able to retrieve it on returning to the previous mode). The system mode and user modes
do not have SPSRs because they are not entered through the mechanism of interrupts.

Interrupt Vector Table

ARM generates predefined interrupt vector (i.e starting address of ISR), whenever
a) Exceptions are generated (Undefined instruction, prefetch abort, data abort)
b) on execution of SWI, software interrupt
c) on RESET
d) on receiving IRQ or FIQ

These addresses/vectors, holds the ISR code or code to branch to ISR (interrupt handlers).

Exception Vector Adds

RESET 0x0000 0000

Undef 0x0000 0004
SWI 0x0000 0008
.
.
.
IRQ 0x0000 0018
FIQ 0x0000 001C
ARM CPU Architecture

An ARM Processor consists of the following parts:

• Arithmetic Logic Unit (32bit)
• Booth Multiplier(32bit)
• Barrel Shifter
• Control Unit
• Register file of 37 registers, each of 32bit.
ARM also consists of a 32bit Program status register instruction register, priority encoder,
etc.
 Overview of ARM Instruction Set
Data Processing Instructions : Data processing instructions accept register operands,
and at most one immediate operand. They are 3 address instructions.

Data/Register Transfer Instructions

Format: MOV REG, REG / IMM
MVN REG, REG / IMM

Example: MOV R1,R2 ; Move contents of R2 to R1

MOV R1,#3 ; Move the immediate 3 to R1
; any Register R0 to R15 can be used for source/destination
; each Register is of size 32 bits

Example : MVN R3,R4 ; Move negated R4 to R3 ; (i.e R3 <- ~R4)

SHIFT AND ROTATE OPERATIONS :

Shift and Rotate operations can be part of other Register Transfer / Arithmetic / Logic
operations. One of the operand can be operated by shift/rotate operations using barrel
shifter.

Example: MOV R1, R0 , LSL #1

; rotate R0, by operation Logical Left Shift & Put the value to R1, the second operand [R0
with LSL #1] is also called as shifter operand. Register can also be used to indicate the
number of bits to be shifted, Ex- MOV R1, R0, LSL R2

Similar logical/rotate options :

LSR #n - Logical Shift Right

LSL #n - Logical Shift Left
ASR #n – Arithmetic Shift Right
ROR #n - Rotate Right
RRX #n - Rotate Right Extended ( i.e with Carry)
(Rotate left ‘n’ bits is equivalent to rotate right by (32-n) bits)

Example: to compute following without multiplication

2 * A + B, given A=2,B=3

MOV R0, #2
MOV R1, #3
ADD R2, R1, R0, LSL #1

Example : Write the output of the following program, after execution of each instruction

AREA RESET , CODE

ENTRY
MOV R0,#01 ; R0 = 0X0000 0001
MVN R0,R0 ; R0 = 0XFFFF FFFE
MOV R1,R0,LSL #31 ; R1 = 0X0000 0000
 MOV R2,R0,LSL #2 ; R2 = 0XFFFF FFF8
MOV R3,R2,LSR #2 ; R3 = 0X3FFF FFFE
MOV R4,R2,ASR #2 ; R3 = 0XFFFF FFFESTOP B STOP
END

Updating of Status Flags

Updation of status flags is possible by appending “S” to the instruction,

MOVS R0, #0

Conditional Execution : Suffixing condition codes is possible for any data processing
and branch instructions, if condition code satisfies instruction works, else it is a NOP
instruction. There are 15 such condition codes.

Ex: MOVEQ R0, #10 ; 10 is moved to R0, if Zero flag is set else it is a NOP
Other Commonly used Condition codes :
EQ Z=1 zero flag set
NE Z=0 zero flag clear
CS C=1 carry flag set
CC C=0 carry flag clear
MI N=1 Sign/Negative flag set (number is MINUS)
PL N=0 Sign/Negative flag is clear(number is POSITIVE)

Example: Write the output for the following code snippet

Case 1:
MOVS R0,#0
MOVEQ R0,#10
Answer - R0 = 10

Case 2:
MOV R0,#0
MOVEQ R0,#10
Answer – R0 = 0

Example: to compute larger of two numbers

MOV R0,#0X0FF
MOV R1,#0X010
CMP R0,R1
MOVCS R2,R0
MOVCC R2,R1
ARITHMETIC INSTRUCTIONS

Format:
ADD REG, REG, (REG/IMM)
SUB REG, REG, (REG/IMM)
RSB REG, REG, (REG/IMM)

Ex : ADDS R2,R3,R4 ; R2  R3 + R4 and update the flags (because of suffix S)

(Similar instructions:
ADC(Addition with Carry), SUB (Substation), SBC (Subtraction with Carry),
RSB(Reverse Subtraction), RSC(Reverse subtraction with borrow).

Program to add two 32 bit numbers

AREA RESET,CODE,READONLY
ENTRY
LDR R0,=NUMS
LDR R1,[R0]
LDR R2,[R0,#4]
LDR R0,=RES
ADD R3,R1,R2
STR R3,[R0]
STOP B STOP
NUMS DCD &10203040,&10203040
AREA MEMORY,DATA
RES SPACE 4
END

Program to add two 64 bit numbers

Logic
(MSB:LSB)
Num1: R1:R2
Num2: R3:R4
Ans : R5:R6
AREA RESET,CODE,READONLY
ENTRY
LDR R0,=NUM1
LDR R1,[R0];read MSB word
LDR R2,[R0,#4];read LSB word
LDR R0,=NUM2
LDR R3,[R0];read MSB word
LDR R4,[R0,#4];read LSB word
ADDS R6,R2,R4
 ADC R5,R1,R3
LDR R0,=RES
STR R5,[R0]
STR R6,[R0,#4]
SWI &11
STOP B STOP
NUM1 DCD &80706050,&40302010
NUM2 DCD &81716151,&41312111
AREA MEMORY,DATA
RES SPACE 8
END

Write an ALP to add the first 5 numbers

AREA RESET,CODE
ENTRY
MOV R0,#0
MOV R1,#0
CONT
ADD R1,R1,R0
ADD R0,R0,#1
CMP RO,#5
BNE CONT

STOP B STOP
END

Program to add N 32 bit numbers stored in code memory

LDR R0,=INPUTS ;set up pointer to input data
LDR R1,=OUTPUTS;set up pointer to store o/p data
MOV R3,#0 ;variable - to store answer
MOV R4,#0 ;variable - to indicate no.of.nos
CONT
LDR R2,[R0] ;get no.from mem and add
ADD R4,R2
ADD R0,#4 ; increment pointer to point next loc
ADD R3,#1 ; 4 bytes represent one memory loc
CMP R3,#3
BNE CONT
STR R4,[R1] ;store answer in memory
STOP B STOP

INPUTS DCD 01,02,03

AREA MEMORY, DATA
OUTPUTS SPACE 4
END
Write a program to perform division of two numbers stored in the memory.
Store the quotient and the remainder in the data memory.

AREA RESET, CODE

MOV R3,#0
LDR R0,=NUM1
LDR R1,[R0],#4
LDR R2,[R0]

CONT SUBS R1,R2

ADDPL R3,#1
BPL CONT
ADD R1,R2
LDR R0,=&40000000
STR R3,[R0],#4
STR R1,[R0]
STOP B STOP
NUM1 DCD 9, 3

Set of N 32 bit signed numbers representing temperatures are stored in the

FLASH memory at the location TEMP. Apply the following function: f(x) = (x /
2) + 3 on all the numbers using ALP, after moving the numbers to SRAM.
Write the appropriate comments.
Assume N=5, and temperatures are stored at TEMP
AREA RESET,CODE,READONLY
ENTRY
LDR R0, =TEMP
LDMIA R0, {R1-R5}
;COPY FROM FLASH TO SRAM,USING REGISTERS
MOV SP, #0X40000000
STMIA SP, {R1-R5}
MOV R0, #0X40000000
MOV R1, #5 ; TOTAL ELEMENTS
CONT
LDR R2,[R0]
MOV R2,R2,ASR #1
ADD R2,#3
STR R2,[R0]
ADD R0,R0,#4
SUBS R1,#1
BNE CONT
STOP B STOP
TEMP DCD 0X30,0X40,0XF0,0X90,0X74
END
LOGICAL INSTRUCTIONS

Format:
AND REG, REG, (REG/IMM)
EOR REG, REG, (REG/IMM)
ORR REG, REG, (REG/IMM)
BIC REG, REG, (REG/IMM)

Ex: ANDS R5, R0 , R1 ; R5  R0 .AND. R1 (bit AND operation), S – updatde flags

Ex: ORRS R5, R0 , R1 ; R5  R0 .OR. R1 (bit AND operation), S – updatde flags
Ex: EORS R5, R0 , R1 ; R5  R0 .OR. R1 (bit AND operation), S – updatde flags

• BIC is used to clear selected bits of the Register

Ex: BIC R5, R0 , R1 ; R5  R0 .AND. ~R1 (i.e R0. AND. NOT R1)

MOV R1,#00100011B
Ex: BIC R0, R0, R1 ; to clear bit 0,1 and 5 of the Register R0

PSEUDO OPERATIONS(COMPARE instructions) WITH FLAG UPDATES

The CPSR register contains four flags Negative(sign flag),Zero,Carry and Overflow flags,
which are affected by the execution of following instructions. Flags are also affected by
using suffix S to the other data processing instructions.

Format:
CMP REG, (REG/IMM)
TST REG, (REG/IMM)
TEQ REG, (REG/IMM)

• CMP R1 , R2 ; pseudo subtraction and updates the flags

• TEQ R1 , R2 ; R1. XOR . R2 pseudo XOR operation and updates the flags
• TST R1 , R2 ; R1. AND . R2 pseudo AND operation and updates the flags

To check for equality of numbers

MOV R3,#0
MOV R0,#5
MOV R1,#5
TEQ R1,R0
ADDEQ R3,R0
STOP B STOP
Write a program to clear D0 bit, set D31 bit , compliment D3 & D2 bits of a
32 bit number stored in memory using suitable mask words and logical
operations.

AREA RESET, CODE, READONLY

ENTRY
LDR R0,=NUM
LDR R1,[R0]
;clearing selected bits of a number
LDR R0,=AND_MASK
LDR R2,[R0]
AND R1,R2
;setting selected bits of a number
LDR R0,=OR_MASK
LDR R2,[R0]
ORR R1,R2
;complimenting selected bits of a number
LDR R0,=EOR_MASK
LDR R2,[R0]
;MOV R2,#0X000000C0
EOR R1,R2
STOP B STOP

NUM DCD &00000000

AND_MASK DCD &0FFFFFFFFE
OR_MASK DCD &80000000
EOR_MASK DCD &000000C0
END

Write a program to check for a D1 bit of number, if it is ‘1’, store 20 in R3

else store 10 .

AREA RESET, CODE, READONLY

ENTRY
LDR R0,=NUM
LDR R1,[R0]
LDR R0,=MASK
LDR R2,[R0]
TST R1,R2 ; we can use AND also
BEQ SKIP
MOV R3,#20
B STOP
SKIP MOV R3,#10
STOP B STOP

NUM DCD &03

MASK DCD &2
END
MULTIPLICATION

Format:
MUL REG , REG, REG
MLA REG , REG, REG, REG

Examples:

MUL R1 , R2 , R3 - Multiply R1  R2 x R3
MLA R4 , R3 , R2 , R1 - Multiply and Accumulate; R4 (R3 x R2) + R1

To compute the factorial of a number

MOV R0,#5; To compute factorial of 5
MOV R1,#1;
CONT
MUL R2,R1,R0 ; MUL R0,R1,R0 not allowed
MOV R1,R2
SUBS R0,#1
BNE CONT
STOP B STOP

BRANCH INSTRUCTIONS

1. B LOOP ; branch to the address with label LOOP

BEQ LOOP ; branch only if Zero Flag is set
BNE LOOP ; branch only if Zero Flag is not set (i.e clear)
(used when executing conditional/unconditional branches)
2. BL NEXT ; branch with LINK, copy the PC(address on next instruction i.e
PC+4) contents to LR, then branch
(used when calling procedures)

Format of Procedure Calls:

Ex: BL PROC1 ; contents of PC is Copied to LR

PROC1 ;logic
;logic
MOV PC , LR ; contents of LR copied back to PC, hence RET is executed
Use procedure to compute square of a number

MOV R0,#2
BL SQU
STOP B STOP

SQU MUL R4, R0,R0

MOV PC, LR

To compute sum of first 5 natural number

MOV R0, #0
MOV R1, #0
CONT
ADD R0, R0, #1
ADD R1, R1, R0
CMP R0, #5
BNE CONT

Use procedure to compute sum of squares 5 natural numbers

AREA RESET , CODE
ENTRY
MOV R0,#1
MOV R1,#0
SKIP BL SQU
ADD R1,R1,R4
ADD R0,R0,#1
CMP RO,#6
BNE SKIP
STOP B STOP

SQU MUL R4,R0,R0

MOV PC,LR
END

Load & Store Instructions

These are the only instructions are available to access memory, LDR instruction used for
loading the data from memory to registers and STR instruction is used to store the data
from registers to memory. Memory is organized as bytes, hence 32 bit number requires 4
bytes (4 contiguous addresses).

ARM supports both the base-index and base-offset addressing modes for load and store
instructions. It has additional support for shifting the index register by treating it as a
shifter operand. It has additional support for loading and storing bytes(8bit) and half-
words(16bit) (default is 32 bits).

Format:

LDR REG, [REG]

LDR REG, [REG,IMM]
LDR REG, [REG,REG]
LDR REG, [REG,REG,SHIFT IMM]

STR REG, [REG]

STR REG, [REG]
STR REG, [REG,IMM]
STR REG, [REG,REG]
STR REG, [REG,REG,SHIFT IMM]

Ex:
LDR R1, [R0] ; contents of memory(32 bit number – 4 bytes) pointed by R0 is loaded
into R1

STR R1, [R0] ; contents of R1(32bit number-4 bytes) is stored in memory pointed by
R0.

LDR R1, [R0,R2,LSL #2] ; the effective memory address is obtained by adding R0 and
shifted R2. The 32 bit number is loaded to R1 from the new effective address. (This kind
of addressing is referred as base addressing; one register can point to the base address and
the other register contents can be used to index from the base address. It is used to access
data structures like arrays). Load & Store also supports pre and post indexed addressing
modes with auto-update].

Program to access memory

AREA RESET,CODE,READONLY
ENTRY
LDR R0,=NUMS
LDR R1,[R0]
LDR R2,[R0,#4]
LDR R0,=RES
ADD R1,R1,R2
STR R1,[R0]
STOP B STOP
NUMS DCD &1,&2
AREA MEMORY,DATA
RES SPACE 4
END
Compute the outputs after executing following code snippets

Examples:

1. Translate the following code in C to the ARM instruction set. Assume variables
are 32bit integers represented in Registers.
A=B+ C+D

MOV R0,#00 ; A
MOV R1,#NUM1 ; B
MOV R2,#NUM2 ; C
MOV R3,#NUM3; D

ADD R0,R2,R1
ADD R0,R0,R3

A = 2*A + B

MOV R0,#NUM1 ; A
MOV R1,#NUM2; B
ADD R0,R1,R0,LSL #2

2. Write the output (in R0 register):

MOV R0,#0X04
MOV R1,#0x02
ORR R0, R0, R1, LSL #1

Ans – 0x04

3. Write the output

MOV R0,#0x02
ADDS R0,R0,R0,ASR R0
Ans – 0x02

4. ARM ALP to compute 2’s compliment of a number

MOV R0, #NUM

MVN R0, R0
ADD R0, R0, #1

5. Write the output in R3

MOV R0,#1
MOV R1,#2
MUL R3,R0,R0
MLA R3,R1,R0,R3

Ans – R3 : 0x03
[EXTRA INFORMATION:
The branch instructions have an L bit to specify if the return address needs to be saved or
not. They use PC-relative addressing and have a 24 bit signed offset. The hardware
assumes that instructions are aligned to 4 byte boundaries, and treats this offset as a
distance in terms of memory words. It thus left shifts the offset by 2 positions.

Load & Store Instructions

These are the only instructions are available to access memory, LDR instruction used for
loading the data from memory to registers and STR instruction is used to store the data
from registers to memory. Memory is organized as bytes, hence 32 bit number requires 4
bytes (4 contiguous addresses).

ARM supports both the base-index and base-offset addressing modes for load and store
instructions. It has additional support for shifting the index register by treating it as a
shifter operand. It has additional support for loading and storing bytes(8bit) and half-
words(16bit) (default is 32 bits).

Format:

LDR REG, [REG]

LDR REG, [REG,IMM]
LDR REG, [REG,REG]
LDR REG, [REG,REG,SHIFT IMM]

STR REG, [REG]

STR REG, [REG]
STR REG, [REG,IMM]
STR REG, [REG,REG]
STR REG, [REG,REG,SHIFT IMM]

Ex:
LDR R1, [R0] ; contents of memory(32 bit number – 4 bytes) pointed by R0 is loaded
into R1
STR R1, [R0] ; contents of R1(32bit number-4 bytes) is stored in memory pointed by
R0.
LDR R1, [R0,R2,LSL #2] ; the effective memory address is obtained by adding R0 and
shifted R2. The 32 bit number is loaded to R1 from the new effective address. (This kind
of addressing is referred as base addressing; one register can point to the base address and
the other register contents can be used to index from the base address. It is used to access
data structures like arrays). Load & Store also supports pre and post indexed addressing
modes with auto-update].

Encoding of Instructions:

ARM has four types of instructions: DataProcessing,Load/Store,Branch, and

miscellaneous. All instructions, encode two pieces of information – condition codes [4bits
to represent 15 types] and the type of instruction[2bits to represent 4 types]. The rest of
the 26 bits contain the instruction type, special conditions, and registers.

Ex: for data processing instruction: Allocation of 32 bits from MSB is indicated below
with the bit allocation.

Condition code,[4bit]
Instruction type – 00 [2],
I – Immediate operand yes/no,[1bit]
Opcode –Type of data processing instruction [4 bits]
S – update CPSR [1 bit],
Rs – Register representing 1st source operand [4 bits-16regs]
Rd – Register representing destination operand[4bits]
Shifter register Operand / Immediate [12 bits]

Encoding Immediate Values:

12bits allocated to represent immediate operand. These 12 bits are split into two parts – a
4 bit constant(rot), and an 8bit payload (payload).

4bit(Rot) 8bit (Payload)

Using these 12 bits, 32 bit number, say ‘n’ is generated as follows:

n = payload ror (2 x rot)
The actual number ‘n’ is obtained by right rotating (ror) the payload by 2 times the value
in the rot field. By doing this, there are 8 bits that correspond to the payload, and the rest
of the 24 bits are all zeros. The rot bits just determine which 8 bits in a 32 bit field are
occupied by the payload. Eventhough, we can’t encode all the possible 232 using 12
bits, the above method chooses meaningful subset of them (to encode wider set of
numbers). The ARM hardware decodes the 12bits and expand them to 32 bits while
processing the instruction.
Ex: Encode the number 0x2A 00 00 00
This number is obtained by right rotating 0x2a by 8 places. Then divide 8 by 2, to get 4.
Hence encoded format is: 0x42a.

Using Stack:

Variation of store instruction is used to save / load multiple registers.

STMFD SP! , {R2,R1,R3}
this instruction pushes the values of multiple registers specified in { }, to memory
pointed by the SP [it is pointing to the last filled word (32bit) location. Stack is growing
from higher address to lower address(downward growing stack). The registers are stored
in an order, such that in the above example, R1 will be on the top of the stack. Since the
symbol ‘!’ is used after the SP, SP is updated after the instruction execution (SP - SP –
12). ]
 Laboratory Programs
Experiment No 1A (i):
AIM: Translate the following code in C to the ARM instruction set. Assume
variables are 32bit integers represented in Registers.
A=B+ C-D

AREA RESET, CODE

ENTRY

MOV R0,#00 ; A
MOV R1,#NUM1 ; B
MOV R2,#NUM2 ; C
MOV R3,#NUM3; D

ADD R0,R2,R1
SUB R0,R0,R3

STOP B STOP
END

A = 2*A + B

AREA RESET, CODE

ENTRY

MOV R0,#NUM1 ; A
MOV R1,#NUM2; B
ADD R0,R1,R0,LSL #2

STOP B STOP
END

Sum of 3X + 4Y + 9Z, where X = 2, Y=3 and Z=4.

AREA RESET, CODE

ENTRY
MOV R1, #2 ; Let X = 2
MOV R2, #3 ; Let Y = 3
MOV R3, #4 ; Let Z = 4
ADD R1, R1, R1, LSL #1
MOV R2, R2, LSL #2
ADD R3, R3, R3, LSL #3
ADD R1, R1, R2
ADD R1, R1, R3
STOP B STOP
END
Sample Output:
Before Execution After Execution
Experiment No 1A(ii):

AIM: Write an ARM ALP to perform addition and subtraction of two 32-bit and
64bit numbers.
MSB:LSB
Value1 = R1 : R2
Value2 = R3 : R4
Result = R5 : R6
Program:
AREA RESET, CODE
ENTRY
LDR R0,=VALUE1
LDR R1,[R0]
LDR R2,[R0,#4]
LDR R0,=VALUE2
LDR R3,[R0]
LDR R4,[R0,#4]
ADDS R6,R2,R4
ADC R5,R1,R3
LDR R0,=RESULT
STR R5,[R0]
STR R6,[R0,#4]
STOP S STOP

VALUE1 DCD &BBBBBBBB,&AAAAAAAA

VALUE2 DCD &CCCCCCCC,&FFFFFFFF

AREA MEMORY, DATA

RESULT SPACE 4
END
Sample Output:
Experiment No 2A:

Algorithm:
1) Initialize first element as smallest [R1] and number of elements n = n-1
2) Loop through all the n [R4] elements. If the current element is smaller than the
smallest, then update smallest.

AIM: Write an ARM ALP to find smallest and largest of N- 32 bit numbers.

AREA RESET,CODE
ENTRY
LDR R0,=DATA1
LDR R3,=0X40000000 ; memory location for storing answer
MOV R4,#05 ; //N- number of elements
LDR R1,[R0],#04; assume first no. as smaller no & increment R0 by 4
SUB R4,R4,#01 ; compare with n-1 elements
BACK
LDR R2,[R0] ; get next number & compare with small
CMP R1,R2
BLS LESS ; // If R1 < R2 , BRANCH
MOV R1,R2 ; update with new smaller no
LESS
ADD R0, R0,#04 ; increment pointer to next number
SUB R4,R4,#01
CMP R4,#00
BNE BACK
STR R1, [R3] ; // SMALLEST VALUE STORED IN MEMORY LOCATION
STOP B STOP

AREA DATA,CODE
DATA1 DCD &64,&05,&96,&10,&65
END

Sample Output:
Experiment No 3A:

AIM: Write an ARM ALP to compute Average of N-32 bit numbers

Algorithm:
1) Initialize sum = 0
2) Loop through all the n elements. Add the current element to sum.

3. Calculate average = sum divide by n

Program:

AREA RESET, CODE

ENTRY

MOV R3,#0
MOV R4, #0
LDR R0, =INPUTS
LDR R1, =OUTPUTS
CONT
LDR R2, [R0]
ADD R4, R4, R2
ADD R0, R0, #4
ADD R3, R3, #1
CMP R3, #5
BNE CONT
MOV R2, #5
MOV R3, #0
REPT SUBS R4, R4, R2
ADDPL R3, R3, #1
BPL REPT
ADDMI R4, R4, R2
STR R3, [R1]

STOP B STOP

INPUTS DCD 01,02,03,04,05

AREA MEMORY, DATA

OUTPUTS SPACE 4

END
Sample Output:
Experiment No 4A:
AIM: Write an ARM ALP to count the occurrences of the given 32-bit number in a
List using Linear Search algorithm
Algorithm:
Linear Search ( array A, key x)
{
for i =0 to n
if A[i] = x then
increment element found count

}
Program:
AREA RESET, CODE, READWRITE
ENTRY
LDR R0,=ARR
MOV R1, #0 ; Loop Iterator
MOV R7, #0 ; Number Of occurrences in The Array
MOV R4, #4 ; key
CONT
LDR R3,[R0]
CMP R3, R4
BNE SKIP
ADD R7, R7,#1
SKIP
ADD R0, #4
ADD R1, #1
CMP R1, #10 ; no of elements
BNE CONT
STOP B STOP
ARR DCD 0,5,1,4,100,4,0,8,7,20
END
Sample Output:
Experiment No 5A(i):

AIM: Write an ARM ALP to compute number of 1’s in a given 32 bit number and
check the parity of the given number
Program:
AREA RESET,CODE
ENTRY
LDR R0,=DATA1
LDR R1,[R0] ;Stores 32bit number-16 ones
MOV R2,#0 ;loop counter, 32 times(32bits)
MOV R4,#0 ;number of 1's counter
MOV R3,#1
LOOP
MOVS R1,R1,LSR #1
ADDCS R4,R4,#1
ADD R2,#1
CMP R2,#32 ; check for 32 bits
BNE LOOP
STOP B STOP
AREA DATA,CODE
DATA1 DCD 0xAAAAAAAA
END

Sample Output:
Experiment No 5A(ii):

AIM: Write an ARM ALP to compute GCD of two given 32-bit numbers.

Algorithm:
int gcd(int x,int y){
while(x!=y)
{
if(x>y)
return gcd(x-y,y);
else
return gcd(x,y-x);
}
return x;
}

Program:
AREA RESET,CODE
ENTRY
MOV R0,#30 ; test values
MOV R1,#45 ; test values
LOOP CMP R0,R1
BEQ EXIT
BGT COND1
SUB R1,R0
B LOOP
COND1 SUB R0,R1
B LOOP
EXIT LDR R0,=GCD
STR R1,[R0]
STOP B STOP
AREA RESULT,DATA
GCD SPACE 4
END
Sample Output:
Experiment No 6A:

AIM: Write an ARM ALP to compute the factorial of a given 32-bit number using
procedure.

Algorithm:
fact(int n)
{
Read number n.
Initialize i =n and fact to 1.
Repeat while i is not equal to 0.
{
fact = fact * i
i = i -1
}
Return fact
}
Program:
AREA RESET,CODE
ENTRY
LDR R0,=INPUT
BL FACT ; CALL SUBROUTINE FACT
LDR R1,=0X40000000 ; RAM area
STR R3,[R1] ; store result in R3 to RAM
STOP B STOP

;subroutine-begin
FACT
LDR R2,[R0] ; get num in R2
CMP R2,#00
BEQ END1
MOV R3,R2 ; result = num
LOOP
SUB R2,#01 ; num = num - 1
CMP R2,#00
MULNE R3,R2,R3 ;result = result * num
BNE LOOP
MOV PC,LR
END1
MOV R3,#01 ; return R3=1, if num=0
END2
MOV PC,LR ; return from subroutine
;subroutine-end

INPUT DCD &05

END
Sample Output:
Experiment No 7A:
AIM: Write an ARM ALP to sort the given list of 32-bit numbers using Bubble sort.
Algorithm:
bubbleSort(list of n elements)
{
for all n elements
n = n-1;
for (i=0 to n, i++)
if ( A[i] > A[i+1] )
temp = A[i]
A[i] = A[i+1]
A[i+1] = temp
}
Program:

AREA RESET, CODE

ENTRY

LDR R0, =ARRAY

LDMIA R0, {R1-R10} ;COPY FROM FLASH TO SRAM,USING
REGISTERS
MOV SP, #0X40000000
STMIA SP, {R1-R10}
MOV R10, #0X40000000 ; STARTING MEMORY ADDRESS OF ARRAY
MOV R1, #10 ; TOTAL ELEMENTS
SUB R1,#1 ; TOTAL ITERATIONS = N-1
LOOP1
MOV R2, R1 ; NO OF COMPARISIONS IN A GIVEN PASS = NO OF
PASSES LEFT
MOV R4, R10 ; SET R4 = STARTING MEM ADDRESS,FOR EVERY PASS
LOOP2
LDR R0, [R4] ; GET FIRST ELEMENT, ARR[i]
LDR R5, [R4, #4] ;GET NEXT ELEMENT,ARR[i+1]
CMP R0, R5
BLS SKIP ;IF ARR[i]<ARR[i+1], skip
MOV R6, R0 ;else, SWAP ARR[i] & ARR[i+1]
MOV R0, R5
MOV R5, R6
STR R0, [R4]
STR R5, [R4,#4]
SKIP
ADD R4, #4
SUBS R2, #1 ; GO TO NEXT COMPARISION
BNE LOOP2
SUBS R1, #1 ; GO TO NEXT ITERATION
BNE LOOP1
STOP B STOP

ARRAY DCD 2,7,4,5,11,18,3,15,8,0

END
Sample Output:
 Microcontrollers & Embedded Systems (18CS44) : Class Assignment #1
Write the value in R0 (32 bit number) after the execution of following instructions:
(Note: Write the answer in Hex with caps; Example: FFFFFF82)
MOV R0,#1
MVN R0,R0,LSL #3
Write the value in R0 (32 bit number) after the execution of following instructions:
(Note: Write the answer in Hex with caps; Example: FFFFFF82)
MOV R0,#1
MVN R0,R0,LSL #1
Write the value in R0 after executing the following instructions:
MOVS R0,#5

MOVEQ R0,#10

Write the value in R0 after executing the following instructions:

MOV R0,#5

MOVEQ R0,#10

Write the value in R0 after executing the following instructions:

(Note: Write the last bits of answer in binary; Example: 11010011)
MOV R0,#00100101B ; number represented in binary form
MOV R1,#00100011B ; number represented in binary form

BIC R0, R0, R1

Write the value in R0 after executing the following instructions:

(Note: Write the last 8 bits of answer in binary; Example: 11010011)
MOV R0,#00100101B ; number represented in binary form
MOV R1,#00100010B ; number represented in binary form

BIC R0, R0, R1

Write the value in R0 (32 bit number) after the execution of following instructions.
(Write Ans: Hex with caps,use zero key for typing ‘0’ Ex: F0FFFF82)
MOV R0,#0X06
MOV R0,R0,ROR #31
MOV R1,#0x02
ORR R0, R0, R1
Write the value in R0 after executing the following instructions:
(Write Ans: Hex with caps,use zero key for typing ‘0’ Ex: F0FFFF82)
MOV R0,#1
MOV R0,R0,LSL #31
MOV R1,R0,ASR #2
Write the value in R0 after executing the following instructions:
(Write Ans: Hex with caps,use zero key for typing ‘0’ Ex: F0FFFF82)
MOV R0,#0X0FF
MOV R1,#0X010
CMP R0,R1
 MOVCS R2,R0
MOVCC R2,R1
Write the value in R3 after executing the following instructions:
MOVS R1,#1
MOVS R0,#0
MOVEQS R0,#5
MOVEQ R1,#5
MOV R4,R1,LSL R0
MLA R3,R0,R1,R4
ARM Assembly Language Programming Fundamentals :

An ALP program comprises two types of instructions to assembler.

1. Actual instructions, like MOV,ADD.. which are converted to binary form and
executed by the ARM processor.
2. Instructions to Assembler, like AREA,END..which are used by the assembler in the
process of generation of binary/hex file. They are not converted to machine codes but
instructs the assembler like where the program is beginning, naming the memory
locations, allocation of memory,end of the assembly program. Etc.

An ALP line has four fields:

1. Label , used to implement branches/looping (CONT)

2. Opcode/pneumonic, ARM instruction to be executed (ADD)
3. Operand/operands, the immediate/Register/Memory operands,which form part of the
instructions (R1,R2,R3)
4. Comment, only for programmers reference (;adding two registers)

Example:
CONT ADD R1,R2,R3 ; adding two registers

Assembly directives:
AREA :
used to name/define memory area for code and data.
Example1: AREA RESET,CODE ,READONLY ; used to name the memory area
RESET, which is meant for storing code and it is of type READONLY (it is optional).
(Note: In Keil, the starting program area to be named as RESET).
Example2: AREA TABLE,DATA ; refers to the memory area by name TABLE used to
store read-write data. We use DATA attribute along with AREA to refer SRAM memory.

ENTRY :
This directive, indicates the first instruction to be executed. An application can have only
one ENTRY point. Hence it can be used in only one source module.

END :
This is an instruction to the assembler, indicating end of the assembly program. Any
instructions written after this, will not be assembled. This will be the last line of any ASM
program and it is compulsory.

DCD :
This directive is used to define, one or more words( a word refers to 32 bit number in
ARM architecture) in code memory.
Example: NUMS DCD 10 , 0X9234ABCD
Here the starting memory location, used store the words are referred by name, NUMS.
Four bytes (i.e 4 addressees) are required to store one 32 bit number. Here the first
number, 10 represented in decimal is stored at NUM, and the second number,
0x9234ABCD,represented in hexadecimal is stored at the memory location, NUM+4. The
actual memory addresses are allocated by the assembler ( it can be checked in the List file,
extension LST, optionally generated by the assembler).
In the above case, if assembler allocates,say 0x00000100 for NUM, then first number is
stored at: 0x0000 0100 and second number is stored at 0x0000 0104

DCB : used to define/allocate memory space in bytes. One byte(one address) for one
number.
NUM DCB 8,0X10

DCW: used to define/allocate memory space in half words. Two bytes (two memory
addresses) are allocated for each number.
NUM DCW 10,0X34

EQU :
This directive is used to equate/name the constants (like macros in C). Constants refers to
numbers represented either in decimal/hex/any other base),characters, strings and Boolean.
Example: CORN_FACTR EQU 2
BASE_ADDR EQU 0X40000000
AREA RESET,CODE
ENTRY
MOV R0,#BASE_ADDR
MOV R1,#CORN_FACTR
RN :
Using this directive we can name the ARM Registers R0 TO R15 ( O TO 15) to user
comprehendible names like x,y,res etc and use these names while writing ASM programs.
It looks easy to the programmer to write programs by referring these names, rather than
Register numbers.

NUM_A RN 0
NUM_ B RN 1
RES RN 2
AREA RESET,CODE
MOV NUM_A ,#1
MOV NUM_B ,#20
ADD RES, NUM_A , NUM_B

Data Types :

ARM can operate on 32 bit data, referred as WORD. It can also operate on 16 bit data
(referred as double word) and 8 bit data (referred as byte operand).
Little Endian and Big Endian storage: Intel processors store the data in little endian
format, (i.e LSB first,MSB last). Motorola processors store data in big endian format
(MSB first,LSB last). One of the special feature of ARM is, it supports storage in both
these formats, suitably can be configured by the initialization code. By default, we are
using little endian format, while writing our ASM programs using Keil.
Ex: Indicate the data and memory addresses, assume little endian format
LDR R0,=0X4000 0000
LDR R1,#0X12345678
STR R1,[R0]
0x4000 0000 0x78
0x4000 0000 0x56
0x4000 0000 0x34
 0x4000 0000 0x12
Data Alignment

ARM 7 core is a 32 bit machine and it has 32 bit data bus. Hence, it can read 32 bit
number (1 Word) from memory in one cycle. But memory is organized in bytes, meaning
every memory address refers to one byte of data, so four memory addresses contributes to
32 bit data. Since, all the four bytes of data are required to put on the data bus
simultaneously, memory is organised into banks, as shown in the below figure.

If we execute one instruction:

LDR R1,[R0] ; assume R0 – 0x4000 0000 and 0x12345678 is stored at that memory
location (0x4000 0000 – 0x78,0x4000 0001 -0x56, 0x4000 0002- 0x34, 0x4000 0003 –
0x12). Now each bank contributes 8 bit data, totalling to 32 bit data, which is loaded into
R1. Hence we have to understand, that we indicate in the instruction only starting address,
but all the four addresses are referred automatically to generate 32 bit data.

Next numbers in the memory is stored at address 0x4000 0004,0x4000 0008..we can
observe the last two bits are always zero. It is referred as, 32 bit data alignment . If last
two bits are zero, then we say it is aligned address, for accessing 32 bit data. If we are
referring memory address in the instruction which is not aligned, say 0x4000 0001, then
we require two memory cycles to load the data from memory. In the first cycle, we access
3 bytes and then in second cycle we access one byte. Hence taking more time, and not
optimised.

Most of the ARM tools ensure that the data is stored in aligned locations, so as to avoid
unnecessary extra cycles of operation.

Note: for half-word (16 bit access), the specified address should have its LSB bit 0, for
alignment.

Storing (and loading also) of 4 bytes in memory can be done in one cycle, because the
processor has a 32 bit data bus. When 32 bit data is stored in memory, four addresses are
needed. We need to specify only one address in our instruction; but there is an aspect
called ‘alignment’. For 32-bit data,’alignment’ implies that the last two bits of this address
are zero. For example, the address 0x00001200 is an aligned address. When this address is
used to store 32 bit data, this address and the next three addresses are automatically
accessed. This is because of the way memory is organized, as four banks.
Conditional Codes and Corresponding Flag Status

CODE MNEMONIC MEANING CONDITION FLAGS

0000 EQ EQUAL Z =1
0001 NE NOT EQUAL Z=0
0010 CS/HS CARRY SET/UNSIGNED >= C=1
0011 CC/LO CARRY CLEAR/UNSIGNED < C=0
0100 MI MINUS/NEGATIVE N=1
0101 PL PLUS/POSITIVE OR ZERO N=0
0110 VS OVERFLOW V=1
0111 VC NO OVERFLOW V=0
1000 HI UNSIGNED HIGHER C=1 AND Z=0
1001 LS UNSIGNED LOWER/EQU C=0 OR Z=1
1010 GE SIGNED >= N=0
1011 LT SIGNED< N=1
1100 GT SIGNED > Z=0 AND N=0
1101 LE SIGNED<= Z=1 OR N=1
1110 AL ALWAYS (ALWAYS EXECUTE)
1111 RESERVED

Conditions for signed and unsigned numbers are different. For unsigned numbers we use
the mnemonic ‘higher’ or ‘lower, while for signed numbers, the conditions are specified as
‘greater than’ or ‘lower than’.
For unsigned numbers, carry flag( also called as borrow flag, when we do
substraction/comparision) and zero flag is used.
MOV R0,#num1
CMP R0,#num2
BHI SKIP ;
MOV R1,#0 ; num1 < num2
SKIP
MOV R1,#1 ; num1 > num2

Note: for unsigned numbers, you can use LS,CS/HS,CC/LO

For signed numbers, N flag and Zero flag is used.

MOV R0,#num1 ; num1 & num2 are signed numbers

CMP R0,#num2
BGT SKIP ;
MOV R1,#0 ; num1 < num2
SKIP
MOV R1,#1 ; num1 > num2
Note: GE/LT/GT/LE