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Analysis of noise margin of CMOS inverter in sub-threshold regime

Conference Paper · April 2013

DOI: 10.1109/SCES.2013.6547499

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Ananda Sankar Chakraborty Manash Chanda

University of California, Berkeley Meghnad Saha Institute of Technology
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 Analysis of Noise Margin of CMOS Inverter in
Sub-Threshold Regime
a
Ananda Sankar Chakraborty, Manash Chanda and Chandan Kumar Sarkar, Senior Member, IEEE

a
Abstract— In this paper, the Noise margin parameters of a especially neglecting the parameters like DIBL coefficient and
CMOS inverter circuit in sub-threshold regime have been body effect parameters, it has been limited to produce more
analyzed thoroughly with respect to variable supply voltage, accurate picture. To express the noise margin in sub-threshold
transistor strength and temperature; without neglecting the regime, we should include the parameters as they play major
significant DIBL and body bias effects. In particular, the change roles in submicron MOSFETs [6], [7].
in the DC characteristics shape due to operation at ultra-low In this paper we have proposed an analytical expression of
voltages is analyzed in detail, evaluating analytically the noise margin in sub-threshold regime, considering the DIBL
degradation in the logic swing, the symmetry and the steepness of and body biasing effect. The noise margin is explicitly
the transition region, as well as the change in the unity-gain
modeled with a simple and accurate expression, which allows
points and logic threshold points. Extensive simulations have
been done under 45 nm CMOS technology using CADENCE
for understanding the dependence of the robustness of static
Spice spectra to ensure the correctness of the analysis. logic on design and process parameters. As it is usually done
for any logic style, the inverter is adopted as a reference
Index Terms--Noise margin, logic threshold, sub-threshold, circuit. Extensive simulations have been done under 45 nm
voltage swing. CMOS technology using CADENCE Spice spectra to ensure
the workability of the proposed expressions.
I. INTRODUCTION This paper is organized as follows. In the first section,

D ue to the robust nature of static CMOS logic, circuits in equivalent model of MOSFETs under sub-threshold condition
is modified, taking the DIBL and body effects into account.
this technology family can operate with supply voltages
Noise margin of Sub-threshold CMOS inverter is deduced in
below the transistor threshold voltage (VTH), while consuming
the next section. Comparative analysis of theoretical and
orders of magnitude less power than in the normal strong- simulated values of different noise margin parameters on the
inversion region. The operating frequency of sub-threshold basis of variable supply voltage, transistor size and
logic is much lower than that of regular strong inversion temperature is also given in section III. Finally conclusion is
circuits (VDD> VTH) due to the small transistor current, which given in section IV.
consists entirely of leakage current. The low operating
frequency and low supply voltage combine to reduce both II. MODIFICATION OF MOSFET MODEL IN SUB-THRESHOLD
dynamic and leakage power, leading to the significant power REGIME
savings seen in sub-threshold designs. When operated in sub-threshold regime, the sub-threshold
Very few of the researchers have constructed the leakage current flowing from drain to source in an NMOS
theoretical models [1]-[4] of circuit parameters to address the dominates over gate current and bulk - junction current. The
pivotal issues like power, delay, noise margin etc. in sub- sub-threshold leakage current for an NMOS is given by the
threshold regimes. Though power dissipation [3], [4] and the [5], [7]
delays [2] have been highlighted in these works yet noise
margin of the sub-threshold circuits has been neglected. VGS −VTH −V
W DS /Vt
However, recently proposed expression [1] of the noise I = I0 ( L )e nVt (1 − e ) (1)
margin in case of a CMOS inverter under sub-threshold
condition can give an idea of voltage swings of sub-threshold Where I0 and n are technology dependent constants, Vt is
circuits. As the expression is based on some approximations, the thermal voltage (= kT / q), (W/L) is the transistor aspect
ratio, VTH is transistor threshold voltage, VGS and VDS are gate
to source and drain to source voltage respectively. As VTH
a
A. S. Chakraborty is pursuing M.Tech in the School of VLSI Technology, depends on VDS and VBS due to DIBL effect and body effect
Bengal Engineering and Science University, Howrah -711103, India (e-mail: respectively, expression for VTH becomes [7],
aschak86@gmail.com).
M. Chanda is working as an Assistant Professor in the Department of VTH = VTH0 + ψBSVSB – λDSVDS
Electronics & Communication Engineering, Meghnad Saha Institute of
Technology, Kolkata -700106, India (e-mail: manash.bst@gmail.com). Hence VTH0 is the zero-bias (VDS=VBS= 0) threshold voltage
C. K. Sarkar is working as Professor in the Department of Electronics and and λDS, ψBS (≈ γ / 8φF ) are constants related to DIBL and
Telecommunication Engineering, Jadavpur University, Kolkata-700032, India
(e-mail: phyhod@yahoo.co.in). Body-effect respectively. Substituting VTH, (1) becomes,
VGS + λ DSVDS − VDS / Vt
978-1-4673-5630-5//13/$31.00 ©2013 IEEE I = β exp( nVt
)(1 − e ) (2)
 ⎛ W ⎞ exp( − VTH0 − ψ BSVBS ) III. ANALYSIS OF NOISE MARGIN PARAMETERS
Where, β = I 0 ⎜ ⎟ nVt
⎝L⎠ A. Analysis of NML and NMH
From [1], in sub-threshold regime, when we apply “high” The noise margin characteristic for a CMOS inverter
(≈ VDD) and “low” (≈ 0) voltages at the gate of NMOS, it circuit is depicted in Fig. 1. Hence VOH, VOL, VIH, VIL are
behaves as resistor and current source respectively. So, output high voltage, output low voltage, input high voltage
VGS + λDSVDS and input low voltage respectively. VLth is the logic threshold
For VDS >>Vt, IDS ≈ βexp( nVt
) (3a) of the inverter, where input and output voltages are equal. In
Hence the current is controlled not only by VGS but also by the following, the main parameters that define in the Fig. 1 are
VDS due to DIBL effect. For VDS<< Vt, analytically modeled for arbitrary values of supply voltage
(VDD).
Vt VGS
R DS ≈ exp ( − nV ) (3b) In Fig. 2 (a) Vin= VGSn= VDD – VSGp and Vout = VDSn = VDD –
β t VSDp. The output high voltage or VOH obtained for Vin=0.
So, for low VDS (≈ Vt) NMOS behaves as a resistance When Vin= 0, the source to gate voltage (VSGp) of the PMOS is
(RDS) which decreases exponentially with increasing gate-to- high (≈VDD) and a ‘weak inversion channel’ of holes is formed
source voltage (VGS).The variation is shown in Fig. 1. in-between source and drain of the PMOS. Thus the PMOS
conducts and VSDp becomes low, and thus VDSn (=VDD – VSDp)
becomes high. So, the PMOS and the NMOS are well
approximated by the resistor and current source, given in (3b)
and (3a) respectively. Complete equivalent circuit is given in
Fig. 3.
From the resultant equivalent circuit, given in Fig. 3(b) we
get,
VOH = VDD – InRp
VDD
Vt μ 2 −μ1 Vt
= VDD – μ W ( α e ) (4)
2 0
Here α 0 =β p / β n , μ1 =(1/n p − λ DSn /n n ) and μ 2 =λ DSn /n n .
W(x) is the “Lambert’s W function of x”, given by x =
Fig. 1. Variation of Drain-Source Resistance (RDS) with Gate-Source Voltage
(VGS) for an NMOS W(x)eW(x). So, VOH strongly depends on α 0 .

Fig. 3. Equivalent inverter circuit for (a) High input and (b) Low input

Analogously output low voltage VOL can be obtained by

Fig. 2. (a) CMOS Inverter circuit (b) Noise Margin parameters
applying Vin= VDD. When Vin = VDD, the gate to source voltage
(VGSn) of the NMOS is high and a ‘weak inversion channel’ of
Table 1 gives the extracted parameter for 45nm technology electrons is formed in between source and drain of the NMOS.
file with 120 nm/ 80nm aspect ratio. So the NMOS conducts and VDSn becomes low, and thus VSDp
(=VDD – VDSn) becomes high. So, the PMOS and the NMOS
TABLE I are well approximated by the current source and resistors. The
45nm (W/L = 120 nm / 80 nm) CMOS PROCESS
complete equivalent circuit is given in Fig. 3 (a). So, from the
Device λDS ψBS n I0 (A) VTH0 (V) equivalent circuit VOL turns out to be,
NMOS 0.12 0.2 1.9 2.89E–007 0.3423 V
− μ DD
PMOS 0.0582 0.16 1.9 7.63E–008 0.23122* Vt 3 V
t )
VOL = IpRn = W (α0μ 4 e (5)
*VTH0 is the magnitude of zero-bias threshold. μ4
 Where μ 3 =(1/n n − λ DSp /n p ) and μ 4 =λ DSp /n p Fig. 7 shows the variation of Voltage Swing, with
transistor strength ratio α 0 (= β p / β n ).

Fig. 4. Comparison of theoretical and simulated values of VOH for variable

supply voltage (VDD)

Fig. 7. Comparison of theoretical and simulated values of VOH for variable

transistor strength ratio ( α 0 = βp / βn )

As VIL is treated as input low voltage, so the corresponding

output will be almost at high level. The equivalent circuit is
thus similar to Fig. 3 (b). Here Rp and In are,
Vt Vin −VDD
Rp ≈ βp
exp(
n p Vt
)

Vin +λ DSnVout
I n = β n exp( n n Vt
)
Fig. 5. Comparison of theoretical and simulated values of VOL for variable
supply voltage (VDD) So, Vout = VDD – InRp (7)

Hence we can get the logic swing (VSW) at the output from Replacing Rp, In and then applying ∂Vout / ∂Vin = −1 in
the expressions of VOH and VOL. Hence (7) we solve for Vin = VIL to ultimately get
VSW = VOH – VOL μ V α μ
VIL = VDD μ1 + μ t ln( μ –0μ )+Vt μ (μ 2– μ ) (8)
VDD VDD 5 5 5 2 5 5 2
−μ −μ
Vt μ
2
1V
t
Vt 3V
t nnnp
= VDD − μ W( α e )−
μ4 W(α 0 μ4e ) (6) Here, μ 5 = n + n = μ 1 + μ 2 + μ 3 + μ 4
2 0 n p

Fig. 6. Comparison of theoretical and simulated values of voltage swings for Fig. 8. Comparison of theoretical and simulated values of VIL for variable
variable supply voltage (VDD) supply voltage (VDD)
 Similarly as VIH is treated as input high voltage, so the
corresponding output will be almost at low level. The
equivalent circuit is thus similar to Fig. 3(a), where Rn and Ip
are,
Vt V
Rn = exp ( − n in )
βn n Vt
VDD (1+λ DSp ) – (Vin +λ DSpVout )
I p = βp exp[ npVt
]

So, Vout = I p Rn (9)

Replacing Rn and Ip and then applying ∂Vout / ∂Vin = −1
in (9) we solve for Vin = VIH, to get,
Fig. 11. Comparison of theoretical and simulated values of NMH for variable
μ V μ
VIH = (1 – μ3 )VDD + μ t ln[α0 (μ5 –μ4 )] – Vt μ (μ 4–μ ) (10)
supply voltage (VDD)
5 5 5 5 4 Change in ambient temperature affects both the high and
Hence both VIH and VIL follow direct linear relationship low noise margins vividly through the change in the inherent
with supply voltage VDD. The variation of VIH and VIL with thermal voltage term (Vt = kT/q). The variation of high and
supply voltage (VDD) is shown in Fig. 8 and 9. low noise margins with temperature are shown in Fig. 12 and
13 respectively.

Fig. 9. Comparison of theoretical and simulated values of VIH for variable

supply voltage (VDD)
Fig. 12. Comparison of theoretical and simulated NMH for variable
So, upper and lower noise margins can be found as, temperature
NMH = VOH − VIH and NML = VIL − VOL
The variations of NML and NMH with supply voltage (VDD)
are shown in Fig. 10 and 11 respectively.

Fig. 13. Comparison of theoretical and simulated NML for variable

temperature

If transistor strength ratio is increased by increasing PMOS

Fig. 10. Comparison of theoretical and simulated values of NML for variable
strength, keeping all other parameters fixed, the PMOS will
supply voltage (VDD)
conduct more. The parameters VIH and VIL will gradually shift
towards the point Vin = VDD in the voltage transfer Fig. 16 shows that the theoretical values of VLth for different
characteristics of the inverter. So for increasing strength ratio supply voltage almost match with the simulated value
α 0 (= β p / β n ) NMH should decrease and NML should increase.
This is depicted in Fig. 14 and 15 respectively.

Fig. 16. Comparison of theoretical and simulated logic threshold Voltage for
Fig. 14. Comparison of theoretical and simulated NMH for variable transistor variable VDD

strength ratio ( α 0 = βp / βn ) With 160mV supply voltage, the theoretical VLth differs from
simulated value by 4.18 mV and the differences diminish with
higher value of VDD (VDD > 175mV).
IV. CONCLUSION
In particular the “Noise Margin” has been analyzed
thoroughly without neglecting the DIBL and Body effects,
with respect to different circuital parameters: Supply Voltage,
Transistor Strength and Temperature. The logic threshold
voltage for an Inverter has also been derived in this paper. The
resulting expressions permit to gain an insight into the basic
dependence of device parameters on transfer characteristics of
an Inverter. Results have been validated through simulations
using 45-nm CMOS technology.
V. REFERENCES
Fig. 15. Comparison of theoretical and simulated NML for variable transistor [1] M. Alioto, “Closed-form analysis of DC noise immunity in subthreshold
CMOS logic circuits,” ISCAS, pp. 1468 - 1471 , June2010.
strength ratio ( α 0 = βp / βn ) [2] A.Valentian, O. Thomas, A. Vladimirescu, A. Amara, “Modeling
subthreshold SOI logic for static timing analysis,” IEEE Transaction on
B. Analysis of Logic Threshold VLSI system, issue 6, vol. 12, pp. 662 – 669, June 2004.
[3] A. Raychowdhury,B. C. Paul, S. Bhunia, K. Roy, “Computing with
The logic threshold VLth of an inverter can be found by subthreshold leakage: device/circuit/architecture co-design for ultralow-
equating the PMOS and NMOS currents with the constraint power subthreshold operation,” IEEE Transaction on VLSI systems, vol.
Vout = Vin = VLth , which leads to the following condition, 13, no. 11, pp. 1213-1224,Nov. 2005.
[4] H. Soeleman, K. Roy, and B. C. Paul, “Robust subthreshold logic for
Ip= In ultralow power operation,” IEEE Trans. Very Large Scale Integr.
1+λ V –V VLth 1+λDSn
(VLSI) Syst., vol. 9, no. 1, pp. 90–99, Sep. 2001.
[( DSp )( DD Lth )] ( ) [5] Christian C. Enz, François Krummenacher and Eric A. Vittoz, “An
np Vt Vt nn
Or, βpe ≈ βne (11) Analytical MOS Transistor Model Valid in All Regions of Operation
and Dedicated to Low-Voltage and Low-Current Applications”.Analog
Integrated Circuits and Signal Processing Journal on Low-Voltage and
Solving (11) for VLth we get, Low-Power Design 8: 83–114, July 1995.
1+λ DSp [6] N. Weste and D. Harris, CMOS VLSI Design. Boston, MA: Addison
V DD ( )+Vt ln(α 0 ) Wesley, 2004.
np (12) [7] Y. Tsividis, Operation and Modeling of the Transistor MOS, 2nd ed.
V Lth = Oxford, U.K.: Oxford University Press, 2003.
⎛ 1+λ DSp ⎞ ⎛ 1+λ DSn ⎞
⎜ n ⎟+⎜ n ⎟
⎝ p ⎠ ⎝ n ⎠

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