ASSIGNMENT

ON
VLSI DESIGN
JOYAL JOSE AUGUSTINE
1.What is the need for demarcation line?

Demarcation line separates n and p transistors.In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to
be on the other side.

2. Compare NMOS and PMOS transistor.

NMOS and PMOS are two different types of MOSFETs. The main difference between NMOS and
PMOS is that, in NMOS, the source and the drain terminals are made of n-type semiconductors
whereas, in PMOS, the source and the drain are made of p-type semiconductors.

3. Define propagation delay of CMOS inverter.

The propagation delay times are defined as the time delay between the 50% crossing of the
input and the corresponding 50% crossing of the output. The rise time and the fall time of the
output signal are defined as the time required for the voltage to change from its 10% level to its
90% level (or vice versa).

4. Mention the different types of scaling technique.

There are three types of scaling as constant voltage, constant field and lateral scaling.

5.Why NMOS transistor is selected as pull down transistor?

Pull down means bring output to Zero from One too. If input is One for an inverter in CMOS, N
transistor will be drive the output to Zero as pull down. If PMOS is used to pull down with source
as VSS output will be at By and similarly, NMOS gives VDD minus one threshold as output if
source connected to VDD.

6. Describe the lambda based design rules used for layout.

The Mead-conway approach is to characterize the process with a single scalable parameter
called lambda, that is process-dependent and is defined as the maximum distance by which a
geometrical feature on any one layer can stray from another feature, due to overetching,
misalignment, distortion, over or under exposure etc. with a suitable safety factor included.

The purpose of defining lambda properly is to make the design itself independent of both
process and fabrication and to allow the design to be rescaled at a future date when the
fabrication tolerances are shrunk.

7.What is stick diagram? Sketch the stick diagram for 2 input NAND gate.

stick diagrams are a means of capturing topography and layer information using simple
diagrams. Stick diagrams convey layer information through colour codes (or monochrome
encoding). Acts as an interface between symbolic circuit and the actual layout.
8.Explain the hot carrier effect.

The hot-carrier effect is a reliability problem which occurs when hot (energetic) carriers cause Si-
Si02 interface damage and/or oxide trapping. This leads to the degradation of the current drive
capability of the transistor, thus eventually causing circuit failure.

9. Draw the DC transfer characteristics of CMOS inverter.

10.Name the different operating modes of transistor?

The four transistor operation modes are:

Saturation -- The transistor acts like a short circuit. Current freely flows from collector to
emitter.

Cut-off -- The transistor acts like an open circuit. No current flows from collector to emitter.

Active -- The current from collector to emitter is proportional to the current flowing into the
base.
 Reverse-Active -- Like active mode, the current is proportional to the base current, but it flows in
reverse. Current flows from emitter to collector (not, exactly, the purpose transistors were
designed for).

12. What are the steps involved in IC fabrication?

IC Fabrication Process

Wafer Preparation.

Oxidation.

Diffusion.

Ion Implantation.

Chemical-Vapor Deposition.

Photolithography.

Metallization.

Packaging.

13.Discuss the limitations of the constant voltage scaling.

In Constant voltage scaling, drain current density and power density are increased which may
eventually cause serious reliability problem for the scaled transistor such as electro-migration,
hot carrier degradation, oxide breakdown & electrical overstress.

14.Define body effect and write the threshold equation including the body effect.

Body effect refers to the change in the transistor threshold voltage (VT) resulting from a voltage
difference between the transistor source and body.

15.Design a 3 input NAND gate.

16. List out second order effects of MOS transistor.

The Second order effects are:-

1) Channel Length Modulation

2) Velocity Saturation

3) Mobility Degradation

4) Threshold Voltage

5) Temperature Dependence

6) Hot-Carrier Effects

18. Summarize the equation for describing the channel length modulation effect in NMOS transistor.

19. Why the tunneling current is higher for NMOS transistors than PMOS transistors with silica gate?
 In the nMOS device, the majority electron tunneling current always exceeds the hole tunneling
current due to the lower electron mass and barrier height (3.2 eV instead of 4.65 eV for holes).

21. Describe path logical effort.

The path effort is expressed in terms of the path logical effort G (the product of the individual
logical efforts of the gates), and the path electrical effort H (the ratio of the load of the path to
its input capacitance).

22. List the methods to reduce dynamic power dissipation.

To reduce the power usage, clock frequency, reduction of switching activity, voltage scaling is
very widely used. This technique is a very popular technique mainly used for the reduction of
dynamic power dissipation . In clock gating technique, more logic gates are added to the circuits
to trim the clock tree.

23.Calculate logical effort and parasitic delay of n input NOR gate.

The logical effort of a two-input NOR gate can be found to be g = 5/3. Due to the lower logical
effort, NAND gates are typically preferred to NOR gates.

for a two-input NOR gate, the delay is

24.Distinguish between static and dynamic CMOS design.

Static CMOS circuits use or utilise complementary nMOS pulldown. And pMOS pull-up networks
to implement logic gates or logic functions in integrated circuits. Dynamic gates use a clocked
pMOS pullup. The enforced logic performs or the gate is achieved through 2 modes of
operation: Precharge and choose.

25. Explain pass transistor logic.

In electronics, pass transistor logic (PTL) describes several logic families used in the design of
integrated circuits. It reduces the count of transistors used to make different logic gates, by
eliminating redundant transistors. Transistors are used as switches to pass logic levels between
nodes of a circuit, instead of as switches connected directly to supply voltages.[1] This reduces
the number of active devices, but has the disadvantage that the difference of the voltage
between high and low logic levels decreases at each stage. Each transistor in series is less
saturated at its output than at its input.[2] If several devices are chained in series in a logic path,
a conventionally constructed gate may be required to restore the signal voltage to the full value.
By contrast, conventional CMOS logic switches transistors so the output connects to one of the
 power supply rails, so logic voltage levels in a sequential chain do not decrease. Simulation of
circuits may be required to ensure adequate performance.

26. Design an AND gate using pass transistor.

If B is high, the output has a low-resistance path to the supply rail or ground, depending on the
state of A (we’re assuming here that the A signal is generated by a low-resistance driver of some
kind). If B is low, the upper transistor is in cutoff, but the output is not floating because the
lower transistor, which is driven by the complement of B, provides a low-resistance path to
ground.

27. Justify why the interconnect increase the circuit delay

Capacitance and resistance of interconnects have increased due to the smaller wire cross
sections, smaller wire pitch and longer length. This has resulted in increased RC delay. As
technology is advancing scaling of interconnect is also increasing.

28.Define critical path

The critical path is the longest path in the circuit and limits the clock speed. When describing a
digital circuit there are two other important factors: latency and throughput.

29. What is Elmore constant?

The Elmore delay for Vout is given as tpd = R1C1+(R1+ R2)C2 , which is similar to the delay
expression gotten for the two-time constant (TTC)

30. State the advantages of transmission gates.

The combination of both an PMOS and NMOS in Transmission Gate arrangement avoids the
problem of reduced noise margin, increase switching resistance and increased static power
dissipation (caused by increased Threshold Voltage), but requires that the control and its
complement be available.

32. Implement a 2:1 MUX using pass transistor.

33.Narrate about logical effort.

Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an
inverter delivering the same output current.

34.Summarize the expression for electrical effort of logic circuits.

35.Illustrate the method for reducing energy consumption of a logic circuit.

The most research on the power consumption of circuits has been concentrated on the
switching power and the power dissipated by the leakage current has been relatively minor
area. In today‟s IC design, one of the key challenges is the increase in power dissipation of the
circuit which in turn shortens the service time of battery-powered electronics, reduces the
long-term reliability of circuits due to temperature-induced accelerated device and
interconnects aging processes, and increases the cooling and packaging costs of these
circuits. In this paper the main aim is to reduce power dissipation. A new design method for
various logical circuits design, which is low power, compared to general Static CMOS logic.
In this technique both NMOS transistor and PMOS transistors in various logic circuits is
 split into two transistors. Leakage current flowing through the NMOS transistor stack reduces
due to the increase in the source to substrate voltage in the top NMOS transistor and
also due to an increase in the drain to source voltage in the bottom NMOS transistor
Leakage current flowing through the PMOS transistor stack reduces due to the increase in the
source to substrate voltage in the top PMOS transistor and also due to an increase in the
drain to source voltage in the bottom NMOS transistor. The tool used is TANNER EDA for
schematic simulation. The simulation technology used is MOSIS 180nm.

36.Discuss the advantages of power reduction in CMOS circuits.

In CMOS circuits, as the technology scales down to nanoscale, the sub-threshold leakage current
increases with the decrease in the threshold voltage. LECTOR, a technique to tackle the leakage
problem in CMOS circuits, uses two additional leakage control transistors, which are self-
controlled, in a path from supply to ground which provides the additional resistance thereby
reducing the leakage current in the path. The main advantage as compared to other techniques
which involves the sleep transistor is that LECTOR technique does not require any additional
control and monitoring circuitry, thereby limits the area increase and also the power dissipation
in active state. Along with this, the other advantage with LECTOR technique is that it does not
affect the dynamic power which is the major limitation with the other leakage reduction
techniques.

37.Point out the factors that cause static power dissipation in CMOS circuits.

Power dissipation in CMOS circuits arises from two different mechanisms: static power, which is
primarily leakage power and is caused by the transistor not completely turning off, and dynamic
power, which is largely the result of switching capacitive loads between two different voltage
states.

38.Mention the sources of power dissipation.

Power dissipation in CMOS circuits comes from two components: Dynamic dissipation due to:
charging and discharging load capacitance as gate switch. "short circuit" current while both
PMOS and NMOS are partially ON.

39. Draw the pseudo NMOS logic gate.

40. If load capacitance increases, what will happen to CMOS power dissipation?
 Larger load capacitance draws more charge from a power supply during each switching and
therefore increases dynamic power dissipation.

41. List the advantages of differential flip flops.

S-R flip flops is that the combination of S=1 and R= 1 cannot occur. The advantage of using this
type offlip flop is the simplicity of it and it generates certain outputs. If we were to use any other
method thecircuit would be bigger and more complex. The flip flop simplifies the desired
outputs.

The advantage of D flip-flops is their simplicity and the fact that the output and input are
essentially identical, except displaced in time by one clock period. A delay flip flop in a circuit
increases the circuit's size, often to about twice the normal. Additionally, they also make the
circuits more complex.

The J-K flip-flop is much faster. The J-K flip-flop does not have propagation delay problems. The
J-K flip-flop has a toggle state.

Advantages of T Flip-Flop

These Flip-Flops has a toggle input and a clock. When a clock is triggered it inverts the value of
Flip-Flops.

They are good for counters.

In Minecraft piston, they are used as they are very small in size.

42.Enumerate about NORA CMOS in brief?

NORA or np-CMOS design style has been proposed as a race-free dynamic CMOS technique for
pipelined circuits. NORA logic is constructed of cascaded nMOS and pMOS dy- namic logic
networks that end on latches

43. Sketch the characteristic curve of meta stable state in static latch.

44. Distinguish between a latches and flip flop

 The major difference between flip-flop and latch is that the flip-flop is an edge-triggered type of
memory circuit while the latch is a level-triggered type. It means that the output of a latch
changes whenever the input changes.

46.Define Clock Jitter.

Clock jitter is deviation of a clock edge from its ideal location. Understanding clock jitter is very
important in applications as it plays a key role in the timing budget in a system.

47.Summarize the operation modes of NORA logic.

A clock signal CLK and its complement CLKB are uti- lized for the circuit operation which is
divided in two phases, the precharge and the evaluation. In the precharge phase the latch is in
the hold mode of operation while in the evaluation phase it is in the transparent mode of
operation.

48.Determine the property of clock overlap in the registers.

A clocking methodology for VLSI chips which uses global overlapping clocks plus locally or
remotely generated non-overlapping clocks. Two overlapping clocks and two non-overlapping
clocks are thus available in each block of a chip for use as timing edges. The global overlapping
clocks are used where possible to provide timing advantages, while the non-overlapping clocks
are used to eliminate race conditions as data propagates down a pipeline of transparent
registers. Generally, one non-overlapping clock has an edge which must fall before a clock edge
of the other non-overlapping clock rises and an edge which must rise after a clock edge of the
other non-overlapping clock falls. These signals may be applied to adjacent stages to prevent
race conditions; however, the "dead" time between the falling of one clock edge and the rising
of the other clock edge has performance costs. Overlapping clocks are used whenever such race
conditions can be avoided, as at the ends of the register pipeline, with the resultant
performance improvement. The non-overlapping clock signals are preferably derived from the
overlapping clock signals inside each block rather than globally so that it is easier to control the
skew between phases of the non-overlapping clock signals. Such use of local non-overlapping
clock generators in each block also reduces the amount of capacitive loading on the global
overlapping clock network, thereby allowing faster edges and smaller skews on the global
overlapping clock which further improves the performance of critical timing paths which use the
global overlapping clock.

49.What is Klass semi dynamic flip flop?

Edge-Triggered Semi-dynamic Flip flop (Klass 1998) The primary requirements of a flip-flop in
highspeed digital design are short latency and a simple & robust clocking scheme. Although, the
design by Klass(1998) provided for short-latency, no considerations were done towards clocking
scheme.

50.Recall the methods of sequencing static circuit.

 SEQUENCING STATIC CIRCUITS

q Combinational logic

– output depends on current inputs

q Sequential logic

– output depends on current and previous inputs

– Requires separating previous, current, future

– Called state or tokens

– Ex: FSM, pipeline

51.Write about pipelining?

Pipelining is the process of accumulating instruction from the processor through a pipeline. It
allows storing and executing instructions in an orderly process. It is also known as pipeline
processing. Pipelining is a technique where multiple instructions are overlapped during
execution.

52.Compare and Contrast Synchronous and Asynchronous Design?

53.Explain simple synchronizer circuit.

Flip-flop based synchronizer (Two flip-flop synchronizer): This is the most simple and most
common synchronization scheme and consists of two or more flip-flops in chain working on the
destination clock domain. This approach allows for an entire clock period for the first flop to
resolve metastability. Let us consider the simplest case of a flip-flop synchronizer with 2 flops as
shown in figure. Here, Q2 goes high 1 or 2 cycles later than the input.

59.Why pipelining is need for of sequential circuits?

 Pipelining keeps all portions of the processor occupied and increases the amount of useful work
the processor can do in a given time. Pipelining typically reduces the processor's cycle time and
increases the throughput of instructions.

66. What is latency?

Latency is the time needed for an input change to produce an output change; latency can be
expressed as a length of time or, in synchronous circuits, as a certain number of clock cycles.

70.Define Clock gating.

Clock gating is a power-saving feature in semiconductor microelectronics that enables switching

off circuits. Many electronic devices use clock gating to turn off buses, controllers, bridges and
parts of processors, to reduce dynamic power consumption.

1.Illustrate with necessary diagrams Electrical properties of MOS transistor in detail.

MOSFET Current – Voltage Characteristics

To understand the current – voltage characteristic of MOSFET, approximation for the channel is
done. Without this approximation, the three dimension analysis of MOS system becomes
complex. The Gradual Channel Approximation (GCA) for current – voltage characteristic will
reduce the analysis problem.

2. Describe the CMOS inverter and Derive the DC characteristics.

DC TRANSFER CHARACTERISTICS OF CMOS INVERTER

The general arrangement and characteristics are illustrated in Figure. The current/voltage
relationships for the MOS transistor may be written as,
Where Wn and Ln, Wp and Lp are the n- and p- transistor dimensions respectively. The CMOS
inverter has five regions of operation is shown in Fig.1.2 and in Fig. 1.3.

Considering the static condition first, in region 1 for which Vin = logic 0, the p-transistor fully
turned on while the n-transistor is fully turned off. Thus no current flows through the inverter
and the output is directly connected to VDD through the p-transistor.

In region 5 Vin = logic 1, the n-transistor is fully on while the p-transistor is fully off. Again, no
current flows and a good logic 0 appears at the output.

In region 2 the input voltage has increased to a level which just exceeds the threshold voltage of
the n-transistor. The n-transistor conducts and has a large voltage between source and drain.
The p- transistor also conducting but with only a small voltage across it, it operates in the
unsaturated resistive region
In region 4 is similar to region 2 but with the roles of the p- and n- transistors reversed.

The current magnitudes in region 2 and 4 are small and most of the energy consumed in
switching from one state to the other is due to the large current which flows in region 3.

In region 3 is the region in which the inverter exhibits gain and in which both transistors are in
saturation.

Write

The currents in each device must be the same since the transistors are in series. So we may

I dsp = - Idsn

Vin in terms of the β ratio and the other circuit voltages and currents

Vin = VDD + Vtp +Vtn (βn + βp)1/2 / 1+ (βn + βp)1/2

Since both transistors are in saturation, they act as current sources so that the equivalent circuit
in this region is two current sources so that the equivalent circuit in this region is two current
sources in series between VDD and VSS with the output voltage coming from their common
point.

The region is inherently unstable in consequence and the change over from one logic level to
the other is rapid.

Since only at this point will the two β factors be equal. But for βn= βp the device geometries
must be such that

µ pWp/Lp = µ n Wn/Ln

The motilities are inherently unequal and thus it is necessary for the width to length ratio of the
p- device to be three times that of the n-device, namely

Wp/Lp = 2.5 Wn/Ln

 The mobility µ is affected by the transverse electric field in the channel and is thus independent
on Vgs.

It has been shown empirically that the actual mobility is

µ= µ z (1 – Ø (Vgs – Vt)-1

Ø is a constant approximately equal to 0.05 Vt includes anybody effect, and µ z is the

mobility with zero transverse field.

3. Narrate in detail about ideal I-V characteristics and non-ideal I-V characteristics of NMOS

and PMOS devices.

An analogy for Ideal IV characteristics of PMOS transistor

We will not be explicitly deriving the IV characteristics for the PMOS device separately because
both the derivation and the final curves obtained are very similar to that of NMOS. A diagram
showing the biasing scheme for a PMOS transistor is shown in figure

It is observed from this diagram that the directions of the currents and voltages are inverted. For
example, if we want to operate the PMOS in its saturation region, then we will apply a positive
V_{SG} and also a V_{SD} which is more than the magnitude of V_{T}. The inversion in the
direction of the current is also taken into account as the current is now coming out of the drain
terminal. In this case, the conduction will be due to the formation of a hole inversion layer when
we apply a voltage less than a threshold value(negative in case of enhancement-mode PMOS) at
the gate w.r.t. Source. Thus it is clear that in the NMOS, if every quantity gets inverted by a
negative sign, then it’s operation will be the same as that of a PMOS.
5. Mention in detail about second order effects in MOS transistor.

The Second order effects are:-

1) Channel Length Modulation:

There are some subtleties to the operation of the transistor in the saturation region. The length
of the channel changes with changing values of VDS. As the value of VDS is increased, it causes
the depletion region of the Drain junction to grow. This reduces the length of the channel which
impacts current. The model current equation must be modified to
In general, lambda is proportional to channel length. The effects of channel length modulation
become more pronounced for smaller feature sizes. Thus, when a high impedance current
source is required, longer channel transistors are used.

2) Velocity Saturation:

For high VDS, carriers experience higher lateral electric fields. Carrier velocity increases with
increasing lateral electric fields. However, once the critical lateral electric field is reached, the
velocity of the carriers does not increase any further. This is caused by an increased rate of
collision and carrier scattering. The current does not increase at the expected rate. Rather, the
current increases very little, if at all.

3) Mobility Degradation:

With increasing VGS, vertical electric fields increase. This increase causes a rise in the number of
carrier collisions, which degrades carrier mobility. The current flowing through the transistor is
therefore than that expected by the ideal models. Mobility decreases with increasing
temperature.

4) Threshold Voltage:

The threshold voltage is the value of gate voltage (VGS) at which strong inversion occurs. In
other words, this is the voltage at which the transistor begins to conduct current. The Threshold
Voltage depends on:

1.Thickness of the oxide layer: 2.Charge of the impurities trapped between the silicon and the
oxide 3.Dosage of ions implanted for threshold adjustment 4.Source to Bulk Voltage

The channel strength and the threshold voltage can be changed through application of
appropriate voltage to the body terminal of the MOSFET. This is known as the body effect.

For gate voltages less than threshold voltage, current drops off exponentially and as feature
sizes decrease the way MOSFETs behave in this region becomes important. The transistor
conducts some current before VGS = Vt. This is called sub-threshold conduction.
 5) Temperature Dependence:

Carrier Mobility: Decreases with temperature

Threshold Voltage: Decreases with temperature

Junction Leakage: Increases with temperature

Velocity Saturation: Occurs sooner with higher temperature

Sub-threshold conduction: Increases exponentially with temperature. This means that at low
temperatures, lower threshold voltages can be used.

Most wear out mechanisms are temperature dependent so transistors are more reliable at
lower temperatures.

6) Hot-Carrier Effects:

The hot carrier effect can cause the threshold voltage of a device to drift over time. Smaller
devices mean that carriers experience higher electric fields. This is because while device sizes
have scaled, power signal voltages have not scaled at the same rate. These high electric fields
can cause electrons to become hot. These electrons have very high energy, and can tunnel into
the gate oxide. These electrons, trapped in the gate oxide, can cause a rise in the Vt of a device.

To avoid this, designers use specially engineered drain and source regions to ensure that the
strength of the electric fields are limited so as to avoid the generation of hot carriers.

6.Summarize the following: i) CMOS process enhancements (8) ii) Layout design rules.

CMOS Process Enhancements :

In the Analog, Digital or RF CMOS integrated circuits along with transistors other elements such
as interconnects, resistors, capacitors are to be integrated on chip. In order to achieve this,
enhancements in CMOS process technology is required. The main goals of adding CMOS
enhancements are :

(1) To provide on chip capacitors for analog circuits.

(2) To provide on chip resistors.

(3) To provide routing of interconnects.

The enhancements in CMOS technology are :

(1) Multilevel metal layers.

(2) Multilevel poly layers.

The layout design rules provide a set of guidelines for constructing the various masks needed in
the fabrication of integrated circuits. Design rules are consisting of the minimum width and
minimum spacing requirements between objects on the different layers.

The most important parameter used in design rules is the minimum line width. This parameter
indicates the mask dimensions of the semiconductor material layers. Layout design rules are
used to translate a circuit concept into an actual geometry in silicon.

The design rules is the media between circuit engineer and the IC fabrication engineer. The
Circuit designers requires smaller designs with high performance and high circuit density
whereas the IC fabrication engineer requires high yield process.

Minimum line width (MLW) is the minimum MASK dimension that can be safely transferred to
the semiconductor material. For the minimum dimension design rules differ from company to
company and from process to process.

To address this issue scalable design rule approach is used. In this approach rules are defined as
a function of single parameter called ' '. For an IC process ' ' is set to a value and the design
dimensions are converted in the form of numbers. Typically a minimum line width of a process is
set to 2 e.g. for a 0.25 m process technology ' ' equals 0.125 m.

Layered Representation of Layout :

 The layer representation of layout converts the masks used in CMOS into a simple layout levels
that are easier to visualise by the designers. The CMOS design layouts are based on following
components :

(1) Substrates or Wells : These wells are p type for NMOS devices and n type for PMOS devices.

(2) Diffusion regions : At these regions the transistors are formed and also called as active layer.
These are defined by n+ for NMOS and p+ for PMOS transistors.

(3) Polysilicon layers : These are used to form the gate electrodes of the transistors.

(4) Metal interconnects layers : These are used to form the power supply and ground rails as
well as input and output rails.

(5) Contact and Via layers : These are used to form the inter layer connections.

8.Analyze the following combinational circuits using the CMOS logic:

i) Two input NOR gate. ii) Parity generator ii i) Two input NAND gate. iv) Multiplexers
Parity checker

Parity checker is the process that transmits the data between nodes

during communication. Original bits are used to create an even and

odd bit number. These bits are transmitted through a link that can be

any medium. Data is considered to be accurate when the transmitted

and received bits are equal. Parity checker is implemented using the

Xor tree.

3.Implementation of Proposed Parity Checker Using

Different Techniques

The Self-checking circuit is comprised of 3 components parity

checker, glitch filter and TD- checker. In this paper, the parity

checker is implemented through different methods and compared the

output and come to conclusion that which method can be used. Parity

checker is implemented by the following ways: -

1. CMOS

2. Pass Transistors

3. Transmission gate
CMOS using both PMOS and NMOS to implement a logic gate. One

MOSFET works at one time and gives us a strong ‘0’ and ‘1’. Here CMOS is implemented by using
8 MOSFETS and 4 MOSFETS.
MUX using CMOS logic

The implementation of 4 : 1 MUX using CMOS logic is shown in Figure below.

9. Describe in detail about

i) Delay estimation. ii) Logical effort. iii) Transistor sizing.

Time delay estimation (TDE) is the problem of estimating the time delay between two received
signals which have originated from same transmitter. 1. This estimation problem is of
fundamental importance in radar signal processing for detecting the presence of targets and
identifying radar transmitters.

Logical effort is defined as the ratio of the input capacitance of a gate to the input capacitance
of an inverter delivering the same output current. It is defined as the number of times worse it is
at delivering output current than would be an inverter with identical input capacitance.

the operation of enlarging or reducing the channel width of transistors, is a powerful and
effective performance optimization tool in the hands of the designer.

Transistor size is an important part of improving computer technology. The smaller your
transistors, the more you can fit on a chip, and the faster and more efficient your processor can
be.

10. With supporting diagrams, give notes on :

i) Static CMOS ii) Bubble pushing iii) Compound gates.

Static logic is a design methodology in integrated circuit design where there is at all times some
mechanism to drive the output either high or low. For example, in many of the popular logic
families, such as TTL and traditional CMOS, there is always a low-impedance path between the
output and either the supply voltage or the ground. The most widely used logic style is static
CMOS. A static CMOS gate is a combination of two networks, called the pull-up network (PUN)
and the pull-down network (PDN). The function of the PUN is to provide a connection between
the output and VDD anytime the output of the logic gate is meant to be 1 (based on the inputs).
Similarly, the function of the PDN is to connect the output to VSS when the output of the logic
gate is meant to be 0 (based on the inputs). The PUN and PDN networks are constructed in a
mutually exclusive fashion such that, one and only one of these networks is conducting in the
steady state.

Static Logic Design of NAND, NOR, XOR and XNOR Gates

Bubble pushing is a technique to apply De Morgan's theorem directly to the logic diagram.
Change the logic gate (AND to OR and OR to AND). Add bubbles to the inputs and outputs where
there were none, and remove the original bubbles.
 Compound logic gates (sometimes Complex logic gate) are simple devices that function like a
few basic logic gates combined. Typically made from a few levels of logic, those gates can be
used in optimizing various circuits in terms of area and transistors, yielding better performance.
This is especially true when development is restricted to a vendor's standard cell library. While
some are rarely used by actual logic designers (simply due to their complexity), those gates are
often used by optimization programs are able to make efficient use of such gates.

11. Discuss briefly the principle and operation of the following along with its

advantages. i) Pass Transistor logic ii) Complementary Pass Transistor Logic

In electronics, pass transistor logic (PTL) describes several logic families used in the design of
integrated circuits. It reduces the count of transistors used to make different logic gates, by
eliminating redundant transistors. Transistors are used as switches to pass logic levels between
nodes of a circuit, instead of as switches connected directly to supply voltages.[1] This reduces
the number of active devices, but has the disadvantage that the difference of the voltage
between high and low logic levels decreases at each stage. Each transistor in series is less
saturated at its output than at its input.[2] If several devices are chained in series in a logic path,
a conventionally constructed gate may be required to restore the signal voltage to the full value.
By contrast, conventional CMOS logic switches transistors so the output connects to one of the
power supply rails, so logic voltage levels in a sequential chain do not decrease. Simulation of
circuits may be required to ensure adequate performance.

The advantages of pass-transistor logic are the simple design, the reuse of already available
signals, and the low contribution to static power. However, as against other types of logic, the x
signals are not regenerated, instead, they are passed through an RC structure.
12.Write the principle of transmission gate using the design of multiplexer.

A transmission gate, or analog switch, is defined as an electronic element that will selectively
block or pass a signal level from the input to the output. This solid-state switch is comprised of a
pMOS transistor and nMOS transistor. The control gates are biased in a complementary manner
so that both transistors are either on or off.

2 : 1 MUX using transmission gate :

A 2:1 multiplexer is shown in Figure below. This gate selects either input A or B on the basis of
the value of the control signal 'C'.When control signal C is logic low the output is equal to the
input A and when control signal C is logic high the output is equal to the input B.

A 2 : 1 multiplexer can be implemented using transmission gates. Figure below shows the
connection diagram of the 2 : 1 multiplexer using transmission gates. The 2 : 1 MUX selects
either A or B depending upon the control signal C. This is equivalent to implementing the
Boolean function,

F = (A C + B ––C)

When the control signal C is high then the upper transmission gate is ON and it passes A through
it so that output = A.

When the control signal C is low then the upper transmission gate turns OFF and it will not allow
A to pass through it, at the same time the lower transmission gate is 'ON' and it allows B to pass
through it so the output = B.