Issue Read Issue Read CPU I/O Issue Read CPU DMA

command to CPU I/O command to Do something block command Do something

I/O module I/O module else to I/O module else

Read status Read status Interrupt Read status Interrupt

of I/O I/O CPU of I/O of DMA
I/O CPU
module module module DMA CPU
Not
ready Next instruction
Check Error Check Error
status condition status condition (c) Direct memory access
Ready Ready
Read word Read word
from I/O I/O CPU from I/O I/O CPU
Module Module

Write word Write word

CPU memory CPU memory
into memory into memory

No No
Done? Done?

Yes Yes
Next instruction Next instruction
(a) Programmed I/O (b) Interrupt-driven I/O
Figure 7.4 Three Techniques for Input of a Block of Data
 Interrupt-Driven I/O
The problem with programmed I/O is that the
processor has to wait a long time for the I/O module
to be ready for either reception or transmission of data

An alternative is for the processor to issue an I/O

command to a module and then go on to do some
other useful work

The I/O module will then interrupt the processor to

request service when it is ready to exchange data with
the processor

The processor executes the data transfer and resumes

its former processing
 Hardware Software

Device controller or
other system hardware
issues an interrupt
Save remainder of
process state
information
Processor finishes
execution of current
instruction

Process interrupt
Processor signals
acknowledgment
of interrupt
Restore process state
information
Processor pushes PSW
and PC onto control
stack
Restore old PSW
and PC
Processor loads new
PC value based on
interrupt

Figure 7.6 Simple Interrupt Processing

 +1
Control Control
Stack Stack

+1 +
Program Program
Counter Counter

Start Start
Interrupt General Interrupt General
Service Registers Service Registers
+ Return Routine + Return Routine
Stack Stack
Pointer Pointer

Processor Processor

+1 User's +1 User's
Program Program

Main Main
Memory Memory

(a) Interrupt occurs after instruction

(b) Return from interrupt
at location N

Figure 7.7 Changes in Memory and Registers for an Interrupt

 Design Issues

Because there will

be multiple I/O
modules how does
the processor
determine which
Two design issues device issued the
arise in interrupt?
implementing
interrupt I/O: If multiple
interrupts have
occurred how does
the processor
decide which one
to process?
 Device Identification
Four general categories of techniques are in common use:
Multiple interrupt lines
Between the processor and the I/O modules
Most straightforward approach to the problem
Consequently even if multiple lines are used, it is likely that each line will have multiple I/O
modules attached to it

Software poll
When processor detects an interrupt it branches to an interrupt-service routine whose job is to
poll each I/O module to determine which module caused the interrupt
Time consuming

Daisy chain (hardware poll, vectored)

The interrupt acknowledge line is daisy chained through the modules
Vector address of the I/O module or some other unique identifier
Vectored interrupt processor uses the vector as a pointer to the appropriate device-service
routine, avoiding the need to execute a general interrupt-service routine first

Bus arbitration (vectored)

An I/O module must first gain control of the bus before it can raise the interrupt request line
When the processor detects the interrupt it responds on the interrupt acknowledge line
Then the requesting module places its vector on the data lines
 Slave
82C59A
interrupt
controller
External device 00 IR0
External device 01 IR1 INT
IR2
IR3
IR4
IR5
IR6
External device 07 IR7

Slave Master
82C59A 82C59A
interrupt interrupt 80386
controller controller processor
External device 08 IR0 IR0
External device 09 IR1 INT IR1 INT INTR
IR2 IR2
IR3 IR3
IR4 IR4
IR5 IR5
IR6 IR6
External device 15 IR7 IR7

Slave
82C59A
interrupt
controller
External device 56 IR0
External device 57 IR1 INT
IR2
IR3
IR4
IR5
IR6
External device 63 IR7

Figure 7.8 Use of the 82C59A Interrupt Controller

 PA3 1 40 PA4
Power +5 V PA2 2 39 PA5
Group Group A
supplies GND PA1 3 38 PA6
A Port A I/O
control (8) PA7 - PA0 PA0 4 37 PA7
RD 5 36 WR
CS 6 35 Reset
Bi-directional Group A GND 7 34 D0
data bus Data Port C I/O A1 8 33 D1
bus upper (4) PC7 - PC4 A0 9 8255A 32 D2
D7 - D0 buffer PC7 10 31 D3
8-bit Group B PC6 11 30 D4
internal Port C I/O PC5 12 29 D5
data bus Lower(4) PC3 - PC0
PC4 13 28 D6
RD PC3 14 27 D7
Read/
WR PC2 15 26 V
write Group
A1 Group B
control B PC1 16 25 PB7
A0 Port B I/O
logic control PC0 17 24 PB6
(8) PB7 - PB0
Reset PB0 18 23 PB5
CS
PB1 19 22 PB4
PB2 20 21 PB3
(a) Block diagram (b) Pin layout

Figure 7.9 The Intel 8255A Programmable Peripheral Interface

Interrupt
request
C3 A0 R0
A1 R1
A2 R2
A3 R3
INPUT A4 R4 KEYBOARD
PORT A5 R5
A6 Shift
A7 Control

C4 Data ready
C5 Acknowledge

82C55A
B0 S0
B1 S1
B2 S2
B3 S3
OUTPUT DISPLAY
B4 S4
PORT
B5 S5
B6 Backspace
B7 Clear

C1 Data ready
C2 Acknowledge
C6 Blanking
C0 C7 Clear line
Interrupt
request

Figure 7.11 Keyboard/Display Interface to 82C55A

 Drawbacks of Programmed and
Interrupt-Driven I/O
Both forms of I/O suffer from two inherent
drawbacks:

1) The I/O transfer rate is limited by the speed with

which the processor can test and service a device

2) The processor is tied up in managing an I/O transfer;

a number of instructions must be executed for each
I/O transfer

When large volumes of data are to be moved a more efficient

technique is direct memory access (DMA)
 Data
count

Data lines Data

register

Address
Address lines register

Request to DMA
Acknowledge from DMA
Control
Interrupt
logic
Read
Write

Figure 7.12 Typical DMA Block Diagram

 Time

Instruction Cycle

Processor Processor Processor Processor Processor Processor

Cycle Cycle Cycle Cycle Cycle Cycle

Fetch Decode Fetch Execute Store Process

Instruction Instruction Operand Instruction Result Interrupt

DMA Interrupt
Breakpoints Breakpoint

Figure 7.13 DMA and Interrupt Breakpoints During an Instruction Cycle

Processor DMA I/O I/O Memory

(a) Single-bus, detached DMA

Processor DMA DMA Memory

I/O

I/O I/O

(b) Single-bus, Integrated DMA-I/O

System bus

Processor DMA Memory

I/O bus

I/O I/O I/O

(c) I/O bus

Figure 7.14 Alternative DMA Configurations

Thank you for your listening