Module-2

Input / Output organization

How program-controlled I/O is performed
using polling
How interrupts are used in I/O transfers
Direct memory access as an I/O mechanism
Synchronous and asynchronous bus
operation
Interface circuits
Commercial standards, such as USB, SCSI,
and PCI Express

1
Text Books:
Carl Hamacher, Zvonko Vranesic, Safwat Zaky:
Computer Organization, 5th Edition, Tata
McGraw Hill, 2002.
Carl Hamacher, Zvonko Vranesic, Safwat Zaky,
Naraig Manjikian : Computer Organization and
Embedded Systems, 6th Edition, Tata McGraw
Hill, 2012.
Reference Books:
William Stallings: Computer Organization &
Architecture, 9th Edition, Pearson, 2015.
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Introduction
Computer is its ability to exchange data with other devices.
Communication capability enables a human operator
Applications like an integral part of home appliances,
manufacturing equipment, transportation systems, banking
and point-of-sale (PoS) terminals.
Input from a sensor switch, a digital camera, a
microphone, or a fire alarm.
Output like a sound signal sent to a speaker, or a digitally
signal that changes the speed of a motor, opens a valve, or
a robot to move in a specified manner.
Computers should have the ability to exchange digital and
analog information with a wide range of devices in many
different environments.
3
Accessing I/O Devices
I/O device must
appear to the
processor as
consisting of some
addressable locations,
just like the memory.
The I/O devices and
the memory share the
same address space,
this arrangement is
called memory-
mapped I/O.
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I/O Mapped I/O Memory Mapped I/O

5
Count..
 Memory-mapped I/O, any machine instruction that can
access memory can be used to transfer data to or from an
I/O device.
 For example, if DATAIN is the address of a register in an
input device, the instruction
Load R2, DATAIN
reads the data from the DATAIN register and loads
them into processor register R2.
 Similarly, the instruction
Store R2, DATAOUT
sends the contents of register R2 to location
DATAOUT, which is a register in an output device.
In Intel Processor IN and OUT instructions used
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 Bus

Processor
DATAIN DATA OUT

SIN SOUT

Ke yboard Display

Figure 2.19 Bus connection for processor , ke yboard, and display

.

7
Hardware needed to access I/O devices
 Processor places a particular
address on the address lines, it
is examined by the address
decoders of all devices on the
bus.
 The device that recognizes this
address responds to the
commands issued on the
control lines.
 The processor uses the control
lines to request either a Read
or a Write operation, and the
requested data are transferred
over the data lines.
 Intel processor uses I/O
mapped I/O.
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Example
Program to reads one line from the keyboard
till return key press, store it in memory buffer
and echoes it back to the display.

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Count..

10
Program Controlled I/O
Above Example is of Program Controlled I/O
In this processor repeatedly checks a status
flags to achieve the required synchronization
between the processor and an input or output
device
Also called Processor Polls the device
Other methods are Interrupt and DMA

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Interrupts -1
Polling method – Processor waits for
response from I/O device. During wait period
processor not able perform useful
computation.
Come out from these problem using Interrupt
Can arrange for the I/O device to alert the
processor when it becomes ready. It can do so
by sending a hardware signal called an
interrupt request to the processor.

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Interrupt Example 1
Consider a task that requires continuous
extensive computations to be performed and
the results to be printed on a printer.

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Interrupt Example 2
COMPUTE produces a
set of n lines of output.
PRINT routine print this
line
After printing one line
printer sends Interrupt
request signal to the
processor. (At i th line.)
So processor interrupt
the execution of
COMPUTE routine and
transfer the control to
PRINT routine.
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Interrupt -2
 The routine executed in response to an interrupt request is called
the interrupt-service routine.
E.g. PRINT routine.
 ISR/ISP similar to Subroutine
 Processor responds or interrupt request responds to interrupted
device by sending the control signal called Interrupt
Acknowledge.
 When interrupt occurs during execution of program processor
register used, flag status information must saved in stack before
execution of the interrupted program is resumed.
 In this way, the original program can continue execution without
being affected in any way by the interruption, except for the
time delay.
 The task of saving and restoring information can be done
automatically by the processor or by program instructions.
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Interrupt -3
The process of saving and restoring registers involves
memory transfers that increase the total execution time,
and hence represent execution overhead.
Saving registers also increases the delay between the time
an interrupt request is received and the start of execution
of the interrupt-service routine.
This delay is called interrupt latency.
The amount of information saved automatically by the
processor when an interrupt request is accepted should be
kept to a minimum.
This kind of delay not acceptable in Real-time processing.
The ISR returns to interrupted program using Return-from-
Interrupt instruction.

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Interrupt Hardware
Interrupt request
If several I/O can request
an interrupt.
A single interrupt request
line may be used as shown
in figure using switch.
When device make
interrupt request by
closing switch the voltage
on the line is ‘0’
INTR is logic OR
 INTR= INTR1+INTR2+…..+INTRn
INTR is active low signal
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Enabling and Disabling Interrupt-1
Interrupt can occur any time which alter the
execution sequence.
To provide programmer complete control
over program execution event.
So interruption of program carefully
controlled i. e. by Enable and disable
interrupt as desire
Some situation interrupt have to ignore e.g.
PRINT interrupt the processor even
COMPUTE is not ready with text to print.
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Enabling and Disabling Interrupt-2
A single interrupt request from one device by
activating the interrupt-request signal, it keeps
this signal activated until it learns that the
processor has accepted its request. This means
that the interrupt-request signal will be active
during execution of the interrupt-service routine.
It is essential to ensure that this active request
signal does not lead to successive interruptions,
causing the system to enter an infinite loop from
which it cannot recover.
So three possibilities used to handle one or more
interrupt request.
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Enabling and Disabling Interrupt-3
First Possibility
Ignore the IR until complete the current ISR
i.e. first instruction of ISR is Interrupt Disable
and last instruction is Interrupt Enable

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Enabling and Disabling Interrupt-4
Second Possibility
Processor first saves the contents of the
program counter (PC) and the processor status
(PS) register with IE=1 on stack and
automatically disable interrupts before starting
the execution of the interrupt-service routine.
When return from interrupt instruction is
executed the contents of PC and PS is popped
with IE=1 from stack.

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Enabling and Disabling Interrupt-4
Third Possibility
IR line must accept only leading edge of the
signal (Edge triggered line)
Processor receive only one request regardless
of how long the line is activated.
So no question of multiple interruption or no
need of explicit instruction for enable/disable
interrupt.

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Summarize the sequence of events involved in
handling an interrupt request from a single
device
1.The device raises an interrupt request.
2.The processor interrupts the program currently being
executed and saves the contents of the PC and PS registers.
3.Interrupts are disabled by clearing the IE bit in the PS to 0.
4.The action requested by the interrupt is performed by the
interrupt-service routine, during which time the device is
informed that its request has been recognized, and in
response, it deactivates the interrupt-request signal.
5.Upon completion of the interrupt-service routine, the saved
contents of the PC and PS registers are restored (enabling
interrupts by setting the IE bit to 1), and execution of the
interrupted program is resumed.

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Handling Multiple Devices-1
The situation where a number of devices
capable of initiating interrupts are connected
to the processor
E.g. X and Y devices make IR

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Handling Multiple Devices-2
Several devices may request interrupts at exactly the
same time. This gives rise to a number of questions:
1. How can the processor determine which device is
requesting an interrupt?
2. Given that different devices are likely to require
different interrupt-service routines, how can the
processor obtain the starting address of the
appropriate routine in each case?
3. Should a device be allowed to interrupt the
processor while another interrupt is being serviced?
4. How should two or more simultaneous interrupt
requests be handled?
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Handling Multiple Devices-3
 When an interrupt request is received it is necessary to identify
the particular device that raised the request.
 If two devices raise interrupt requests at the same time.
 The information needed to determine whether a device is
requesting an interrupt is available in its status register.
 IRQ bit e.g. KIRQ and DIRQ
 Device request for interrupt the IRQ=1
 Processor serve the device using polling method.
 But polling need more time
 So go for Vectored Interrupt

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Handling Multiple Devices-4
 Vectored Interrupt
 To reduce the time involved in the polling process, a device
requesting an interrupt may identify itself directly to the processor.
Then, the processor can immediately start executing the
corresponding ISR.
 A device requesting an interrupt can identify itself if it has its own
interrupt-request signal, or if it can send a special code (like memory
address of ISR) to the processor through the interconnection network.
 A commonly used scheme is to allocate permanently an area in the
memory to hold the addresses of interrupt-service routines. These
addresses are usually referred to as interrupt vectors, and they are
said to constitute the interrupt-vector table.
 When an interrupt request arrives, the information provided by the
requesting device is used as a pointer into the interrupt-vector table,
and the address in the corresponding interrupt vector is automatically
loaded into the program counter.

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Handling Multiple Devices-5
Interrupt Nesting
 If request from more than one device.
 Sometimes some device need immediate response from
processor e.g. System Clock, Real time system.
 This can be resolved by using Priority Based Interrupt.
 Multiple-level priority
 Interrupt requests will be accepted from some devices but
not from others, depending upon the device’s priority. To
implement this scheme, we can assign a priority level to the
processor that can be changed under program control.
 Interrupt requests from higher-priority devices will
accepted.
 The processor’s priority can be encoded in a few bits of the
processor status register.
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Handling Multiple Devices-6
Privileged Instruction
Works in supervisor mode i.e. when executing
operating system routine.
But in Used mode user program cannot
accidently or intentionally change the priority
which disrupt the system operation which can
be avoided using privilege exception.

29
Handling Multiple Devices-7
 Multiple priority scheme implemented using individual INTR
and INTA lines.

 Priority arbitration circuit: A logic circuit which combines all

interrupts but allows only the highest-priority request. 30
Handling Multiple Devices-8
Simultaneous Requests
Polling the status registers of the I/O devices is
the simplest such mechanism. In this case,
priority is determined by the order in which the
devices are polled.
When vectored interrupts are used, we must
ensure that only one device is selected to send
its interrupt vector code.

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Handling Multiple Devices-9
Daisy Chain

INTR is common to all device

INTA connected in daisy chain fashion where
INTA signal propagate serially through the
devices.
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Handling Multiple Devices-10
When IR is active on INTR line then INTA
sent to Device 1 and passes to device 2 if it
does not require any service.
In daisy chain, the device that is electrically
closest to the processor had the highest
priority.

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Handling Multiple Devices-11
Combining the Multiple-priority and daisy
chain.
Where device organized in group and each
have different priority level.

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Controlling Device Request-1
It is important to ensure that interrupt requests
are generated only by those I/O devices that the
processor is currently willing to recognize.
Need a mechanism in the interface circuits of
individual devices to control whether a device is
allowed to interrupt the processor.
The control needed is usually provided in the form
of an interrupt-enable bit in the device’s interface
circuit.
To reduce unnecessary interrupt from other I/O
devices which are not used by current executing
program.
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Controlling Device Request-2
Keyboard interrupt
enable bit KEN
Display interrupt enable
bit DEN
KEN and/or DEN = 1
then only interface
circuit generate an IR.
Same time KIRQ and/or
DIRQ = 1 indicate that
both devices is
requesting an
interrupt.
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Controlling Device Request-3
Example
When a program wish to read an input line
from the keyboard and store the character in
successive byte location

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Controlling Device Request-4

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Exceptions-1
Any event that causes an interruption.
I/O interrupts are one example of an
exception
but other types of exceptions

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Exceptions-2
Recovery from Errors
 Many computers include an error-checking code in
the main memory, which allows detection of errors
in the stored data. If an error occurs, the control
hardware detects it and informs the processor by
raising an interrupt.
 The processor proceeds in exactly the same
manner as in the case of an I/O interrupt request.
 It suspends the program being executed and starts
an exception-service routine, which takes
appropriate action to recover from the error, if
possible or to inform the user about it.
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Exceptions-3
Debugging
System software usually includes a program
called a debugger, which helps the
programmer find errors in a program.
The debugger uses exceptions to provide two
important facilities: trace mode and
breakpoints.

41
Exceptions-4
Debugging
Trace Mode
 In this mode, an interrupt occurs after the execution of
every instruction. An interrupt-service routine in the
debugger program is invoked each time this interrupt
occurs.
 It allows the debugger to assume execution control,
enabling the user to enter commands for examining the
contents of registers and memory locations.
 When the user enters a command to resume execution of
the object program, a Return from- interrupt instruction
is executed.
 The next instruction in the program being debugged is
executed, then the debugger is activated again with
another interrupt.
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Exceptions-5
Debugging
Breakpoints
Breakpoints provide a similar interrupt-based
debugging facility, except that the object
program being debugged is interrupted only at
specific points indicated by the programmer.
For example, the programmer set a breakpoint
to determine whether a particular subroutine.
A special instruction called Trap or Software-
interrupt is usually used to implement
breakpoints.

43
Exceptions-6
Privilege Exception
To protect the OS from being corrupted by user
programs certain instructions (Privilege
Instructions) can executed only when
processor is in superior mode.
In user mode these instruction not executed,
so that user program does not change the
priority level of the processor or program
access area.

44
Direct Memory Access (DMA)-1
To transfer large blocks of data at high
speed, an alternative approach is used.
A special control unit provided to allow
transfer of a block of data directly between
an external device and the main memory,
without continuous intervention by the
processor. This approach is called DMA.

45
Direct Memory Access (DMA)-2
DMA transfers are performed by a control
circuit that is part of the I/O device interface
called DMA controller.
For each word transferred, processor
provides the memory address and all the
bus signals that control data transfer.
Since processor has to transfer blocks of
data, the DMA controller must increment the
memory address for successive words and
keep track of the number of transfers.

46
Direct Memory Access (DMA)-3
 DMA controller can transfer data without intervention by the
processor, but its operation under the control of a program
executed by the processor.
 To initiate the transfer of a block of words, the processor
sends the starting address, the number of words in the
block, and the direction of the transfer.
 On receiving this information, the DMA controller proceeds to
perform the requested operation.
 When the entire block has been transferred, the controller
informs the processor by raising an interrupt signal.
 While a DMA transfer is taking place, the program that
requested the transfer cannot continue, and the processor can be
used to execute another program.
 After the DMA transfer is completed, the processor can return to
the program that requested the transfer.
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Direct Memory Access (DMA)-4
 DMA controller registers that are
accessed by the processor to initiate
transfer operations.
 Two registers are used for storing the
Starting address and the word count.
 The third register contains status and
control flags.
 The R/W bit determines the direction
of the transfer.
 When this bit is set to 1 by a program
instruction, the controller performs a
read operation, that is, it transfers data
from the memory to the I/O device.
 When the controller has completed
transferring a block of data and is
ready to receive another command, it
sets the Done flag to 1.
 Bit 30 is the Interrupt-enable flag, IE.
When this flag is set to 1, it causes the
controller to raise an interrupt after it
has completed transferring a block of
data.
 The controller sets the IRQ bit to 1 48
Direct Memory Access (DMA)-5

49
Direct Memory Access (DMA)-6
The disk controller, which controls two
disks, also has DMA capability and
provides two DMA channels. It can
perform two independent DMA
operations, as if each disk had its own
DMA controller.
The registers needed to store the memory
address, the word count, and so on are
duplicated, so that one set can be used with
each device.

50
Direct Memory Access (DMA)-8
 Requests by DMA devices for using the bus are always given higher
priority than processor requests.
 Among different DMA devices, top priority is given to high-speed
peripherals such as a disk, a high-speed network interface, or a
graphics display device.
 Since the processor originates most memory access cycles, the DMA
controller can be said to “steal” memory cycles from the processor.
 Interweaving technique is usually called cycle stealing.
 Alternatively, the DMA controller may be given exclusive access to the
main memory to transfer a block of data without interruption. This is
known as block or burst mode.
 A conflict may arise if both the processor and a DMA controller or two
DMA controllers try to use the bus at the same time to access the main
memory. To resolve these conflicts, an arbitration procedure is
implemented on the bus to coordinate the activities of all devices
requesting memory transfers.

51
Direct Memory Access (DMA)-9
Bus Arbitration
 The device that is allowed to initiate data transfers on the bus at
any given time is called the bus master.
 When the current master relinquishes control of the bus, another
device can acquire this status.
 Bus arbitration is the process by which the next device to become
the bus master is selected and bus mastership is transferred to it.
 The selection of the bus master must take into account the needs of
various devices by establishing a priority system for gaining access
to the bus.
 There are two approaches to bus arbitration: centralized and
distributed.
 In centralized arbitration, a single bus arbiter performs the
required arbitration. In distributed arbitration, all devices
participate in the selection of the next bus master.

52
Direct Memory Access (DMA)-10
Bus Arbitration
 Centralized Arbitration
 The bus arbiter may be the processor or a separate unit
connected to the bus. The processor is normally the bus master
unless it grants bus mastership to one of the DMA controllers.
 A DMA controller indicates that it needs to become the bus
master by activating the Bus-Request line BR (Active Low).
 When Bus-Request is activated, the processor activates the
Bus-Grant signal, BG1, indicating to the DMA controllers that
they may use the bus when it becomes free.
 This signal is connected to all DMA controllers using a daisy-
chain arrangement.
 The current bus master indicates to all device that it is using the
bus by activating line called Bus-Busy (Active Low)
 Bus-Busy to prevent other devices from using the bus at the same time
53
Direct Memory Access (DMA)-11

54
Direct Memory Access (DMA)-12
Bus Arbitration
 Distributed Arbitration
 Distributed arbitration means that all devices waiting to
use the bus have equal responsibility in carrying out the
arbitration process, without using a central arbiter.
 Each device on the bus assigned a 4-bit identification
number. When one or more devices request the bus, they
assert the Start Arbitration (Active Low) signal and
place their 4-bit ID numbers on four line, ARB0 through
ARB3 .
 A winner is selected as a result of the interaction among
the signals transmitted over those liens by all contenders.
 The net outcome is that the code on the four lines
represents the request that has the highest ID number.
55
Direct Memory Access (DMA)-13
Device A and B having ID 5
(0101) and 6 (0110).
Both sent the ID
Code seen by both device is
0111.
Each device compares the
pattern on the arbitration
lines to it own ID, starting
from MSB. If it detects a
difference at any bit
position, it disables its
drivers at that bit position
and for all lower order bits.

56
Direct Memory Access (DMA)-13
It does so by placing
0 at the input of
these drivers.
Device-A detects a
difference on line
ARB1 so it disable
line ARB1 and
ARB0.
So Device-B wins
because pattern
change to 0110.
57
Buses-1
The bus protocol determines when a device
may place information on the bus, when it may
load the data on the bus into one of its
registers, and so on.
These rules are implemented by control signals
that indicate what and when actions are to be
taken.
Master or initiator- Device which initiate
data transfers
Slave or target- Device addressed by
master
58
Buses-2 Synchronous Bus
All devices derive timing information from a
control line called the bus clock
The timing diagram shows an idealized
representation of the actions that take place
on the bus lines.

59
Buses-3 Synchronous Bus
 The sequence of signal events during an input (Read) operation.
 At time t0, the master places the device address on the address lines
and sends a command on the control lines indicating a Read operation.
 Information travels over the bus.
 The clock pulse width, t1 − t0, must be longer than the maximum
propagation delay over the bus. Also, it must be long enough to allow
all devices to decode the address and control signals, so that the
addressed device (the slave) can respond at time t1 by placing the
requested input data on the data lines.
 At the end of the clock cycle, at time t2, the master loads the data on
the data lines into one of its registers.
 To be loaded correctly into a register, data must be available for a
period greater than the setup time of the register.
 Hence, the period t2 − t1 must be greater than the maximum
propagation time on the bus plus the setup time of the master’s
register.
60
Buses-4 Synchronous Bus
The exact times at which signals change
state are somewhat different from idealized
representation, because of propagation
delays on bus wires and in the circuits of the
devices.

61
Buses-5 Synchronous Bus

62
Buses-6 Synchronous Bus
 The master sends the address and command signals on the
rising edge of the clock at the beginning of the clock cycle (at
t0). However, these signals do not actually appear on the bus
until tAM, largely due to the delay in the electronic circuit
output from the master to the bus lines.
 A short while later, at tAS, the signals reach the slave. The
slave decodes the address, and at t1 sends the requested data.
 Here again, the data signals do not appear on the bus until tDS.
 They travel toward the master and arrive at tDM. At t2, the
master loads the data into its register.
 Hence the period t2 − tDM must be greater than the setup time
of that register. The data must continue to be valid after t2 for
a period equal to the hold time requirement of the register.

63
Buses-7 Synchronous Bus
Multiple-Cycle Data Transfer
 However, it has some limitations.
 Because a transfer has to be completed within one clock cycle, the
clock period, t2 − t0, must be chosen to accommodate the longest
delays on the bus and the slowest device interface.
 This forces all devices to operate at the speed of the slowest
device.
 To overcome these limitations, most buses incorporate control
signals that represent a response from the device. These signals
inform the master that the slave has recognized its address and
that it is ready to participate in a data transfer operation. They
also make it possible to adjust the duration of the data transfer
period to match the response speeds of different devices.
 This is often accomplished by allowing a complete data transfer
operation to span several clock cycles. Then, the number of clock
cycles involved can vary from one device to another.
64
Buses-8 Synchronous Bus
Multiple-Cycle Data Transfer

65
Buses-9 Synchronous Bus
Multiple-Cycle Data Transfer
 During clock cycle 1, the master sends address and command information
on the bus, requesting a Read operation.
 The slave receives this information and decodes it. It begins to access the
requested data on the active edge of the clock at the beginning of clock
cycle 2.
 Due to the delay involved in getting the data, the slave cannot respond
immediately. The data become ready and are placed on the bus during
clock cycle 3.
 The slave asserts a control signal called Slave-ready at the same time.
 The master, which has been waiting for this signal, loads the data into its
register at the end of the clock cycle.
 The slave removes its data signals from the bus and returns its Slave-
ready signal to the low level at the end of cycle 3.
 The bus transfer operation is now complete, and the master may send
new address and command signals to start a new transfer in clock cycle 4.
 If the addressed device does not respond at all, the master waits for some
predefined maximum number of clock cycles, then aborts the operation.
66
Buses-10 Asynchronous Bus
An alternative scheme for controlling data
transfers on a bus is based on the use of a
handshake protocol between the master and
the slave.
A handshake is an exchange of command and
response signals between the master and the
slave.

67
Buses-10 Asynchronous Bus
The master places the address and command
information on the bus. Then it indicates to all
devices that it has done so by activating the Master-
ready line.
This causes all devices to decode the address. The
selected slave performs the required operation and
informs the processor that it has done so by
activating the Slave-ready line.
The master waits for Slave-ready to become asserted
before it removes its signals from the bus.
In the case of a Read operation, it also loads the data
into one of its registers.
68
Buses-10 Asynchronous Bus

69
Buses-10 Asynchronous Bus
 t0—The master places the address and command information on
the bus, and all devices on the bus decode this information.
 t1—The master sets the Master-ready line to 1 to inform the
devices that the address and command information is ready.
Sufficient time should be allowed for the device interface
circuitry to decode the address. The delay needed can be
included in the period t1 − t0.
 t2—The selected slave, having decoded the address and
command information, performs the required input operation by
placing its data on the data lines. At the same time, it sets the
Slave-ready signal to 1. If extra delays are introduced by the
interface circuitry before it places the data on the bus, the slave
must delay the Slave-ready signal accordingly. The period t2 − t1
depends on the distance between the master and the slave and
on the delays introduced by the slave’s circuitry.
70
Buses-11 Asynchronous Bus
 t3—The Slave-ready signal arrives at the master, indicating
that the input data are available on the bus. After a delay to
the master loads the data into its register. Then, it drops the
Master-ready signal, indicating that it has received the data.
 t4—The master removes the address and command
information from the bus. The delay between t3 and t4 is
again intended to allow for bus skew. Erroneous addressing
may take place if the address, as seen by some device on the
bus, starts to change while the Master-ready signal is still
equal to 1.
 t5—When the device interface receives the 1-to-0 transition
of the Master-ready signal, it removes the data and the
Slave-ready signal from the bus. This completes the input
transfer.
71
Buses-12 Asynchronous Bus

72
Interface Circuits

73
Interface circuits-1
I/O interface consists of the circuitry required to connect
an I/O device to a computer bus.
Side of the interface which connects to the computer has
bus signals for:
 Address,
 Data
 Control

Side of the interface which connects to the I/O device

has:
 Datapath and associated controls to transfer data between the interface and the
I/O device.
 This side is called as a “port”.

Ports can be classified into two:

 Parallel port,
 Serial port.

74
Interface circuits-2
Parallel port transfers data in the form of a
number of bits, normally 8 or 16 to or from
the device.
Serial port transfers and receives data one
bit at a time.
Processor communicates with the bus in the
same way, whether it is a parallel port or a
serial port.
 Conversion from the parallel to serial and vice versa takes
place inside the interface circuit.

75
 Parallel port Data

Address
DATAIN Data
Encoder
R/W and Keyboard
Processor SIN
debouncing switches
Master-ready circuit
Valid
Input
Slave-ready
interface

•Keyboard is connected to a processor using a parallel port.

•Processor is 32-bits and uses memory-mapped I/O and the asynchronous bus
protocol.
•On the processor side of the interface we have:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
 Parallel port (contd..)
Data

Address
DATAIN Data
Encoder
R /W and Keyboard
Processor SIN
debouncing switches
Master-ready circuit
Valid
Input
Slave-ready
interface

On the keyboard side of the interface:

- Encoder circuit which generates a code for the key pressed.
- Debouncing circuit which eliminates the effect of a key bounce (a single key
stroke may appear as multiple events to a processor).
- Data lines contain the code for the key.
- Valid line changes from 0 to 1 when the key is pressed. This causes the code
be loaded into DATAIN and SIN to be set to 1.
Input Interface Circuit
•Output lines of DATAIN are
are connected to the data lines of
the bus by means of 3 state drivers
•Drivers are turned on when the
processor issues a read signal and
the address selects this register.

•SIN signal is generated using a status flag circuit

•It is connected to line D0 of the processor bus
using a three-state driver.
•Address decoder selects the input interface based
on bits A1 through A31.
•Bit A0 determines whether the status or data
register is to be read, when Master-ready is
active.
•In response, the processor activates the Slave-rea
signal, when either the Read-status or Read-data
is equal to 1, which depends on line A0.
 Parallel port (contd..)
Data

Address DATAOUT Data

Processor
CPU R /W SOUT Printer
Valid
Master-ready
Output Idle
Slave-ready interface

•Printer is connected to a processor using a parallel port.

•Processor is 32 bits, uses memory-mapped I/O and asynchronous bus protocol.
•On the processor side:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
 Parallel port (contd..)
Data

Address DATAOUT Data

Processor
CPU R /W SOUT Printer
Valid
Master-ready
Output Idle
Slave-ready interface

n the printer side:

- Idle signal line which the printer asserts when it is ready to accept a charac
This causes the SOUT flag to be set to 1.
- Processor places a new character into a DATAOUT register.
- Valid signal, asserted by the interface circuit when it places a new characte
on the data lines.
Output Interface Circuit
•Data lines of the processor
bus are connected to the
DATAOUT register of the
interface.
•The status flag SOUT is
connected
to the data line D1 using a
three-state driver.
•The three-state driver is
turned on,
when the control Read-status
line is
1.
•Address decoder selects the
output
interface using address lines
A1
through A31.
•Address line A0 determines
whether
the data is to be loaded into
 Bus
D7 PA7

DATAIN
D1
D0 PA0

SIN
•Combined I/O interface circuit.
Input •Address
CA bits A2 through A31, that is
status
30 bits are used to select the overall
PB7
interface.
DATAOUT •Address bits A1 through A0, that is, 2
bits
PB0 select one of the three registers,
SOUT
namely,
CB1
DATAIN, DATAOUT, and
Handshake
control
theCB2status register.
Slave-
Ready 1 •Status register contains the flags SIN an
SOUT in bits 0 and 1.
•Data lines PA0 through PA7 connect the
Master- input device to the DATAIN register.
Ready
R/ W
•DATAOUT register connects the data
A31 lines on the processor bus to lines PB0
Address
decoder
My-address
through PB7 which connect to the output
A2 device.
A1
RS1 •Separate input and output data lines for
connection to an I/O device.
RS0
A0
 D7 P7
•Data lines to I/O device are bidirectional.
DATAIN •Data lines P7 through P0 can be used for
D0 bothP0 input, and output.
•In fact, some lines can be used for input &
some for output depending on the pattern
in the Data Direction Register (DDR).
DATAOUT •Processor places an 8-bit pattern into a D
•If a given bit position in the DDR is 1, the
corresponding data line acts as an output
line, otherwise it acts as an input line.
Data •C1 and C2 control the interaction between
Direction
Register the interface circuit and the I/O devices.
•Ready and Accept lines are the handshake
control lines on the processor bus side, an
My-address are connected to Master-ready & Slave-re
RS2 •C1
Input signal My-address is connected to th
RS1 Status
RS0
Register
and output of an address decoder.
R/W
select control •Three register select lines that allow up to
Ready C2
Accept registers to be selected.

INTR
Serial port
Serial port is used to connect the processor
to I/O devices that require transmission of
data one bit at a time.
Serial port communicates in a bit-serial
fashion on the device side and bit parallel
fashion on the bus side.
 Transformation between the parallel and serial formats is
achieved with shift registers that have parallel access
capability.
 Input shift register Serial
input
•Input shift register accepts input one
at a time from the I/O device.
•Once all the 8 bits are received, the
DATAIN
contents of the input shift register are
loaded in parallel into DATAIN register
•Output data in the DATAOUT register
are loaded into the output shift registe
•Bits are shifted out of the output shift
D7
register and sent out to the I/O device
D0 bit at a time.
•As soon as data from the input shift re
are loaded into DATAIN, it can start
My-address DATAOUT
accepting another 8 bits of data.
RS1 •Input shift register and DATAIN regist
RS0
Chip and are both used at input so that the inpu
Serial
R /W register Output shift re gister shift register can start receiving anoth
Ready select
set of 8 bits from the input device after
Accept
loading the contents to DATAIN, before
Receiving clockthe processor reads the contents of
I NTR Status
and
DATAIN. This is called as double-
ransmission clock
control
T buffering.
Serial port (contd..)
Serial interfaces require fewer wires, and hence serial
transmission is convenient for connecting devices that
are physically distant from the computer.
Speed of transmission of the data over a serial interface
is known as the “bit rate”.
 Bit rate depends on the nature of the devices connected.

In order to accommodate devices with a range of

speeds, a serial interface must be able to use a range of
clock speeds.
Several standard serial interfaces have been developed:
 Universal Asynchronous Receiver Transmitter (UART) for low-speed serial
devices.
 RS-232-C for connection to communication links.
Standard I/O interfaces
I/O device is connected to a computer using an
interface circuit.
Do we have to design a different interface for every
combination of an I/O device and a computer?
A practical approach is to develop standard interfaces
and protocols.
A personal computer has:
 A motherboard which houses the processor chip, main memory and some I/O
interfaces.
 A few connectors into which additional interfaces can be plugged.

Processor bus is defined by the signals on the processor

chip.
 Devices which require high-speed connection to the processor are connected
directly to this bus.
Standard I/O interfaces (contd..)
Because of electrical reasons only a few devices
can be connected directly to the processor bus.
Motherboard usually provides another bus that
can support more devices.
 Processor bus and the other bus (called as expansion bus) are
interconnected by a circuit called “bridge”.
 Devices connected to the expansion bus experience a small delay in
data transfers.
Design of a processor bus is closely tied to the
architecture of the processor.
 No uniform standard can be defined.

Expansion bus however can have uniform standard

defined.
Standard I/O interfaces (contd..)
A number of standards have been developed
for the expansion bus.
 Some have evolved by default.
 For example, IBM’s Industry Standard Architecture.

Three widely used bus standards:

 PCI (Peripheral Component Interconnect)
 SCSI (Small Computer System Interface)
 USB (Universal Serial Bus)

89
Standard I/O interfaces (contd..)
Main
Processor
memory
Bridge circuit translates
signals and protocols from
Processor bus
processor bus to PCI bus.

Bridge

PCI bus
Expansion bus on
the motherboard
Additional SCSI Ethernet USB ISA
memory controller Interface controller Interface

SCSI bus
IDE
disk
Video
Disk CD-ROM
controller controller

CD-
Disk 1 Disk 2 ROM K eyboard Game
91
92
PCI Bus
 Peripheral Component Interconnect
 Introduced in 1992
 Low-cost bus
 Processor independent
 Plug-and-play capability
 In today’s computers, most memory transfers involve a burst of data rather
than just one word. The PCI is designed primarily to support this mode of
operation.
 The bus supports three independent address spaces: memory, I/O, and
configuration.
 We assumed that the master maintains the address information on the bus
until data transfer is completed. But, the address is needed only long
enough for the slave to be selected. Thus, the address is needed on the bus
for one clock cycle only, freeing the address lines to be used for sending
data in subsequent clock cycles. The result is a significant cost reduction.
 A master is called an initiator in PCI terminology. The addressed device that
responds to read and write commands is called a target.
Data transfer signals on the PCI bus.

Name F
unction
CLK A 33-MHz or 66-MHz clock.

FRAME# Sent by the initiator to indicate the duration of a

transaction.

AD 32address/data lines, which may beoptionally

increased to 64.

C/BE# command/byte-enable
4 lines (8 for a 64-bit bus).

IRDY#, TRDY# Initiator-ready and Target-readysignals.

DEVSEL# A response from the device indicating that it has

recognized its address and is ready for a data
transfertransaction.

IDSEL# Initialization Device Select.

A signal whose name ends with the symbol # is asserted when in

the low-voltage state.
 1 2 3 4 5 6 7

CLK

Frame#

AD Adress #1 #2 #3 #4

C/BE# Cmnd Byte enable

IRDY#

TRD Y#

DEVSEL#

A read operation on the PCI bus

 1 2 3 4 FRAME#
5 6 indicate
7 the
beginning of a transaction.
Address on the AD lines
CLK Read on the C/BE# lines.

Frame#

AD Adress #1 #2 #3 #4

C/BE# Cmnd Byte enable

IRDY#

TRD Y#

DEVSEL#

A read operation on the PCI bus

 1 2 3 4 5 6 7

CLK

The initiator removes the

Frame# address, from the AD lines
The selected target asserts
DEVSEL# to indicate
recognized its address and is
AD Adress #1 #2 #3 to respond
#4
ready

C/BE# Cmnd Byte enable

IRDY#

TRD Y#

DEVSEL#

A read operation on the PCI bus

 1 2 3 4 5 6 7

CLK

Frame#

AD Adress #1 #2 #3 #4

Asserts IRDY# to indicate

C/BE# Cmnd Byte enable
ready to receive data.
Target asserts TRDY# and
begins to send data.
IRDY#

TRD Y#

DEVSEL#

A read operation on the PCI bus

 1 2 3 4 5 6 7
If target is not ready , it
would delay
CLK asserting
TRDY# until it is ready.
The entire burst of data
need not be sent in
Frame#
successive clock cycles.
Either the initiator or the
target may introduce a
pause by AD deactivating itsAdress #1 #2 #3 #4
ready signal, then asserting
it again when it is ready to
resume the transfer of data.Cmnd
C/BE# Byte enable

IRDY#

TRD Y#

DEVSEL#

A read operation on the PCI bus

 1 2 3 4 5 6 7

CLK

Frame#
FRAME# deactivates this
signal during the second-last
word of the transfer. Adress #1 #2 #3 #4
AD

C/BE# Cmnd Byte enable

IRDY#

TRD Y#

DEVSEL#

A read operation on the PCI bus

 1 2 3 4 5 6 7

CLK

Frame#

AD Adress #1 #2 #3 #4

C/BE# Cmnd Byte enable

IRDY#

TRD Y#

DEVSEL#

Target sends one more word then stops.

A read operation on the PCI bus After sending the fourth word, the target
deactivates TRDY# and DEVSEL# and
disconnects its drivers on the AD lines.
Device Configuration
 When an I/O device is connected to a computer, several actions are
needed to configure both the device and the software that
communicates with it.
 PCI incorporates in each I/O device interface a small configuration
ROM memory that stores information about that device.
 The configuration ROMs of all devices are accessible in the
configuration address space. The PCI initialization software reads
these ROMs and determines whether the device is a printer, a
keyboard, an Ethernet interface, or a disk controller. It can further
learn bout various device options and characteristics.
 Devices are assigned addresses during the initialization process.
 This means that during the bus configuration operation, devices
cannot be accessed based on their address, as they have not yet been
assigned one.
 Hence, the configuration address space uses a different mechanism.
Each device has an input signal called Initialization Device Select,
IDSEL#
 Electrical characteristics:
 PCI bus has been defined for operation with either a 5 or 3.3 V power
supply
SCSI Bus
 The acronym SCSI stands for Small Computer System Interface.
 It refers to a standard bus defined by the American National
Standards Institute (ANSI) under the designation X3.131 .
 In the original specifications of the standard, devices such as
disks are connected to a computer via a 50-wire cable, which
can be up to 25 meters in length and can transfer data at rates
up to 5 megabytes/s.
 The SCSI bus standard has undergone many revisions, and its
data transfer capability has increased very rapidly, almost
doubling every two years.
 SCSI-2 and SCSI-3 have been defined, and each has several
options.
 Because of various options SCSI connector may have 50, 68 or
80 pins.
104
 SCSI Bus (Contd.,)
 Devices connected to the SCSI bus are not part of the address space of the
processor
 The SCSI bus is connected to the processor bus through a SCSI controller. This
controller uses DMA to transfer data packets from the main memory to the device,
or vice versa.
 A packet may contain a block of data, commands from the processor to the device,
or status information about the device.
 A controller connected to a SCSI bus is one of two types – an initiator or a target.
 An initiator has the ability to select a particular target and to send commands
specifying the operations to be performed. The disk controller operates as a target.
It carries out the commands it receives from the initiator.
 The initiator establishes a logical connection with the intended target.
 Once this connection has been established, it can be suspended and restored as
needed to transfer commands and bursts of data.
 While a particular connection is suspended, other device can use the bus to
transfer information.
 This ability to overlap data transfer requests is one of the key features of the SCSI
bus that leads to its high performance.
SCSI Bus (Contd.,)
Data transfers on the SCSI bus are always
controlled by the target controller.
To send a command to a target, an initiator
requests control of the bus and, after winning
arbitration, selects the controller it wants to
communicate with and hands control of the
bus over to it.
Then the controller starts a data transfer
operation to receive a command from the
initiator.
Standard I/O interfaces (contd..)
Main
Processor
memory
Bridge circuit translates
signals and protocols from
Processor bus
processor bus to SCSI bus.

Bridge

PCI bus
Expansion bus on
the motherboard
Additional SCSI Ethernet USB ISA
memory controller Interface controller Interface

SCSI bus
IDE
disk
Video
Disk CD-ROM
controller controller

CD-
Disk 1 Disk 2 ROM K eyboard Game
SCSI Bus (Contd.,)
 Assume that processor needs to read block of data from a disk drive and
that data are stored in disk sectors that are not contiguous.
 The processor sends a command to the SCSI controller, which causes the
following sequence of events to take place:
1. The SCSI controller, acting as an initiator, contends for control of the
bus.
2. When the initiator wins the arbitration process, it selects the target
controller and hands over control of the bus to it.
3. The target starts an output operation (from initiator to target); in
response to this, the initiator sends a command specifying the required
read operation.
4. The target, realizing that it first needs to perform a disk seek operation,
sends a message to the initiator indicating that it will temporarily
suspend the connection between them. Then it releases the bus.
5. The target controller sends a command to the disk drive to move the
read head to the first sector involved in the requested read operation.
Then, it reads the data stored in that sector and stores them in a data
buffer. When it is ready to begin transferring data to the initiator, the
target requests control of the bus. After it wins arbitration, it reselects
the initiator controller, thus restoring the suspended connection.
SCSI Bus (Contd.,)
6. The target transfers the contents of the data buffer to
the initiator and then suspends the connection again
7. The target controller sends a command to the disk
drive to perform another seek operation. Then, it
transfers the contents of the second disk sector to the
initiator as before. At the end of this transfers, the
logical connection between the two controllers is
terminated.
8. As the initiator controller receives the data, it stores
them into the main memory using the DMA approach.
9. The SCSI controller sends as interrupt to the processor
to inform it that the requested operation has been
completed
Bus Signals
Operation of SCSI bus from H/W point of view
Category Name u
Fnction

Data – DB(0)to Datalines:Carry onebyte ofinformation

– DB(7) duringtheinformationtransferphase and
identifydevice duringarbitration,
selectionand
reselection phases
– DB(P) Paritybitforthedatabus
Phase – BSY Busy:Asserted whenthebus isnotfree

– SEL Selection:Assertedduringselectionand
reselection

Information – C/D Con

trol/Data:Asserted duringtransfer of
type controlinformation(command, status or
message)

– MSG Message:indicates thattheinformation being

transferred is amessage

Table 4. The SCSI bus signals.

 Table 4. The SCSI bus signals.(cont.)
Category Name u
Fnction

Handshake – REQ Request:Assertedbyatargettorequest adata

transfercycle

– ACK Ackno
wledge:Assertedbytheinitiatorwhenit
hascompletedadatatransfer operation

Direction of – I/O Input/Output:

Assertedtoindicateaninput
transfer op e to theinitiator)
eration(relativ

Other – ATN Attention:Assertedby aninitiatorwhenit

wishestosendamessage to atarget

– RST Reset:Causesalldevicecontrols todisconnect

fromthebusandassume theirstart-up
state
Main Phases involved
 Arbitration
 A controller requests the bus by asserting BSY and by asserting
it’s associated data line
 When BSY becomes active, all controllers that are requesting bus
examine data lines
 Selection
 Controller that won arbitration selects target by asserting SEL
and data line of target. After that initiator releases BSY line.
 Target responds by asserting BSY line
 Target controller will have control on the bus from then
 Information Transfer
 Handshaking signals are used between initiator and target
 At the end target releases BSY line
 Reselection
 Targets examine ID

DB 2

DB 5

DB 6

BS Y

S EL

Free Arbitration Selection

Figure 42. Arbitration and selection on the SCSI bus.

Device 6 wins arbitration and selects device 2.
USB
Universal Serial Bus (USB) is an industry standard
developed through a collaborative effort of several
computer and communication companies,
including Compaq, Hewlett-Packard, Intel, Lucent,
Microsoft, Nortel Networks, and Philips.
Speed
 Low-speed(1.5 Mb/s)
 Full-speed(12 Mb/s)
 High-speed(480 Mb/s)
Port Limitation
Device Characteristics
Plug-and-play
Universal Serial Bus tree structure

Host computer

Root
hub

Hub Hub

Hub I/O I/O I/O I/O

de vice de vice de vice de vice

I/O I/O
de vice de vice
Universal Serial Bus tree structure
 To accommodate a large number of devices that can be added or
removed at any time, the USB has the tree structure as shown in the
figure.
 Each node of the tree has a device called a hub, which acts as an
intermediate control point between the host and the I/O devices. At
the root of the tree, a root hub connects the entire tree to the host
computer. The leaves of the tree are the I/O devices being served (for
example, keyboard, Internet connection, speaker, or digital TV)
 In normal operation, a hub copies a message that it receives from its
upstream connection to all its downstream ports. As a result, a
message sent by the host computer is broadcast to all I/O devices,
but only the addressed device will respond to that message. However,
a message from an I/O device is sent only upstream towards the root
of the tree and is not seen by other devices. Hence, the USB enables
the host to communicate with the I/O devices, but it does not enable
these devices to communicate with each other.
 Addressing
 When a USB is connected to a host computer, its root hub is attached to the
processor bus, where it appears as a single device. The host software
communicates with individual devices attached to the USB by sending packets
of information, which the root hub forwards to the appropriate device in the
USB tree.
 Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit
address. This address is local to the USB tree and is not related in any way to
the addresses used on the processor bus.
 A hub may have any number of devices or other hubs connected to it, and
addresses are assigned arbitrarily. When a device is first connected to a hub, or
when it is powered on, it has the address 0. The hardware of the hub to which
this device is connected is capable of detecting that the device has been
connected, and it records this fact as part of its own status information.
Periodically, the host polls each hub to collect status information and learn
about new devices that may have been added or disconnected.
 When the host is informed that a new device has been connected, it uses a
sequence of commands to send a reset signal on the corresponding hub port,
read information from the device about its capabilities, send configuration
information to the device, and assign the device a unique USB address. Once
this sequence is completed the device begins normal operation and responds
only to the new address.
USB Protocols
 All information transferred over the USB is organized in packets,
where a packet consists of one or more bytes of information. There are
many types of packets that perform a variety of control functions.
 The information transferred on the USB can be divided into two broad
categories: control and data.
 Control packets perform such tasks as addressing a device to initiate
data transfer, acknowledging that data have been received correctly, or
indicating an error.
 Data packets carry information that is delivered to a device.
 A packet consists of one or more fields containing different kinds of
information. The first field of any packet is called the packet identifier,
PID, which identifies the type of that packet.
 They are transmitted twice. The first time they are sent with their true
values, and the second time with each bit complemented
 The four PID bits identify one of 16 different packet types. Some
control packets, such as ACK (Acknowledge), consist only of the PID
byte.
 PID0 PID1 PID2 PID3 PID0 PID1 PID2 PID3

(a) Packet identifier field

Bits 8 7 4 5
Control packets used for
PID ADDR ENDP CRC16 controlling data transfer
operations are called
token packets.
(b) Token packet, IN or OUT

Bits 8 0 to 8192 16

PID DATA CRC16

(c) Data packet

Figure 45. USB packet format.

 Host Hub I/O Device

Token
Data0

ACK
Time
Token
Data0

ACK

Token
Data1
Figure: An output
transfer
ACK

Token
Data1

ACK
Isochronous Traffic on USB
 One of the key objectives of the USB is to support the transfer of
isochronous data.
 Devices that generates or receives isochronous data require a time
reference to control the sampling process.
 To provide this reference. Transmission over the USB is divided into
frames of equal length.
 A frame is 1ms long for low-and full-speed data.
 The root hub generates a Start of Frame control packet (SOF) precisely
once every 1 ms to mark the beginning of a new frame.
 The arrival of an SOF packet at any device constitutes a regular clock
signal that the device can use for its own purposes.
 To assist devices that may need longer periods of time, the SOF packet
carries an 11-bit frame number.
 Following each SOF packet, the host carries out input and output
transfers for isochronous devices.
 This means that each device will have an opportunity for an input or
output transfer once every 1 ms.
USB Frames

122
Electrical Characteristics
The cables used for USB connections consist of four
wires.
Two are used to carry power, +5V and Ground.
 Thus, a hub or an I/O device may be powered directly
from the bus, or it may have its own external power
connection.
The other two wires are used to carry data.
Different signaling schemes are used for different
speeds of transmission.
 At low speed, 1s and 0s are transmitted by sending a
high voltage state (5V) on one or the other o the two
signal wires. For high-speed links, differential
transmission is used.