See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/337972148

A Fast and Compact Binary to BCD Converter Circuit

Conference Paper · December 2019

DOI: 10.1109/WIECON-ECE48653.2019.9019980

CITATIONS READS
0 1,654

4 authors, including:

Mubin Ul Haque
University of Adelaide
16 PUBLICATIONS   30 CITATIONS   

SEE PROFILE

All content following this page was uploaded by Mubin Ul Haque on 17 December 2019.

The user has requested enhancement of the downloaded file.

 A Fast and Compact Binary to BCD Converter
Circuit
Nafiz Hossain∗, Nowrin Hossain†, Zarrin Tasnim Sworna‡, Mubin Ul Haque§
∗†‡ Department of Computer Science & Engineering, University of Dhaka, Dhaka, Bangladesh
∗ nhremon8181@gmail.com, † nowrinneetu95@gmail.com, ‡ zarrin@cse.du.ac.bd, § mubin@cse.du.ac.bd

Abstract—Digital devices use decimal arithmetic in most of Section III the proposed algorithm is illustrated and in Section
the application which make devices easy to use and feasible IV the proposed circuit is elucidated with required figures. In
to human computation. BCD (Binary Coded Decimal) is very Section V, the simulation results and performance analysis of
common in digital computational devices which display decimal
numbers whereas binary is the number system that is recognized the proposed circuit are illustrated. Last of all, Section VI
by machines. So, BCD is needed to make machine results human concludes the paper.
readable that is to be converted from binary number. In this
work, a new algorithm is proposed to provide hardware support II. P RIOR WORK
for binary to BCD conversion. This converter can be used for 2-
digit BCD number to be translated from a 7-bit binary number. A good number of works had already been done on binary to
The proposed circuit is 20.08% area-efficient and 33.49% delay
efficient than the existing best known Shift Add by Constant
BCD conversion focusing on the purpose of decimal multipli-
Architecture. The proposed architecture works for all the general cation. Three algorithms are introduced in [4]. They modified
purpose of binary to BCD conversion whereas the existing previous 3-3-1 algorithm [4] by splitting 7-bit binary input into
best known converters are for specific multiplication purpose 3 parts the higher 3 bits (HSBs), the middle 3 bits (LSBs) and
and are not feasible for generalized use. Hence, the proposed the lowest significant bit. If the LSBs is greater than (4)10 then
converter circuit is area and delay efficient with the large-scale
(3)10 is added with LSBs and carry is added with the HSBs.
and extensive applicability.
HSBs not only contribute to the higher significant BCD digit
Index Terms—Decimal arithmetic, Binary Coded Decimal
(BCD), VLSI Design, Binary to BCD Converter, High perfor- but also in lower significant BCD digit and adding this also
mance. may need an correction.
The second architecture, Range detection algorithm [4]
I. I NTRODUCTION detects the range of the number by range detection circuit
and put a function high and then by subtraction they get the
Devices are getting compact, faster, cheaper and more power lower significant BCD digit. This algorithm considers only 37
efficient in every progressing second in modern days. Decimal possible states.
data processing applications have grown exponentially in The Shift Add by Constant [4] architecture can show all
recent years thereby increasing the need to have hardware the possible 81 states for digit by digit multiplication. Two
support for decimal arithmetic [1]–[3]. To display binary types of adder block- 3-bit conditional adder block and 4-bit
number in decimal, binary to BCD conversion is required in conditional adder block is used. If the input in these adder
very first step. Binary to BCD converter is used in different block is greater than (4)10 than (3)10 is added with the input.
computational fields like finance or in scientific methods, com-
Compliment Based Logic Circuit (CBLD) [5] is fastest
mercial and budgetary purposes [4]. Therefore improvement of
among all the existing circuits but it occupies a great amount
the converter circuit can speed up the regular computation and
of area. Moreover the circuit was created for binary to BCD
can make devices fast and area effective.
conversion used in decimal multiplication which was improved
Main contributions of this paper are as follows: in terms of power and delay from the previous works which
1) The required number of transistors have been reduced was done before. In the literature [1], they come with two
by selection of the input, partitioning and merging of the different algorithm for conversion 7-bit binary partial products
input by the blocks in the proposed circuit as shown in to 2-digit BCD. In literature [2] a new method called recoding
Fig. 1. method is introduced for fast binary to BCD conversion for
2) The range of the proposed converter circuit is 0 to 99, decimal multiplication.
so it covers all the 100 states possible to be presented by The range detection [4] implementation consumes lower
2-digit BCD number where the input can be maximum of power than all other existing architectures but occupies more
7 bit binary number. area. The shift add by constant algorithm [4] implementation
3) The circuit becomes 33.49% time faster by reducing the occupies lowest area than all over the architectures but it is
area in terms of transistors and 20.08% efficient in area. poor in speed. Almost all these architectures used merely for
Rest of the paper is organized as follows: Section II gives an multiplication purpose. Most of them cannot cover all the
overview about how the work done previouSection II presents states hence can cover at most 37 states that can be resulted
the existing best known binary to BCD converter circuits. In from digit by digit multiplication.
 III. P ROPOSED A LGORITHM IV. P ROPOSED A RCHITECTURE
A new algorithm for binary to BCD conversion is being This section proposes the converter circuit. Essential figures
proposed as the algorithm converts a 7-bit binary number to and equations are elucidated to clarify the proposed ideas.
2-digit BCD that supports high-performance for conversion Table I had been formed for each input/output combination
processes. and the corresponding circuit architecture was proposed shown
TABLE I: Block Simulation Results for the Proposed Algo- in Fig. 2. The lower 4 significant bits of the output represents
rithm lower significant BCD digit and the 4 higher significant bits
represents higher significant BCD digit.
Binary Number to be converted To be added After Conversion
00000 00000 00000
00001 00000 00001
00010 00000 00010
00011 00000 00011
00100 00000 00100
Binary Number to be converted To be added After Conversion
00101 00011 01000
00110 00011 01001
00111 00011 01010
01000 00011 01011
01001 00011 01100
Binary Number to be converted To be added After Conversion
01010 00110 10000
01011 00110 10001 Fig. 2: Proposed architecture for binary to BCD conversion
01100 00110 10010
01101 00110 10011 A. The 4-input 5-output block
01110 00110 10100
As shown the 4-input 5-output block in Fig. 3 the working
Binary Number to be converted To be added After Conversion procedure is given in Algorithm 1. The adder block takes 4
01111 01001 11000
10000 01001 11001 bits from the MSBs of the 7-bit binary number. So, possible
10001 01001 11010 input range is (0000)2 to (1111)2 . Generally for upto (99)10
10010 01001 11011 no binary number required whose four most significant bits
10011 01001 11100
are (1111)2 , thus (1111)2 is beyond consideration as input in
this block.
Equation(1-7) are used for the 4-input 5-output block
X = (N1 + N2 )N3 (1)
F = X ⊕ ((N0 + N1 )N2 + N3 ) (2)
O0 = F ⊕ N0 (3)
O1 = (X ⊕ N1 )F + (N0 ⊕ N1 )F (4)
O2 = (((N1 ⊕ N2 )X + N2 X) ⊕ (N1 + N2 ))F + N2 F (5)
O3 = X (6)
O4 = F (7)
Here, X and F are two symbols used to point out two pointed
gates outputs in Fig. 3 and O0 , O1 , O2 , O3 , O4 are the outputs
of the block.

Fig. 1: Data-flow diagram for proposed algorithm

In this approach, we have used one 4-input 5-output adder
block and one 5-input 5-output adder block. In 4-input adder
block, 4 bits are fed into the block and In 5-bit input adder
block 5 bits are fed into the block. In Block simulation Table I,
if the bits represents the number between 510 (01002 ) and
910 (10012), then 310 (0112 ) is added with the binary number.
If the represented number is more than 910 (10012) and less
than 1510 (11112 ) then 610 (1102 ) is added with (0101)2. If
the binary bits represents the number 1510 (11112 ) or more
then both 310 (112 ) and 610 (1102 ) is added to the number, that
means 910 (10012 ) is added with the number. The approaches
of the two adder blocks are same. Fig. 3: Proposed 4-input 5-output adder block
Algorithm 1 Proposed algorithm of 4-input 5-output block
Input: 4 bit Binary number I = {I3 I2 I1 I0 }
Output: O = {O4 O3 O2 O1 O0 }
if ((Ai )2 < (1111)2 ) then
if ((Ai )2 > (1001)2 ) then
(Ii )2 ← (Ii )2 + (110)2
end
if ((Ii )2 > (100)2 ) then
if ((Ii )2 < (1010)2 ) then
(Ii )2 ← (Ii )2 + (11)2
end
end
else
end Fig. 4: Proposed 5-input 5-output adder block

The 4-input 5-output block in Fig.3, if the bits represents the

number between 510 (0100)2 and 910 (10012 ) then 310 (0112 ) Algorithm 2 Proposed algorithm of 5-input 5-output block
is added with the binary number. If the represented number Input: 5 bit Binary number I = {I4 I3 I2 I1 I0 }
is more than 910 (10012) and less than 1510 (11112 ) then Output: O = {O4 O3 O2 O1 O0 }
610 (1102 ) is added with the binary number. if ((Ii )2 >= (1111)2 ) then
(Ii )2 ← (Ii )2 + (1001)2
B. The 5-input 5-output block end
The Fig. 4 shows 5-input 5-output block and the operation if ((Ai )2 < (1111)2 ) then
is given in Algorithm 2. The block takes 5 bits as input and if ((Ai )2 > (1001)2) then
gives 5 bits as output whereas the input range is from (00000)2 (Ii )2 ← (Ii )2 + (110)2
to (11111)2. For the addition purpose most of the operation end
is similar to the 4-input 5-output block for this block. The 5- if ((Ai )2 > (100)2 ) then
input 5-output block checks if the bits represents the number if ((Ai )2 < (1010)2 ) then
between 510 (0100)2 and 910 (10012), then 310 (0112 ) is added (Ii )2 ← (Ii )2 + (11)2
with the binary number. If the represented number is more end
than 910 (10012) and less than 1510 (11112) then 610 (1102 ) is end
added with the binary number and if the represented number else
is equal to or more than 1510 (11112 ) then 910 (1102 ) is added end
with the binary number. But input considered here is up-to
(10011)2, however larger binary number than this cannot be V. S IMULATION A NALYSIS
possible in input block.
Equation(8-17) are used for the 5-input and 5-output block. All the architectures are described using verilog HDL data
flow and designed layout simulated using micro wind DSCH
X = (N1 + N2 )N3 + N4 (8) simulator using 0.12μm cell library. The correctness of the
F = X ⊕ ((N0 + N1 )N2 + N3 ) (9) proposed circuit has been verified by ensuring all the 100 (0-
P = N0 .N1 .N2 .N3 (10) 99) states and showed in Fig. 5.
S = P + N4 (11)
T =P +F (12)
O0 = T ⊕ N0 (13)
O1 = ((X ⊕ N1 )T + (N0 ⊕ N1 )T )S + (N0 ⊕ N1 )S (14)
O2 = (((N1 ⊕ N2 )X + N2 X)T + (N2 ⊕ (N1 + N0 ))T )
S + (N2 ⊕ N0 .N1 )S
(15)
O3 = T (16)
Fig. 5: Simulation Analysis of Proposed Novel Area efficient
O4 = X (17) Binary to BCD converter
Here, X, F, P, S, T are some symbols used to point out some The area (in transistor count) is improved 20.08% than ex-
pointed gates outputs in Fig. 4 and O0 , O1 , O2 , O3 , O4 are the isting Shift Add by Constant [4] algorithm which is elucidated
outputs of the block. in Table II.
 TABLE II: Comparison of Hardware Complexity
n

Gates Shift Add by Constant [4] Proposed
Total Gates Transistors Total Gates Transistors E= ((η + γ) × (n − i)) − n(γ + α)
2-To-1 MUX 15 300 8 160 (19)
i=1
Inverter 4 4 0 0
2-Input-OR 7 42 9 54 + (n − 3) × (x − β) − (n + 3) × (η + γ)
2-Input-AND 4 24 8 48
2-Input-XOR 11 88 9 72 n

2-Input-XNOR 0 0 4 32 P = ((η + q) × (n − i)) + (β + p)
Total= 458 Total= 366 (20)
i=1
− (n − 3)q − (2n + 1) × (η + q)
TABLE III: Comparison of Area among the Existing and VI. C ONCLUSION
Proposed Architectures
BCD (Binary Coded Decimal) representation is advanta-
Methods Area Expression geous due to its finite place value representation, rounding,
Shift add by constant 4 × AAND + 7 × AOR + 4 × AINV +
[4] 11 × AX−OR + 15 × AM U X easy scaling by a factor of 10, simple alignment and conver-
CBLD method [5] 50 × AAND + 19 × AOR + 11 ×AX−OR sion to character form. Hence, faster and efficient binary to
Proposed 8 × AAND + 9 × AOR + 4 × AX−NOR + BCD converter circuit is desired. In this paper, a compact
9 × AX−OR + 8 × AM U X
binary to BCD converter circuit has been proposed. The
TABLE IV: Comparison of Delay among the Existing and proposed circuit can convert a 7-bit binary number to a 2-digit
Proposed Architectures BCD number ranging from 0 to 99 which is the maximum
Methods Delay Expression possible value represented by 2-digit BCD number. Two con-
Shift add by constant 4 × DAND + 7 × DOR + 3 × DX−OR + ditional adder blocks are used to derive this output from input.
[4] 4 × DM U X An efficient algorithm has been proposed for the design of the
CBLD method [5] 2 × DAND + 4 × DOR + 1 ×DX−OR
Proposed 2 × DAND + 5 × DOR + 2 × DX−OR converter circuit. Selection, partition and merging have been
performed in the conversion process. The proposed circuit
The comparison of area and delay among the existing best is 20.08% and 33.49% area and delay efficient, respectively
known circuits and proposed circuit are shown in Table III and than the existing best known converter circuits. Moreover, the
Table IV, respectively. proposed compact circuit can be utilized in vast and wide-
range applications wherever a conversion is required. The
proposed compact converter circuit will subsequently influence
the advancement in computation and manipulation of BCD
digits in aspects of applications like scientific computation,
embedded applications, digital communication and financial
calculations.
R EFERENCES
[1] O. Al-Khaleel, Z. Al-Qudah, M. Al-Khaleel, C. A. Papachristou, and F. G.
Wolff, “Fast and compact binary-to-bcd conversion circuits for decimal
multiplication,” in 2011 IEEE 29th International Conference on Computer
Design (ICCD), pp. 226–231, IEEE, 2011.
[2] T.-B. Juang and Y.-M. Chiu, “Fast binary to bcd converters for decimal
communications using new recoding circuits,” in 2014 International
Symposium on Integrated Circuits (ISIC), pp. 188–191, IEEE, 2014.
[3] J. Bhattacharya, A. Gupta, and A. Singh, “A high performance binary
Fig. 6: Graphical Analysis of Area, Delay and the Product to bcd converter for decimal multiplication,” in Proceedings of 2010
between Existing [4], [5] and Proposed circuit International Symposium on VLSI Design, Automation and Test, pp. 315–
The delay in existing circuit [4] is 3.125ns whereas the 318, IEEE, 2010.
[4] S. R. Rangisetti, A. Joshi, and T. Nikoubin, “Area-efficient and power-
delay in proposed circuit is 2.8ns which implies 33.49% efficient binary to bcd converters,” in 2015 6th International Conference
improvement in delay over the existing circuit. Fig. 6 shows on Computing, Communication and Networking Technologies, IEEE.
that, the proposed architecture has drastic improvement over [5] A. Joshi, S. Rangisetti, P. Lohray, and T. Nikoubin, “Fast & energy
efficient binary to bcd converter with complement based logic design
area with a slight overhead in delay than CBLD [5] circuit (cbld) for bcd multipliers,” in 2019 IEEE 9th Annual Computing and
which is reasonable. The area delay product is improved than Communication Workshop and Conference (CCWC), pp. 0426–0434,
all other circuits. IEEE, 2019.
[6] Z. T. Sworna, M. UlHaque, N. Tara, H. M. H. Babu, and A. K. Biswas,
In hardware complexity representation n denotes the number “Low-power and area efficient binary coded decimal adder design using a
of input. α, β, γ, p, q represents AND gate, OR gate, NOT look up table-based field programmable gate array,” IET Circuits, Devices
gate, XOR gate, XNOR gate, respectively. Besides, x depicts & Systems, vol. 10, no. 3, pp. 163–172, 2016.
[7] M. U. Haque, Z. T. Sworna, H. M. H. Babu, and A. K. Biswas, “A fast
multiplexer. fpga-based bcd adder,” Circuits, Systems, and Signal Processing, vol. 37,
η =α+β+p+x (18) no. 10, pp. 4384–4408, 2018.
[8] Z. T. Sworna, M. U. Haque, H. M. H. Babu, and L. Jamal, “A cost-
Hardware complexity for Shift Add by Constant [4] (E) and efficient look-up table based binary coded decimal adder design,” in
proposed architectures (P) are given respectively as follows. Future Technologies Conference (FTC), pp. 874–882, IEEE, 2017.

View publication stats