A Fast 16x16 Vedic Multiplier Using Carry Select Adder On FPGA

ISSN (Online) 2278-1021
IJARCCE ISSN (Print) 2319 5940
International Journal of Advanced Research in Computer and Communication Engineering

Vol. 5, Issue 4, April 2016
A Fast 16x16 Vedic Multiplier Using

Carry Select Adder on FPGA
Shiksha Pandey1, Deepak Kumar2
M.Tech. Scholar EC Dept., Vidhyapeeth Inst. Sc.& Tech., Bhopal, India1
Assistant Professor, EC Dept., Vidhyapeeth Inst. Sc.& Tech., Bhopal, India2
Abstract: Vedic mathematics is one of the ancient Indian system of mathematics that was rediscovered in the early
twentieth century This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic
Mathematics that have been modified to improve performance using Carry select adders. A high speed processor
depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as
well as in general processors. In Vedic Mathematics calculation based on 16 sutras is a unique technique of calculations
. This paper presents design and implementation of high speed 16x16 bit Vedic multiplier architecture which is quite
different from the Conventional method of multiplication like addition and shifting . Further, the Verilog HDL coding
of Urdhva tiryakbhyam Sutra for 16x16 bits multiplication and carry select adder is simulated and implemented on
XilinxISE9.2i.
Keywords: Ripple Carry (RC) Adder, Vedic Mathematics, Vedic Multiplier (VM), Urdhava Tiryakbhyam Sutra, Carry
select adder, Verilog HDL.
I. INTRODUCTION
Multiplication is an fundamental function in arithmetic Section II describes basic methodology of Vedic

operations based on this operations such as Multiply and multiplication technique. Section III describes the
Accumulate(MAC) and inner product are among some of proposed methodology of Vedic multiplication technique
the frequently used Computation Intensive Arithmetic with Carry select adders. Section IV describes the design
Functions(CIAF) currently implemented in many Digital and implementation of Vedic multiplier module by using
Signal Processing(DSP) applications such as convolution, XilinxISE9.2i. Section V comprises of Result and
Fast Fourier Transform(FFT), filtering and in Discussion in which device utilization summary and
microprocessors in its arithmetic and logic unit. computational path delay obtained for the proposed Vedic
multiplier (after synthesis) is discussed. Finally Section VI
[1]. Since multiplication dominates the execution time of comprises of Conclusion
most DSP algorithms, so there is a need of high speed
multiplier. Currently, multiplication time is still the II. VEDIC MULTIPLICATION TECHNIQUE
dominant factor in determining the instruction cycle time
of a DSP chip. The demand for high speed processing has The use of Vedic mathematics is to reduce the typical
been increasing as a result of expanding computer and calculations in conventional mathematics to very simple
signal processing applications. one. Because the Vedic formulae are claimed to be based
on the natural principles on which the human mind works.
Higher throughput arithmetic operations are important to Vedic Mathematics is a methodology of arithmetic rules
achieve the desired performance in many real-time signal that allow more efficient speed implementation. It also
and image processing applications. One of the key provides some effective algorithms which can be applied
arithmetic operations in such applications is multiplication to various branches of engineering such as computing.
and the development of fast multiplier circuit has been a
subject of interest over decades. Reducing the time delay The proposed Vedic multiplier is based on the “Urdhva
and power consumption are very essential requirements Tiryagbhyam” sutra (algorithm). These Sutras have been
for many applications. This work presents different traditionally used for the multiplication of two numbers in
multiplier architectures. the decimal number system. In this work, we apply the
same ideas to the binary number system to make the
In this paper a simple 16 bit digital multiplier is proposed proposed algorithm compatible with the digital hardware.
which is based on Urdhva Tiryakbhyam (Vertically & It is a general multiplication formula applicable to all
Crosswise) Sutra of the Vedic Math’s. Two binary cases of multiplication. It literally means “Vertically and
numbers (16-bit each) are multiplied with this Sutra. The Crosswise”. It is based on a novel concept through which
main concept of this paper is that the speed of propagation the generation of all partial products can be done with the
and decrease in delay of the conventional architecture. concurrent addition of these partial products. The
This paper is organized as follows. algorithm can be generalized for n x n bit number. Since
Copyright to IJARCCE DOI 10.17148/IJARCCE.2016.54243 989


the partial products and their sums are calculated in

parallel and the multiplier is independent of the clock
frequency of the processor. Due to its regular structure, it
can be easily layout in microprocessors and designers can
easily circumvent these problems to avoid catastrophic
device failures. The processing power of multiplier can
easily be increased by increasing the input and output data
bus widths since it has a quite a regular structure. Due to
its regular structure, it can be easily layout in a silicon
chip. The Multiplier based on this sutra has the advantage
that as the number of bits increases, gate delay and area
increases very slowly as compared to other conventional
multipliers.
A. Vedic Multiplier for 2X2 bit Module

The method is explained below for two, 2 bit numbers A Fig. 2.2 RTL model of 2X2 Vedic Multiplier
and B where A = a1a0 and B = b1b0 as shown in Fig. 2.1.
Firstly, the least significant bits are multiplied which gives B. Vedic Multiplier for 4X4 bit Module
the least significant bit of the final product (vertical). For higher no. of bits in input, little modification is
Then, the LSB of the multiplicand is multiplied with the required. Divide the no. of bit in the inputs equally in two
next higher bit of the multiplier and added with, the parts.
product of LSB of multiplier and next higher bit of the
multiplicand (crosswise). The sum gives second bit of the Let’s analyze 4x4 multiplications, say A3A2A1A0 and
final product and the carry is added with the partial B3B2B1B0. Following are the output line for the
product obtained by multiplying the most significant bits multiplication result, Q7Q6Q5Q4Q3Q2Q1Q0. Block
to give the sum and carry. The sum is the third diagram of 4x4 Vedic Multiplier is given in fig 2.3.
corresponding bit and carry becomes the fourth bit of the
final product. Let’s divide A and B into two parts, say A3 A2 & A1 A0
for A and B3B2 & B1B0 for B. Using the fundamental of
Vedic multiplication, taking two bit at a time and using 2
bit multiplier block,
A3A2 A1A0
X B3B2 B1B0
-------------------
Fig. 2.1 Block diagram of 2X2 Vedic Multiplier
Let’s take two inputs, each of 2 bits; say A1A0 and B1B0.
Since output can be of four digits, say Q3Q2Q1Q0. As per
basic method of multiplication, result is obtained after
getting partial product and doing addition.
A1 A0
X B1 B0
------------------
A1B0 A0B0 Fig. 2.3 Algorithm of 4x4 bit Vedic Multiplier
A1B1 A0B1
----------------------------- Each block as shown above is 2x2 bits multiplier. First
Q3 Q2 Q1 Q0 2x2 multiplier inputs are A1 A0 and B1 B0.The last block
is 2x2 multiplier with inputs A3 A2 and B3 B2.
In Vedic method, Q0 is vertical product of bit A0 and B0,
Q1 is addition of crosswise bit multiplication i.e. A1 & B0 The middle one shows two, 2x2 bits multiplier with inputs
and A0 and B1, and Q2 is again vertical product of bits A1 A3A2 & B1B0 and A1A0 & B3B2. So the final result of
and B1 with the carry generated, if any, from the previous multiplication, which is of 8 bit, Q7Q6Q5Q4Q3Q2Q1Q0.
addition during Q1. Q3 output is nothing but carry
generated during Q2 calculation. This module is known as The 4x 4 bit multiplier is structured using 2X2 bit blocks
2x2 multiplier block [5,6,7]. as shown in figure 2.4.


decomposed into pair of 8 bits AH-AL. Similarly

multiplicand B can be decomposed into BH-BL.
The outputs of 8X8 bit multipliers are added accordingly

to obtain the 32 bits final product.
Thus, in the final stage two adders are also required [12].
The structure of 16X16 is again obtained from the
decomposition of 8X8 vedic multiplier.
Fig. 2.4: RTL View of 4x4 Bit Vedic Multiplier by

ModelSim
C. Implementation of 8x8 bits Vedic Multiplier

The 8x 8 bit multiplier is structured using 4X4 bit blocks
as shown in figure 2.5. In this figure the 8 bit multiplicand
A can be decomposed into pair of 4 bits AH-AL. Similarly
multiplicand B can be decomposed into BH-BL. The 16
bit product can be written as: Fig. 2.6 16x16 Bits decomposed Vedic Multiplier
P= A x B= (AH-AL) x (BH-BL)
= AH x BH+AH x BL + AL x BH+ AL x BL III. VEDIC MULTIPLICATION USING CARRY
SELECT ADDER
The outputs of 4X4 bit multipliers are added accordingly
to obtain the final product. Thus, in the final stage two The vedic multiplier requires 4 bit, 6 bit , 12 bit, 16 bit , 24
adders are also required [10,12]. bit adders at each stage of 2X2, 4X4, 8X8 and 16x16
multiplication. The carry-select adder generally consists of
Now the basic building block of 8x8 bits Vedic multiplier two ripple carry adders and a multiplexer. Adding two n-
is 4x4 bits multiplier which implemented in its structural bit numbers with a carry-select adder is done with two
model. For bigger multiplier implementation like 8x8 bits adders (therefore two ripple carry adders) in order to
multiplier the 4x4 bits multiplier units has been used as perform the calculation twice, one time with the
components which are P= A x B= (AH-AL) x (BH-BL) assumption of the carry-in being zero and the other
= AH x BH+AH x BL + AL x BH+ AL x BL assuming it will be one. After the two results are
calculated, the correct sum, as well as the correct carry-
The outputs of 4X4 bit multipliers are added accordingly out, is then selected with the multiplexer once the correct
to obtain the final product. Thus, in the final stage two carry-in is known.
adders are also required [11,12].
The structural modelling of any design shows fastest

design.
Fig. 3.1 4 bit Carry Select Adder
The number of bits in each carry select block can be

uniform, or variable. In the uniform case, the optimal
delay occurs for a block size of . When variable, the
Fig.2.5 8X8 Bits decomposed Vedic Multiplier block size should have a delay, from addition inputs A and
B to the carry out, equal to that of the multiplexer chain
D. Implementation of 16x16 bits Vedic Multiplier leading into it, so that the carry out is calculated just in
The 16X16 bit multiplier structured using 8X8 bits blocks time. The delay is derived from uniform sizing,
as shown in Fig. 2.6. The 16 bit multiplicand A can be where the ideal number of full-adder elements per block is


equal to the square root of the number of bits being added, Implementation and simulation of its decomposed 8X8,
since that will yield an equal number of MUX delays. 4X4, 2X2 and carry select adder is also done in
XilinxISE9.1i.
In this paper we propose a 16X16 vedic multiplier using
carry select adders as its one of the basic component. This
will reduce the area in FPGA and also improve the
performance in terms of speed. It will be verified by
comparing it will hardwired unsigned multiplier.
IV. DESIGN AND IMPLEMENTATION OF

16X16 VEDIC MULTIPLIER USING
CARRY SELECT ADDER
The 16X16 multiplier is implemented and simulation

results were tested in XilinxISE9.1i and ModelSim inbuilt
Fig.4.1 16X16vedic multiplier RTL view
simulator.
Fig.4.2 16X16vedic multiplier components (a)
Fig.4.3 16X16vedic multiplier components (c)
Fig.4.4 4X4vedic multiplier simulation result1


V. RESULT AND DISCUSSION methods effectively implement hardware, it will reduce

the computational speed drastically. Therefore, it could be
Simulation of 16X16 vedic multiplier using carry select possible to implement a complete ALU using all these
adder shows a large reduction in area and better methods using Vedic mathematics methods.
performance in terms of speed. The area delay product is
also reduced but it is greater than a normal udhrava Vedic mathematics is long been known but has not been
tribhakayam multiplier due the fact that redundancy in the implemented in the DSP and ADSP processors employing
adder section is increased. large number of multiplications in calculating the various
transforms like FFTs and the IFFTs. By using these
TABLE I: COMPARISON OF DIFFERENT MULTIPLIERS ancient Indian Vedic mathematics methods world can
PERFORMANCE IN TERMS OF AREA AND SPEED achieve new heights of performance and quality for the
cutting edge technology devices.
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ISSN (Online) 2278-1021

IJARCCE ISSN (Print) 2319 5940

International Journal of Advanced Research in Computer and Communication Engineering