Noise in High-Speed Digital-to-Analog Converters

P.-Y. Bourgeois1 , T. Imaike2 , G. Goavec-Merou1 and E. Rubiola1

1
FEMTO-ST Institute, Time & Frequency Dept, UMR 6174-CNRS, University of Franche-Comté, Besançon, France
2
Nihon University, Dept of Electronic Engineering, Japan
Email: pyb2@femto-st.fr

Abstract—We report on the measurement of phase noise where fs represents the sampling rate.
of high speed analog to digital converters in a full digital
measurement setup and for various development boards. The III. D IGITAL A RCHITECTURES
tested configurations ensures a Nyquist rate higher than 100 MHz
suitable for conventional ultralow noise devices. Several analog In this project, we have operated a selection of various
to digital converters featuring a SNR higher than 140 dB enable platforms with integration of FPGA and CPU cores. All
the measurement of AM and PM noise with a background noise algorithms have been developped from scratch in C as a library
of -185 dBc (floor) and -160 dBc (flicker, 10 Hz off the carrier)
featuring basic blocks functions, double and single precision in
using cross-correlation technique.
order to predict correct behaviour of their hardware description
counterparts. To our point of view, this is the correct way to
I. I NTRODUCTION
fully master the full system flow and measurement chain at
Digital tools are a mature technology to perform dynamic every stage. In this manner it will be possible in the future
signal analysis on ultrastable clocks and devices presenting to develop accurate models including quantization noises pro-
unpreceedent levels of stability[1-3]. Jointly with the help of cesses. Indeed this excludes the use of any proprietary black-
Soc FPGAs used as realtime coprocessors and CPUs running boxes.
multitasks operating systems with double precision, cross-
We present here 3 digital architectures that are, amongst
correlation techniques on full samples phase times series
others, under test at FEMTO-ST.
benefit from high bandwidths up to 100 MHz off the carrier.
The IF conversion is done after sampling, analysis resolution We have selected a high-speed digitizing system, from
is limited in the measurement time by the resolution of the Alazartech company, consisting of 2 synchronized boards em-
analog to digital converters. We present in this paper various bedding each 2 AD9467 (16 bits, 250 Msps), 2 Altera Stratix
tests performed on several kind of platforms based on FPGAs III FPGAs (main/coprocessor) and PCIe extension connected
with deported CPUs or the latest SoCs embedding hard cores to multicore PC station running debian-based GNU-Linux
CPUs. kernel 3.16. The versatility of such a system enable ease of
retrieving continuous samples at full speed, fast developpment
II. N UMBERS and algorithms testing as the interfaces and communication
parts are already provided.
Assuming a uniform quantizer, the quantum resolution step
is defined as the ratio of the voltage full scale range and the Second, the recent multicore SoC FPGAs as Zynq/Cyclone
number of bits M : vf sr V systems offer potential high-end features and are of growing
q= M (1) interrest. For we have conducted tests on Zynq-based platforms
2 1 (ZC706 coupled to 2 dual-channel LTC2158 (14 bits, 310
The associated noise is a statistical process representing the Msps), and also tested the dual-channel LTC2145 (14 bits, 125
density of probability of states within a measurement lenght ⌧ Msps) of the Redpitaya system, although this last platform is
: more dedicated to low-quality general purposes (small FPGA,
Z only 2 channels, not Open Source/Hardware. . . ).
2 1 ⌧ /2 2 q
= eq (t)dt = (2)
⌧ ⌧ /2 12
IV. P HASE NOISE MEASUREMENT SETUP
Finally the total noise represents the integrated noise over
the measurement bandwidth, directly related to the Nyquist
frequency :
(D)
FFT −> Norm −> PS −> PSD
S' (f ) , L' (f )

2
N = (3) 'k = atan(Q/I) D FFT −> Norm −> PS −> PSD
fN ADC
NCO
p D x 10
Ak = Q2 + I 2
This last equation remains only when proper filtering and DUT
CLK
small fraction of aliasing occurs, thanks to Parseval theorem.
π /2

Eventually, for an incoming wave of peak voltage a ⇠ vf sr , (D)

one may derive the signal to noise ratio :

DDC

4 · q2 4
SN R = ⇠ (4)
2 2
3 · vf sr · a · fs M
3 · 2 · fs Fig. 1. Principle of a digital phase noise measurement system

978-1-4799-8866-2/15/$31.00 ©2015 IEEE 672

 The digital phase noise measurement system[3] is depicted RF
frontend
Direct access to
in the preceeding figure. The phase modulated noise degrading
a perfect sinusoid is downconverted to DC after sampling RF frontend/ADC noise
thanks to a numerically controlled oscillator (NCO) set up frontend

at the carrier frequency. Successive filtering/decimation stages CLK

allows to focus on lower decades off the carrier or examine
the spectral measure at lower sampling rates by filtering out
aliased noise while reducing the measurement bandwidth.
Phase estimation is done by calculating the arctangent function
A splitted low noise 10 MHz synthesizer feeds the rf-
of the in-phase and quadrature components of the demodulated
frontend and ADC. Both arms are differentiated, allowing the
and filtered signal. Eventually the amplitude is also estimated.
common clock noise circuitry to be inherently filtered out.
From the phase time series (amplitude time series), the Fourier
Only remains a small fraction. The differenciation allows a
transform is computed thanks to the FFTW[4] algorithm.
direct interpretation of the noise of the frontend/ADC couple.
Other filtering/decimation stages completes the process of
Unless specified, the clocking system was done with an
lowering the decades. Finally the spectrum of variances is
external low-noise synthesizer. Successive filtering/decimation
reconstructed from these decades. The demodulation process
processes (up to 3 embedded into the FPGA) enable a fast
and first decimation/filtering stages may be abusively called
estimation of the system noise. The sinc filters are based
digital down converter (DDC).
on Kaiser window with 128 convolutions. Careful adjustment
of gains and rescaling ensure the lowest added quantization
noise. The resulting voltage noise spectrums are shown in the
following figures for the 3 tested ADCs ( dBV2 /Hz).
V. S OFTWARE CALIBRATION
-40
"temp_g2p16_OK/dif_ab.dat"
In order to verify the correct interpretation of the spec- -60 "temp_2stages/dif_ab.dat"
"temp_3stages/dif_ab.dat"
tral measure (normalizations processes), a noise generator -80

calibrated at -113 dBc mixed with a low noise 10 MHz -100

reference signal is send to the analog to digital

 converter. -120

 -140

 @@ABCD -160

-180

-200

-220

-240
0.001 0.01 0.1 1 10 100 1000 10000 1000001e+06 1e+07 1e+08

For the LTC2158, the input carrier was 6.6 dBm, with a
 voltage fullscale range of vf sr = 1.35 V. Slices of 217 points
were taken at every output stage of the filters
p to reconstruct

      the spectrum.
p White noise is about 10 nV/ Hz and flicker
of 5.6 µV/ Hz. SNR=154 dB for white noise.
The power spectral density is evaluated from the collected
-40
samples at full speed with double precision (’calculated pn "temp_redp_50_0diff/dif_ab.dat"
"temp_redp_50_1diff/dif_ab.dat"
from samples’ in the figure). The counterpart digital down -60
"temp_redp_50_2diff/dif_ab.dat"
conversion in single precision version embedded into the -80

FPGA, by using a squarewave NCO (inverted samples every 25 -100

points per period for a 10 MHz carrier at 250 MHz sampling -120

rate) and a 127 coefficients Blackman-Harris windowed sinc -140

filter to ensure sufficient aliased noise rejection, shows similar -160

results. The first stage output effectively ensures that no extra -180
quantization noise is induced by the chain, particularly the -200
full bit width remains unchanged. This process is no longer -220
true when multiple stages must be embedded while performing -240
slice rescaling, and additive noise may be taken into account. 0.01 0.1 1 10 100 1000 10000 100000 1e+06 1e+07 1e+08

For the Redpitaya system, the input stage was bypassed and
loaded to 50 ⌦. Only the LVDS amplifier was kept to prepare
the ADC to be feeded with differential signal. The gain is
VI. ADC NOISE MEASUREMENTS about 2, for a 0 dBm signal and a vf sr = 1.25 V at the input
of the analog to digital converter (the measure was done in
A. ADC noise measurement principle a differential mode). The onboard clock system was used to
clock the ADC at 125 Msps, slices of 214 data were taken, and
The setup of ADC phase noise measurement is depicted in because of spare space, only two filtering/decimation stages
the following figure. were performed within the FPGA. The obtained white noise

673
 p p
is 29nV/ Hz, and 4.5µV/ Hz for flicker. SNR=143.5 dB -100
"250M_floor.dat" u 1:($2-3)
(white) in a 1Hz bandwidth. "100M_floor.dat" u 1:($2-3)
"50M_floor.dat" u 1:($2-3)
-120 -159.05
-155.7
-152.6

-140

-90
"dif_cha_chb_avg100.dat"
-100 "dif_chc_chd_avg100.dat" -160
f(x)
-110

-120 -180

-130

-140 -200
1 10 100 1000 10000 100000 1e+06
-150

-160
The measured noise floors for various sampling rates are in
-170
perfect agreement with their theroretical expectations.
-180
VII. S INGLE CHANNEL NOISE MEASUREMENT
-190
1 10 100 1000 10000 100000 1e+06 1e+07 1e+08
The digital single channel noise floor measurement obeys
the setup described on the following figure. When the two
Results from the AD9467 of the Alazartech boards pre- converters are feeded with a full scale range 10 MHz low
sented, for a 12 dBm carrier (vf sr = 2.5
p V), a white noise noise wave, we may have access to the single channel noise
floor of about -157 dBVp2
/Hz (14 nV/ Hz) and a flicker of by differentiating the 2 arms after digital down conversion,
110dBV2 /Hz (3 µV/ Hz). Referred to the carrier, this is phase extraction and spectrum calculation.
equivalent to a SNR of 156 dB (white) and 109 (1 Hz) in a 1 nA + nclk + nADC1

Hz bandwidth. A (DUT)
DDC

nA nB + nADC1 + nADC2
Taking into account the 1 dBc of carrier power, the pre- B (REF)
sented results are compatible with phase noise measurements. DDC

CLK nB + nclk + nADC2

B. Effective number of bits evaluation For the noise budget, the uncorrelated arms noises are
suppressed and just remains the contribution of the converters
noises.
This technique is perfectly suitable to a fast evaluation of
the effective number of bits (ENOB) of the analog to digital "fast-alazar-floor--10M-floor.dat"
converters. One may just analyze the white noise floor for -60
"fast-alazar-floor--10M-floor.dat" u 1:3

quick evaluation of the ENOB. Technically, this may only need

1024 samples for example and a FFT evaluation on 512 points, -80

or even less ; to get better accuracy, simple averaging may -100

help. We have derived the ENOB calculation assuming uniform
quantization and the fact that it is directly related to the signal -120

to noise ratio : -140

! -160
vf sr
EN OB = log2 1+ p (5) -180
12 · fN · Sf loorL 1 10 100 1000 10000 100000 1e+06

The presented Lf spectrum shows it is possible to perform

where Sf loorL is the measured white voltage noise floor, vf sr measurement of low noise oscillators up to -160 dBc without
is the voltage full scale range and fN the Nyquist frequency. the need of more complex architecture.

Applied to the AD9467 system, the measurement of VIII. A PPLICATION TO THE MEASUREMENT OF CSO
Sf loor ⇠= 158 dBV2 /Hz lead to an effective number of It is possible to apply the 2 channels technique to
bits of about 12 in agreement with the technical datasheet. the measurement of a pair of cryogenic sapphire oscilla-
tors (CSO) exhibiting a frequency instability in the 10 15
DDC PS PS1
Uliss
7.029 MHz L'(f )

C. ADC noise vs sampling rate DDC PS

PS2*

Marmotte
White phase noise floor directly depends on the sampling
rate as shown on the following figure. range. The

674
beatnote of about 7.029 MHz of a pair of CSO feeds a two- As an application, we have performed the measure-
channel digital phase noise measurement system. The beatnote ment of the low noise synthesizer used in our experiments,
is downconverted and successive filtering/decimation stages the R&S SMA 100A with low noise option. The result-
are applied. ing plot is compared to the expensive Agilent PN5052B.
-20
-20 "sma-agilent-meas.dat"
"Uliss-vs-Marmotte-7MHz--250Msps.dat" "sma-alazar.dat" u 1:($2-10*log10(2))
"Uliss-vs-Marmotte-7MHz--100Msps.dat" -40
-40 "sma-datasheet.dat"
"Uliss-vs-Marmotte-7MHz--50Msps.dat"
"Uliss-vs-Marmotte-7MHz--25Msps.dat" -60
-60 "Uliss-vs-Marmotte-TSC5125.dat"
"fast-alazar-floor--10M-floor.dat"
-80 "noise-floor-TSC5125-10MHz.dat" -80

-100 -100

-120 -120

-140
-140
-160
-160
-180
-180
-200
0.1 1 10 100 1000 10000 100000 1e+06 -200
1 10 100 1000 10000 100000 1e+06 1e+07

The setup favorably compares with the indicated noise floor

of the TSC5125 but with only a 2 channels configuration. X. C ONCLUSION
In this paper we have presented a correct all-digital tech-
IX. 4- CHANNELS DIGITAL SIGNAL ANALYZER WITH
nique for the evaluation of the noise of high-speed analog to
CROSS - CORRELATION
digital converters. The setup is suitable for fast analysis of the
We have applied the all-digital 4-channel cross-correlation effective number of bits of such converters, the main parameter
technique as described in [3]. After sampling and gain related to quantization noise and signal to noise ratio, directly
adjustment, the digital down conversion is applied and impacting the resolution of digital measurement systems. A 2
phase extracted from the I/Q data flow at a rate of 25 channel phase and amplitude noise measurement system has
Msps. The phases time series of 2 pairs of channels been developped and applied to the measurement of ultra-
are differentiated and the cross-spectrum is calculated. stable cryogenic sapphire oscillator. Also we have presented
A (DUT)
DDC
nA + nclk + nADC1
an extension of a 4-channels cross-correlation system resulting
nA nB + nADC1 + nADC2
of noise floor of 185dBc, confirming the potential of such
a technique.
PS
B (REF)
DDC P1
nB + nclk + nADC2 nA nB

nB + nclk + nADC3
ACKNOWLEDGMENT
P2*
DDC
This work is a part of the Programme d’Investissement
d’Avenir at TF Dept of FEMTO-ST Institute (Oscillator IMP,
PS

First-TF, and Refimeve+), supported by the French ANR, and

DDC
nA nB + nADC3 + nADC4
nA + nclk + nADC4
CLK also supported the Region Franche Comté and by the Nihon
University, Japan.
For the measurement of the system noise floor, a 10
MHz signal is send to each of the 4 channels. With 107 R EFERENCES
correlations on a continuous data flow, the obtained floor [1] Grove et al, Direct-Digital Phase-Noise Measurement, Proc. of the IEEE
quickly reaches -185 dBc and is below -160 dBc for Fourier UFFC, 2004.
frequencies at 10 Hz off the carrier (1000 correlations). [2] Angrisani et al, Real-time phase noise meter based on a digital signal
processor, Instrumentation and Measurement Technology Conference,
-40
-185 2006.
"dif_cross_avg1000.dat"
-60 [3] Nelson, Howe, A sub-sampling digital PM/AM noise measurement sys-
tem, proc. IEEE IFCS 2012.
-80
[4] http://fftw.org/ ; FFTW was written by Matteo Frigo and Steven G.
-100 Johnson
-120

-140

-160

-180

-200

-220
1 10 100 1000 10000 100000 1e+06

Better results could be expected, even if they already represent

state-of-the-art results.

675