5024 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO.

11, NOVEMBER 2011

An Efficient DSP-FPGA-Based Real-Time

Implementation Method of SVM Algorithms
for an Indirect Matrix Converter
Mahmoud Hamouda, Handy Fortin Blanchette, Member, IEEE, Kamal Al-Haddad, Fellow, IEEE, and
Farhat Fnaiech, Senior Member, IEEE

Abstract—This paper proposes a real-time DSP- and FPGA- indirect matrix converter (IMC) which is also referred to in
based implementation method of a space vector modulation literature as a two-stage direct power converter is a recent topol-
(SVM) algorithm for an indirect matrix converter (IMC). There- ogy that is characterized by a lower commutation problem than
fore, low-cost and compact control platform is built using a 32-bit
fixed-point DSP (TMS320F2812) operating at 150 MHz and a conventional direct topologies [6]–[10]. However, the digital
SPARTAN 3E FPGA operating at 50 MHz. The method consists implementation of the switching patterns for both topologies
in using the event-manager modules of the DSP to build specified remains until now a hard task owing to the high complexity
pulses at its PWM output peripherals, which are fed to the digital of matrix converters’ modulation schemes. Over the last few
input ports of a FPGA. Moreover, a simple logical processing and years, several implementation methods have been reported in
delay times are thereafter implemented in the FPGA so as to
synthesize the suitable gate pulse patterns for the semiconductor- literature. In [12] and [13], the authors proposed the use of pow-
controlled devices. It is shown that the proposed implementation erful DSP boards that can be plugged directly into the PCI bus
method enables high switching frequency operation with high of a desktop computer. Despite their user-friendly interfaces,
pulse resolution as well as a negligible propagation time for the these control platforms are always expensive and not compact;
generation of the gating pulses. Experimental results from an thereby, they are not suitable for industrial implementations.
IMC prototype confirm the practical feasibility of the proposed
technique. Other approaches proposed the use of a microcontroller in
conjunction with logic circuits [14]. In most of aforementioned
Index Terms—DSP, FPGA, matrix converters, space vector methods, the obtained switching frequency is not high enough
modulation (SVM).
so as to increase the power density of the converter as suggested
I. I NTRODUCTION by today’s technology [15]. Moreover, the PWM output signals
are in general updated by specific software routines, which
ATRIX converters are modern ac-ac power conversion
M devices. They need a small line filter to reduce the
current harmonics injected into the mains as well as a clamping
results in a mediocre pulse resolution and needs an additional
CPU processing. At present, the use of a DSP in conjunction
with a FPGA module is a common hardware structure in many
protection circuit to ensure safe operation of the converter power electronic applications [16]–[21]. Some authors have
during abnormal operating conditions. The absence of large already made the association between DSP and PLD modules
energy storage elements in the dc bus such as the bulky and to build a matrix converter control platform [22], [23]. In this
limited lifetime electrolytic capacitor is their major advantage framework, two different approaches have been developed to
over conventional rectifier inverter-based systems that allows perform the communication between the two chips. In the first
size and weight reduction of the converter and increasing its approach [22], the DSP calculates at every sampling period
reliability as well. Moreover, the latter can be considered as the the opportune duty cycles as well as the position of the input
most favorite topology that can utilize the new silicon carbide- current and output voltage reference vectors. The results are
based devices, which could operate at 300 ◦ C [1]–[5]. The next transmitted to the PLD chip through a data transfer bus.
An interface block is implemented in the PLD module so as to
Manuscript received November 24, 2010; revised March 3, 2011 and hold the data supplied to it by the DSP. Based on the results of
April 13, 2011; accepted May 5, 2011. Date of publication June 16, 2011;
date of current version September 7, 2011. This work was supported in
data processing as well as on the commutation strategy, a PWM
part by NSERC, Canada Research Chair in Electric Energy Conversion and generator block should generate the opportune gating pulses for
Power Electronics CRC-EECPE, ETS de Montréal, and Research Unit SICISI, the overall converter’s transistors. In the second approach [23],
ESSTT, University of Tunis.
M. Hamouda and F. Fnaiech are with the University of Tunis, the data transfer complexity is reduced. In fact, the DSP outputs
ESSTT, SICISI, Tunis 1008, Tunisia, and are also with the CRC-EECPE, only 5-bit encoded data corresponding to the position of the
Ecole de technologie supérieure, Montréal, QC H3C1K3, Canada (e-mail: two reference vectors. Next, it generates four width-modulated
mahmoudhamouda@yahoo.fr; Fnaiech@ieee.org).
H. F. Blanchette and K. Al-Haddad are with the CRC-EECPE, pulses. A decode block and a PWM generator module should
Ecole de technologie supérieure, Montréal, QC H3C1K3, Canada (e-mail: thereafter be implemented in the FPGA so as to distribute the
handyblanchette@hotmail.com; kamal@ele.etsmtl.ca). switching pulses according to pulse widths and encoded data
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. supplied to it by the DSP module. For both approaches, to
Digital Object Identifier 10.1109/TIE.2011.2159952 achieve a correct data transfer between the DSP and the FPGA,

0278-0046/$26.00 © 2011 IEEE

HAMOUDA et al.: IMPLEMENTATION METHOD OF SVM ALGORITHMS FOR AN INDIRECT MATRIX CONVERTER 5025

Fig. 1. Topology of an indirect matrix converter under study.

it is essential to synchronize the timing of the different events

in the two chips.
This paper proposes a much easier DSP-FPGA-based imple-
mentation method of the SVM scheme for IMCs wherein the
data transfer between the two devices is completely removed.
Consequently, the FPGA chip is relieved from processing and
decoding these data. First, a DSP TMS 320F2812 is used
to generate only ten specified pulses at the output ports of
its two event-manager modules. Second, by using a FPGA
Spartan 3E device, simple logic processing and delay times are
∗
implemented to achieve the suitable gate pulse patterns of the Fig. 2. (a) Synthesis of the input current reference vector im corresponding to
converter switches. The merits of this method are the following. the input currents ima , imb , and imc . I 1,...,6 are fixed space vectors depending
on the switching states of the input stage four-quadrant switches. (b) Synthesis
– Unlike conventional techniques, no data transfer or syn- ∗
of the output voltage reference vector V o corresponding to the phase-to-neutral
chronization signals between the DSP and the FPGA are output voltages VA , VB , and VC . V 1,...,6 are fixed space vectors depending
required. on the switching states of the output stage two-quadrant switches.
– A high switching frequency operation with high pulse ∗
reference vector im , which represents the modulated currents
resolution is achieved.
ima , imb , and imc , is synthesized by impressing its two adjacent
– The control platform is compact and not expensive.
active vectors I i and I i+1 (i = 1, . . . , 6) by the opportune duty
The paper is organized as follows. In the next section, a
cycles namely d1R and d2R , respectively as shown in Fig. 2(a).
brief review of the IMC topology and SVM principle is pre-
The analytical expressions of d1R and d2R are given in (1)
sented. The DSP- and FPGA-based implementation of the SVM
below wherein γ̄i is the phase angle within its respective sector
scheme is explained in detail in Section III. In Section IV, some
of the input current reference vector [24]
experimental results are presented to confirm the effectiveness ⎧
of the proposed implementation method. Finally, concluding ⎨ d1R = sin( π3 −γ̄i )
⎪ π

remarks are given. cos( 6 −γ̄i )

(1)
⎩ d2R = cossin(γ̄
⎪ i)
.
( 6 −γ̄i )
π

II. I NDIRECT M ATRIX C ONVERTERS ’ T OPOLOGY

AND SVM P RINCIPLE On the other side, the output stage (inverter stage) should
generate sinusoidal output voltages with controllable amplitude
The power topology of an IMC consists of a current source and frequency. The reference vector v ∗o , corresponding to the
type PWM rectifier connected to a voltage source inverter as phase-to-neutral output voltages VA , VB , and VC , is modulated
shown in Fig. 1. A second-order low-pass input filter is mounted by impressing its two adjacent active vectors V i and V i+1 (i =
between the mains and the rectifier so as to reduce the current 1, . . . , 6) as well as a zero vector with the opportune duty cycles
harmonics injected into the ac source. Esa,b,c and isa,b,c are the namely d1I , d2I , and d0I as depicted in Fig. 2(b). (The zero
mains voltages and line currents, respectively. ima,b,c are the vector is not displayed). The duty cycles d1I , d2I , and d0I are
switched currents at the input side of the converter. VA,B,C and determined as shown in (2) wherein θ̄o is the phase angle within
iA,B,C are the phase-to-neutral output voltages and output cur- its respective sector of the output voltage reference vector, q is
rents, respectively. idc is the current flowing through the dc bus the input to output voltage transfer ratio, and ϕi is the target
connecting the two conversion stages. TaH,bH,cH,aL,bL,cL are input displacement angle [24]
four-quadrant switches of the input stage. TAH,BH,CH,AL,BL,CL ⎧
θ̄o ) cos( π
⎪ d1I = √2 q sin( 3 −cos(ϕ 6 −γ̄i )
π
are two-quadrant switches of the output stage. ⎪
3 i)
⎨
The matrix converter’s input stage (rectifier stage) is con- sin(θ̄o ) cos( π (2)
6 −γ̄i )
trolled in such a way to provide sinusoidal input currents with d = √23 q
⎩ 2I cos(ϕi )
⎪
⎪
unity input power factor. During each switching period, the d0I = 1 − d1I − d2I .
5026 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011

Fig. 3. Converter’s switching patterns when the input current and output
voltage reference vectors are assumed to be both lying within sector 1, as
displayed in Fig. 2(a) and (b).

In the upper part of Fig. 3 is displayed the switching pattern of

the input stage when the input current reference vector is lying
within sector 1 of the complex plane [25] i.e., this reference
∗
vector im is synthesized using I 1 and I 2 . Since there are
two different switching states of the input stage, moreover, as
the two conversion stages are not decoupled by any reactive
element, the output stage duty cycles should be distributed to
each switching state as follows.
– During the first input stage switching state, the duty
Fig. 4. Block diagram of the EVA found on the TMS320 X281X family of
cycles of V i , V i+1 and the zero vector are derived by processors (For EVB, the timers 1, 2 are substituted by timers 3, 4; the output
multiplication of d1I , d2I , and d0I with d1R , as shown signals PWM1, . . ., 6 are renamed PWM7, . . ., 12, the output signals T1PWM,
in (3). T2PWM are renamed T3PWM, T4PWM).
– During the second input stage switching state, the duty these modules is that for a fixed switching frequency operation,
cycles of V i , V i+1 and the zero vector are determined by only five compare registers have to be reloaded by the CPU
multiplication of d1I , d2I , and d0I with d2R , as shown at each sampling period. Moreover, they are able to generate
in (4) higher switching frequency higher pulse resolution PWM sig-
nals with a minimum CPU overhead. Fig. 4 shows a general
⎧
2 sin( 3 −γ̄i ) sin( 3 −θ̄o )
π π

⎨ d11 = d1R d1I = √3 q

⎪
block diagram of the event-manager module EVA, which can
⎪ cos(ϕi )
2 sin( 3 −γ̄i ) sin(θ̄o )
π
(3) generate five independent 16-bit PWM signals at the output
d = d1R d2I = 3 q √
⎩ 12 cos(ϕi )
⎪
channels namely P W M 1, 3, 5, T 1P W M , and T 2P W M ,
⎪
d10 = d1R d0I = d1R − d11 − d12
respectively. Three additional PWM signals complementary to
3 −θ̄o )
sin(γ̄i ) sin( π
⎧
⎨ d21 = d2R d1I = √23 q
⎪ P W M 1, 3, 5 could also be generated at the output channels
cos(ϕi )
sin(γ̄i ) sin(θ̄o ) (4) P W M 2, 4, 6. Unfortunately, the ten independent PWM output
√2
⎩ d22 = d2R d2I = 3 q cos(ϕi )
⎪ signals that could be generated simultaneously by EVA and
d20 = d2R d0I = d2R − d21 − d22 . EVB remain insufficient for generating the required switching
In the lower part of Figs. 3 is depicted the switching pattern patterns. In fact, these signals could be either center aligned or
of the output stage when the output voltage reference vector edge aligned, which does not allow the correct control of the
is assumed to be lying within sector 1 of the complex plane converter’s output stage.
i.e., this reference vector v ∗o is constructed using V 1 , V 2 , and a
zero vector. As can be observed, the commutation of the input B. Implementation of the Space Vector Modulation Scheme
stage switches (turn-on and turn-off) occurs during the zero-
First, the gating pulses for the output stage three upper tran-
vector operation of the output stage, i.e., the current in the dc
sistors will be synthesized by using the PWM output channels
bus is zero. Accordingly, the input stage switches commutate at
P W M 1, 3, 5 of EVA as well as P W M 7, 9, 11 of EVB. To
zero-current, which allows avoiding the commutation problem
clarify the approach, let us consider the gating pulse of TBH
that is associated with conventional direct matrix converters,
depicted in Fig. 5, which corresponds to an output voltage
and therefore drastic reduction of the switching losses.
reference vector varying within sector 1 of the complex plane.
In this case, the output signal P W M 3 of EVA will be set
III. DSP- AND FPGA-BASED I MPLEMENTATION active high and the “compare register” of compare unit 3 is
OF THE SVM S CHEME loaded with the relative value (d10 /2 + d11 ). On the other hand,
the output signal P W M 9 of EVB will be set active low
A. Overview of the Structure of an Event-Manager Module
and the “compare register” of its own compare unit is loaded
The processors of TMS320X281X family include two iden- with the relative value (1 − d21 − d20 /2). Next, by using a
tical event-manager modules in their peripheral units, which simple AND logical operator between P W M 3 and P W M 9,
are referred to as EVA and EVB [26]. The attractive feature of one can provide exactly the required gating pulse of transistor
HAMOUDA et al.: IMPLEMENTATION METHOD OF SVM ALGORITHMS FOR AN INDIRECT MATRIX CONVERTER 5027

one switch in the bottom half of input bridge should be ON at

any given instant. It follows, for given time intervals within the
switching period, both switches in the same terminal could be
off, i.e., their states are not complemented to each other at any
instant. Hence, the output channels T 1P W M and T 2P W M
of DSP will be used to generate the gating pulses of TaH and
TaL . On the other hand, the outputs T 3P W M and T 4P W M
will generate the gating pulses of TbH and TbL , respectively.
Since only one upper switch and one lower switch of this
conversion stage should be ON at any time, the remaining
PWM gating pulses of TcH and TcL can be derived from those
of T iP W M (i = 1, . . . , 4) by using a simple logical operator
NOR as follows:


TcH = TaH + TbH = T 1P W M + T 3P W M (6)
TcL = TaL + TbL = T 2P W M + T 4P W M .

The AND and NOR logic operators applied to the ba-

sic PWM output signals generated by the DSP are imple-
mented in the FPGA chip as depicted in Fig. 7(a) below. The
Fig. 5. Transistors’ gating pulses when the input current and output voltage
reference vectors are assumed to be both lying within sector 1, as displayed in
terms between parentheses indicate the FPGA pin assignments.
Fig. 2(a) and (b) (where Transistors TaL , TbH , and TcH are not conducting Since the inputs of the driver circuits–feeding the transistors’
during this operating state). gates–are connected to pull-up resistors, all FPGA PWM output
signals are inverted to achieve a correct operation of the con-
verter. As can be seen, we need typically three AND gates and
nine inverting gates to generate the gating pulses of the output
stage power transistors. For the input stage, two NOR gates and
six inverting gates are needed. As mentioned in Section II, the
input stage switches commutate during zero vector operation
of the output stage i.e., at this moment, the current idc (Fig. 1)
is zero; thus, no freewheeling path is needed during the input
stage (rectifier stage) switches commutation. However, to avoid
a short circuit across the terminals of the input bridge as well
as across the dc bus connecting the two bridges, turn-on delay
times should be applied for each of the commutated switches
[Fig. 7(a)]. This figure shows also that any synchronization
signal is needed between DSP and FPGA chips. Moreover,
there is no data exchange between the two chips. In particular,
Fig. 6. Synthesis of the PWM gating pulse of TBH when the output voltage
reference vector is lying within sector 1. (TBH = PWM3 & PWM9). In the the FPGA has not to be informed neither of the beginning of
actual implementation, TBH is active low logic (cf. Fig. 7(a), Fig. 11). the switching period nor of the positions of the input current
and output voltage reference vectors.
The DSP control algorithm that should generate the ten spec-
TBH as shown in Fig. 6. In a similar technique, we synthesize ified PWM output signals fed to the FPGA chip is implemented
the gating pulses of TAH and TCH so that according to the flowchart of Fig. 7(b). The initialization pro-

TAH = P W M 1 & P W M 7 cedure includes the following tasks: set up the CPU internal
TBH = P W M 3 & P W M 9 (5) clock, set up EVA and EVB registers so as their logical input-
TCH = P W M 5 & P W M 11. output peripherals operate in PWM mode. On the other side, the
timer 1 of EVA is selected to handle the switching frequency
Next, the gating pulses of lower transistors (TAL , TBL , and and is programmed in a continuous counting mode so as to
TCL ) are generated simply by inverting those of upper tran- provide edge-aligned PWM signals at the output peripherals of
sistors. Among the ten DSP PWM output channels, it remains the DSP. At each timer 1 interrupt request, the DSP updates
now only four available PWM channels that could be used first the input current and output voltage reference vectors,
to synthesize the gating pulses for the input stage transistors. respectively. Next, the duty cycles are computed according to
The modulation scheme of the input stage is quite different (1)–(4). Afterward, each compare unit register (Fig. 4) is re-
from the one used for the output stage. To prevent short circuit loaded by updated value so as to provide the target PWM shape
of the supply voltages and ensure a freewheeling path for the at its corresponding PWM output. Finally, the next interruption
current idc (Fig. 1), only one switch in the upper half and only service for timer 1 is enabled.
5028 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011

Fig. 8. Photo of the DSP- and FPGA-based control platform.

achieved, which increases the accuracy of the switching pulses.

Finally, the software flexibility of the DSP, the reduced number
of instructions that should be used, and the reduced number of
logic operations developed within the FPGA have made quite
simple and efficient the implementation of this complex SVM
scheme.
The use of a DSP for this application is motivated by its
high computing performance as well its reliability which was
predicted to be ten times better than the one of a FPGA as
reported in [28]. In fact, its architecture is optimized to achieve
complex arithmetic and accumulation operations, which are
inherently suggested to achieve the control of this complex
converter. Moreover, owing to its appropriate built-in periph-
eral modules, the used DSP (TMS320F2812) is dedicated to
operate with power electronic applications; this makes easy and
flexible the software implementation. In particular, only few
instructions are required to implement the overall algorithm.
The use of a single FPGA chip with an embedded processor
would be a more compact solution. However, this will make
much more difficult the implementation of intensive arithmetic
operations and trigonometric calculations. In other words, we
will not benefit from the easier software implementation on
the DSP. Moreover, the FPGA must generate the PWM gating
signals not from specific signals as those generated from the
Fig. 7. (a) Logic operations and delay times implemented using the FPGA. TMS 320F2812 but from the opportune data calculated by the
(b) DSP control algorithm flowchart.
embedded processor. First, this will need much more time and
effort to implement an extra PWM generator that emulates
C. Discussion on the Features of the Proposed Implementation
the EVA and EVB modules of the DSP. Second, unlike the
Method and Control Platform
proposed solution, a data transfer bus and synchronization
As can be observed, the contribution of the paper is focalized signals are mandatory to achieve the communication between
on a new implementation method rather than the enhancement the processor and FPGA. Finally, the cost of a more advanced
of the modulation scheme of the converter. The novelty in our FPGA chip including an embedded processor or a Power PC
design is that we demonstrate for the first time and unlike remains up to now much more expensive than that of the
all of the previous realizations that it is possible to build a two chips used in the control platform [29], [30]. It should
DSP-FPGA-based control platform without using any data- also be pointed out that even in recent literature, the use of a
transfer bus between the two chips. As a major advantage, FPGA in conjunction with external processors such as DSPs
the parallel efficiency of the FPGA will be independent of or rapid prototyping controllers (dSPACE) remains up to now
the data transfer rate. On the other hand, the FPGA module a competitive solution in most power electronic and motion
will be relieved from decoding and processing the encoded control applications [18]–[21].
data received from the DSP. It follows that a near-to-real-time From another point of view, owing to the simple implemen-
transfer of PWM signals from the DSP to the optodrivers is tation method that we proposed in this paper, which avoids
HAMOUDA et al.: IMPLEMENTATION METHOD OF SVM ALGORITHMS FOR AN INDIRECT MATRIX CONVERTER 5029

Fig. 9. Waveforms of Esa phase a mains voltage, iA , iB , and iC load Fig. 10. Waveforms of phase to neutral input voltage Esa , line current isa ,
currents, and isa , isb , and isc line currents during steady-state operation: input and load current iA for (a) step decrease of the input to the output voltage
frequency 60 Hz (mains voltage and line currents), output frequency 70 Hz transfer ratio from q = 0.75 to q = 0.5 and (b) step decrease of the output
(load currents). frequency from 70 Hz to 40 Hz.

any data processing or decoding within the FPGA chip, it is translation from 3.3 V to 5 V is realized through the dual
obvious that this latter could be replaced by a simple PLD chip supply bus transceiver SN74LVCC4245A  3 so as to feed
to implement the required Boolean logic operations and delay the optodrivers HCPL3120 used to drive the power transistors.
times. However, it should be pointed out that the proposed al- The Board  3 is also designed to make electrical connections
gorithm should be extended in the future so as to include much between the appropriate pins of FPGA and DSP. The operating
more complex tasks such as the control of three-phase machines clock frequencies of DSP and FPGA are 150 and 50 MHz,
as well as the reactive power transfer between the converter respectively. The development tool used for the DSP is the
and the utility network, which needs the implementation of Texas Instruments Code Composer Studio v.3.1. The FPGA
additional extra control blocks in the PLD chip. For that reason, development software is the XILINX ISE v.7.1. The switching
we preferred using a FPGA chip so as to achieve an extensible frequency is set to fsw = 18 kHz. This quantity is programmed
and more flexible solution. in the counter registers of Timer1 and Timer3, respectively,
which are loaded by the same value 4096. The resulting gating
pulse resolution is thereafter equal to 13.34 ns. Fig. 9 depicts
IV. E XPERIMENTAL R ESULTS
the line and load currents during steady-state operation. These
To show the effectiveness of the proposed implementation waveforms are obtained with an input to the output voltage
method, an IMC prototype was constructed. The converter is transfer ratio q = 0.75, an output frequency fo = 70 Hz. As can
feeding a three-phase star connected R-L load (R = 25 Ω and be seen, the line and load currents are sinusoidal, balanced, and
L = 10 mH). The LC filter inserted at the utility side consists free of low-order harmonic components. Fig. 10(a) displays the
of three shunt-connected capacitors (ten µF) and three series- line and load current waveforms in response to a step decrease
connected inductors (L = 500 µH). The network three-phase of the input to the output voltage transfer ratio from q = 0.75
voltage amplitude and frequency are 50 V and 60 Hz, respec- to q = 0.5. In Fig. 10(b) is shown the line and load current
tively. The proposed control platform is shown in Fig. 8. It waveforms during a step decrease of the output frequency from
consists of a DSP Board eZdsp F2812 from Spectrum Digital 1 fo = 70 Hz to fo = 40 Hz. These results confirm the validity
and a FPGA board Nexys2 from DIGILENT 2 . A voltage level and accuracy of the proposed implementation method during
5030 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 11, NOVEMBER 2011

Fig. 11. Zoom of TBH gating signal obtained from the DSP PWM outputs PWM3 and PWM9 showing 30-ns propagation time.

steady-state and transient operations. In Fig. 11 is displayed – Compared to other DSP-PLD-based control platforms,
a zoom of the gating signal of transistor TBH . This signal is the authors demonstrated for the first time, and unlike all
synthesized in the FPGA chip from the DSP outputs PWM3 of the previous realizations, that it is possible to build
and PWM9 by using one AND logical operator as well as one such a platform without using any data-transfer bus or
inverting gate as shown in Fig. 7(a). The propagation time from synchronization signals between the two chips. In partic-
the DSP to transistors’ gates through the FPGA and the dual ular, it is not necessary to inform the FPGA chip neither
supply bus transceiver SN74LVCC4245A is approximately 30 of the starting of the switching period nor of the duty
ns, which is quite negligible compared to the switching period cycles’ values. The FPGA is thereafter relieved from
(55 µs) i.e., a negligible propagation time of the gating pulses decoding and processing the data supplied to it by the
is achieved. DSP, which will improve its parallel operation efficiency.
These results show thus the capability of the proposed im- On the other side, it was found that the propagation time
plementation method to achieve a high switching frequency of the PWM signals from the peripheral outputs of the
operation with high pulse resolution as well as a negligible DSP to the transistors’ gates through the FPGA chip
propagation time for the generation of the gating pulses. With does not exceed few tens of nanoseconds, which allows
regard to the design methodology, the switching frequency the generation with negligible propagation time of the
could easily be programmed to reach hundreds of kilohertz. gating pulses.
This is due to the two following reasons, which have not
been fulfilled together with previous implementations. First,
the two event-manager modules of the DSP have their own R EFERENCES
timers, which are totally independent of those of the main
[1] H. M. Nguyen, H. H. Lee, and T. W. Chun, “Input power factor
processing unit. Thereafter, the frequency and pulse resolution compensation algorithms using a new direct-SVM method for matrix
of the basic PWM signals that are generated by the DSP are converter,” IEEE Trans. Ind. Electron., vol. 58, no. 1, pp. 232–243,
totally independent of the time processing of the main unit i.e., Jan. 2011.
[2] H. Hojabri, H. Mokhtari, and L. Chang, “A generalized technique of
the complexity of advanced control algorithms such as sliding modeling, analysis, and control of a matrix converter using SVD,” IEEE
mode or predictive control does not affect neither the maximum Trans. Ind. Electron., vol. 58, no. 3, pp. 949–959, Mar. 2011.
permissible switching frequency nor the pulse resolution of the [3] R. K. Gupta, K. K. Mohapatra, A. Somani, and N. Mohan, “Direct-matrix-
converter-based drive for a three-phase open-end-winding ac machine
gating pulses. Second, since there is no data transfer between with advanced features,” IEEE Trans. Ind. Electron., vol. 57, no. 12,
the DSP and FPGA, the maximum switching frequency is found pp. 4032–4042, Dec. 2010.
to be totally independent of the maximum data transfer rate [4] R. Cardenas, R. Peña, G. Tobar, J. Clare, P. Wheeler, and G. Asher, “Sta-
bility analysis of a wind energy conversion system based on a doubly fed
as well as the minimum time range required by the FPGA to induction generator fed by a matrix converter,” IEEE Trans. Ind. Electron.,
process and decode these data. vol. 56, no. 10, pp. 4194–4206, Oct. 2009.
[5] M. Y. Lee, P. Wheeler, and C. Klumpner, “Space-vector modulated multi-
level matrix converter,” IEEE Trans. Ind. Electron., vol. 57, no. 10,
pp. 3385–3394, Oct. 2010.
V. C ONCLUSION [6] L. Wei and T. A. Lipo, “A novel matrix converter topology with
simple commutation,” in Conf. Rec. IEEE IAS Annu. Meeting, 2001,
A new real-time implementation method of SVM algorithm pp. 1749–1754.
for IMCs is presented. The proposed method allows a compact [7] R. Peña, R. Cardenas, E. Reyes, J. Clare, and P. Wheeler, “A topology
for multiple generation system with doubly fed induction machines and
design, low-cost, and easier implementation. With regard to indirect matrix converter,” IEEE Trans. Ind. Electron., vol. 56, no. 10,
previous implementation methods, the main benefits of the pp. 4181–4193, Oct. 2009.
proposed one are as follows. [8] M. Hamouda, F. Fnaiech, and K. Al-Haddad, “Control of the line current
provided by Dual-Bridge Matrix Converters using a discrete-time sliding
mode control approach,” in Proc. IEEE IECON, Paris, France, 2006,
– Compared to rapid prototyping controllers such as pp. 1727–1732.
dSPACE 1104 or 1103, a high PWM switching fre- [9] J. W. Kolar, F. Schafmeister, S. D. Round, and H. Ertl, “Novel three-phase
quency operation with a high pulse resolution of the ac-ac sparse matrix converters,” IEEE Trans. Power Electron., vol. 22,
no. 5, pp. 1649–1661, Sep. 2007.
gating pulses could be achieved independent of the com- [10] M. Hamouda, F. Fnaiech, and K. Al-Haddad, “Input filter design for
plexity of the control algorithm. In fact, multistep control SVM Dual-Bridge Matrix Converters,” in Proc. IEEE ISIE, Montréal, QC,
strategies as well as advanced reactive power controllers Canada, 2006, pp. 797–802.
[11] P. Correa, J. Rodríguez, M. Rivera, J. R. Espinoza, and J. W. Kolar,
could easily be implemented without affecting the fea- “Predictive control of an indirect matrix converter,” IEEE Trans. Ind.
tures of the PWM gating pulses. Electron., vol. 56, no. 6, pp. 1847–1853, Jun. 2009.
HAMOUDA et al.: IMPLEMENTATION METHOD OF SVM ALGORITHMS FOR AN INDIRECT MATRIX CONVERTER 5031

[12] M. Hamouda, F. Fnaiech, and K. Al-Haddad, “A DSP based real-time Handy Fortin Blanchette (S’07–M’10) received the
simulation of Dual-Bridge matrix converters,” in Proc. IEEE ISIE Conf., B.Eng., M.Eng., and Ph.D. degrees in electrical en-
Vigo, Spain, 2007, pp. 594–599. gineering from the École de Technologie Supérieure
[13] S. Müller, U. Ammann, and S. Rees, “New time-discrete modulation (ÉTS), Montreal, QC, Canada, in 2001, 2003, and
scheme for matrix converters,” IEEE Trans. Ind. Electron., vol. 52, no. 6, 2010, respectively.
pp. 1607–1615, Dec. 2005. From 1994 to 1997, he was engaged in indus-
[14] M. Jussila, M. Salo, and H. Tuusa, “Realization of a three-phase indirect trial automation. From 1998 to 2000, he was with
matrix converter with an indirect vector modulation method,” in Proc. the Bombardier Transport-ETS Research Labora-
IEEE PESC Conf., Acapulco, Mexico, 2003, pp. 689–694. tory, Montréal, where he was involved in a high-
[15] J. W. Kolar, U. Drofenik, J. Biela, M. L. Heldwein, H. Ertl, T. Friedli, and power traction system. From 2001 to 2003, he was
S. D. Round, “PWM converter power density barriers,” in Proc. 4th PCC, involved in the development of an electrical drive
Nagoya, Japan, Apr. 2–5, 2007, pp. 9–29. library in Simulink (MATLAB) environment. From 2007 to 2010, he was with
[16] X. Shao and D. Sun, “Development of a new robot controller architec- OPAL-RT group, where he was engaged in power electronics real-time simula-
ture with FPGA-based IC design for improved high-speed performance,” tion on CPU and FGPA. From 2010 to 2011, he was a Visiting Scholar at Center
IEEE Trans. Ind. Informat., vol. 3, no. 4, pp. 312–321, Nov. 2007. for Power Electronic and System, Virginia Polytechnic Institute and State Uni-
[17] C. A. Silva, L. A. Córdova, P. Lezana, and L. Empringham, “Implemen- versity, Blacksburg, where he was involved in packaging of high temperature
tation and control of a hybrid multilevel converter with floating dc links converters for aircraft applications. His current research interests include EMI
for current waveform improvement,” IEEE Trans. Ind. Electron., vol. 58, prediction, circuit modeling, and high density power converters packaging.
no. 6, pp. 2304–2312, Jun. 2011.
[18] Ó. López, J. Álvarez, J. Doval-Gandoy, and F. D. Freijedo, “Multilevel
multiphase space vector PWM algorithm with switching state redun- Kamal Al-Haddad (S’82–M’88–SM’92–F’07) was
dancy,” IEEE Trans. Ind. Electron., vol. 56, no. 3, pp. 792–804, Mar. 2009. born in Lebanon, in 1954. He received the B.Sc.A.
[19] E. J. Bueno, Á. Hernández, F. J. Rodríguez, C. Girón, R. Mateos, and and M.Sc.A. degrees from the University of Québec
S. Cóbreces, “A DSP- and FPGA-based industrial control with high-speed à Trois-Rivières, Trois-Rivières, QC, Canada, in
communication interfaces for grid converters applied to distributed power 1982 and 1984, respectively, and the Ph.D. degree
generation systems,” IEEE Trans. Ind. Electron., vol. 56, no. 3, pp. 654– from the Institut National Polythechnique, Toulouse,
669, Mar. 2009. France, in 1988.
[20] Ó. López, J. Álvarez, J. Doval-Gandoy, F. D. Freijedo, A. Nogueiras, From June 1987 to June 1990, he was a Pro-
A. Lago, and C. M. Peñalver, “Comparison of the FPGA implementa- fessor with the Engineering Department, Université
tion of two multilevel space vector PWM algorithms,” IEEE Trans. Ind. du Québec à Trois Rivières. Since June 1990, he
Electron., vol. 55, no. 4, pp. 1537–1547, Apr. 2008. has been a Professor with the Electrical Engineering
[21] R. Dubey, P. Agarwal, and M. K. Vasantha, “Programmable logic devices Department, École de Technologie Supérieure (ETS), Montreal, QC, where
for motion control—A review,” IEEE Trans. Ind. Electron., vol. 54, no. 1, he has been the holder of the Canada Research Chair in Electric Energy
pp. 559–566, Feb. 2007. Conversion and Power Electronics, since 2002. He has supervised more than
[22] K. Sun, D. Zhou, L. Huang, K. Matsuse, and K. Sasagawa, “A novel 70 Ph.D. and M.Sc.A. students working in the field of power electronics. From
commutation method of matrix converter fed induction motor drive us- 1992 to 2003, he was the Director of the graduate study programs at the ETS.
ing RB-IGBT,” IEEE Trans. Ind. Appl., vol. 43, no. 3, pp. 777–786, He is a Consultant and has established a very solid link with many Canadian
May/Jun. 2007. industries working in the field of power electronics, electric transportation,
[23] S. Mukherjee, A. Dasgupta, P. Syam, and A. K Chattopadhay, “Imple- aeronautics, and telecommunications. He is the Head of CRC-EECPE, Ecole de
mentation of indirect SVPWM control for a three phase matrix converter technologie supérieure. He is the Chief of the ETS-Bombardier Transportation
using TMS 320LF2407 in combination with FPGA EPIC6Q240C8,” in North America division, which is a joint industrial research laboratory on
Proc. IEEE ICIT Conf., Mumbai, India, 2006, pp. 1442–1447. electric traction system and power electronics. He is also a coauthor of the
[24] M. Hamouda, F. Fnaiech, and K. Al-Haddad, “Space vector modulation Power System Blockset software of Matlab. He has coauthored more than
scheme for dual-bridge matrix converters using safe-commutation strat- 300 transactions and conference proceeding papers. His research interests
egy,” in Proc. IEEE IECON, Raleigh, NC, 2005, pp. 1060–1065. are highly efficient static power electronic converters design; harmonics and
[25] M. Hamouda, F. Fnaiech, and K. Al-Haddad, “Analytical calculation of reactive power control using hybrid filters; active rectifiers and switch-mode
current and voltage stress on power semiconductors of two-stage matrix and resonant converters, including the modeling, control, and development of
converters,” in Proc. IEEE IECON, Orlando, FL, 2008, pp. 561–566. prototypes for various industrial applications in electric traction, power supply
[26] TMS320x281x DSP Event Manager (EV) Reference Guide, Literature for drives, telecommunication, chemical industry, heat induction, lighting,
Number SPRU065C, Nov. 2004. renewable energy converters, etc.
[27] R. Vargas, U. Ammann, J. Rodriguez, and J. Pontt, “Predictive strategy to Dr. Al-Haddad is a Fellow Member of the Canadian Academy of Engineering
control common-mode voltage in loads fed by matrix converters,” IEEE and a Life Member of the Circle of Excellence of the University of Quebec.
Trans. Ind. Electron., vol. 55, no. 12, pp. 4372–4380, Dec. 2008. He is active in the IEEE Industrial Electronics Society, where he is the Vice
[28] M. Aten, G. Towers, C. Whitley, P. Wheeler, J. Clare, and K. Bradley, President for Publication, an AdCom member, and serves as an Associate Editor
“Reliability comparison of matrix and other converter topologies,” IEEE and distinguished lecturer. He is a member of the Order of Engineers of Quebec,
Trans. Aerosp. Electron. Syst., vol. 42, no. 3, pp. 867–875, Jul. 2006. Canada.
[29] [Online]. Available: http://www.xilinx.com/products/boards_kits/spartan.
htm
[30] [Online]. Available: http://www.spectrumdigital.com/index_orig.php? Farhat Fnaiech (M’85–SM’01) was born in
cPath=30_84&osCsid=5f8cb40175a24bdcc9cb7c4b3d1b0207 La Chebba, Tunisia, in 1955. He received the B.Sc.
degree in mechanical engineering, the M.Sc. degree
in electrical engineering, the Ph.D. degree, and the
Mahmoud Hamouda was born in Mahdia, Tunisia, D.Sc. degree from the University of Tunis, Tunis,
in 1972. He received the B.S., Agregation, M.S., and Tunisia, in 1978, 1980, 1983, and 1999, respectively.
Ph.D. degrees in electrical engineering from ENSET He is currently Professor at the Ecole Superieure
and the Ecole Superieure des Sciences et Techniques, des Sciences and Techniques of Tunis. He has pub-
University of Tunis, Tunis, Tunisia, in 1995, 1996, lished More than 200 research papers in many jour-
2004, and 2010, respectively. nals and international conferences. His main interest
He is currently an Assistant Professor of Electrical research areas are nonlinear adaptive signal process-
Engineering at the National Engineering School of ing, nonlinear control of power electronic devises, digital signal processing,
Sousse, University of Sousse, Sousse, Tunisia. He is image processing, intelligent techniques and control.
a member of the research group “SICISI,” ESSTT, Dr. Fnaiech was the General Chairman and member of the international
University of Tunis, and also affiliated with Canada board committee of many international conferences. He is Associate Editor of
Research Chair in Electric Energy conversion and power electronics, “CRC- the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS. He has served as
EECPE,” Ecole de technologie supérieure, Montreal, QC, Canada. His main IEEE chapter committee coordination sub-committee delegate of Africa Region
research interests include modeling and control of static power electronic 8 and Vice Chair of IEEE Tunisia Section. Recently, he has been appointed as
converters using FPGA and DSP devices. an AdCom member in IEEE Industrial Electronics Society.