QM_XC7A35T_DDR3 CORE BOARD

USER MANUAL

Preface

The QMTech® XC7A35T DDR3 core board uses Xilinx Artix®-7 devices to demonstrate the highest
performance-per-watt fabric, transceiver line rates, DSP processing, and AMS integration in a cost -
optimized FPGA. Featuring the MicroBlaze™ soft processor and 1,066Mb/s DDR3 support, the family is the
best value for a variety of cost and power-sensitive applications including software-defined radio, machine
vision cameras, and low-end wireless backhaul.

QM_XC7A35T_DDR3 Core Board User Manual V03

Table of Contents

1. INTRODUCTION ............................................................................................... 3
1.1 DOCUMENT SCOPE ................................................................................ 3
1.2 KIT O VERVIEW ...................................................................................... 3
2. GETTING STARTED........................................................................................... 4
2.1 I NSTALL DEVELOPMENT TOOLS .............................................................. 5
2.2 QM_XC7 A35T_DDR3 H ARDWARE DESIGN ........................................ 6
2.2.1 QM_XC7A35T_DDR3 Power Supply ................................ 6
2.2.2 QM_XC7A35T_DDR3 SPI Boot.......................................... 7
2.2.3 QM_XC7A35T_DDR3 Memory ......................................... 8
2.2.4 QM_XC7A35T_DDR3 System Clock ................................. 8
2.2.5 QM_XC7A35T_DDR3 Extension IO .................................. 9
2.2.1 QM_XC7A35T_DDR3 3.3V Power Supply .....................10
2.2.2 QM_XC7A35T_DDR3 JTAG Po rt .....................................10
2.2.3 QM_XC7A35T_DDR3 User LED .......................................10
2.2.4 QM_XC7A35T_DDR3 User Key .......................................11
3. REFERENCE......................................................................................................12
4. REVISION .........................................................................................................13

QM_XC7A35T_DDR3 Core Board User Manual V03

1. Introduction

1.1 Document Scope

This demo user manual introduces the QM_XC7A35T_DDR3 core board and describes how to setup the
core board running with application software Xilinx Vivado 2018.2. Users may employee the on board rich
logic resource FPGA XC7A35T-1FTG256C and large DDR3 memory MT41J128M16 to implement
various applications. The core board also has 108 non-multiplexed FPGA IOs for extending customized
modules, such as UART module, CMOS/CCD camera module, LCD/HDMI/VGA display module etc.

1.2 Kit Overview

Below section lists the parameters of the QM_XC7A35T_DDR3 core board:
➢ On-Board FPGA: XC7A35T-1FTG256C;
➢ On-Board FPGA external crystal frequency: 50MHz;
➢ XC7A35T-1FTG256C has rich block RAM resource up to 1,800Kb;
➢ XC7A35T-1FTG256C has 33,280 logic cells;
➢ On-Board MT28QL128 SPI Flash, 16M bytes for user configuration code;
➢ On-Board 256MB Micron DDR3, MT41J128M16JT-125:K;
➢ On-Board 3.3V power supply for FPGA by using MP2315 wide input range DC/DC;
➢ XC7A35T development board has two 64p, 2.54mm pitch headers for extending user IOs. All IOs are
precisely designed with length matching;
➢ XC7A35T development board has 2 user switches;
➢ XC7A35T development board has 3 user LEDs;
➢ XC7A35T development board has JTAG interface, by using 6p, 2.54mm pitch header;
➢ XC7A35T development board PCB size is: 6.7cm x 8.4cm;
➢ Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm;

Figure 1-1. QM_XC7A35T_DDR3 Core Board Overview

QM_XC7A35T_DDR3 Core Board User Manual V03

2. Getting Started
The QM_XCA35T_DDR3 core board includes below item:

Figure 2-1. QM_XC7A35T_DDR3 Top View

Below image shows the dimension of the QM_XC7A35T_DDR3 core board: 6.7cm x 8.4cm. The unit in
below image is millimeter(mm).

Figure 2-2. QM_XC7A35T_DDR3 Core Board Dimension

QM_XC7A35T_DDR3 Core Board User Manual V03

2.1 Install Development Tools
The QM_XC7A35T_DDR3 core board tool chain consists of Xilinx Vivado 2018.2, Xilinx USB platform cable,
XC7A35T core board and 5V DC power supply. Below image shows the Xilinx Vivado 2018.2 development
environment which could be downloaded from Xilinx office website:

Figure 2-3. Vivado 2018.2

Below image shows the JTAG connection between Xilinx USB platform cable and XC7A35T core board:

TMS (Green)
TDI (Purple)
TDO (White)
TCK (Yellow)
GND (Black)
VREF (Red)

5V DC

Figure 2-4. JTAG Connection and Power Supply

QM_XC7A35T_DDR3 Core Board User Manual V03

2.2 QM_XC7A35T_DDR3 Hardware Design

2.2.1 QM_XC7A35T_DDR3 Power Supply

The core board needs 5V DC input as power supply which could be directly injected from power header or the 64P
female header U7/U8. Users may refer to the hardware schematic for the detailed design. The on board LED D4
indicates the 3.3V supply, it will be turned on when the 5V power supply is active. In default status, all the FPGA banks
IO power level is 3.3V because bank power supply is 3.3V. However, BANK34 and BANK35 IO’s power level could be
changed according to detailed custom requirement. There’re three 0 ohm resisters could be removed: R223/R224/
R225, and instead the BANK34 and BANK35’s power supply could be injected from 64P female header U8. Detailed
design refer to hardware schematic.
Note: FPGA core supply 1.0V is regulated by On-Semi DC/DC chip NCP1529 which could output maximum 1A
current.
1V8 3V3
U9F
L10 L6
1V8 K11 VCCAUX_0 VCCO_0 3V3
C77 J10 VCCAUX_1 L16 C18
G10 VCCAUX_2 VCCO_14_0 M13
4.7uF VCCAUX_3 VCCO_14_1 N10 4.7uF
10V VCCO_14_2 P7 10V
C79 T16 VCCO_14_3 R14
GND_0 VCCO_14_4 C19 C21
100NF T6 T11 100NF 100NF
C78 R9 GND_1 VCCO_14_5 C20 C22
100NF P12 GND_2 E7 100NF 100NF
P2 GND_3 CFGBVS_0 VCCO_34_35
N15 GND_4 A6
N5 GND_5 VCCO_35_0 B3 VCCO_34_35
M8 GND_6 VCCO_35_1 D7
L11 GND_7 VCCO_35_2 E4 C61 C74
L1 GND_8 VCCO_35_3 F1
K14 GND_9 VCCO_35_4 J2 4.7uF 4.7uF
K6 GND_11 VCCO_35_5 10V 10V
K4 GND_12 M3 C63 C76
J11 GND_13 VCCO_34_0 R4 100NF 100NF
J9 GND_14 VCCO_34_1 T1 C62 C75
H6 GND_15 VCCO_34_2 1V5 100NF 100NF
G13 GND_16 A16
G9 GND_17 VCCO_15_0 B13 1V5
G3 GND_18 VCCO_15_1 C10
F16 GND_19 VCCO_15_2 E14 C53
C28 C29
F10 GND_20 VCCO_15_3 H15
F6 GND_21 VCCO_15_4 J12 4.7uF
100NF 100NF
E9 GND_22 VCCO_15_5 10V
D12 GND_23 F7
D2 GND_24 VCCINT_0 F9 1V0
C15 GND_25 VCCINT_1 G6
C5 GND_26 VCCINT_2 H9 1V0
B8 GND_27 VCCINT_3 J6
A11 GND_28 VCCINT_4 K9
A1 GND_29 VCCINT_5 L8
GND_30 VCCINT_6 C35

G8 E10 4.7uF
1V8 VCCADC_0 VCCBRAM_0 F11 10V
VCCBRAM_1 C36
100NF
C37
G7 F8 100NF
GNDADC_0 VCCBATT_0 1V8

J8
VREFP_0

H7
VREFN_0

H8
XADC is not used!

VP_0

J7
VN_0
XC7A35T-FTG256

Figure 2-5. Power Supply for the FPGA

QM_XC7A35T_DDR3 Core Board User Manual V03

2.2.2 QM_XC7A35T_DDR3 SPI Boot
In default, QM_XC7A35T boots from external SPI Flash, detailed hardware design is shown in below figure.
The SPI flash is using MT25QL128 manufactured by Micron, with 128Mbit memory storage.

3V3 3V3
U2
4.7K R15 FPGA_CSO_B 1 8
nCE VDD
FPGA_DQ1 2 7 FPGA_DQ3 4.7K R234
SO/SIO1 SIO3

C33
4.7K R233 FPGA_DQ2 3 6 FPGA_CCLK
SIO2 SCK

100nF
4 5 FPGA_DQ0
VSS SI/SIO0
MT25QL128

Figure 2-6. SPI Flash

The FPGA boot sequence setting M0:M1:M2 is configured as 1:0:0 which indicates FPGA will boot from SPI
Flash after power on. In default, the jumper J1 is under closed status.

U9A
K7
DXN_0 K8
DXP_0
L9 PROG_B
PROGRAM_B_0
K10 R229 4.7K
INIT_B_0 3V3
H10 FPGA_DONE
DONE_0 J1
M11 R231 1K
M2_0 M10 3V3
M1_0 M9 R230 1K
M0_0 3V3
M7 TMS
TMS_0 L7 TCK
TCK_0 N8 TDO
TDO_0 N7 TDI
TDI_0
XC7A35T-FTG256

Figure 2-7. M0:M1 Hardware Settings

The LED D2 will be turned on after the FPGA successfully loading configuration file from SPI Flash during
power on stage. In this case, LED D2 could be used as FPGA loading status indicator.
3V3

R13
1K

FPGA_DONE
1

D2

Red
2

R25
1K

Figure 2-8. FPGA_DONE Status Indicator

QM_XC7A35T_DDR3 Core Board User Manual V03

2.2.3 QM_XC7A35T_DDR3 Memory
QM_XC7A35T has on board 16bit width data bus, 256MB memory size DDR3 MT41J128M16JT-125:K
provided by Micron. Below image shows the detailed hardware design:
100 ohm s dif f er ent ial t r ace

impedance
Rout ing t op or bot t om

U1

DDR_RESETN T2
DDR_CLK+ RESET#
DDR_CLK+ J7 N3 DDR_A0
DDR_CLK- K7 CK A0 P7 DDR_A1
R2 DDR_CKE K9 CK# A1 P3 DDR_A2
DNP(100R 1%) DDR_CS L2 CKE A2 N2 DDR_A3
DDR_CLK- DDR_RAS J3 CS# A3 P8 DDR_A4
DDR_CAS K3 RAS# A4 P2 DDR_A5
DDR_CS DDR_WE L3 CAS# A5 R8 DDR_A6
WE# A6 R2 DDR_A7
DDR_D0 E3 A7 T8 DDR_A8
R29 DDR_D1 F7 DQ0 A8 R3 DDR_A9
4.7K DDR_D2 F2 DQ1 A9 L7 DDR_A10
DDR_D3 F8 DQ2 A10/AP R7 DDR_A11
DDR_D4 H3 DQ3 A11 N7 DDR_A12
DDR_D5 H8 DQ4 A12/BC# T3 DDR_A13
DDR_RESETN DDR_D6 G2 DQ5 A13 T7
DDR_D7 H7 DQ6 A14 M7
DDR_D8 D7 DQ7 A15 M2 DDR_BA0
R1 DDR_D9 C3 DQ8 BA0 N8 DDR_BA1
4.7K DDR_D10 C8 DQ9 BA1 M3 DDR_BA2
DDR_D11 C2 DQ10 BA2
DDR_D12 A7 DQ11 K1 DDR_ODT
DDR_D13 A2 DQ12 ODT
DDR_D14 B8 DQ13 B2 1V5
DDR_D15 A3 DQ14 VDD1 G7
DQ15 VDD2 R9
DDR_DQS1+ C7 VDD3 K2
DDR_DQS1- B7 UDQS VDD4 K8 C52 C57
UDQS# VDD5 N1 1V5
1V5 DDR_DQS0+ F3 VDD6 N9 4.7uF4.7uF
DDR_DQS0- G3 LDQS VDD7 R1 10V 10V
LDQS# VDD8 D9 C11
DDR_DQM1 D3 VDD9 100NF
C54 C1 DDR_DQM0 E7 UDM A9 C10
LDM VSS1 B3 100NF
4.7uF4.7uF VSS2 E1
10V 10V 1V5 A1 VSS3 G8
A8 VDDQ1 VSS4 J2
C2 VDDQ2 VSS5
100NF C1 J8
C3 C9 VDDQ3 VSS6 M1
100NF D2 VDDQ4 VSS7 M9
E9 VDDQ5 VSS8 P1
F1 VDDQ6 VSS9 P9
1V5 H2 VDDQ7 VSS10 T1
H9 VDDQ8 VSS11 T9
VDDQ9 VSS12
J1 B1
J9 NC1 VSSQ1 B9
L1 NC2 VSSQ2 D1
C17 R7 L9 NC3 VSSQ3 D8
100nF 1K 1% NC4 VSSQ4 E2
DDR_VREF VSSQ5 E8
C32 VSSQ6 F9
100nF DDR_VREF M8 VSSQ7 G1
R8 VREFCA VSSQ8 G9
C34
1K 1% VSSQ9
100nF
DDR_VREF H1 L8
VREFDQ ZQ
R5
C15 C16
100nF 100nF MT41J128M16JT-125:K 240R 1%

Figure 2-9. DDR3

2.2.4 QM_XC7A35T_DDR3 System Clock

FPGA chip XC7A35T-1FTG256C has system clock frequency 50MHz which is directly provided by external
crystal. The crystal is designed with high accuracy and stability with low temperature drift 10ppm/°c. Below
image shows the detailed hardware design:
3V3
R9 4.7K

1 OE VDD 4
50 MHz
C42
100NF
2 VSS OUT 3 SY S_CLK

Y1

SG-8002JC-50.0000M-PCB

Figure 2-10. 50MHz System Clock

QM_XC7A35T_DDR3 Core Board User Manual V03

2.2.5 QM_XC7A35T_DDR3 Extension IO
The core board has two 64P 2.54mm pitch female headers which are used for extending user modules,
such as ADC/DAC module, audio/video module, ethernet module, etc.

U8
1 2
VCCO_34_35 3 4 VCCO_34_35
BANK34/35 Voltage BANK35_B7 5 6 BANK35_A7
7 8
Supply Pins. BANK35_B6
9 10
BANK35_B5
BANK35_E6 BANK35_K5
BANK35_J5 11 12 BANK35_J4
BANK35_G5 13 14 BANK35_G4
BANK35_C7 15 16 BANK35_C6
BANK35_D6 17 18 BANK35_D5
BANK35_A5 19 20 BANK35_A4
BANK35_B4 21 22 BANK35_A3
BANK35_D4 23 24 BANK35_C4
BANK35_C3 25 26 BANK35_C2
BANK35_B2 27 28 BANK35_A2
BANK35_C1 29 30 BANK35_B1
BANK35_E2 31 32 BANK35_D1
BANK35_E3 33 34 BANK35_D3
BANK35_F5 35 36 BANK35_E5
BANK35_F2 37 38 BANK35_E1
BANK35_F4 39 40 BANK35_F3
BANK35_G2 41 42 BANK35_G1
BANK35_H2 43 44 BANK35_H1
BANK35_K1 45 46 BANK35_J1
BANK35_L3 47 48 BANK35_L2
BANK35_H5 49 50 BANK35_H4
BANK35_J3 51 52 BANK35_H3
BANK35_K3 53 54 BANK35_K2
BANK34_L4 55 56 BANK34_M4
BANK34_N3 57 58 BANK34_N2
59 60
61 62
VIN 63 64 VIN
HDR_32X2
Connected to VIN
power header.

U7
1 2
3V3 3 4 3V3
BANK14_M12 5 6 BANK14_N13
BANK14_N14 7 8 BANK14_N16
BANK14_P15 9 10 BANK14_P16
BANK14_R15 11 12 BANK14_R16
BANK14_T14 13 14 BANK14_T15
BANK14_P13 15 16 BANK14_P14
BANK14_T13 17 18 BANK14_R13
BANK14_T12 19 20 BANK14_R12
BANK14_L13 21 22 BANK14_N12
BANK14_K12 23 24 BANK14_K13
BANK14_P10 25 26 BANK14_P11
BANK14_N9 27 28 BANK14_P9
BANK14_T10 29 30 BANK14_R11
BANK14_T9 31 32 BANK14_R10
BANK14_T8 33 34 BANK14_R8
BANK14_T7 35 36 BANK14_R7
BANK14_T5 37 38 BANK14_R6
BANK14_P6 39 40 BANK14_R5
BANK14_N6 41 42 BANK14_M6
BANK34_L5 43 44 BANK34_P5
BANK34_T4 45 46 BANK34_T3
BANK34_R3 47 48 BANK34_T2
BANK34_R2 49 50 BANK34_R1
BANK34_M5 51 52 BANK34_N4
BANK34_P4 53 54 BANK34_P3
BANK34_N1 55 56 BANK34_P1
BANK34_M2 57 58 BANK34_M1
59 60
61 62
VIN 63 64 VIN
HDR_32X2
Connected to VIN
power header.
Figure 2-11. Extension IO

QM_XC7A35T_DDR3 Core Board User Manual V03

2.2.1 QM_XC7A35T_DDR3 3.3V Power Supply
The core board’s 3.3V power supply is using high efficiency DC/DC chip MP2315 provided by MPS Inc. The
MP2315 supports wide voltage input range from 4.5V to 24V. In normal use case, 5V DC power supply is
suggested to be applied on the board. Below image shows the MP2315 hardware design:
3V3 VCCO_34_35

R223 0R
R224 0R
R225 0R

REG ULATED

5V O NLY

3V3 VIN
L6 U11
C5 R238
100nF 20R 5 2
BST IN 4
4.7uH 3
100K

2
C7 22pF

3 6 R10 100K
+

C81 C82 SW EN/SY NC +

C58 1
JP5
R235

47uF100nF 7 C80 100nF 47uF C68 Power_Header_SMT

VCC 100nF

GND
R239 33K 8 1 R237 75K
FB AAM
MP2315

4
R236
33K

Figure 2-12. MP2315 Hardware Design

2.2.2 QM_XC7A35T_DDR3 JTAG Port

The on board JTAG port uses 6P 2.54mm pitch header which could be easily connected to Xilinx USB platform
cable. Below image shows the hardware design of the JTAG port:
3V3
J2
1
2 TCK
3 TDO
4 TDI
5 TMS
6
JTAG

Figure 2-13. JTAG Port

2.2.3 QM_XC7A35T_DDR3 User LED

Below image shows one user LED and 3.3V power supply indicator:
3V3 VCCO_34_35

R131 R218
1K 1K

1 2 BANK35_E6
D3
1 2
D4

Figure 2-14. LEDs

QM_XC7A35T_DDR3 Core Board User Manual V03

2.2.4 QM_XC7A35T_DDR3 User Key
Below image shows the PROGRAM_B key and one user key:

3V3 VCCO_34_35

R228 R221
4.7k 4.7k

PROG_B BANK35_K5

2 2

SW1 SW2

1 1

Figure 2-15. Keys

QM_XC7A35T_DDR3 Core Board User Manual V03

3. Reference
[1] ug470_7Series_Config.pdf
[2] ds181_Artix_7_Data_Sheet.pdf
[3] ug475_7Series_Pkg_Pinout.pdf
[4] n25q_64a_3v_65nm.pdf
[5] MT41J128M16.pdf
[6] MP2315.pdf
[7] NCP1529-D.PDF

QM_XC7A35T_DDR3 Core Board User Manual V03

4. Revision
Doc. Rev. Date Comments
0.1 05/10/2017 Initial Version.
1.0 05/14/2017 V1.0 Formal Release.
2.0 29/01/2019 V2.2 Formal Release.
3.0 14/06/2019 SPI Flash part number changed to MT25QL128.

QM_XC7A35T_DDR3 Core Board User Manual V03