IETE Technical Review

ISSN: 0256-4602 (Print) 0974-5971 (Online) Journal homepage: https://www.tandfonline.com/loi/titr20

Advances in Logic Device Scaling

Anil Kumar Bansal & Abhisek Dixit

To cite this article: Anil Kumar Bansal & Abhisek Dixit (2015) Advances in Logic Device Scaling,
IETE Technical Review, 32:4, 311-318, DOI: 10.1080/02564602.2015.1023372

To link to this article: https://doi.org/10.1080/02564602.2015.1023372

Published online: 13 Apr 2015.

Submit your article to this journal

Article views: 309

View related articles

View Crossmark data

Citing articles: 4 View citing articles

Full Terms & Conditions of access and use can be found at

https://www.tandfonline.com/action/journalInformation?journalCode=titr20
 Advances in Logic Device Scaling
Anil Kumar Bansal and Abhisek Dixit
Integrated Electronic Circuits Group, Department of Electrical Engineering, Indian Institute of Technology Delhi Hauz Khas,
New Delhi 110016, India

ABSTRACT
Major industry trends that have the potential to take logic device scaling to the next level are reviewed in this
article. Contemporary device designs competing for mainstream in future complementary metal oxide semi-
conductor (CMOS) nodes have been discussed. Recent advances in process modules such as gate, channel,
and source/drain are discussed. Impact of these advanced process modules on device performance and
short channel control has been briefly reviewed. Furthermore, status of variability in terms of known as well as
new sources is reviewed. We find the introduction of extreme ultraviolet lithography and 450-mm wafer size as
two upcoming challenges and gate-all-around architecture with Si and III V nanowires as the most natural
extension of existing technology for next CMOS node at 7 nm.
Keywords:
CMOS, FinFET, Logic, Nanowire, Scaling, Variability.

1. INTRODUCTION sub-193-nm optical lithography. As these next genera-

tion lithography tools are still under research and
With increasing penetration of hand-held devices, development, industry is surviving with mostly dou-
such as tablets and cell phones, standby leakage reduc- ble and at times multiple patterning steps using 193-
tion is of utmost importance in integrated circuits (ICs) nm high numerical aperture immersion lithography.
designed for mobile applications. At the same time, Requirement for cumbersome resolution enhancement
device designs for even high performance applica- techniques and optical proximity corrections at these
tions, such as servers, have to achieve standby leakage nodes with 193-nm lithography adds to the process
reduction due to package maximum temperature complexity overhead and further shrinks profit mar-
restrictions. While most of the recent mobile logic gins. The extreme ultraviolet lithography (EUVL) is
designs are on 32- and 28-nm bulk complementary generally considered as the technology to take over
metal oxide semiconductor (CMOS), majority of the from 193-nm immersion lithography, but has been
microprocessors are being fabricated in 22-nm bulk delayed due to a number of critical problems that
and silicon on insulator (SOI)-CMOS. From current remain to be solved. Compared to 193-nm immersion
industry trends, it is evident that a shift from planar lithography, EUVL uses 13.5 nm as exposure wave-
MOSFET device design to multigate FinFETs is near length, requiring the optical path to change from clean
complete at 22- and 14-nm nodes, with 14-nm FinFET- air (in case of 193-nm) to ultra-high vacuum [1].
based designs hitting the market as early as 2016. The
fin-type architecture is well known to have superior Such 15£ reduction in wavelength (from 193 to 13.5 nm)
gate control over the short channel, thereby achieving significantly extends resolution capability. Before
low sub-threshold leakage at short channel lengths as EUVL can be introduced as a manufacturable alterna-
compared to planar MOSFETs. In this paper, logic tive to 193-nm immersion lithography, a number of
device scaling is reviewed and future challenges are critical challenges still need to be resolved: (1) EUV
discussed. This review report is organized in the fol- source power at wafer level needs to be increased by
lowing sub-topics: (1) industry trends, (2) advanced an order to increase throughput for cost feasibility, (2)
devices, (3) gate engineering, (4) source/drain engi- the defect density on the reflective masks has to
neering, (5) channel engineering, and (6) variability. become low enough to yield functional ICs, and (3) the
resist technology needs to further improve to allow
2. INDUSTRY TRENDS successful integration in advanced process flows,
delivering the expected resolution, line edge rough-
As CMOS device is scaled below 22-nm node, pattern- ness (LER), and productivity [1].
ing for some of the process modules such as fin,
gate, and contact to active gets tougher. Primary In addition to shifting from 193-nm to EUVL, a transi-
reason for this added complexity is requirement for tion from 300-mm wafer size to 450-mm is also

IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015 311

 Bansal A K and Dixit A: Advances in Logic Device Scaling

probable due to cost feasibility. The 450-mm transition transconductance in low drain bias regime to sub-
is a great opportunity to reduce the die cost and stimu- threshold slope (SS) in high drain bias regime (gm
late another wave of equipment and manufacturing /SSsat) of relaxed Ge FinFET devices reported to date
innovations. There are many challenges ahead for the [7]. Recently, transition metal dichalcogenides (TMD)
450-mm transition including innovations for tool are emerging as an alternative to silicon material. It is
productivity, uniformity, precision, cost-of-ownership made up of a series of 2D semiconducting layers
reduction, green concept designing tools, and advanced arranged in hexagonal lattice and exhibits a band gap
manufacturing systems. According to the G450C indus- of 1.1 1.2 eV. TMD could be a potential channel mate-
trial roadmap, R&D tools will be ready in 2015. Tools rial for low power digital applications [8]. A new
for IC maker pilot line will be ready in 2016 and tools advanced device which uses polarity control techni-
for high volume manufacturing ready in 2018 [2]. ques to switch between PMOS and NMOS is as shown
in Figure 1. In this ambipolar device, two gates are
3. ADVANCED DEVICES used: a control gate for switching the device on or off
and a polarity gate for switching the device polarity
As the channel length shrinks, the gate loses control of dynamically between n- and p-type. As a result, this
the short channel and a leakage current flows between device shows potential for logic design [9].
source and drain while the MOSFET is in off state.
Scaling of gate dielectric thickness using high-k dielec- For CMOS logic applications, high performance and
trics can control this short channel effect to some extent low power are the two essentials requirements. The
but beyond 22-nm CMOS, it is not enough as the gate tunnel FET (TFET) as shown in Figure 2 is emerging as
cannot control leakage paths which are far from it. a promising choice for benchmarking beyond CMOS
Gate-all-around (GAA) FETs emerged out as a best devices. In a TFET, we arrange semiconducting mate-
candidate for future high performance and low power rial in p i n and n i p configurations. The i stands
logic applications because they have excellent electro- for “intrinsic”, and it corresponds to the maximum
static control of the channel [3,4]. Room temperature resistivity that a semiconductor can have.
electron and hole transport in high performance short
channel silicon nanowire (NW) MOSFETs has been In the off state, a thick energy barrier is formed so that
studied. It has an interesting observation that NW- charge carriers in the source are unlikely to traverse.
PFETs have 25% higher saturation drain current (Ion) By applying a voltage to the transistor gate, it causes
than NW-NFETs. To investigate this, room tempera- the conduction band in the source and the valence
ture transport of electrons and holes in Si NW-MOS- band in the channel to overlap and hence opening up a
FETs with effective diameter and gate length down to tunnelling window for an electron from valence band
8 and 25 nm, respectively, has been analysed. The of source to the conduction band in the channel. TFETs
result shows that holes in Si NW along the h110i direc- should be able to switch with a much smaller voltage
tion have higher thermal velocity and lower conduc- swing than MOSFETs because only enough voltage to
tivity effective mass than electrons [5]. create or remove an overlap of the bands is to be
applied. Since carriers flow due to tunnel phenomenon
Using stress memorization technique through a dis- as compared to thermionic emission, SS below 60 mV/
posable silicon nitride (SiN) on the gate in 10-nm NW decade can be achieved. TFET is particularly a poten-
transistors, significant parasitic reduction and mobility tial device for replacing CMOS as it stands out in both
enhancement has been achieved. In addition, a thin delay and power criteria in NAND and adder circuits
box in this structure offers sufficient body effect and [10]. The drawbacks associated with TFET are low
hence enable threshold voltage (Vt) tuning [6]. To fur-
ther improve the device performance, a high-mobility
semiconductor material is required, such as InGaAs
for n-type and Ge for p-type transistors. In a novel
architecture, Ge p-channel FinFETs were fabricated on
a Si bulk FinFET baseline using aspect-ratio-trapping
(ART) technique. In ART technique during heteroge-
neous epitaxial growth inside trenches, the height to
width ratio of the heterogeneous epitaxy region is
larger than 1.4. Due to this, threading dislocations in
narrow trenches originating from interface will termi-
nate at the shallow trench isolation sidewalls leaving
the top part defect free for device simulations. Results
show that Ge FinFET has the best ratio of Figure 1: Structure of ambipolar silicon NW device.

312 IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015

 Bansal A K and Dixit A: Advances in Logic Device Scaling

Figure 2: Structure of TFET along with energy band dia-

gram in off and on state.

on-state current due to low tunnelling efficiency and

randon variability in device performance due to ran-
dom dopant fluctuation (RDF). It has been reported Figure 3: Junctionless-FET structure (a) on state and (b) off
that dopingless TFET provides immunity to RDF due state.
to absence of dopant atoms and an increase in on-state
current by using strain, high-k dielectric, and narrow an alternative to conventional MOSFETs due to poten-
band gap materials [11]. tial advantages such as higher mobility and lower gate
capacitance. Along with these advantages, JL-FET has
To take advantage of high intrinsic transconductance the drawback of high variability in device performance
in advanced devices, series resistance due to source due to their intrinsic high bulk doping level. Recently,
and drain (S/D) contacts must be low. With raised S/D a number of reports on modelling of the variability of
architecture and optimized silicides, specific contact JL-FETs have been published [13].
resistance can be reduced. However, reduction in the
sheet resistance due to S/D extensions seems more dif- 4. GATE ENGINEERING
ficult to achieve. To have strong short channel control,
shallow extensions are required. Since a decrease in Replacement metal gate (RMG) process, essentially a
junction depth causes increase in sheet resistance, an gate last process, has mostly replaced the gate-first
increase in extension doping concentration is required process since sub-22-nm node. The RMG flow uses
to keep the sheet resistance low. The ultimate goal of gate fill process with low resistance materials on top of
this research has been to realize highly doped shallow work function tuning metal. In these RMG processes,
S/D extensions and hence the junction technology is Ti layer deposited by physical vapour deposition
regarded as a critical issue. Junctionless- FET (JL-FET) served as a suitable wetting layer. A wetting layer is
has been proposed as a solution to this problem. needed for Al to flow into the open spaces to fill the
gates. But the Ti wetting layer should maintain a cer-
JL-FET is considered a “gated resistor” that is identi- tain minimum thickness to provide feasible wettability
fied by the absence of S/D p n junctions as shown in for Al reflow to occur. This minimum thickness pre-
Figure 3 [12]. The turn-on and -off process is accom- vents the Ti layer to go below 25 nm. Therefore, for
plished by body depletion. Current flow in a JL-FET is extreme scaling, i.e. at 25 nm or below Lgate, a novel
controlled by formation of depletion layer induced by Co Al based metal fill scheme was reported [14].
the gate voltage. In the on state, there is a large current Lower resistance with much less variability than con-
flow due to the high doping concentration of channel ventional Ti Al fill was achieved with Co Al fill
region to which surface accumulation current can be option. In addition, it provides matched device charac-
added. In the off state, there is no current flow because teristics and less gate leakage variability than RMG
of the depletion of charge carriers in the channel region gates with Ti Al fill.
due to the work function difference between the gate
material and substrate material together with voltage In advanced CMOS devices, reliability of high-k/
applied at the gate. Also, JL-FET has been reported as metal-gate (HK-MG) emerges out as a key issue.

IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015 313

 Bansal A K and Dixit A: Advances in Logic Device Scaling

Reported results show that when a 150-nm thick TaN In FinFETs, a good sidewall doping is required in S/D
gate layer is deposited on HfO2 dielectric, a peak stress extensions for low resistance. This can be achieved by
of about 3.28 GPa is generated, resulting in significant conventional beamline ion implant (I/I) with large tilt
trap generation in the high-k layer. The graphene gate angles for isolated fins. In real technologies with multi-
electrodes could be an excellent alternative in improv- fin devices, use of large tilt results in implant shadow-
ing reliability of the HK-MG stack [15]. ing by adjacent fins. To eliminate this problem, ion
assisted deposition and doping (IADD) is used which
Challenges in HK-MG devices are equivalent oxide uses simultaneous dopant deposition and knock in. In
thickness scalability with controlled effective work- one of the examples, AsC and AsxHyC ions, which are
function (EWF), gate leakage density (JG), and on the extracted from plasma source, are directed to the
variability and reliability of these scaled devices. In wafer. As shown in Figure 4, ion assisted deposition of
RMG high-k last flow devices, a tight distribution of arsenic and the knock in of this deposited As by ener-
low Vt NMOS for Lgate  35 nm is attained by con- getic AsC are the two main processes of IADD through
trolled EWF metal alloying. Also a low gate resistance which a superior sidewall doping can be achieved
(Rgate) and small Rgate distribution down to 20 25 nm even with low tilt implantation [21]. Another method
critical dimension was achieved with tuned Al liner/ to boost performance of n-FinFETs is by P SiC epitax-
barrier [16]. ial growth on S/D. It provides strain to boost n-FinFET
mobility and drive current. Due to small gate pitch in
Self-aligned contacts emerge as a key aspect to enable 14-nm CMOS and beyond, contact etch stop layer loses
scaling to go below 22-nm technology node. In self- stress efficiency but P-SiC S/D can still maintain
aligned contact process, gate material is recessed past mobility enhancement. Laser annealing and low tem-
planarization. Then a silicon nitride etch stop layer is perature rapid thermal annealing is necessary to retain
deposited and planarized. This is followed by a cap- stress of P SiC epitaxial layer [22].
ping layer deposition prior to contact patterning.
Finally, the contacts are etched selective to the silicon
nitride to avoid gate shorts [17].
6. CHANNEL ENGINEERING
The main emphasis of channel engineering is on
5. SOURCE/DRAIN ENGINEERING improving the channel mobility and quality of the MOS
interface. Among the techniques that are generally used
The on-state channel resistance of MOSFETs has been for improving the channel mobility are strain engineer-
continuously lowered with scaling and strain engi- ing and use of high mobility Ge/III V channel materi-
neering, which has led to external resistance (Rext) as als. In the past decade, strain technology has played a
the dominant component of the series resistance that key role in improving transistor performance. A great
limits MOSFET performance. Main contribution to deal of work has already been done and reported in
Rext is the S/D contact resistance. There are number of this field. Using group IV (C, Si, Ge, and Sn) elements
ways through which this S/D resistance can be han- for stress enhancement is more prevalent as it provides
dled. A new contact technology comprising shallow
co-implantation of Sb, As, and Ge has been proposed.
It greatly reduces the Schottky barrier height (SBH)
and parasitic series resistance for n-FinFET, which
resulted in an increased Ion [18].

The interface resistance (Rco) between the S/D region

and the metal silicide layer is also a critical contribu-
tion to Rext. For future FinFET transistor, metal-inter-
facial layer semiconductor contact technology scales
better than silicides. By inserting an ultra-thin dielec-
tric layer of TiO2 having low conduction band offset
and tunnelling mass (mTunnel) between the metal and
semiconductor interface, lowering of Rco can be
achieved. A record low specific contact resistivity of
9.1£10¡9 ohm-cm2 and low 
SBH of 0.15 eV is achieved
for Ti metal using 10 A thick TiO2-x interlayer [19].
For n-Ge, nC-ZnO interlayer greatly reduces the
specific contact resistance and gives highest current Figure 4: (A) Deposition and (B) knock-in doping process
density [20]. of IADD in fin sidewall.

314 IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015

 Bansal A K and Dixit A: Advances in Logic Device Scaling

low-cost and manufacturable solutions, e.g. FinFET on a removing EWFV. TaSiN has been reported as a suitable
strain relaxed buffer (SRB). For Ge p-FinFET, it was amorphous metal gate due to its thermal stability and
found that SiGe SRB and GeSn S/D could achieve com- suitability for gate-first process. Elimination of EWFV is
pressive longitudinal stress for mobility enhancement. also effective in suppressing variations in gm [29].
In addition, for Ge n-FinFET, mobility of electrons rela-
tive to Si is expected to be 1.1 times on the top surface Random discrete dopant (RDD) distribution seems to
of the fin and 6 times along the fin sidewalls [23]. be a major concern for nano-scaled MOSFETs as it
Hence, this results in the high mobility even for relaxed gave rise to fluctuations in device characteristics. Effect
Ge n-FinFET which can be further enhanced by stress- of RDD in implanted and annealed As atoms on n-type
ers, e.g. GeSn SRB and SiGe S/D. GAA silicon NW transistors have been reported. It was
found that As dopants which diffused into the central
It was also reported that strained Si1¡xGex tri-gate region of the channel, strongly affect the Vt fluctuation
PFET has excellent electrostatic control and hence can of Si NW transistor. Sidewall gate spacer technique is
be a promising candidate for future generations of used to suppress these fluctuations and it is found that
high performance logic applications [24]. Due to small number of As dopants in the channel region is greatly
band gap of Ge and poor gate interface, the cut-off reduced with these spacers as compared to devices
characteristics are still not good. Inserting a GeOx layer without such spacers. As a result, it significantly sup-
between high-k dielectric and strained Ge layers has pressed Vt variations and also reduced off-current
significantly improved both mobility and cut-off char- fluctuations [30]. Also, dependence of width of NW
acteristics of the Ge p-MOSFETs [25]. GeSn PFETs (Wnw) and phonon scattering effect on Ion fluctuation
have emerged out as a probable replacement for Ge (sI/Ion) has been investigated. It is found that sI/Iave
PFETs. GeSn PFETs offer higher hole mobility as com- for Wnw D 5nm is larger than that of Wnw D 3 nm
pared to Ge PFETs. This high mobility is attributed to which can be attributed to the better gate control. For
uniaxial compressive strain in GeSn channel, which phonon scattering two different effects are reported, i.
leads to a significant reduction of hole effective mass e. current enhancement in low-current state and reduc-
[26]. For bulk FinFET, region underneath the fin should tion in high-current state which finally resulted in sup-
be carefully engineered for scalability down to 7 nm pression of Ion fluctuation [31].
and beyond. Placing quantum barrier doped ground
plane under the fin can help improve electrostatics in In 14 nm SOI FinFETs, impact of low drain bias Vt
bulk FinFETs at 7-nm node and beyond [27]. Apart (Vtlin), gm, and Rext variation on the overall effective
from strain engineering, intrinsic channels formed by current (Ieff) variability has been studied. As shown in
III V material can achieve high mobility. InGaAs-based Figure 5, it is found that gm variability is the vital con-
channels are quite popular due to their high channel tributor to Ieff variation. In nFETs, about 30% 40%
mobility. But as body thickness decreases due to scal- variation is from Vtlin which is independent of Nfin.
ing, mobility reduction may take place. To boost the
channel mobility, two boosters are introduced. First, This variation can be reduced by improving fin surface
higher In content InAs channels and second, MOS inter- with methods such as H2 bake [32]. Variability in tran-
face buffers where higher In content layer is sand- sistor performance as a function of number of parallel
wiched between lower In content layer, i.e. In0.3 Ga0.7 NWs is also studied. The performance deteriorates for
As (3 nm)/InAs (3 nm)/In0.3 Ga0.7 As (3 nm) [28]. multiple NWs devices because self-heating becomes
more at higher density of NWs, leading to increased off
7. VARIABILITY current and SS. In multiple NWs, the transfer character-
istics are the summation of the individual NW which
With continuous scaling of CMOS devices, variability resulted in the spread of Vt. This spread in transistor Vt
due to process variations has substantially increased. increases with the number of NWs, which is reflected in
Primary source of variations are the fabrication pro- the degradation of the overall SS of the transistor [33].
cesses for fin and NWs, which mainly include fin pat-
terning and NW size reduction. Some of the dominant Apart from conventional variability sources, such as
sources of mismatch in these nano-devices are RDF, RDF, EWFV, and LER, flicker (1/f) noise variability
LER, and metal gate EWF variability. All of these effects has become a subject of attention and concern for low
lead to variations in the Vt and Ion. EWF variation power analog designs using smaller device geometry.
(EWFV) is the primary source of Vt variations in The effect of halo, bias, and oxide thickness on noise
undoped channel FinFET. EWFV arises due to poly- variability has been reported. It is found that magni-
crystalline metal grains having orientation-dependent tude of noise variation is higher for strong halo as com-
work function. Amorphous metal gates have been pared to a weak halo. Higher noise variation in strong
reported which successfully suppress Vt variation by halo is due to the effect of additional trap density

IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015 315

 Bansal A K and Dixit A: Advances in Logic Device Scaling

ORCID
Anil Kumar Bansal http://orcid.org/0000-0002-6984-2877

REFERENCES
1. K. Ronse, P. De Bisschop, G. Vandenberghe, E. Hendrickx, R.
Gronheid, A. V. Pret, A. Mallik, D. Verkest, and A. Steegen,
“Opportunities and challenges in device scaling by the intro-
duction of EUV lithography,” in Proceedings of the IEEE IEDM,
San Francisco, CA, 2012, pp. 435 8.
2. J. Lin, P. Lin, W.-Y. Ku, M. C. Kelling, G. Akiki, S. Kwon, K. Lee,
W. Collison, S. Chang, R. Cottle, Y.-C. Wang, C. Borst, D. Skil-
bred, F. Robertson, and P. Farrar, “Opportunities and chal-
lenges of the 450mm transition,” in Proceedings of the IEEE
IEDM, Washington DC, 2013, pp. 365 8.
3. V. Subramanian, “Multiple gate field- effect transistors for future
CMOS technologies,” IETE Tech. Rev., Vol. 27, no. 6, pp.
446 54, Nov. 2010.
4. L. Zhanga, S. Wanga, C. Maa, J. Heab, C. Xub, Y. Mab, Y. Yeb,
H. Liangb, Q. Chenb, and M. Chanc, “Gate underlap design for
short channel effects control in cylindrical gate-all-around MOS-
FETs based on an analytical model,” IETE Tech. Rev., Vol. 29,
no. 1, pp. 29 35, 2012.
Figure 5: Relative contribution of the three parameters to 5. A. Majumdar, S. Bangsaruntip, G. M. Cohen, L. M. Gignac, M.
the overall Ieff variability. Guillorn, M. M. Frank, J. W. Sleight, and D. A. Antoniadis,
“Room-temperature carrier transport in high-performance
short-channel Silicon nanowire MOSFETs,” in Proceedings of
which is also present at the S/D edges of the channel in the IEEE IEDM, San Francisco, CA, 2012, pp. 179 82.
addition to channel area. At high gate bias, channel 6. M. Saitoh, K. Ota, C. Tanaka, K. Uchida, and T. Numata,
non-uniformity reduces which minimizes inversion “10 nm-diameter tri-gate silicon nanowire MOSFETs with
enhanced high- field transport and Vth tunability through thin
carrier density variation along the channel and results BOX,” in Proceedings of the Symposium on VLSI Technology,
in lower noise variation. Also at low gate bias, thick Honolulu, HI, Jun. 2012, pp. 11 2.
gate oxides are seen to show higher noise variations 7. M. J. H. van Dal, G. Vellianitis, G. Doornbos, B. Duriez, T. M.
than thin gate oxide devices [34]. Shen, C. C. Wu, R. Oxland, K. Bhuwalka, M. Holland, T. L. Lee,
C. Wann, C. H. Hsieh, B. H. Lee, K. M. Yin, Z. Q. Wu, M. Pas-
slack, and C.H. Diaz, “Demonstration of scaled Ge p-channel
8. CONCLUSION FinFETs integrated on Si,” in Proceedings of the IEEE IEDM,
San Francisco, CA, 2012, pp. 521 4.
Industry trends in advanced logic devices have been dis- 8. J. Kang, D. Sarkar, W. Liu, D. Jena, and K. Banerjee, “A compu-
cussed. It was reported that introduction of EUVL and a tational study of metal- contacts to beyond-graphene 2D semi-
conductor materials,” in Proceedings of the IEEE IEDM, San
transition to 450-mm wafer size are the major leaps that Francisco, CA, 2012, pp. 407 10.
industry may be taking to keep up with economics of 9. M. D. Marchi, D. Sacchetto, S. Frache, J. Zhang, P.-E. Gaillardon,
scales. Among many contenders of mainstream device Y. Leblebici, and G. D. Micheli, “Polarity control in double gate,
for sub-10-nm CMOS nodes, Si and III V NWs-based gate-all-around vertically stacked silicon nanowire FETs,” in
Proceedings of the IEEE IEDM, San Francisco, CA, Dec. 2012,
devices seem the most natural extension of Si FinFET pp. 183 6.
based 10-nm CMOS technology. However, ability of 10. D. E. Nikonov, and I. A. Young, “Uniform methodology for
TFETs to beat the 60-mV/decade minimum sub-thresh- benchmarking beyond- CMOS logic devices,” in Proceedings
old swing barrier is promising and depending upon of the IEEE IEDM, San Francisco, CA, 2012, pp. 573 6.
manufacturing feasibility, TFETs could be a promising 11. M. J. Kumar, and S. Janardhanan, “Doping-less tunnel field
effect transistor: Design and investigation,” IEEE Trans. Elec-
device design for futuristic CMOS nodes. As discussed, tron Devices, Vol. 60, no. 10, pp. 3285 90, Aug. 2013.
various innovations in gate, channel, and S/D engineer- 12. S. Migita, Y. Morita, M. Masahara, and H. Ota, “Electrical per-
ing are required to ensure performance and short chan- formances of junctionless-FETs at the scaling limit (LCH D
nel control. Variability appears to be the decisive factor 3 nm),” in Proceedings of the IEEE IEDM, San Francisco, CA,
2012, pp. 191 4.
in selection of device architecture and process technolo-
13. G. Giusi, and A. Lucibello, “Variability of the drain current in
gies, may ultimately limit further scaling of CMOS junctionless nanotransistors induced by random dopant fluctu-
beyond certain nodes. ation,” IEEE Trans. Electron Devices, Vol. 61, no. 3, pp. 702 6,
Jan. 2014.
Funding 14. U. Kwon, K. Wong, S. A. Krishnan, L. Econimikos, X. Zhang, C.
Ortolland, L. D. Thanh, J.-B. Laloe, J. Y. Huang, L. F. Edge, H.
M. Wang, M. A. Gribelyuk, D. L. Rath, R. Bingert, Y. Liu, R. Bao,
This work is partially supported by Department of Science I. Kim, R. Ramachandran, W. L. Lai, J. Cutler, D. S. Salvador, Y.
and Technology, Government of India SERB [grant no. SB/ Zhang, J. Muncy, V. Paruchuri, M. Krishnan, V. Narayanan, R.
S3/EECE/037/2014]. Divakaruni, X. Chen, and M. P. Chudzik, “A novel low resistance

316 IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015

 Bansal A K and Dixit A: Advances in Logic Device Scaling

gate fill for extreme gate length scaling at 20nm and beyond for O. Richard, H. Bender, S.H. Lee, M. Van Dal, N. Kabir, W.
gate-last high- k/metal gate CMOS technology,” in Proceed- Vandervorst, M. Caymax, N. Horiguchi, N. Collaert, and A.
ings of the Symposium on VLSI Technology, Honolulu, HI, Thean, “Stress simulations for optimal mobility group IV p- and
2012, pp. 29 30. nMOS FinFETs for the 14nm node and beyond,” in Proceed-
15. J. K. Park, S. M. Song, J. H. Mun, and B. J. Cho, “Dramatic ings of the IEEE IEDM, San Francisco, CA, 2012, pp. 131 4.
improvement of high-k gate dielectric reliability by using 24. P. Hashemi, M. Kobayashi, A. Majumdar, L. A. Yang, A. Baras-
mono-layer graphene gate electrode,” in Proceedings of the kar, K. Balakrishnan, W. Kim, K. Chan, S. U. Engelmann, J. A.
Symposium on VLSI Technology, Honolulu, HI, 2012, pp. 31 2. Ott, S. W. Bedell, C. E. Murray, S. Liang, R. H. Dennard, J. W.
16. A. Veloso, Y. Higuchi, S. A. Chew, K. Devriendt, L.-A. Ragnars- Sleight, E. Leobandung, and D.-G. Park, “High - performance
son, F. Sebaai, T. Schram, S. Brus, E. Vecchio, K. Kellens, E. Si1-x Gex channel on insulator trigate PFETs featuring an
Rohr, G. Eneman, E. Simoen, M. J. Cho, V. Paraschiv, Y. implant-free process and aggressively-scaled fin and gate
Crabbe, X. Shi, H. Tielens, A. Van Ammel, H. Dekkers, P. Favia, dimensions,” in Proceedings of the Symposium on VLSI Tech-
J. Geypen, H. Bender, A. Phatak, J. del Agua Borniquel, K. Xu, nology, Hsinchu, Taiwan, 2013, pp. T18 9.
M. Allen, C. Liu, T. Xu, W. S. Yoo, A. Thean, and N. Horiguchi, 25. K. Ikeda, Y. Kamimuta, Y. Moriyama, M. Ono, K. Usuda, M.
“Process control & integration options of RMG technology for Oda, T. Irisawa, K. Furuse, and T. Tezuka, “Enhancement of
aggressively scaled devices,” in Proceedings of the Sympo- hole mobility and cut-off characteristics of strained Ge nano-
sium on VLSI Technology, Honolulu, HI, 2012, pp. 33 4. wire pMOSFETs by using plasma oxidized GeOx inter-layer for
17. C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, gate stack,” in Proceedings of the Symposium on VLSI Tech-
M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, nology, Hsinchu, Taiwan, 2013, pp. T31 2.
W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. 26. X. Gong, G. Han, S. Su, R. Cheng, P. Guo, F. Bai, Y. Yang, Q.
Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Zhou, B. Liu, K. H. Goh, G. Zhang, C. Xue, B. Cheng, and Y.-C.
Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, Yeo, “Uniaxially strained germanium-tin (GeSn) gate-all-around
J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, nanowire PFETs enabled by a novel top-down nanowire forma-
S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. tion technology,” in Proceedings of the Symposium on VLSI
Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, Technology, Hsinchu, Taiwan, 2013, pp. T34 5.
K. Zawadzki, and K. Mistry, “A 22 nm high performance and 27. G. Eneman, G. Hellings, A. De Keersgieter, N. Collaert, and A.
low-power CMOS technology featuring fully-depleted tri-gate Thean, “Quantum-barriers and ground-plane isolation: A path
transistors, self-aligned contacts and high density MIM capaci- for scaling bulk-FinFET technologies to the 7 nm-node and
tors,” in Proceedings of the Symposium on VLSI Technology, beyond,” in Proceedings of the IEEE IEDM, Washington DC,
Honolulu, HI, 2012, pp. 131 2. 2013, pp. 320 3.
18. C.R. Kenney, K.-W. Ang, K. Matthews, M. Liehr, M. Minakais, J. 28. S. Takagi, R. Zhang, S.-H Kim, N. Taoka, M. Yokoyama, J.-K.
Pater, M. Rodgers, V. Kaushik, S. Novak, S. Gausepohl, C. Suh, R. Suzuki, and M. Takenaka, “MOS interface and channel
Hobbs, P. D. Kirsch, and R. Jammy, “FinFET parasitic resis- engineering for high-mobility Ge/III-V CMOS,” in Proceedings
tance reduction by segregating shallow Sb, Ge and As of the IEEE IEDM, San Francisco, CA, 2012, pp. 505 8.
implants at the silicide interface,” in Proceedings of the Sympo-
sium on VLSI Technology, Honolulu, HI, 2012, pp. 17 8. 29. T. Matsukawa, Y. Liu, W. Mizubayashi, J. Tsukada, H. Yamau-
chi, K. Endo, Y. Ishikawa, S.-I. O’uchi, H. Ota, S. Migita, Y.
19. A. Agarwal, J. Lin, B. Zheng, S. Sharma, S. Chopra, K. Wang, Morita, and M. Masahara, “Suppressing Vt and Gm variability
A. Gelatos, S. Mohney, and S. Datta, “Barrier height reduction of FinFETs using amorphous metal gates for 14 nm and
to 0.15 eV and contact resistivity reduction to 9.1£10¡9 V-cm2 beyond,” in Proceedings of the IEEE IEDM, San Francisco, CA,
using ultrathin TiO2¡x interlayer between metal and silicon,” in 2012, pp. 175 8.
Proceedings of the Symposium on VLSI Technology, Hsinchu,
Taiwan, 2013, T200 1. 30. M. Uematsu, K. M. Itoh, G. Mil’nikov, H. Minari, and N. Mori,
“Simulation of the effect of arsenic discrete distribution on
20. P. Paramahans, S. Gupta, R. K. Mishra, N. Agarwal, A. Nainani, device characteristics in silicon nanowire transistors,” in Pro-
Y. Huang, M.C. Abraham, S. Kapadia, U. Ganguly, and S. ceedings of the IEEE IEDM, San Francisco, CA, 2012,
Lodha, “ZnO: An attractive option for n-type metal- interfacial pp. 709 12.
layer-semiconductor (Si, Ge, SiC) contacts,” in Proceedings of
the Symposium on VLSI Technology, Honolulu, HI, 2012, pp. 31. N. Mori, G. Mil’nikov, H. Minari, Y. Kamakura, T. Zushi, T. Wata-
83 4. nabe, M. Uematsu, K. M. Itoh, S. Uno, and H. Tsuchiya, “Nano
device simulation from an atomistic view,” in Proceedings of
21. Y. Sasaki, L. Godet, T. Chiarella, D. P. Brunco, T. Rockwell, J. W. the IEEE IEDM, Washington DC, 2013, pp. 116 9.
Lee, B.Colombeau, M. Togo, S. A. Chew, G. Zschaetszch, K.B.
Noh, A. De Keersgieter, G. Boccardi, M. S. Kim, G. Hellings, P. 32. A. Paul, A. Bryant, T. B. Hook, C. C. Yeh, V. Kamineni, J. B.
Martin, W. Vandervorst, A. Thean, and N. Horiguchi, “Improved Johnson, N. Tripathi, T. Yamashita, G. Tsutsui, V. Basker, T. E.
sidewall doping of extensions by AsH3 ion assisted deposition Standaert, J. Faltermeier, B. S. Haran, S. Kanakasabapathy, H.
and doping (IADD) with small implant angle for scaled NMOS Bu, J. Cho, J. Iacoponi, and M. Khare, “Comprehensive study
Si bulk FinFETs,” in Proceedings of the IEEE IEDM, Washington of effective current variability and MOSFET parameter correla-
DC, 2013, pp. 542 5. tions in 14 nm multi-Fin SOI FINFETs,” in Proceedings of the
IEEE IEDM, Washington DC, 2013, pp. 361 4.
22. M. Togo, J. W. Lee, L. Pantisano, T. Chiarella, R. Ritzenthaler, R.
Krom, A. Hikavyy, R. Loo, E. Rosseel, S. Brus, J. W. Maes, V. 33. S. H. Shin, M. Masuduzzaman, J.J Gu, M. A. Wahab, N.
Machkaoutsan, J. Tolle, G. Eneman, A. D. Keersgieter, G. Boc- Conrad, M. Si, P. D. Ye, and M. A. Alam, “Impact of nanowire
cardi, G. Mannaert, S. E. Altamirano, S. Locorotondo, M. variability on performance and reliability of gate- all-around
Demand, N. Horiguchi, and A. Thean, “Phosphorus doped SiC III-V MOSFETs,” in Proceedings of the IEEE IEDM, Washington
Source Drain and SiGe channel for scaled bulk FinFETs,” in DC, 2013, pp. 188 91.
Proceedings of the IEEE IEDM, San Francisco, CA, 2012, pp. 34. P. Srinivasan and S. Dey, “New and critical aspects of 1/f
423 6. noise variability in advanced CMOS SoC technologies,” in Pro-
23. G. Eneman, D.P. Brunco1, L. Witters, B. Vincent, P. Favia, A. ceedings of the IEEE IEDM, San Francisco, CA, 2012,
Hikavyy, A. De Keersgieter, J. Mitard, R. Loo, A. Veloso, pp. 458 61.

IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015 317

 Bansal A K and Dixit A: Advances in Logic Device Scaling

Authors
Anil Kumar Bansal received his MTech Abhisek Dixit is an assistant professor in the
degree from the National Institute of Technol- Department of Electrical Engineering at IIT
ogy Hamirpur, India in 2013. He has been a Delhi, India. He works on design, modelling,
PhD student at Indian Institute of Technology processing and characterization of CMOS and
(IIT) Delhi, India since January 2014. His solar cell devices. Prior to joining IIT Delhi, he
research interests include sub-10nm logic worked at IBM Semiconductor Research and
CMOS device design and characterization. Development Center (SRDC) for more than
6 years as a senior technical leader in enable-
E-mail: eez138521@ee.iitd.ac.in
ment and TCAD groups. Before IBM, he
worked at International Microelectronics Center (IMEC) Leuven in
CMOS device integration group for 5 years and got a PhD degree
from Katholieke University of Leuven, Belgium in 2007. He got an
MTech. from IIT Bombay in 2002. He has 6 US patents and more than
40 publications in apex international conferences and journals. He is
a senior member of IEEE.
E-mail: adixit@ee.iitd.ac.in

DOI: 10.1080/02564602.2015.1023372; Copyright © 2015 by the IETE

318 IETE TECHNICAL REVIEW | VOL 32 | NO 4 | JUL AUG 2015