Voltage Drop Mitigation by Adaptive Voltage

Scaling using Clock-Data Compensation

Andrés Malavasi-Mora1 and Renato Rimolo-Donadio2
1
Intel Labs, Hillsboro, Oregon 97124, USA. andres.f.malavasi@intel.com
2
Instituto Tecnológico de Costa Rica, 30101 Cartago, Costa Rica. rimolo@tec.ac.cr

Abstract— High-frequency power supply noise compromises

performance and energy efficiency of microprocessor-based
products, restricting the maximum frequency of operation for
electronic systems and decreasing device reliability. A guard band
needs to be set in order to tolerate voltage drops without having
any execution problem but leading to a performance reduction.
This work proposes a technique to enhance voltage drop tolerance
through adaptive scaling, taking advantage of the clock-data
compensation effect. The proposed solution is validated with test
cases in a FinFet CMOS technology at a post-layout simulation
level, reaching from 6% up to 30% more voltage drop tolerance.

Index Terms—Adaptive voltage scaling, clock-data

compensation, CMOS circuit, power noise, voltage drop. Fig. 1. Illustration of clock-data non-ideal effects: (a) simple clock and data
path pipeline, (b) voltage drop event with ideal clock, (c) voltage drop event
I. INTRODUCTION with a non-ideal clock.
High-frequency supply voltage (VCC) drop degrades the
In traditional analysis, the clock period is assumed constant
performance and energy efficiency of microprocessor products, while only the data path delay is assumed to change under the
limiting the maximum frequency (fmax) of operation for influence of supply noise. Fig. 1(b) illustrates example
electronic systems such as microprocessors [1]. Supply noise waveforms based on the traditional analysis showing several
caused by on-chip current introduces delay variation in data sampling failures during the event of a supply voltage
paths, as well as jitter in clock paths. As a result, the launched undershoot. In reality, however, the clock path delay is also
data from one stage in a pipeline can no longer be guaranteed modulated by the supply noise and therefore stretches the clock
to be captured by the next clock edge within a given timing period during supply downswings. As a result, the clock path
window, leading to a timing failure. This is why a guard band delay and data path delay compensate for each other, which
needs to be set in order to tolerate voltage drops without having alleviates the timing margin. Fig. 1(c) depicts example
any execution problem but leading to a performance penalty. waveforms for this scenario. This clock period modulation
Several adaptive circuit techniques have been reported in the effect results in an extra timing margin that compensates for the
literature (e.g. [2]-[4]) aiming to reduce the effect of the voltage slowdown in the data path.
drops by explicitly sensing the variation with on-die monitors Using this idea, adaptive clock distribution (ACD) along
and adjusting the operating condition. Although this is effective with clock gating techniques have become an interesting
at low frequencies, the chances to mitigate high frequency drop solution to mitigate the effect of voltage drop on
are very limited. Other techniques like resilient timing-error microprocessor performance [1]. These techniques take
detection and recovery circuits [5]-[8] can be very useful since advantage of the clock-data compensation effect, in which both
they detect the timing violation, isolates the error from clock and data are affected by the drop: changing the clock
corrupting the architecture state, and corrects the error through signal compensates changes on data paths. Nevertheless, clock
instruction replay. However, the architectural design gating can bring synchronization problems between blocks.
complexity for implementing error recovery into a high- This work evaluates a different approach to address this
performance microprocessor while ensuring coverage for all problem by proposing an adaptive and scalable technique to
failure scenarios is a significant challenge. enhance voltage drop tolerance in CMOS circuits through
It is possible to enhance fmax immunity to power supply adaptive voltage scaling, taking advantage of the clock-data
noise by designing the clock distribution such that the compensation effect without doing any clock gating o
clock edge sampling the data at the receiver is pushed out frequency reduction. The proposed solution is explained and
every time the data signal is delayed due to power supply validated by applying it to different scenarios, considering
drop [9]. This effect is known as “Clock-Data process corners and diverse operating conditions in a FinFet-
Compensation” (CDC) and it is illustrated in Fig. 1; a CMOS technology. Finally, layout solutions and their
simple pipeline circuit consisting of a phase-locked loop evaluation were incorporated in order to improve confidence on
(PLL), a clock path and a data path is shown. the results with the proposed technique.

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 II. CLOCK TREE AND CDC IMPACT ON THE CRITICAL PATH earlier. When there is not enough compensation like in clk30,
the circuit tents to fail earlier with a higher voltage level (15
This section evaluates the effect of the clock-data mV higher). The paths with no compensation or clk30, fail even
compensation (CDC) when a voltage drop arises. The focus is in the second order drop, which has less voltage drop compare
on high-frequency voltage drops, since available literature on to the first order drop.
this topic indicates that the resonant supply noise typically lies
in the 50-300MHz range with a maximum magnitude of
approximately 10% of VCC [10]. The configuration under study
is depicted in Fig. 2.
The purpose of having a tunable data path is to mimic the
different timing paths present in a design, which can be slow,
medium or fast delay paths. Also, an error signal is generated
when the data is not captured correctly at the output flip-flop.
Choosing the clock tree length to have the optimum delay for
the critical path in a circuit is a key task to maximize the benefit Fig. 2. High level schematic for DUT built with a clock tree, launching and
of the clock-data compensation effect. For extremely long or receiving flip-flops, a tunable data path and error signal generation.
short clock path delays, the slack considering the beneficial
jitter effect (i.e. noisy clock supply) approaches the
conventional analysis case (i.e. clean clock supply). A very
short clock path makes the clock period modulation effect
weaker, and conversely, in very long clock paths each clock
edge will see a similar average supply voltage.
The impact of adding different stages (clock buffers) to the
clock tree will give a better picture of the sensitivity of the clock
path, meaning the ratio of the increase in the path delay
normalized to the percentage decrease in the supply voltage
under a supply noise condition.
Fig. 3 illustrates how the clock period changes during the
voltage drop depending on its length. On Fig. 3(a), the voltage
drop is present, then the maximum drop occurs at 52.5 ns, which
corresponds to 100MHz frequency. The voltage level at this
point is ~587mV, which corresponds to ~10% voltage drop. On
Fig. 3(b), the clock period change on different clock trees is
displayed, where the impact of adding 30, 100, and 190 stages
to the clock path is shown.
It is notorious that the biggest change is given by the clock
Fig. 3. Impact of voltage drop on clock period: (a) voltage supply; (b) clock
with 190 stages (clk190). This clock tree stretches up to a 561ps period measurement for different clock lengths.
clock period (61ps extra clock period) but compresses about
35ps when the drop is recovering. The next stretching
corresponds to clk100 that is about 40ps stretching and 25ps
compressing. Finally, for clk30, the clock tree has a very short
clock path, making the clock period modulation effect weaker.
Regarding timing of the path, the slack changes depending
on the different clock lengths. The clock of 190 stages presents
the lesser slack change due to the CDC effect, dropping up to
-50ps, which is greater than the most affected path driven by the
clock tree (-75ps slack) without any compensation. As the
clock length increase, the lesser the slack reduction the circuit
is going to have.
The slack presents the biggest change during the first order
drop, in the subsequence drops the slacks varies but less than
the first drop. For example, for the second order voltage drop,
the slack in the circuit when there is not any compensation falls
up to -10 ps, causing a new failure in the circuit. For the clock
of 190 stages due to the compensation, the slack remains
positive avoiding any failure in the circuit.
Fig. 4 shows the behavior of the error signal; for the clk190
path, it fails until the voltage reaches its lowest value, and in the
rest of the cases (with smaller clock tree), the circuit fails Fig. 4. Error signal for 30, 100 and 190 clock buffers in the clock tree. Error
signal occurs later when having more CDC effect.

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 III. PROPOSED VOLTAGE DROP MITIGATION SCHEME

The proposed solution is depicted in Fig. 5. It is assumed that

the system has a load, which can be certain part of a chip that
can experience fluctuations in the voltage supply due to changes
in the surrounding circuitry. The variable load will represent
these changes through an increase or decrease of the current
consumption. The voltage droop monitor (VDM) senses the
supply voltage level and capture these fluctuations. Based on a
voltage threshold and the supply voltage, will send information
to the voltage controller, which can vary the resistance seen by
the power supply and inject more charge to the system.
The VDM (Fig. 6) constantly checks if the nearby Vcc_exp
value crosses a programmable drop threshold, and if so, the
associated drop controller turns on the local PG (power gate) Fig. 5. Block diagram for the regulated system with a voltage comparator,
block to inject a local charge from a clean power supply voltage controller, and current regulation block in a variable load system with
(Vcc_hi) to Vcc_exp and restores the voltage quickly (very a power grid model.
similar to [2]). The block features a time-to-digital converter
(TDC). This block is used to measure the voltage drop in the
system. The tunable length delay block performs an “offset” for
the TDC, in case we need to overcome any timing issues
between the clock and the TDC at the time to test the circuit.
However, the delay to measure cannot be greater than the offset
plus the resolution of the TDC, in such case we need either to
decrease the offset or add more stages to the VDM. The
threshold selector allows to adjust the voltage threshold
externally (assuming this technique gets prototyped) depending
of the critical path timing slack by changing the input code for
the controller.
The voltage controller manages the current injection based
on a user defined threshold and the VDM code (thermometer
code coming from the TDC) and its previous value. It can
determine if the system is experiencing a voltage drop or not.
Since both values present and past of the voltage are an input to
the controller, the voltage controller can determine if the drop Fig. 6. Voltage Drop Monitor (VDM) block diagram.
is going down or up.
When the voltage exceeds the threshold and its going down,
the voltage controller will inject more current to the system
through the current injection block. On the other hand, if the
voltage is exceeding the threshold but is going up, this means
the voltage is recovering then in order to save power will turn
off the current injection block.
The VDM allows having a multi-threshold operation plus
voltage drop direction detection, in which the controller can
react depending on the voltage level. In order to have a better
performance of the VDM, the clock source needs to be isolated
from the system clock; otherwise, the VDM will be affected by
the CDC effect, causing an inaccurate code when a voltage drop
is occurring. The proposed VDM comes with an extra area
overhead of 360 μm2 for the studied case.
Fig. 7 shows how PG size can be swept, in order to find the
minimum size to avoid any overdesign in mitigation scheme.
Having more PGs than necessary translates to extra area and
leakage power consumption. The minimum PG number to
inject enough charge to the system in order to star recovering Fig. 7. PG size sweep for the current regulation block optimizing the minimum
the voltage was six in the evaluated scenario. numbers of PGs needed to start injecting enough charge to the circuit to
overcome voltage drop.

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 IV. RESULTS V. CONCLUSIONS
In this section, the results are based on post-layout simulations, This work proposed an alternative to enhance voltage drop
where a non-regulated system is being compared to the tolerance in digital circuits by exploiting the CDC effect using
proposed technique, analyzing the voltage drop tolerance a second order power grid model. An in-situ adjustable
(guard band reduction) of both circuits, which translates to a threshold voltage drop monitor (VDM) was developed to detect
higher tolerance of an extra current variation event. Also, the and react to the voltage drop in a fast way. The post-layout
performance improvement is shown, where both systems are simulations show a 10% (slow path), 16% (medium delay path)
under the same current variation event, finding their maximum and 32.5% (fast path) extra current tolerance improvement in
operating frequency. This comparison was performed for the circuit using the proposed scheme compared to a circuit
different timing paths, where the voltage threshold can be without it. Additionally, it shows 6.2% (slow path), 6.2%
adjusted according to the most critical path. The fast path (medium delay path) and 22.4% (fast path) frequency
corresponds to 72% of the clock period, the medium path is improvement in the circuit using the voltage drop mitigation
78%, and finally the slow path is 90% of the clock period. scheme in comparison to the reference case without it.
Table I summarizes iso-frequency test for all the different paths, The response of the VDM is limited by its maximum
and the amount of extra current variation (ǻI) the system can operating frequency, which was 770 MHz in this study. This
tolerate comparing both proposed technique and the baseline limits the voltage controller reaction if the load frequency is
system, which is the non-regulated (NR system). In Table II, much higher than this, and its response to low voltages, since it
the summary corresponds to the fmax improvement under iso- can be a misread of the voltage code, causing potential incorrect
current variation conditions, finding the maximum operating behaviors of the voltage controller.
frequency of the NR system when the current variation is the
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