Integrated Logic

Analyzer v6.1

LogiCORE IP Product Guide

Vivado Design Suite

PG172 April 6, 2016
Table of Contents
IP Facts

Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 2: Product Specification

Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 3: Designing with the Core

Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 4: Design Flow Steps

Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 5: Example Design

Directory and File Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chapter 6: Test Bench

Appendix A: Verification, Compliance, and Interoperability

Appendix B: Migrating and Upgrading

Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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 Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Appendix D: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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 IP Facts

Introduction LogiCORE IP Facts Table

Core Specifics
The customizable Integrated Logic Analyzer UltraScale+™ Families,
Supported
(ILA) IP core is a logic analyzer that can be used Device Family(1)
UltraScale™ Architecture, Zynq®-7000 All
to monitor the internal signals of a design. The Programmable SoC, 7 Series

ILA core includes many advanced features of Supported User

IEEE Standard 1149.1 – JTAG
Interfaces
modern logic analyzers, including boolean
Resources Performance and Resource Utilization web page
trigger equations and edge transition triggers.
Because the ILA core is synchronous to the Provided with Core
design being monitored, all design clock Design Files N/A
constraints that are applied to your design are Example Design Verilog
also applied to the components of the ILA core. Test Bench VHDL and Verilog
Constraints File XDC
Simulation
Not Provided
Features Model
Supported
Not Provided
S/W Driver
• User-selectable number of probe ports and
Tested Design Flows(2)
probe_width
Design Entry Vivado® Design Suite
• Multiple probe ports, which can be Simulation Not Provided
combined into a single trigger condition Synthesis(3) Vivado Synthesis

• AXI interface on ILA IP core to debug AXI IP Support

cores in a system Provided by Xilinx at the Xilinx Support web page

For more information about the ILA core, see Notes:

1. For a complete list of supported devices, see the Vivado
the Vivado ® Design Suite User Guide: IP catalog.
Programming and Debugging (UG908) [Ref 1]. 2. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
3. The standard synthesis flow for Synplify is not supported
for the core.

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 Chapter 1

Overview

Feature Summary
Signals in the FPGA design are connected to ILA core clock and probe inputs (Figure 1-1).
These signals, attached to the probe inputs, are sampled at design speeds and stored using
on-chip block RAM (BRAM). The core parameters specify the number of probes, trace
sample depth, and the width for each probe input. Communication with the ILA core is
conducted using an auto-instantiated debug core hub that connects to the JTAG interface
of the FPGA.
X-Ref Target - Figure 1

,/$&RUH

FON WULJBRXW
WULJBLQ WULJBLQBDFN
WULJBRXWBDFN 6ORWBB$;,
SUREH
SUREH

SUREH

;

Figure 1-1: ILA Core Symbol

Note: The numerical range from probe3 to probe1022 is indicated by ellipses (...) in Figure 1-1.

After the design is loaded into the FPGA, use the Vivado ® logic analyzer software to set up
a trigger event for the ILA measurement. After the trigger occurs, the sample buffer is filled
and uploaded into the Vivado logic analyzer. You can view this data using the waveform
window.

Regular FPGA logic is used to implement the probe sample and trigger functionality.
On-chip block RAM memory stores the data until it is uploaded by the software. No user
input or output is required to trigger events, capture data, or to communicate with the ILA
core.

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 Chapter 1: Overview

ILA Probe Trigger Comparator

Each probe input is connected to a trigger comparator that is capable of performing various
operations. At run time the comparator can be set to perform = or != comparisons. This
includes matching level patterns, such as X0XX101. It also includes detecting edge
transitions such as rising edge (R), falling edge (F), either edge (B), or no transition (N). The
trigger comparator can perform more complex comparisons, including >, <, ≥ , and ≤ .

IMPORTANT: Note that the comparator is set at run time through the Vivado logic analyzer.

ILA Trigger Condition

The trigger condition is the result of a Boolean "AND" or "OR" calculation of each of the ILA
probe trigger comparator result. Using the Vivado logic analyzer, you select whether to
"AND" probe trigger comparators probes or "OR" them. The "AND" setting causes a trigger
event when all of the ILA probe comparisons are satisfied. The "OR" setting causes a trigger
event when any of the ILA probe comparisons are satisfied. The trigger condition is the
trigger event used for the ILA trace measurement.

Applications
The ILA core is designed to be used in any application that requires verification or
debugging using the Vivado logic analyzer.

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 Chapter 1: Overview

Licensing and Ordering Information

This Xilinx ® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado
Design Suite under the terms of the Xilinx End User License.

Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information about pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.

License Checkers
If the IP requires a license key, the key must be verified. The Vivado design tools have
several license checkpoints for gating licensed IP through the flow. If the license check
succeeds, the IP can continue generation. Otherwise, generation halts with error. License
checkpoints are enforced by the following tools:

• Vivado synthesis
• Vivado implementation
• Bitstream generation

IMPORTANT: IP license level is ignored at checkpoints. The test confirms a valid license exists. It does
not check IP license level.

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 Chapter 2

Product Specification

Performance
The ILA core can be configured to Select 1,024 probes each of width ranging from 1 to
4,096. This probe ports should be connected to user design signals which needs to be
monitored in Vivado ® logic analyzer during the run time.

Resource Utilization
For full details about performance and resource utilization, visit the Performance and
Resource Utilization web page.

Port Descriptions
ILA Ports and Parameters
Table 2-1 and Table 2-2 provide the details about the ILA ports and parameters.

Table 2-1: ILA Ports

Port Name I/O Description
clk I Design clock that clocks all trigger and storage logic.
Probe port input. The probe port number <n> is in the range from 0 to 1,023. The
probe<n>[<m> – 1:0] I probe port width (denoted by <m>) is in the range of 1 to 4,096.
You must declare this port as a vector. For a 1-bit port, use probe<n>[0:0].
The trig_out can be generated either from trigger condition or from an external
trig_out O trig_in port. There is a run time control from the Logic Analyzer to switch between
trigger condition and trig_in to drive trig_out. See Figure 1-1.
Input trigger port used in process based system such as Zynq-7000 AP SoC for
trig_in I Embedded Cross Trigger. Can be connected to another ILA to create cascading
Trigger.

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 Chapter 2: Product Specification

Table 2-1: ILA Ports

Port Name I/O Description
trig_out_ack I An acknowledgment to trig_out.
trig_in_ack O An acknowledgment to trig_in.

Table 2-2: ILA Parameters(1)

Default
Parameter Name Allowable Values Description
Value
String with A–Z, 0–9, and _
Component_Name ila_0 Name of instantiated component.
(underscore)
C_NUM_OF_PROBES 1–1,024 1 Number of ILA probe ports.
Probe storage buffer depth. This number
1,024, 2,048, 4,096, 8,192,
represents the maximum number of samples
C_DATA_DEPTH 16,384, 32,768, 65,536, 1,024
that can be stored at run time for each probe
131,072
input.
Width of probe port <n>. Where <n> is the
C_PROBE<n>_WIDTH 1–4,096 1
probe port having a value from 0 to 1,023.
Enables the trig out functionality. Ports trig_out
C_TRIGOUT_EN True/False FALSE
and trig_out_ack are used.
Enables the trig in functionality. Ports trig_in
C_TRIGIN_EN True/False FALSE
and trig_in_ack are used
Add extra flops to the probe ports. One
C_INPUT_PIPE_STAGES 0–6 0
parameter applies to all of the probe ports.
Enable the Capture (Storage) Qualifier. By
enabling this you can specify the capture
condition in Vivado Logic Analyzer thus
capture the probes selectively.
C_EN_STRG_QUAL 0, 1 0 This takes one extra compare values (match)
unit. This means if advance trigger
(C_ADV_TRIGGER) option is enabled, the
maximum number of match units per probes
reduces to three from four.
Enables the advance trigger option. This
enables trigger state machine and you can
C_ADV_TRIGGER True/False FALSE
write your own trigger sequence in Vivado
Logic Analyzer.
This forces the same compare value units
ALL_PROBE_SAME_MU True/False TRUE
(match units) to all of the probes.
Number of Compare Value (Match) units per
C_PROBE<n>_MU_CNT 1–16 1 probe. This is valid only if
ALL_PROBE_SAME_MU is FALSE.

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 Chapter 2: Product Specification

Table 2-2: ILA Parameters(1) (Cont’d)

Default
Parameter Name Allowable Values Description
Value
DATA To choose a selected probe for specifying
DATA and TRIGGER,
C_PROBE<n>_TYPE and trigger condition or for data storage purpose
TRIGGER, DATA
TRIGGER or for both.

Notes:
1. The maximum number of compare value (match) units are limited to 1,024. For the basic trigger (C_ADV_TRIGGER = FALSE),
each probe has one compare value unit (as in the earlier version). But for the advance trigger option (C_ADV_TRIGGER =
TRUE), this means the individual probes can still have possible selection of number of compare values units from one to four.
But all of the compare value units cannot exceed more than 1,024. This also means if you need four compare units per probe
then you are allowed to use only 256 probes.

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 Chapter 3

Designing with the Core

This chapter includes guidelines and additional information to facilitate designing with the
core.

Clocking
The clk input port is the clock used by the ILA core to register the probe values. For best
results, it should be the same clock signal that is synchronous to the design logic that is
attached to the probe ports of the ILA core.

Resets
ILA can only be reset using the Vivado ® logic analyzer.

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 Chapter 4

Design Flow Steps

This chapter describes customizing and generating the core, constraining the core, and the
simulation, synthesis and implementation steps that are specific to this IP core. More
detailed information about the standard Vivado® design flows and the Vivado IP integrator
can be found in the following Vivado Design Suite user guides:

• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
[Ref 3]
• Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2]
• Vivado Design Suite User Guide: Getting Started (UG910) [Ref 4]

Customizing and Generating the Core

This section includes information about using Xilinx ® tools to customize and generate the
core in the Vivado Design Suite.

If you are customizing and generating the core in the IP integrator, see the Vivado Design
Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 3] for detailed
information. IP integrator might auto-compute certain configuration values when
validating or generating the design. To check whether the values change, see the
description of the parameter in this chapter. To view the parameter value, run the
validate_bd_design command in the Tcl console.

You can customize the IP for use in your design by specifying values for the various
parameters associated with the IP core using the following steps:

1. Select the IP from the IP catalog.

2. Double-click the selected IP or select the Customize IP command from the toolbar or
right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2] and
the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 4].

Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment. This
layout might vary from the current version.

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 Chapter 4: Design Flow Steps

To access the core name, perform the following:

1. Open a project by selecting File then Open Project or create a new project by selecting
File then New Project in Vivado.
2. Open the IP catalog and navigate to any of the taxonomies.
3. Double-click ILA to bring up the core name Vivado IDE.

General Options Panel

Figure 4-1 shows the General Options tab in the Native setting that allows you to specify
the options.
X-Ref Target - Figure 4-1

Figure 4-1: General Options Panel – Native Monitor Type

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 Chapter 4: Design Flow Steps

Figure 4-2 shows the General Options tab in the AXI setting that allows you to specify the
options.
X-Ref Target - Figure 4-2

Figure 4-2: General Options Panel – AXI Monitor Type

• Component Name – Use this text field to provide a unique module name for the ILA
core.
• Monitor Type – This option specifies which type of interface ILA should be debugging.
Currently the values for this parameter are "native" and "AXI."
• C_NUM_MONITOR_SLOTS (Only available in AXI type) – This option allows you to
select the number of AXI interface slots that needs to be connected to the ILA. For
2014.1 to currently, only one slot is supported for the ILA.
• Number of Probes – Use this text field to select the number of probe ports on the ILA
core. The valid range used in the Vivado IDE is 1 to 64. If you need more than 64 probe
ports, you need to use the Tcl command flow to generate the ILA core.

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 Chapter 4: Design Flow Steps

• Sample Data Depth – Select the suitable sample depth from the drop-down menu.

° Trigger Out Port – Check to enable the optional trigger out port.

° Trigger In Port – Check to enable the optional trigger in port.

• Input Pipe Stages – Select the number of registers you want to add for the probe. This
parameter applies to all of the probes.
• Storage Qualification – Check to enable the qualifier for the trace capture.
• Advanced Trigger – Check to enable the state machine-based trigger sequencing.
• Same No. of Comparators for all Probes – Check to enable the same number of
comparators for all the enabled ports and interfaces. This IP version allows you to use
this option in both Basic and Advanced Trigger modes.
• No. of Comparators – Select to enable the number of comparators that applies to all
enabled probes. In this IP version, the number of comparators limit is increased to 16
per probe. The number of comparators can now be set to any number from 1 to 16 in
both Basic and Advanced Trigger modes.

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 Chapter 4: Design Flow Steps

Probe Port Panels

Figure 4-3 shows the Probe Ports tab that allows you to specify the settings.
X-Ref Target - Figure 4-3

Figure 4-3: Probe Ports Panel

• Probe Port Panels – Width of each Probe Port can be configured in Probe Port Panels.
Each Probe Port Panel has up to seven ports.

Also, number of comparator per probe can be configured on this panel. This option
appears only when Advanced Trigger option is selected and the Same No. of
Comparator for all Probes is disabled on the first page of Vivado IDE.

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 Chapter 4: Design Flow Steps

Monitor Interface0 Panel

Figure 4-4 shows the Monitor Interface0 tab that allows you to specify the settings.
X-Ref Target - Figure 4-4

Figure 4-4: Monitor Interface0 Panel

• C_ENABLE_AXI_MON – Enables AXI monitor in the ILA IP core. This option allows you
to debug designs with AXI interface at interface level.
• C_SLOT_0_AXI_ARUSER_WIDTH – Default value is always 1 (Not shown in the AXI Read
Address Channel User Width of the Vivado IDE).
• C_SLOT_0_AXI_RUSER_WIDTH – Default value is always 1 (Not shown in the AXI Read
Channel User Width of the Vivado IDE).
• C_SLOT_0_AXI_AWUSER_WIDTH – Default value is always 1 (Not shown in the AXI
Write Address Channel User Width of the Vivado IDE).

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 Chapter 4: Design Flow Steps

• C_SLOT_0_AXI_WUSER_WIDTH – Default value is always 1 (Not shown in the AXI Write

Channel User Width of the Vivado IDE).
• C_SLOT_0_AXI_BUSER_WIDTH – Default value is always 1 (Not shown in the AXI Write
Response Channel User Width of the Vivado IDE).
• C_SLOT_0_AXI_ID_WIDTH – AXI ID Width. Valid range is from 1 to 32 (Shown in the
Vivado IDE).
• C_SLOT_0_AXI_DATA_WIDTH – AXI data width. Valid values are 32, 64, 128, 256, 512,
and 1,024 (Shown in the Vivado IDE).
• C_SLOT_0_AXI_ADDR_WIDTH – AXI address width. Valid range is from 1 to 32 (Shown
in the Vivado IDE).
• C_SLOT_0_AXI_PROTOCOL – AXI interface protocol. AXI protocols supported are AXI3,
AXI4, AXI4-Lite, and AXI-Stream (AXIS).
• C_SLOT_0_AXIS_TDATA_WIDTH – AXIS data width. Valid values are 8, 16, 32, 64, 128,
256, 512, and 1,024.
• C_SLOT_0_AXIS_TID_WIDTH – AXIS ID width. Valid range is from 1 to 32.
• C_SLOT_0_AXIS_TUSER_WIDTH – AXIS user width. Valid range is from 0 to 1,024.
• C_SLOT_0_AXIS_TDEST_WIDTH – AXIS destination width. Valid range is from 1 to 32.

Output Generation
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2].

Constraining the Core

This section contains information about constraining the core in the Vivado Design Suite.

Required Constraints
The ILA core includes an XDC file that contains appropriate false path constraints to prevent
the over-constraining of clock domain crossing synchronization paths. It is also expected
that the clock signal connected to the clk input port of the ILA core is properly constrained
in your design.

Device, Package, and Speed Grade Selections

This section is not applicable for this IP core.

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 Chapter 4: Design Flow Steps

Clock Frequencies
This section is not applicable for this IP core.

Clock Management
This section is not applicable for this IP core.

Clock Placement
This section is not applicable for this IP core.

Banking
This section is not applicable for this IP core.

Transceiver Placement
This section is not applicable for this IP core.

I/O Standard and Placement

This section is not applicable for this IP core.

Simulation
This core does not support simulation.

Synthesis and Implementation

This section contains information about synthesis and implementation in the Vivado Design
Suite. For details about synthesis and implementation, see the Vivado Design Suite User
Guide: Designing with IP (UG896) [Ref 2].

IMPORTANT: Synthesis with Synopsys Synplify is not supported for the core.

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 Chapter 5

Example Design
This chapter contains information about the example design provided in the Vivado®
Design Suite.

Directory and File Contents

<component name>_example/<component name>_example.srcs/
Top-level project directory; name is user-defined
constrs_1/imports/<component name>/
example_<component name>.xdc
sources_1/imports/<component name>/
example_<component name>.v
sources_1/ip/<component name>
Note: Only Verilog is supported.

<component name>_example/<component
name>_example.srcs/
This directory contains the source files needed to synthesize the ILA core whose name is
<component name>.

Table 5-1: ILA Example Design Source Files

Name Description
constrs_1/imports/<component name>/
example_<component name>.xdc Constraints file for the example design
sources_1/imports/<component name>/
example_<component name>.v Verilog (.v) source file for the example design

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 Chapter 5: Example Design

Implementation
To implement the example design, select Run Implementation in the Vivado Project
Manager window. For further details on setting up the implementation, see the Vivado
Design Suite User Guide: Implementation (UG904) [Ref 6].

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 Chapter 6

Test Bench
There is no test bench for this IP core release.

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 Appendix A

Verification, Compliance, and

Interoperability
Xilinx ® has verified the ILA v6.1 core in a proprietary test environment, using an internally
developed bus functional model.

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 Appendix B

Migrating and Upgrading

This appendix contains information about upgrading to a more recent version of the IP
core.

Migrating to the Vivado Design Suite

For information on migrating to the Vivado Design Suite, see the ISE to Vivado Design Suite
Migration Guide (UG911) [Ref 7].

Upgrading in the Vivado Design Suite

This section provides information about any changes to the user logic or port designations
between core versions.

Port Changes
• The maximum number of Probe ports is 1,024 and the maximum width of each Probe
port can be up to 4,096. However, the total number of bits (sum of all probe ports)
cannot exceed 65,536 bits.
• The port names are changed from uppercase to lowercase and you have to take care of
updating this in your design.
• There are other new parameters added to support the new features. For example,

° Storage Qualifier

° Advance Trigger
• The new features are default disable to have backward compatibility.
• To upgrade the IP to the latest version use the upgrade IP service in Vivado.

Functionality Changes
The ILA v5.1 core no longer has separate Data and Trigger ports. The Probe port is used for
both Data and Trigger.

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 Appendix B: Migrating and Upgrading

IMPORTANT: The ILA v5.1 core is not compatible with the legacy ChipScope™ Pro Analyzer tool. The
ILA v5.1 core requires the Vivado logic analyzer feature for run time interaction.

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 Appendix C

Debugging
This appendix includes details about resources available on the Xilinx Support website and
debugging tools.

TIP: If the IP generation halts with an error, there might be a license issue. See License Checkers in
Chapter 1 for more details.

Finding Help on Xilinx.com

To help in the design and debug process when using the ILA, the Xilinx Support web page
contains key resources such as product documentation, release notes, answer records,
information about known issues, and links for obtaining further product support.

Documentation
This product guide is the main document associated with the ILA. This guide, along with
documentation related to all products that aid in the design process, can be found on the
Xilinx Support web page or by using the Xilinx Documentation Navigator.

Download the Xilinx Documentation Navigator from the Downloads page. For more
information about this tool and the features available, open the online help after
installation.

Answer Records
Answer Records include information about commonly encountered problems, helpful
information on how to resolve these problems, and any known issues with a Xilinx product.
Answer Records are created and maintained daily ensuring that users have access to the
most accurate information available.

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 Appendix C: Debugging

Answer Records for this core can be located by using the Search Support box on the main
Xilinx support web page. To maximize your search results, use proper keywords such as:

• Product name
• Tool message(s)
• Summary of the issue encountered

A filter search is available after results are returned to further target the results.

Master Answer Record for the ILA

AR: 54606

Technical Support
Xilinx provides technical support in the Xilinx Support web page for this LogiCORE™ IP
product when used as described in the product documentation. Xilinx cannot guarantee
timing, functionality, or support if you do any of the following:

• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.

To contact Xilinx Technical Support, navigate to the Xilinx Support web page.

Debug Tools
There are many tools available to address ILA design issues. It is important to know which
tools are useful for debugging various situations.

Vivado Design Suite Debug Feature

The Vivado ® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly
into your design. The debug feature allows you to set trigger conditions to capture
application and integrated block port signals in hardware. Captured signals can then be
analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a
design running in Xilinx.

The Vivado logic analyzer is used with the logic debug IP cores, including:

• ILA 2.0 (and later versions)

• VIO 2.0 (and later versions)

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 Appendix C: Debugging

See the Vivado Design Suite User Guide: Programming and Debugging (UG908) [Ref 1].

For more information on the ability to interact with the ILA core using Tcl Console
commands, see Chapter 5 in the Vivado Design Suite User Guide: Programming and
Debugging (UG908) [Ref 1].

Hardware Debug
Hardware issues can range from link bring-up to problems seen after hours of testing. This
section provides debug steps for common issues. The Vivado debug feature is a valuable
resource to use in hardware debug. The signal names mentioned in the following individual
sections can be probed using the debug feature for debugging the specific issues.

General Checks
Ensure that all the timing constraints for the core were properly incorporated from the
example design and that all constraints were met during implementation. If using MMCMs
in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.

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 Appendix D

Additional Resources and Legal Notices

Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.

References
These documents provide supplemental material useful with this product guide:

1. Vivado Design Suite User Guide: Programming and Debugging (UG908)

2. Vivado Design Suite User Guide: Designing with IP (UG896)
3. Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)
4. Vivado Design Suite User Guide: Getting Started (UG910)
5. Vivado Design Suite User Guide: Logic Simulation (UG900)
6. Vivado Design Suite User Guide: Implementation (UG904)
7. ISE to Vivado Design Suite Migration Guide (UG911)

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 Appendix D: Additional Resources and Legal Notices

Revision History
The following table shows the revision history for this document.

Date Version Revision

04/06/2016 6.1 • Updated allowable values for C_PROBE<n>_MU_CNT in Table 2-2: ILA
Parameters.
• Updated to latest GUIs in Figs. 4-1 to 4-4.
11/18/2015 6.0 Added support for UltraScale+ families.
09/30/2015 6.0 • Moved Resource Utilization to HTML.
• Added C_PROBE<n>_TYPE in Table 2-2: ILA Parameters.
• Updated to latest GUIs in Figs. 4-1 to 4-4.
04/01/2015 5.1 • Updated to latest GUIs in Figs. 4-1 to 4-4.
10/01/2014 5.0 • Updated Figs. 4-1 to 4-4.
• Updated C_SLOT_0_AXI_PROTOCOL description.
• Added C_SLOT_0_AXIS_TDATA_WIDTH to C_SLOT_0_AXIS_TDEST_WIDTH.
04/02/2014 4.0 • Added AXI interface on ILA IP core to debug AXI to Features in IP Facts.
• Updated Fig. 1-1 in Overview chapter.
• Added UltraScale Device Utilization table in Resource Utilization section.
• Updated trig_out description in Table 2-2: ILA Ports.
• Added Design Flow Steps chapter.
• Updated descriptions in Vivado Lab Tools section in Debug Appendix.
12/18/2013 3.0 Added UltraScale support.
10/02/2013 3.0 Revision number advanced to 3.0 to align with core version number 3.0.
• Updated Fig. 1-1.
• Updated Table 2-1: Device Utilization – Kintex-7 FPGAs
• Updated Table 2-3: ILA Parameters.
• Updated Figs. 4-1 to 4-3 in Customizing and Generating the Core.
• Added descriptions in General Options Panel. and Probe Port Panels.
• Updated Migrating Appendix.
06/19/2013 2.1 Initial Xilinx release of Product Guide, derived from DS875.

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 Appendix D: Additional Resources and Legal Notices

Please Read: Important Legal Notices

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