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DLD Lab#5 Report

This document summarizes Lab 5 of the digital logic design course. It includes implementing a minimized logic function using logic gates, the truth table and circuit diagram for the function, and a Verilog implementation of an 8-variable logic function. The lab tasks involve minimizing the function F(A,B,C,D) = ∑(0,2,6,8,9,10,13,14) using a K-map and implementing it with logic gates, as well as writing Verilog code for the 8-variable function F(A,B,C,D,E,F,G,H) = ∑(1,9,14,15) and simulating the wave form.

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326 views

DLD Lab#5 Report

This document summarizes Lab 5 of the digital logic design course. It includes implementing a minimized logic function using logic gates, the truth table and circuit diagram for the function, and a Verilog implementation of an 8-variable logic function. The lab tasks involve minimizing the function F(A,B,C,D) = ∑(0,2,6,8,9,10,13,14) using a K-map and implementing it with logic gates, as well as writing Verilog code for the 8-variable function F(A,B,C,D,E,F,G,H) = ∑(1,9,14,15) and simulating the wave form.

Uploaded by

Aitazaz
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DIGITAL LOGIC DESIGN

EEE-241

Lab 5

Name Aitazaz Ahmad Qureshi

Registration CIIT/FA19-BCE-050/ISB
Number

Class BCE-2A

Ma’am Asma Ramay


Instructor’s Name
LAB#05: Logic Minimization of Complex
Functions using Automated Tools

In lab Task:
Implement the minimized function given below using logic gate IC’s.

F(A, B, C, D) = ∑ (0,2,6,8,9,10,13,14).

Function in Sum of Min-Terms Form:

(A’B’C’D’)+(A’B’CD’)+(A’BCD’)+(AB’C’D’)+(AB’C’D)+

(AB’CD’)+(ABC’D)+(ABCD’)]

Function in Simplified for using K-map:

(AC’D)+(B’D’)+(CD’)
Circuit Diagram of min-terms form of function:

Circuit Diagram of Simplified function:


TRUTH TABLE:

A B C D F F1 F2

0 0 0 0 1 1 1

0 0 0 1 0 0 0

0 0 1 0 1 1 1

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 0 1 0 0 0

0 1 1 0 1 1 1

0 1 1 1 0 0 0

1 0 0 0 1 1 1

1 0 0 1 1 1 1

1 0 1 0 1 1 1

1 0 1 1 0 0 0

1 1 0 0 0 0 0

1 1 0 1 1 1 1

1 1 1 0 1 1 1

1 1 1 1 0 0 0
In lab Task 2:

VERILOG for 8-variable function “F”.

F(A,B,C,D,E,F,G,H) = ∑ (1,9,14,15)

Simplified form using K-Map Minimizer:

B’C’DH’G’F’E’+ABCH’G’F’E’

VERILOG CODE:
Wave Form:

VERILOG for 8-variable function “F”.

F(A,B,C,D,E,F,G,H) = ∑ (1,9,14,15)

Simplified form using K-Map Minimizer:

B’C’DH’G’F’E’+ABCH’G’F’E’
VERILOG CODE:

Wave Form:

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