1

Modeling and Analysis of DC-DC Converters

Under Pulse Skipping Modulation
Santanu Kapat, Soumitro Banerjee, Senior Member, IEEE, and Amit Patra, Member, IEEE
Department of Electrical Engineering,
Indian Institute of Technology, Kharagpur - 721302, India

Abstract— The technique to model dc-dc converters governed balance principle. Most importantly, the averaged approxima-
by Pulse Skipping Modulation (PSM), which is based on energy tion of the quantities under consideration may not hold true
balance principle, is not accurate enough. In this paper, an due to the large voltage ripple. Again, the assumption, that
attempt has been made to model them accurately using the
discrete-time modeling approach. PSM scheme is essential to the inductor current is maintained within DCM in each clock
improve the efficiency of a dc-dc converter during the light load cycle, may not remain valid over a large range of the input
condition, mainly during standby or sleep mode. Here, a dc-dc voltage and load resistance. Therefore, the available models
boost converter has been considered as an example. There are fail to accurately capture the actual circuit behavior. Thus, the
four different ways by which the inductor current and output analysis remains inaccurate.
voltage can evolve from one clock instant to the next for the
PSM operation, i.e., four different regions. The discrete maps In this paper, the discrete-time map [9] through stroboscopic
have been derived for those regions, which are piecewise smooth. sampling has been derived by observing the state at the
The derived maps have been validated with the actual circuit beginning of each clock cycle.
behavior. For a specific range of the input voltage, it is shown that A dc-dc boost converter has been considered here. Depending
the entire map turns out to be a one-dimensional discontinuous upon the evolution of the inductor current and output voltage,
map. The border collision bifurcation of the map is then analyzed.
Stable higher periodic behavior is observed with a nonmonotonic four different regions are obtained, each of which has different
variation in periodicity for a smooth parameter variation, but functional form. The derived discrete maps are validated with
no chaos. The experimental investigation has been carried out the time domain simulation of the actual circuit. If the input
and the results have been presented to validate the theoretical voltage is lower than half of the reference voltage, it has been
predictions. shown that the resulting discrete map takes the form of a
one-dimensional discontinuous map. We analyze the border
collision bifurcation [10], [11]. We carry out the experimental
I. I NTRODUCTION
investigation and present those results. Beyond the region
Improving power conversion efficiency of dc-dc converters considered above, it can be shown that the map remains a
during light load condition, especially during standby or sleep discontinuous map with 1-D in one side and 2-D on the other
mode, becomes an essential requirement for the portable side [12], [13]. The proposed approach can be generalized for
battery powered applications such as mobile phone, laptop, other converters under PSM.
PDA, digital camera etc. To extend their battery lives, power
consumption needs to be minimized. Conventional pulse width II. M ODELING OF A PSM B OOST C ONVERTER
modulation (PWM) scheme results in poor efficiency during We consider a PSM boost converter as shown in Fig. 1. It
the light load condition, mainly due to the switching loss. Pulse consists of a controlled switch S (MOSFET), an uncontrolled
frequency modulation (PFM) and pulse skipping modulation switch D (diode), an inductor L, a capacitor C, and a load
(PSM) are the alternative schemes to improve the efficiency resistance R. The gate of the MOSFET, S, is solely controlled
[1]– [4]. TPS61200, FAN5308, MAX1771, Si9169 etc. are by the PSM control logic using an externally generated clock
some of the commercially available power management ICs of time period T and duty ratio D, which is fixed.
which adopt PSM/PFM during light load. PFM considers a
change in switching frequency by keeping either the ON time
or the OFF time of the power MOSFET constant. Hence A. Overview of PSM Control Scheme
it is difficult to design an input filter, thus giving rise to PSM control scheme decides whether a charge pulse with
the problems of EMI. PSM considers few charged pulses fixed duty ratio or a skipped pulse (no switching) is to be
(switching in between) with fixed duty ratio followed by few generated depending upon the status of the output voltage.
skipped pulses (no switching) depending upon the status of the This is achieved by obtaining an error voltage ve = (Vref −vo ),
output voltage. Since the clock frequency of PSM operation as a difference between the output voltage vo and the reference
remains fixed, there is neither the problem due to EMI nor the voltage Vref . The error voltage ve is compared with the ground.
difficulty in input filter design. Over the past few years, several For the nth clock period, if ve (nT ) ≥ 0, S turns on and
PSM control schemes have been reported [5]– [8]. Each of remains on until t = nT + DT . Then, S turns off till the end
them has its own advantages and disadvantages. Nevertheless, of the clock period. If ve (nT ) < 0, S remains off throughout
their modeling techniques are completely based on the energy the clock period.
 2

The duty ratio related to the PSM control scheme can be in L

the form +
 +
iL
D if vo (nT ) ≥ Vref
d=
0 if vo (nT ) < Vref
(1)
−
vin S
C R vo
The inductor current ramps up during the ON time and the _
system is said to be in Mode 1. During OFF interval, inductor
current falls until it reaches zero and the system is said to be CLR
in Mode 2. If the inductor reaches zero before the arrival of _
Q 7 D
the next clock, the operation is said to be in discontinuous 4 +
conduction mode (DCM), else it is in the continuous conduc- Vref
_ 7
tion mode (CCM). When inductor current continues to be at Q 4
zero, the system is said to be in Mode 3.
There are essentially three modes representing three different PR
subsystems described by the following sets of differential Clock
equations: Fig. 1. A dc-dc boost converter under PSM: iL = inductor current and
• The equations during Mode 1 vo = output voltage.
   1 
dx 0 0
= −1 x + L vin ; (2)
dt 0 RC 0 B. Operating Region for PSM
• The equations during Mode 2 A PSM scheme is applicable at light load condition which is
   1  well within the DCM mode of operation. The border between
dx 0 −1L L CCM and DCM, in terms of R, can be formulated as [14]
= 1 −1 x + vin ; (3)
dt C RC 0 2Vo L
Rt = (8)
• The equations during Mode 3 Vin (1 − D)DT
    where Rt is the threshold value of the load resistance. Hence,
dx 0 0 0
dt
=
0 RC−1 x +
0
vin ; (4) for a PSM operation, the load resistance must satisfy R  Rt .
  The external clock considered here, has a duty ratio D = 50%
iL and time period T = 50μs.
where x = ; iL and vo are the inductor current and the
vo The system parameters considered, are given below
output voltage respectively.
L = 60μH, C = 470μF, R = 80Ω,
The corresponding solutions are as follows:
Vref = 5V, Vin ∈ [1.2V, 4V].
• During Mode 1:
The same parameter set has been considered for the theoretical
vin (t−t )
iL (t) = iL (t ) + L
analysis, MATLAB simulation and experimental investigation.

(t−t ) (5)
vo (t) = vo (t )e− RC .
• During Mode 2: III. S TRUCTURE OF THE D ISCRETE S TATE S PACE

iL (t) = vRin + k1 e−σ(t−t ) cos ω(t − t )+ We obtain the discrete-time map through stroboscopic sam-
k2 −k1 σ −σ(t−t ) pling by observing the state at the beginning of each clock
ω e sin ω(t − t )
−σ(t−t ) (6) cycle. Fig. 2 shows that there can be four different ways in
vo (t) = vin + k3 e cos ω(t − t )+
k4 −k3 σ −σ(t−t ) which the state can evolve from one clock instant to the next
ω e sin ω(t − t ).
under the PSM operation. As a result, the discretized state
where space is divided into four regions with four different mappings
giving the complete model of the system.
k1 = iL (t ) − vRin ; k3 = vo (t ) − vin ;
 Let the inductor current and the voltage at the start of the nth
k4 = iLC(t ) − 2σvin ; clock pulse be in and vn , and those at the end of the clock
(t )   v
k2 = iLRC − voL(t )
+ RL − 2σ R ;
in
period be in+1 and vn+1 respectively.
σ= 1
2RC ; ω= 1
LC − σ2
A. Region 1
• During Mode 3:
In this region, all the Mode 1, Mode 2 and Mode 3 occur, as
iL (t) = 0 shown in Fig. 2(a), and the system enters into the DCM with
(t−t ) (7) vn+1 ≤ Vref . The final value of the state vector of Mode 1
vo (t) = vo (t )e− RC .
(vn , in ) becomes the initial condition for Mode 2, and the final
where t indicates the initial time when a mode starts operat- value of the state vector at the end of Mode 2 (vn , in ) is equal
ing. to the initial state vector of the discontinuous mode (Mode 3).
 3

D. Region 4
iL iL Mode 2 and Mode 3 exist in this region maintaining the
m 1 −m 2 i n+1 m1 −m 2 i n+1 sequence Mode 2 → Mode 3 shown in Fig. 2(d). The following
in in cycle needs to be skipped here, but the inductor needs to be
vn Vref vn+1 vn Vref vn+1 completely discharged first by forcing iL to zero within a time
duration, T1 and then it continues to be at zero till the end of
the clock. The discrete map can be approximated as
vo vo
DT DT in+1 = 0;
T12 αT12
vn+1 = αT 1
C (1 +
T1
2RC )in + α(1 − 2LC )vn + 2LC Vin .
T T (12)
t t
(a): Case 1 (b): Case 2 where √
2
T1 = −b+ 2a
b −4ac
; a = (in − vRn );
i n+1 b = 2C(vn − Vin ); c = −2LCin .
iL i n i n+1 iL i n
vn+1 vn+1 IV. M ODEL VALIDATION
vn vn
Vref Vref The accuracy of the derived discrete-time maps needs to
vo vo be validated. To accomplish that, we present the simulation
T1
results of the inductor current and the output voltage of the
T T actual circuit along with those obtained from the discrete
t maps. Since the maps consider the status of the state variables
(c): Case 3 (d): Case 4
at each clock instant, we assign them using the symbol, ‘o’.
Fig. 2. Possible evolutions of the inductor current and the output voltage For a load resistance of 75Ω, Fig. 3 and Fig. 4 show that
between two clock instants (t = nT and t = (n + 1)T ) where: (a) the maps accurately capture the actual circuit behavior for the
Case 1 (Region 1): in = 0, vn ≤ Vref and in+1 = 0; (b) Case 2 (Region 2): input voltages of 1.5V and 3.3V respectively. Also, Fig. 3
in = 0, vn ≤ Vref and in+1 > 0; (c) Case 3 (Region 3): in = 0, vn > Vref
and in+1 = 0 and (d): Case 4 (Region 4): in > 0, vn > Vref and in+1 = 0. indicates the circuit behavior with a combination of Region 1
and Region 2, whereas Fig. 4 shows the combined behavior
of Region 2, Region 3 and Region 4. Since those results are
Then using (5)–(7), we get the complete map in this region. obtained by considering two extreme input voltage conditions,
The above map can be approximated by considering upto 2nd we can conclude the accuracy of the maps to be good enough.
order damped sinusoidal terms and simplified as Hence, we can proceed further for their bifurcation analysis.
in+1 = 0
Output Voltage (V) Inductor Current (A)

(9) Model Validation: Vin = 1.5; R = 75.

βD 2 vin
2
vn+1 = αvn + (vn −vin ) . 0.6
T T2 T2 0.4
where α = 1 − RC + 2R2 C 2 ; β= 2LC . 0.2
0
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (s) −3
B. Region 2 x 10

In this region, only Mode 1 and Mode 2 exist as shown in

5
Fig. 2(b). From (5)–(6), the discrete map can be derived in a
similar way and represented as 4.99
      
in+1 a11 a12 in b1 0 0.5 1 1.5 2 2.5 3 3.5 4
= + Vin . (10) Time (s) −3
vn+1 a21 a22 vn b2 x 10
where,
Fig. 3. Model validation for an input voltage of 1.5V and load resistance of
a11 = 1 − (1 − D)2 β; a22 = α − (1 − D)2 β; 75Ω.
2
a12 = −(1−D)T
L + (1−D) β
R2 2 ;
(1−D)T (1−D) T
a21 = C − 2RC 2 .
V. A NALYSIS OF THE PSM B OOST C ONVERTER
C. Region 3 For the specified input voltage range, we can show that the
In this region, only Mode 3 exists throughout the clock cycle entire map turns out to be a one-dimensional discontinuous
as shown in Fig. 2(c). The discrete map can be represented as map comprising Region 1 and Region 3. Since we are inter-
ested only in the bifurcations that occur when a fixed point
in+1 = in = 0; crosses the border, the system is studied through the piecewise
(11)
vn+1 = αvn . linear approximation in the neighborhood of the border. Vref
 4

Output Voltage (V) Inductor Current (A)

Model Validation: Vin = 3.3; R = 75. the border at μ = 0 and the fixed point x∗R collides with the
1 border at μ = −l . Therefore, it is expected that two border-
collision events would occur as the parameter μ is varied
0.5
smoothly.
0
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (s) −3
x 10 L R
x n+1 = x n
x n+1
5.05
μ >0
5
0 0.5 1 1.5 2 2.5 3 3.5 4 xn
Time (s) −3
x 10
μ <_ 0
Fig. 4. Model validation for an input voltage of 3.3V and load resistance of
75Ω.
x L*

is the only border here and the piecewise linear map can be Fig. 5. The graph of the map: ‘L’ and ‘R’ indicate the side and right side
of the border, solid line indicates the graph of the corresponding map and
written as dashed line indicates the unity slope line.

avn + μ for vn ≤ Vref
vn+1 = f (v; μ) = (13) For the 1-D discontinuous map considered here, it can be
bvn + μ + l for vn > Vref
shown that l , which depends on the input voltage, is always
where a, b, μ and l are obtained by linearizing (9) and (11)
negative. a and b , both of which depend on the load re-
and represented as
sistance, always maintain, 0 < a < 1 and 0 < b < 1
βD2 vin2
βD2 vin
2
(2Vref − vin ) irrespective of the load resistance range. μ depends on the
a=α− ; μ = (14)
(Vref − vin )2 (Vref − vin )2 input voltage which may be negative or positive. The quantity,
μ + l can be expressed as
and  
−βD2 vin2
βD2 Vin3
b = α; l = . (15) μ + l = − + (1 − α)V . (17)
(Vref − vin ) (Vref − Vin )2
ref

The piecewise map given in (13) clearly shows a 1-D discon- Equation (17) clearly shows that μ < −l . Therefore, the
tinuous map with a discontinuity of length l [10]. The 1-D entire analysis for the region of interest is reduced to two
map, f (v; μ), maps the real line 1 to itself and depends subcases, Subcase 1: μ < 0 and Subcase 2: −l > μ > 0
smoothly on the parameter μ. The border in the real line which is discussed below.
divides it into two regions. The map is piecewise continuous in
the sense that it is continuous in (v; μ) on each of the regions,
but is discontinuous at Vref . It can be shown that the partial A. For μ < 0
derivatives of the map and the length of the discontinuity at Here, there is a stable fixed point shown in the bifurcation
the border are independent of the parameter μ. A co-ordinate diagram in Fig. 11. The experimental bifurcation diagram is
transformation can be applied by substituting, xn = vn − Vref shown in Fig. 12. It is restricted to μ = 0, which gives us
and xn+1 = vn+1 − Vref , to move the break-point, Vref , into the input voltage range of the actual circuit, Vin ≤ 1.45V .
the origin. After transformation, the map, f (v; μ) can be The simulated time domain waveform of the converter’s output
represented as voltage is shown in Fig. 6 which also confirms the period-1
  operation. The eigenvalue of the Jacobian matrix can be shown
a xn + μ for xn ≤ 0 to be inside the unit circle. Hence, the period-1 orbit is stable.
xn+1 = (16)
b xn + μ + l for xn > 0 In this region, the input voltage is not sufficient to provide
where enough energy to boost the output voltage to the desired value
Vref , though the inductor current goes into DCM. Since there is
a = a; b = b; l = l; μ = −(1 − α)Vref − l. no skipped pulse, it is not a feasible region for PSM operation.
From (16), it is clear that after co-ordinate transformation, Therefore, it is necessary either to increase the duty ratio D to
the slopes of the map in the either side of the border and operate the converter under PSM or to handover the controller
the length of the discontinuity remain unchanged whereas the from PSM to PWM mode.
bifurcation parameter, μ changes. The state space is divided
into two halves L (left) and R (right) which is shown in Fig. 5. B. For −l > μ > 0
μ
The fixed point in L is located at x∗L = (1−a  ) and that in R
Here, there is no fixed point, because x∗L > 0 and x∗R < 0.
μ +l
is located at = x∗R
The left half of the map intersects (1−b ) . The orbits in the left half move towards the right and those
with unity slope line for μ < 0 and the right half intersects in the right half move towards the left enabling stable high
for μ > −l . This shows that the fixed point x∗L collides with period orbits to exist. Since the map is piecewise linear in
 5

Output Voltage (V) events, the circuit undergoes an extra skipped phase (Region 3)
followed by an usual pair of events. The incremental change
5.01
in energy after each pair along with an extra skipped pulse
forces output voltage to change accordingly, hence resulting
5 in stable high periodic orbits. Similarly, it can be explained
for a decrease in the input voltage. Hence, the variation of
periodicity occurs in a nonmonotonic manner for a smooth
4.99
parameter variation.
Clock Pulse

For Vin = 2.25V , there exists a stable period-3 orbit. Fig. 9

4.98 and Fig. 10 show the simulation result and experimental
result respectively for period-3 orbit consisting of alternative
0.0341 0.0342 0.0343 0.0344 0.0345
Time (s) occurrence of a charge followed by two skipped pulses. Here,
the injected energy during the charged phase is released during
Fig. 6. Time domain simulation result for an input voltage of 1.45V. two consecutive skipped phases without leaving any excess
or deficit of energy. A small variation of parameter in either
direction results in stable high periodic orbits in a similar way
either side, high periodic orbits cannot exist with all points in mentioned earlier. This period adding cascades are mainly due
L or all points in R. The period-2 fixed
 
point must be of LR to the grazing for the above discontinuous map [15].
μ +μ +l )
type, with the points in L given by (b (1−a  b ) and the point
(a μ +μ +a l )
in R given by . This orbit will exist so long as

Output Voltage (V)

(1−a b )
5.006
(b μ + μ + l ) (a μ + μ + a l )
< 0 and > 0. (18) 5.004
(1 − a b ) (1 − a b )
5.002
There can be two types of period-3 orbits - LRR type and LLR
5
type and the existence can be verified in a similar manner, but
4.998
the expressions become cumbersome, and are thus excluded
here. A few conclusions can be drawn from the above which 4.996
Clock Pulse

are enumerated below. 4.994

1) Since a and b are both less than unity, if any high- 4.992
periodic orbit exists it is stable, and there can be no 0.0226 0.0228 0.023 0.0232 0.0234 0.0236 0.0238
Time (s)
chaotic orbit since the map is not stretching.
2) There is one range of parameter where period-2 orbit Fig. 7. Period-2 operation for vin = 1.92V : simulation result.
will exist, two range of parameter where period-3 orbit
will exist, and similarly the period-n orbit will exist in
(n-1) ranges of the parameter.
3) The ranges of occurrence of orbits of consecutive peri-
odicity (e.g., period-2 and period-3) are not continuous
here. Therefore, the occurrence of high-periodic orbits
is non-monotonic.
The bifurcation diagram shown in Fig. 11 indicates that for
Vin = 1.92V , period-2 orbit exists. The eigenvalues of the
Jacobian are found to be within the unit circle, hence stable.
Fig. 7 and Fig. 8 show the simulation result and experimental
result respectively for period-2 orbit consisting of alternative
occurrence of a charge and a skipped pulse. There is a steady
difference of 0.35V between simulation and experimental
results, which is half of the diode voltage, not included in
the discrete-time map.
There is a synchronization between the injected energy during
charge phase and the released energy during the skipped phase. Fig. 8. Experimental result for period-2 operation for vin = 2.27V where,
Ch1 and Ch2 indicate the external clock and output voltage, respectively.
After each pair, there will be neither any excess nor deficit of
energy, hence it continues to occur in that pair throughout.
Now if the input voltage is slightly increased, then the above
pair of events (Region 1 → Region 3) continues to occur but VI. C ONCLUSION
a small amount of excess energy goes on accumulating at In this paper, we accurately derived the discrete-time model
the end of each pair. When the accumulated energy becomes of a PSM boost converter, which is piecewise smooth, divided
sufficiently large after a large number of similar pair of into four regions, each with a different functional form. We
 6

Output Voltage (V)

5.02

5.015
5.01

Output Voltage (V)

5.01 5.005

5.005
5
Clock Pulse

5
4.995
4.995

0.0298 0.03 0.0302 0.0304 0.0306 0.0308 0.031 0.0312 0.0314 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3
Time (s) Input Voltage (V)

Fig. 9. Period-3 operation for vin = 2.23V : simulation result. Fig. 11. Bifurcation diagram for the dc-dc boost converter considering the
input voltage as a bifurcation parameter.

Fig. 10. Experimental result for period-3 operation for vin = 2.58V where,
Ch1 and Ch2 indicate the inductor current and output voltage, respectively. Fig. 12. Bifurcation diagram obtained experimentally for R = 80Ω and the
input voltage as the bifurcation parameter where X axis represents the input
voltage (V) and Y axis represents the sampled output voltage (V).
also found that the derived model accurately reflects the actual
circuit behavior with an error lower than 0.2%. Within a
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