Average Current Mode Control in Digitally Controlled

Discontinuous-Conduction-Mode PFC Rectifier for

Improved Line Current Distortion

Jong-Won Shin* and Bo-Hyung Cho Jae-Ho Lee

School of Electric Engineering and Computer Science EV Control, Central R&D Center
Seoul National University LS Industrial System
Seoul, Korea Anyang, Korea
nf84@snu.ac.kr*

Abstract—This paper proposes a digital average current mode open-loop control. One-cycle control method enables the
control method in discontinuous conduction mode (DCM) variable duty cycle control with two resettable integrators
power factor correction (PFC) rectifier. The proposed control and resistive sensing network of rectified input voltage [6].
technique can directly sense the average value of the inductor Harmonic injection methods to achieve near-unity PF have
current in each switching cycle digitally by employing a been also reported though their analog control circuits are
conventional current sensing circuit. Thanks to the current complicated [7]-[8]. Another variable frequency control
control loop, high speed analog-to-digital converters (ADC’s) scheme is implemented with input voltage feedforward [9].
or high performance digital IC’s are not needed. The technique Reference [10] digitally realized the control scheme in [9] by
achieves lower total harmonic distortion (THD) and higher using multiplying and square-root operations.
power factor (PF) than conventional DCM PFC rectifiers.
Experimental results using prototype hardware verify the On the other hand, sensing the average inductor current
feasibility and performance of the proposed sensing method. in DCM is not straightforward in digital control
implementation. Generally, digital controllers employ one-
sample-per-switching-cycle to sense the analog information.
I. INTRODUCTION The sampling instant of the average inductor current depends
Harmonic current by various non-resistive electronic not only on the on-time of switch as in continuous
loads is known as the cause of problems such as power loss, conduction mode (CCM) [11] but also on the on-time of
noise, voltage distortion and reduced line utilization [1]. diode. Sample correction method in CCM rectifier, which
Especially, regulations on line current distortion in electronic corrects the sampled inductor current by multiplying
devices pose a challenge for low power converters [2]. correction factor, has been proposed to minimize distortion
Active PFC units based on switch mode power supplies are at both ends of the half line period where the inductor current
considered as a general solution to minimize the harmonic is temporarily in DCM [12].
current. They feature smaller size, higher efficiency and PF
An average current mode control in digitally controlled
than passive PFC circuit [3].
DCM PFC rectifier is suggested in this paper. The control
DCM operation of active PFC rectifiers features low method uses conventional sensing circuit and fixed sampling
diode recovery loss, zero-current turn-on of main switch, and instant to achieve the variable duty cycle control. It requires
constant switching frequency. It is usually adopted in low to same calculation burden with conventional CCM PFC
medium power range, i.e., under 200~300W, where the rectifier and does not need any additional computation. The
conduction losses in semiconductor devices are not dominant. proposed control technique also features low THD and high
As its conventional control law, open-loop control or PF.
constant duty cycle control is widely used due to its
The paper consists of following sections: In Section II,
simplicity in the control scheme. The controller needs only a
the mode analysis is given and the mathematical expression
low-bandwidth voltage loop which dispenses with current
of properly controlled inductor current shape is derived.
sensing and control circuit [4]. The drawbacks of the open-
Section III illustrates the design procedures including boost
loop control technique, however, are relatively low PF and
inductor and digitally realized control loops. Experimental
high THD, especially when high line input voltage is applied
results with 200W prototype hardware such as oscillograms
[5]. Various researches have been done on the variable duty
and measured THD data are presented in Section IV. The
cycle control to overcome the aforementioned problems of
paper is summarized and concluded in Section V.

978-1-4244-8085-2/11/$26.00 ©2011 IEEE 71

 II. PROPOSED CONTROL TECHNIQUE t
1
A. Operational Mode Analysis
vCs (t ) =
nCS ∫ i (t )dt
t0
L (1)

A circuit diagram of a boost rectifier with proposed

control technique is shown in Fig. 1. Rectified input and n represents the turn number of secondary winding
output voltage sensing networks and gate driver are omitted of T. vCs(t) increases in parabolic way from zero
for clarity. The rectifier operates in DCM with fixed because the rectifier operates in DCM.
frequency and fixed sampling instant. The current sensing • Mode 2 [t1~t2]: When Q1 turns off at t1 by the current
circuit which consists of current sensing transformer T, zener
diode DZ, sensing capacitor CS, and reset switch Q2 is the vO − | vin |
loop, iL decreases with the slope . vCs(t)
same as that in conventional control [13]-[14]. The digital L
controller controls the gate signals of the two switches Q1 still increases but the sign of the parabolic curve is
and Q2. inverted.
The operation of the current sensing circuit is different • Mode 3 [t2~t3]: After t2, iL maintains zero and vCs(t)
from the conventional one in two ways: First, the gate signal remains constant as in (2):
of Q2 is not complementary to that of the main switch Q1.
The turn-on instant of Q2 is delayed until the inductor current ⎡ t ⎤ ⎡ TS ⎤
TS ⎢ 1 T ⎢1
becomes zero thus the sensing capacitor voltage vCs remains
constant. After vCs is sampled by the digital controller, Q2
vCs (t ) =
nCS ⎢ TS ∫
iL (t )dt ⎥ = S
⎥ nCS ⎢ TS ∫ iL (t )dt ⎥
⎥
⎣ t0 ⎦ ⎣ t0 ⎦
turns on to discharge CS. Second, the turn-off of Q1 is
controlled by a current loop in the average current mode T
= S iavg , (2)
control. nCS
The operational waveforms are illustrated in Fig. 2. vgs1, where TS is the switching period and the term in the
iL, vCs and vgs2 are gate signal of Q1, inductor current, sensing braces is the average inductor current in a switching
capacitor voltage, and gate signal of Q2 respectively. Unit cycle or iavg . In this interval, vCs(t) represents the
switching period is separated in three modes to explain the
operation of the proposed current control. Time segments average inductor current because iL in Mode 1 and
d1TS and d2TS represent the on-time of Q1 and output diode D Mode 2 is fully integrated. The digital controller
respectively. To simplify the analysis, semiconductor devices then triggers the internal ADC to sample the vCs(t) to
are assumed to be ideal. Rectified input voltage |vin| and compare it with the inner loop current reference.
output voltage vO are also approximated to be constant within After the sampling, Q2 turns on to discharge CS
a switching period. before the next turn-on signal of Q1 occurs. Because
the sampling instant is fixed in unit switching cycle,
• Mode 1 [t0~t1]: At t0, Q1 turns on by the fixed the digital controller does not spend any resource to
frequency signal of the digital controller. iL linearly determine when the sampling should occur in each
| vin | switching cycle.
increases with the slope , where L is
L
inductance of boost inductor. Then the current
sensing transformer T outputs the scaled inductor
current through DZ to CS. vCs(t) is shown in (1).

Figure 1. Proposed current control circuit with boost rectifier. Figure 2. Operational waveforms of the proposed current control
technique.

72
B. Inductor Current Shaping Substituting (3), (4) and (6) into (5) yields (7).
Generally, the inductor current waveform of average
2TS V pk X V pk sin ωL t
current mode controlled CCM boost rectifier resembles the i pk (t ) = 1− sin ωL t (7)
sinusoid of the input voltage to achieve high PF and low L vO
THD. However, unlike in CCM rectifier, the envelope of the
inductor current in DCM rectifier does not look like a The unknown constant X can be derived from input
sinusoid. Fig. 3 compares the current shapes in general CCM power consideration. If Pin, PO and η are the input power,
and DCM PFC rectifier over half line period. The envelope output power, and efficiency of the rectifier system, i.e.,
of the inductor current of DCM PFC, ipk(t), does not follow input filter and rectifier, (8) can be achieved.
the sine wave though its average value per switching cycle,
PO 1
iavg(t), tracks sine wave as in Fig. 3(b). Pin = = I rmsVrms = V pk X (8)
η 2
If the average inductor current per switching cycle is
controlled to be proportional to the sinusoidal input voltage, Irms and Vrms in (8) represent rms value of the input current
ipk(t) can be derived from the duty ratios d1 and d2 as in (3) iavg and the input voltage vin respectively. Rearranging and
and (4): substituting (8) into (7) finally yields (9).
Li pk (t ) Li pk (t ) TS PO V pk sin ωL t
d1 = , d2 = . (3), (4) i pk (t ) = 2 1− sin ωL t (9)
vin (t )TS ( vO − vin (t ) ) TS ηL vO
iavg(t) is derived from the geometry of the waveform shown Fig. 4 illustrates the inductor current envelopes for
in Fig. 2 with unknown constant X as shown in (5). various line input voltages and 200W load. The current
envelope shows a “saddle” in the middle of the half line
1 period. It is because the term in the second square root in (9)
iavg (t ) = (d1 + d 2 )i pk (t ) = X sin ωL t (5)
2 is not a constant but a function of sin ω L t . The performance
vin(t) is assumed to be the pure sine wave with peak value Vpk improvement between the proposed and the conventional
2π current control techniques is emphasized when high line
and period TL = which is expressed in (6). voltage is applied because the saddle is deeper at higher line
ωL
voltages.
vin (t ) = V pk sin ω L t (6)
III. RECTIFIER DESIGN WITH THE PROPOSED CONTROL
TECHNIQUE

A. Inductor Design
The proposed control method samples vCs as the current
information after iL reaches zero in Mode 3. To properly

Figure 3.Comparison of inductor current shapes between (a) CCM and Figure 4. Inductor current envelopes for various line voltages and
(b) DCM rectifier. 200W load in average current mode DCM rectifier.

73
 B. Sensing Gain of the Proposed Control Circuit
Though the proposed current sensing circuit integrates
the inductor current, the integrating operation does not
continue over consecutive switching cycles. Thus the sensing
circuit does not have any frequency-dependent dynamics
such as analog integrators. Fig. 6 shows the small-signal
block diagram of the proposed current control technique. The
effect of the sensing circuit on the small-signal modeling
appears as the fixed gain, Ki, which is the shaded box in Fig.
T
6. Ki is defined to be S , the coefficient of Iavg as shown in
nCS
(2). In this paper, TS, n, and CS are selected to be 15.385μs
(reciprocal of 65kHz), 50, and 220nF and the resultant Ki is
1.4.

C. Control Loop Design

Current loop gain Ti is defined as in (14):
Figure 5. The sum of d1 and d2 for various line voltages with 70μH Ti = Gid K i H e K adc GC FM (14)
inductance and 200W output.
where Gid, He, Kadc, GC, and FM are open-loop control-to-
sample and reset vCs, maximum L should be limited to il
guarantee the length of Mode 3. If L is designed to be larger inductor current transfer function L , sampling effect,
than the maximum value, the operation of the rectifier may d
go into CCM and lose control even though the control loop is internal ADC gain of digital controller, and modulator gain.
stable. Equation (14) is similar with the characteristic of the
conventional CCM average current mode controlled
Equation (10) shows the sum of d1 and d2. converter. Gid, which can be derived from the averaged
Li pk (t ) circuit model shown in [15] shows flat gain with high
1 frequency single pole over half of switching frequency.
d1 + d 2 = (10)
TS V pk sin ωL t V pk Current compensator GC is designed to have an integrator
1− sin ω L t
vO with single pole to attenuate the high frequency noise. It is
designed at first in s-domain and is interpreted into z-domain
When (9) is substituted into (10), (11) is achieved. with zero-order-hold discretization method. Resultant Ti has
2kHz bandwidth and sufficient phase margin. Bode plot of Ti
2 LPO 1 is illustrated in Fig. 7 with those of GidHe and GC.
d1 + d 2 = (11)
V pk TSη V pk
1− sin ω L t
vO
The maximum of d1 + d2 occurs where the middle of the half
T
line period, t = L . If the minimum duty ratio of Mode 3, d3,
4
is set to be dmin, (12) is obvious.
( d1 + d 2 )max ≤ 1 − d min (12)

The maximum limit of L is determined from (11) and (12):

2
⎛ V pk ⎞ TSηV pk
L ≤ (1 − d min ) 2 ⎜⎜ 1 − ⎟⎟ (13)
⎝ vO ⎠ 4 PO
In this paper, dmin is set to 0.2 and L is designed to be
70μH. Fig. 5 graphically expresses (11) with the resultant L
for various line input voltage with 200W load. It is
confirmed that the designed inductance always guarantees
the DCM operation of rectifier because over 30% of the
switching period is allocated for Mode 3. Figure 6. Small-signal block diagram of the proposed current control
technique.

74
 TABLE I. CIRCUIT PARAMETERS OF LABORATORY PROTOTYPE

Device Parameter

L 70μH

Power C 220nF/450V electrolytic

Component Q1 STW20NM50

D FSF10A60

T turns ratio 1:50

Current
Sensing DZ 1N4744
Circuit
CS 220nF/50V ceramic

Part name dsPIC33FJ1GS502

Switching/sampling
Figure 7. Bode plots of GidHe, GC, and resultant Ti. 65kHz
frequency
Q15 method based on
As the voltage loop compensation, GV contains an Digital Number operation
fractional data type
integrator and a closely coupled pole-zero pair. With output Controller
ADC resolution 10 bits
voltage sensing gain Kv and input voltage feedforward gain
Kff, the resultant bandwidth of overall loop gain is set to Kadc 0.3
approximately 10Hz. FM 2.2245
The calculation procedure for loop compensation
algorithm only contains two vector inner products for each The line input voltage to the prototype circuit is 60Hz
loop and single multiplying operation for sensed input 230VAC and the output voltage is controlled to be 400VDC.
voltage and voltage compensator output. It requires the same Fig. 8 shows the waveform of vCs and the change of duty
calculation burden with conventional digitally controlled cycle according to the instantaneous line voltage at 85% load.
CCM PFC rectifier. There is no additional square-root, The traces indicate line input voltage, inductor current, gate-
multiplying, or dividing operation which spends a lot of source voltage of the main switch Q1, and voltage across the
resource of digital controller. sensing capacitor CS from the top respectively. When line
voltage is higher, inductor carries larger average current
IV. EXPERIMENTAL RESULTS though the duty cycle is smaller.
The proposed current control technique is verified by Fig. 9 compares current waveforms between
200W laboratory prototype circuit. The circuit parameters conventional open-loop control and the proposed variable
are summarized in Table I. duty cycle control at full load with same power stage. The
line input current iavg is the filtered version of iL by simple

(a) (b)
Figure 8. Duty cycle modulation within half line cycle. (a) when vin is 80V. (b) when vin is 320V.

75
 (a) (b)
Figure 9. Current waveforms comparison between (a) conventional open-loop control and (b) proposed variable duty cycle control.

second-order L-C filter as shown in Fig. 1. In Fig. 9(a), iavg 10 follows milliamps per Watt (mA/W) harmonics currents
in conventional control does not resemble sine wave and is defined in [2]. The proposed control outperforms the
distorted. However, in Fig. 9(b), saddles are observed in the conventional control by obtaining lower THD and higher PF.
inductor current envelope as explained in Fig. 4. The line
input current of the proposed control scheme is much less V. CONCLUSION
distorted and looks like sinusoid. An average current control method for digital DCM PFC
Measured harmonic components of two control methods rectifier has been proposed. The control method achieves
at 75% load are shown in Fig. 10. Corresponding calculated lower current distortion by employing a conventional sensing
THD’s and measured PF’s are in Table II. Regulation in Fig. circuit method than conventional open-loop control method.
Operational modes, current shaping, and rectifier design
procedure have been analyzed and explained with
mathematical expressions. The proposed control technique
has been verified and compared with conventional one by
experimental results of 200W a prototype system.
Waveforms and measured data have proved that the
proposed control with average current sensing and sampling
technique achieves lower line current distortion.

VI. ACKNOWLEGEMENT
This research is supported by KD Power, Co. Ltd., Korea.

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