CHAPTER 16

VLSI Process Technology

KEY TOPICS
• Crystal growth • Ion implantation
• Photolithography • Etching
• CMOS technology • Epitaxial growth
• Oxidation • Metallization
• Diffusion • Packaging

16.1 Introduction
Integrated circuit (IC) chips are designed and fabricated using very large scale inte-
gration (VLSI) technique. VLSI technique has two wings: (a) designing of circuits
and layouts using EDA tools and algorithms is known as VLSI design; and (b) fab-
rication or manufacturing of VLSI circuits is known as VLSI technology or process
technology. In this chapter, we discuss the basic steps for IC fabrication. First, we
examine the different techniques for crystal growth followed by photolithography
technique, oxidation, diffusion, ion implantation, etching techniques, and epitaxial
growth techniques. The chapter concludes with metallization and packaging.

16.2  Crystal Growth

VLSI fabrication starts with a substrate material of either intrinsic or extrinsic
type. A technique called lithography is used to create patterns on the substrate.
Creating patterns on wafer means to fabricate the circuit components at the exact
locations. For example, for a CMOS inverter circuit, the pMOS and nMOS will
be fabricated physically. But to start the IC fabrication, we need the substrate or
the wafer. In reality, the semiconductor material is not available in the elemental
form. The elemental semiconductor needs to be extracted from its compounds.
Then the crystalline form of the semiconductor needs to be grown. The techniques
that grow the semiconductor crystals are known as crystal growth techniques. The
grown crystal is often called the single crystal as it ensures that the growth of crys-
tal follows a particular crystal plane.

16.2.1 Silicon Crystal Growth

Silicon (Si) and germanium (Ge) are the two elemental semiconductors which are
of interest to the semiconductor device people because of their excellent proper-
ties. Although Ge was initially used to make semiconductor devices, eventually
it was subdued by Si because of mainly the native oxide of Si, silicon dioxide
498  VLSI Design

(SiO2). More than 90% of semiconductor devices fabricated across the world, use
Si, and that too is purely CMOS because of its low power and area requirements.
In this section, we discuss the single crystal Si growth technique. Si is avail-
able in nature abundantly in the form of sand (SiO2). So, first the elemental Si is
extracted from sand using a series of chemical reactions as follows:
coal, coke, woodchips
1. SiC + SiO 2 → Si + SiO + CO (16.1)
Sand is taken with coal, coke, and woodchips in a furnace and is reacted at 1400°C
to form metallurgical grade silicon (MGS). MGS is 98% pure, where impurities
are in the order of parts per million (ppm).
300 o C
2. Si + 3HCl → SiHCl 3 ↑ + H 2 ↑ (16.2)

MGS is reacted with hydrogen chloride at 300°C to form trichlorosilane (SiHCl3).

3. → Si + 3HCl (16.3)
SiHCl 3 + H 2 
Next, fractional distillation of trichlorosilane is used to remove the impurities. It
is then reacted with hydrogen gas at 1150°C (Otto, 1964) to reduce the hydrogen
atom and produce electronic grade silicon (EGS). EGS has the highest purity and
its impurity level is in the order of parts per billion (ppb).
The EGS that is obtained from the chemical process discussed above produces
polycrystalline silicon which is not suitable for device fabrication. A single crystal
is to be grown from EGS.

16.2.2  Czochralski Technique

In the Czochralski growth technique, the crystal growth takes place from the melt.
The molten silicon is taken in a crucible. A seed crystal is placed just on top of
the melt so that it touches the melt. Then the seed is pulled upwards slowly and
rotated. The molten silicon is cooled slowly and solidifies underneath the seed in
the desired crystal direction. The arrangement is shown in Fig. 16.1.
The grown crystal takes a cylindrical shape, which is known as an ingot. An
ingot is shown in Fig. 16.2.

16.2.3  Dopant Distribution

During the process of crystal growth, dopants are introduced to make the grown
crystal either p-type or n-type by adding boron or phosphorus into the melt, re-
spectively. The doping concentration in the crystal and the melt differs from do-
pant to dopant. The ratio of dopant concentration in a solid (Csolid) to that in a
liquid (Cliquid) is known as segregation coefficient or distribution coefficient,
Csolid
kd = (16.4)
Cliquid

If kd is less than 1.0, then Cliquid > Csolid, which indicates dopants prefer to stay in
the melt than in the solid. Hence, as the crystal grows, dopant concentration in the
 VLSI Process Technology  499

Anti-clockwise rotation
Seed crystal

Fused silica Single crystal Graphite

crucible susceptor
RF Coils

Liquid melt

Clockwise rotation

Fig. 16.1  Czochralski crystal growth technique Fig. 16.2  Silicon ingot

melt increases. Table 16.1 lists segregation coefficients for some of the dopants
for silicon.

Table 16.1  Typical segregation coefficients

Dopant kd Type
−1
Boron (B) 8 × 10 P
Aluminium (Al) 2 × 10−3 P
Gallium (Ga) 8 × 10−3 P
Indium (In) 4 × 10−4 P
Phosphorus (P) 3.5 × 10−1 N
Arsenic (As) 3 × 10−1 N
Antimony (Sb) 2.3 × 10−2 N

Let us consider a crystal grown from its melt. The mass of the melt is m0 and the
initial doping concentration is C0 in the melt (i.e., the amount of the dopant per
gram of melt).
Assume that after a certain amount of crystal is grown, its mass is ms. Hence,
the remaining amount of melt is (m0 – ms), and let us assume the amount of dopant
remaining in the melt is md.
For a small amount of the crystal of mass dms, the reduction of the dopant (– dms)
from the melt is Csolid dms, where Csolid is the doping concentration in the crystal:
−dmd = Csoliddms (16.5)
500  VLSI Design

Now, the mass of the melt left in the crucible is (m0 − ms ) , and the doping concen-
tration in the liquid, Cliquid, is given by
Amount of dopant in melt md
Cliquid = = (16.6)
Amount of melt m0 − ms

Combining Eqns (16.5) and (16.6), and substituting Csolid Cliquid = kd yields

dmd  dms 
= − kd  (16.7)
md  m0 − ms 

Initial condition: when ms = 0, md = C0 m0

After some point: when ms = ms , md = md
Using these two limits, integrating Eqn (16.7), we get
md ms
dmd − dm
∫ md
= kd ∫ m0 − ms s (16.8)
C0 m0 0

md ms
or ln m d = kd ln( m − m )
C0 m0 0 s 0

 m   m − ms 
or ln  d  = kd ln  0
 C 0 m0   m0 
kd
md  m − ms 
or = 0
C0 m0  m0 
or (substituting the value of md)
kd
Cliquid (m0 − ms )  m − ms 
= 0
C 0 m0  m0 

or (substituting the value of Cliquid)

kd −1
Csolid  m0 − ms 
=
kd C0  m0 

kd −1
 m 
or Csolid = k d C0  1 − s  (16.9)
 m 
0

ms
where is called the fraction solidified.
m0
As the crystal grows, the dopant concentration increases continually for kd < 1,
and decreases continually for kd > 1. For kd ≅ 1, a uniform dopant distribution is
 VLSI Process Technology  501

obtained. Figure 16.3 shows the variation of Csolid C0 with respect to fraction
solidified.

101

3.0
2.0

1.0
100
0.5
Csolid/C0
0.2

0.1
10−1
0.05

0.01
10−2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Fraction solidified
Fig. 16.3  Dopant distribution vs fraction solidified

Example 16.1  A Si crystal is grown from the melt to contain 1017 phosphorus
atoms/cm3. Assume kd = 0.35, density of Si is 2.33 g/cm3.
(a) What should be the initial concentration of phosphorus atoms in the
melt?
(b) Assume the initial melt is of 6 kg. What is the amount of P to be added to
the melt? Atomic weight of P is 31.

Solution
(a) Initial concentration of P in the melt is

Csolid 1017
Cliquid = = = 2.857 × 1017 / cm 3
kd 0.35

Mass 6000
(b) Volume of the melt = = = 2.575 × 103 cm 3
Density 2.33

Number of dopant atoms in the melt = Volume of melt × Dopant concentration

= 2.857 × 1017 × 2.575 × 103
= 7.357 × 1020
 502  VLSI Design

Number of P atoms × Atomic weight of P 7.357 × 10 20 × 31

Therefore, the amount of P = = =
Avogadro’s number 6.023 × 10 23

Number of P atoms × Atomic weight of P 7.357 × 10 20 × 31

= = 0.0379 g
Avogadro’s number 6.023 × 10 23

16.2.4  Float-zone Technique

Float-zone technique is used to grow a single
crystal silicon. The arrangement is shown in
Fig. 16.4. Poly Si rod
The polycrystalline silicon rod is kept verti-
cal. A radio frequency (RF) coil is used to heat RF coil
a small region and the region is melted. The
Molten zone
impurities which prefer to stay in liquid than in
solid come into the melt. As the molten zone is Single crystal
moved upward, it continues to become enriched
with impurities and the crystal freezes from bot- Seed
tom with less or no impurity. The molten zone is
moved along the length of the rod starting from
the bottom seed and the crystal grows with the
plane of the seed. This process achieves a high Fig. 16.4  Float-zone technique
purity single crystal silicon.

16.2.5  Bridgman Technique

In this technique, the Ge and GaAs single crystal is grown. The molten Ge is taken in
a crucible and a small seed crystal is placed at one end. The crucible is pulled slowly
in the horizontal direction. As the molten zone moves out of the furnace, it is slowly
cooled, and the Ge solidifies following the seed crystal. This technique is known as
the horizontal Bridgman technique. The arrangement is shown in Fig. 16.5.
Seed Crystal Melt

Pull
Furnace
Crucible

RF heater
Fig. 16.5  Bridgman crystal growth technique
16.2.6  Wafer Preparation
An ingot is cut into thin slices which are known as wafers. Before the ingot is
sliced, there are several steps. First, both the ends of the ingot are removed and
its surface is ground so that any diameter variation is made constant. Then, the
primary and secondary flat regions, as shown in Fig. 16.6 are cut along the entire
 VLSI Process Technology  503

length of the ingot. These flat regions are cut to identify the type (p-type or n-type)
of the wafer and crystal orientation. The primary flat gives mechanical stability
to the wafer when it undergoes further processing steps. The ingot is then sliced
into wafers. A diamond tipped saw is used to slice the ingot. The sliced wafers are
again lapped for better flatness. A mixture of glycerin and Al2O3 is used for the
lapping purpose. The lapped wafers are finally polished once again to get a smooth
surface so that the microelectronic devices can be fabricated using the photoli-
thography technique. Typical wafer diameters are 5, 6, 8, and 12 inch. The wafer
thickness is about 500–775 μm depending on the wafer diameter.

Secondary flat

Primary flat
(a) (b) (c)
Fig. 16.6  Wafers: (a) with primary flat; (b) with both primary and secondary flats

16.2.7  Wafer Characterization

The electrical, optical, and mechanical characteristics of a crystal are strongly
dependent on the crystal imperfections or defects. There are four different types
of defects in a crystal:
n Point defects, such as
– Substitutional
– Interstitial
– Vacancy
– Frenkel
n Line defects or dislocations, such as
– Edge
– Screw
n Area defects, such as
– Twins
– Grain boundaries
n Volume defects

After the crystal growth, the wafers are cut and they are characterized for mobility,
lifetime, and resistivity. Mobility is characterized using the Hall effect measure-
ment. The lifetime is characterized using the ‘Haynes–Shockley’s experiment’.
The resistivity is measured using a standard technique called four-probe technique.

16.2.8  Mobility
The mobility of a carrier in an electric field E, moving with drift velocity vd is
given by
vd
µ= (16.10)
E
504  VLSI Design

The drift current density J is given by

J = nevd = neµ E = σ E (16.11)
where n is the carrier concentration, e (=1.6 × 10–19) the electronic charge, and σ
is the conductivity. The resistivity is given by
1 1
ρ= = (16.12)
σ neµ

Example 16.2  Calculate the resistivity of n-type Si having doped with 1017
phosphorous atoms/cm3. Assume mobility of electron as 580 cm2/V s.
Solution  The resistivity of n-type Si for the given data is

1 1
ρ= = = 0.10776 Ω cm
 neµ 1017 × 580 × 1.6 × 10 −19

16.2.9  Hall Effect

The carrier concentration n is measured by the Hall effect. The carrier concentra-
tion is given by
I x Bz
n=− (16.13)
etVAB

where Ix is the applied current in the x-direction, Bz is the applied magnetic field in
the z-direction, t is the thickness of the material, and VAB is the voltage established
due to the Hall effect. The Hall effect is illustrated in Fig. 16.7.

Bz Ix
z

y C

x
(+) (−)
A B
Ey
L

t D

w
Ix

Fig. 16.7  The Hall effect

By measuring the Hall voltage VAB, we can measure the carrier electron concentra-
tion according to Eqn (16.13).
 VLSI Process Technology  505

The type of a sample, i.e., n-type or p-type is also determined by Hall’s experi-
ment by measuring the sign of the Hall voltage. For p-type material, the Hall volt-
age is positive, and for n-type material, the Hall voltage is negative.
The Hall coefficient RH is given by
1
RH = − (16.14)
ne
Combining Eqns (16.12) and (16.14), we obtain
RH
µ= (16.15)
ρ
Hence, the mobility of electrons can be measured by measuring the Hall coef-
ficient and the resistivity of the material. For bulk semiconductor, Eqn (16.15) is
used to measure the mobility. But for two-dimensional (2D) semiconductor (e.g.,
electrons in the inversion layer in a MOSFET), mobility of electrons is aniso-
tropic. In the 2D systems, Haynes and Shockleys proposed methodology is used
to directly measure mobility.

Example 16.3  A p-type Si sample with doping density 1016 atoms/cm3 is using
Hall experiment under the following conditions. Calculate the Hall voltage.
Ix = 2  mA,  Bz = 10−5  Weber/cm2,  and thickness,  t = 100 μm

Solution  We calculate the Hall voltage developed in the sample as follows:

I x Bz RH I B 2 × 10− 3 × 10− 5
V= =− x z =− −19 16 −4
= − 1.25 × 10 − 3 V
 t en0t 1.6 × 10 × 10 × 100 × 10

16.2.10  Haynes–Shockley Experiment

An electric field is applied along the length of the bar as shown in Fig. 16.8(a).
Through the emitter contact, a pulse of holes (minority carrier) is injected into the
bar. The hole pulse drifts towards the collector contact. While drifting, the pulse
spreads out due to diffusion as shown in Fig. 16.8(b). At the collector end, the hole
pulse is collected and observed using an oscilloscope.
If the hole pulse takes t amount of time to drift through the length d, we can
write drift velocity as
d
vd = (16.16)
t

Hence, mobility of the holes can be expressed as

vd d d
µp = = = (16.17)
E Et (V/L)t

where V is the applied sweep voltage and L is the length of the bar.
506  VLSI Design

x
Emitter Collector
Injection Collector
voltage voltage
n-Type
Sweep
Oscilloscope
voltage
d
L
(a)

t=0 t = t1 t = t2 t = t3

(b)
Fig. 16.8  (a) Experimental set-up of Haynes–Shockley experiment; (b) spreading of hole pulse

Measuring the drift time t, the mobility of the minority carrier (hole) can be meas-
ured using Eqn (16.17).

16.2.11  Lifetime Measurement

As shown in Fig. 16.8(b), it is observed that the pulse amplitude decreases and the
pulse width increases as the pulse drifts towards the collector end. The amplitude
decreases due to the recombination of holes with the majority carrier electrons
present in the bar. The lifetime is defined as the time that a carrier survives before
it recombines with the opposite polarity carrier. Hence, the pulse drift time can
give a measure of the hole lifetime. The lifetime (τp) is given by
eτp
µp = (16.18)
mp*

where m*p is the effective mass of the hole. Using Eqn (16.18), the lifetime (τp) can
also be measured knowing the mobility and effective mass of the carrier.

16.2.12  Resistivity of the Semiconductor

The resistance of a rectangular slab of semiconducting material, as shown in
Fig. 16.9 is given by
l l ρ l l
R=ρ =ρ = × = ρs × (16.19)
A w×t t w w
where ρ is the resistivity of the material and ρs = ρ t is the sheet resistance of the
material. The unit of sheet resistance is ohm per square.

Four-probe Technique
Resistivity of a semiconducting material is measured by a technique called four-
probe technique. The technique is depicted in Fig. 16.10.
 VLSI Process Technology  507

w
1 2 3 4
P
s s s
r
l

t d

Fig. 16.9  A conductor of length l, width Fig. 16.10  Four-point probe technique to
w, and thickness t  measure resistivity

In the four-probe technique, four-point probes are placed on the semiconducting

substrate with a spacing s. A constant current source carrying a small current (I)
is connected between the outer two probes. A voltmeter is connected between the
inner two probes to measure the voltage. The resistivity of the sample can be ob-
tained from the measured voltage and known current.
Let us consider a point P at a distance r from the first probe. The voltage at
point P is given by
ρI
V= (16.20)
2π r
where ρ is the resistivity of the semiconducting material. With respect to zero ref-
erence potential, the voltage measured is given by

ρ I  1 1  (16.21)
V0 = −
2π  r1 r4 

where r1 and r4 are the distances from probes 1 and 4, respectively.

The voltage at probe 2 is given by

ρ I  1 1  (16.22)
V2 = −
2π  s 2s 
The voltage at probe 3 is given by

ρ I  1 1  (16.23)
V3 = −
2π  2s s 
The measured voltage (V) between the probes 2 and 3 is given by
ρI 1
V = V2 − V3 = × (16.24)
2π s
508  VLSI Design

Hence, the resistivity ρ is given by

V
ρ = 2π × s   (16.25)
I
The above derivation is valid for semi-infinite dimension. As the wafers are finite
in both horizontal and vertical dimensions, Eqn (16.25) needs to be corrected. By
introducing a correction factor (CF), we can rewrite Eqn (16.25) as
V
ρ = 2π × s × CF ×   (16.26)
I
Typically CF = 4.532 for d/s > 20.

Example 16.4  In a four-probe technique, resistivity of n-type Si is measured

with the following parameters. Find out the resistivity of the material.
Probe spacing, s = 0.5 mm
Probe radius = 30 μm
V = 10 mV
I = 0.4 mA
Solution  Resistivity can be written from Eqn (16.26),

V  10 × 10 −3 
ρ = 2π s × CF ×   = 2π × 0.5 × 10 −3 ×   = 0.356 Ω m
I  0.4 × 10 −3 

16.3  Photolithography
Photolithography is the technology to create a pattern on the silicon wafer using an
ultraviolet (UV) ray of light. The steps are shown in Fig. 16.11.

SiO2
Step 1 Si wafer

Photoresist
Step 2

UV light

Mask
Step 3

Pattern
Step 4 photoresist

Strip
Step 5
resist
Fig. 16.11  Photolithography process: creating patterns on the photoresist, pattern transfer from
the photoresist to the SiO2 layer by etching (see Plate 7)
 VLSI Process Technology  509

The components of the photolithography process are as follows:

n Si wafer
n Photoresist—a light-sensitive material
n Lens
n Mask (for each layer to be patterned) with the desired pattern
n UV light source and method of projecting the image of the mask onto the
photoresist
n Developer solution—a method of ‘developing’ the photoresist, i.e., selectively
removing it from the regions where it was exposed
The wafer is first cleaned and silicon dioxide (SiO2) layer is deposited on the sur-
face of the wafer. The wafer is then coated with the photoresist on the top. Then
the UV light is projected on the wafer through the mask and a lens. The mask has
certain regions transparent and other regions opaque. The transparent regions of
the mask allow the UV light to pass through and fall on the photoresist. Depending
on whether the photoresist is positive or negative, it undergoes some chemical
changes and becomes more soluble or less soluble in an etchant solution. A pattern
is formed on the photoresist. For positive photoresist, the pattern is the same as the
mask, and for negative photoresist, the pattern is the inverse of the mask.
The wafer is dipped into a developer solution. The soluble part of the ­photoresist
and the underneath SiO2 layer are etched out. The photoresist is then stripped off
and the replica of mask is formed on the SiO2 layer.
16.3.1  Exposure Techniques
There are mainly two types of exposure techniques:
n Shadow printing
– Contact printing
– Proximity printing
n Projection printing

In the shadow printing, the wafer and the mask are either in direct contact or sepa-
rated by a small gap. But in projection printing, the wafer and the mask are separated
by a large distance, typically few centimetres away. Shadow printing is again of two
types: contact printing and proximity printing. In contact printing, the mask and the
wafer are in direct contact, whereas in proximity printing the mask and the wafer
are separated by a small gap. The exposure mechanisms are illustrated in Fig. 16.12.
In shadow printing, the minimum feature size that can be patterned depends on the
wavelength (l ) of the light used for exposure and the gap (g) between the mask and
wafer. The minimum feature size is called critical dimension (CD) and is given by
CD = λ g (16.27)
For projection printing, the resolution of the projection system is given by

λ
lm = k1 (16.28)
NA
where k1 is a constant (typically k1 = 0.6) that depends on the process, and NA is
the numerical aperture of the lens.
510  VLSI Design

Contact Proximity Projection

Light source

Lens
Mask
Photoresist
SiO2
Si wafer

(a) (b) (c)

Fig. 16.12  Schematic diagram of (a) contact printing; (b) proximity printing; and
(c) projection printing
The depth of focus (DOF) is given by

λ (16.29)
DOF = k2
( NA)2
where k2 is another constant (0.5 < k2 < 1.0) that depends on the process.
Figure 16.13 illustrates the numerical aperture of a lens and a projection imag-
ing system
DOF
(Focal plane)
Aperture
R q
Object lm
q f
Image
Focal plane Focal plane

(a) (b)
Fig. 16.13  (a) Numerical aperture of a lens; (b) projection image system

16.3.2  Comparison between Different Exposure Systems

n Limitations of contact printing are reduced mask life, high defect density in the
printed pattern, and introduction of defects in the resist and the mask.
n In proximity printing, a small gap between mask and photoresist eliminates
defects as there is no direct contact. But the disadvantages are increased diffraction
effects and hence, a limit on the minimum feature size that can be printed.
n Projection printing is commonly used. The wafer is separated from the mask by
several centimetres.
n Advantages of projection printing are an increased mask life and the features on
the reticle do not have to be as small as the final image.

16.3.3  Clean Room

The IC fabrication requires a specially designed clean environment which is gen-
erally called a clean room. As the device dimension is very small, any tiny dust
 VLSI Process Technology  511

particle can cause disruption in the device processing. Therefore, a clean room
environment is a must for IC fabrication. A clean room is defined by class: one in
the British system and another in the metric system. In the British system, a class
10 clean room indicates there are 10 particles/ft3 with particle diameter of 0.5 μm
or larger. Similarly, a class M 2.544 clean room, in the metric system, indicates
102.544 = 350 particles/m3 with particle diameter of 0.5 μm or larger.
Table 16.2 shows the typical particle size and number for the different classes
of a clean room.
Table 16.2  For different classes of a clean room; number of particles/ft3
Class 0.1 μm 0.2 μm 0.3 μm 0.5 μm 5 μm
1 3.5 × 10 7.5 3.0 1.0
10 3.5 × 102 7.5 × 10 3.0 × 10 1.0 × 101
100 7.5 × 102 3.0 × 102 1.0 × 102
1000 1.0 × 103 7.0
10000 1.0 × 104 7.0 × 10

16.3.4  Mask
The mask is the photocopy of the layout generated at the end of the physical de-
sign step in the VLSI design flow. The layout information is transferred onto the
mask using a pattern generator. The mask is made of fused silica covered with a
chromium layer.

16.3.5  Resolution Enhancement Techniques

As the VLSI process technology advances, the device and interconnect dimen-
sions scale down. In the sub-micron and nanometer regime, the printability and
process window of the finer lithographic patterns are significantly reduced due to
the fundamental limit of the micro/nano lithography systems and process varia-
tions. Till now, the 193 nm lithography systems are used to print sub-wavelength
feature size (e.g., 65 nm or even 45 nm); with the aid of various resolution en-
hancement techniques (RET), as given by
n Optical proximity correction (OPC)
n Phase shift mask (PSM)
n Off-axis illumination (OAI)
n Sub-resolution assist feature (SRAF) insertion

These techniques modify illuminations, mask patterns, or transmissions.

16.3.6  Photoresist
It is a photosensitive polymer that is used to create patterns by the use of solvents
after irradiation. It is of two types: positive photoresist (PPR) and negative pho-
toresist (NPR).

Positive Photoresist
On exposure to light it becomes more soluble. It consists of a resin and a photoac-
tive compound dissolved in an organic solvent. The unexposed regions are insoluble
512  VLSI Design

in the developer solution. Upon exposure, the chemical structure is changed and it
becomes more soluble in the developer solution. The exposed regions are removed.

Negative Photoresist
On exposure to light it becomes less soluble. It consists of a chemically inert poly-
isoprene rubber and a photosensitive compound. Its disadvantage is that the exposed
resist has low molecular weight, so it swells as the unexposed part is dissolved in,
developer solvent. The swelling distorts the pattern features which limits the resolu-
tion. Advantages are: (a) resistance to etching and (b) good adhesion to the substrate.

16.3.7  Pattern Generation

The mask is the design created using Layout Editor where the user specifies layout
objects on different layers. The layout information is stored in a file called layout
file. Generally, the GDSII format is used for layout file.
The pattern generator reads the layout file, and generates an enlarged master
image of each mask layer, and the image printed on glass. The step and repeat
camera is used for this purpose. It reduces the image and copies the image onto
the mask, one copy for each die on a wafer. While overlapping masks of different
layers, the alignment of masks is of great concern.
The most common layers used in the layout are given in Table 16.3.

Table 16.3  Mask layers

Sl. No. Layer Colour Purpose Note
1. Metal1 Blue First metal layer
2. Poly Red Poly-Si
3. Active Green
4. n-select Hashed blue
5. p-select Dotted red
6. n-diff Green n-diffusion Combination of
active, n-select
7. n-transistor Green/red crosshatch nMOS Combined poly, n-diff
8. p-diff Brown p-diffusion Combination of active,
p-select
9. p-transistor Brown/red crosshatch pMOS Combined poly, p-diff
10. Polycontact Black polymetal contact
11. Active Black Metal—semiconductor
contact contact
12. n-well Hatched black n-well

16.3.8  Optical Proximity Correction

The small shapes that are nearly equal to the resolution limit of the photolithogra-
phy system are modified when it is transferred. For example, a small square hole
becomes a small circle. This is illustrated in Fig. 16.14.
To avoid this problem, the layout is modified near the bends and corners. The
corners are over-shaped and the bends are under-shaped.
 VLSI Process Technology  513

(a) (b) (c)

Fig. 16.14  (a) Layout without optical proximity correction (OPC); (b) image pattern
of layout without OPC that is transferred; (c) layout with OPC

16.4  CMOS Technology: n-well and p-well Process

The CMOS process technology has the capability of fabricating both nMOS and
pMOS on the same wafer. The substrate region of an MOS device is ­oppositely
doped to that of the channel type. An nMOS device requires p-type substrate where-
as a pMOS device requires n-type substrate. To accommodate both types of MOS
devices on a single substrate (either p-type or n-type) special regions are created
which are known as wells. If the substrate is of p-type then n-type well is created
which is called n-well. If the substrate is of n-type then p-type well is created which
is called p-well. The cross-sectional view of a CMOS inverter is shown in Fig. 16.15.
It illustrates how an nMOS transistor is created on the p-type substrate and n-well is
created on the p-type substrate to create pMOS transistor.
Input

VDD

Body/ Output Body/

Bulk Source Gate Drain Drain Gate Source Bulk

Poly silicon Poly silicon

VSS Oxide Oxide

p+ n+ n+ p+ p+ n+

Substrate (p-type) n-well (n-type)

Fig. 16.15  Cross-sectional view of CMOS inverter

16.5  Oxidation
Silicon is the most popular semiconductor for IC fabrication because of its native
oxide SiO2. SiO2 has excellent insulating properties. A very good quality oxide
can be grown on the Si substrate. SiO2 has a number of uses in the IC fabrication
process. Some of its important uses are as follows:
n SiO2 acts as a protecting buffer layer during device fabrication.
n It is used for device isolation.
n It is used in the MOSFET device (gate oxide).
n It is used for interconnected isolation (field oxide, FOX).
514  VLSI Design

Oxidation is the process of growing the SiO2 layer on top of the Si substrate. Two
types of oxidation techniques are generally used:
n Thermal growth (has excellent quality)
– Dry oxidation
– Wet oxidation
n Chemical vapour deposition (required to put SiO2 on materials other than Si)

The oxidation process starts from the top surface of the Si wafer and it slowly pen-
etrates into the wafer. The separation line between the Si substrate and the grown
SiO2 layer is known as the Si–SiO2 interface. The quality of oxide and the Si–SiO2
interface greatly influences the behaviour of the MOSFET device. A layer called
SiOx (0 < x < 2) at the interface between Si and SiO2 is formed due to unsaturated
Si bonds. These unsaturated bonds are called dangling bonds, and they behave like
traps at the interface. The traps have energy states within the bandgap energy of Si,
which are known as interface states.

16.5.1  Dry Oxidation

The chemical reaction that governs the dry oxidation is expressed as
Si + O 2↑ → SiO 2 (16.30)
The reaction takes place in the temperature range 900°C–1200°C.

16.5.2  Wet Oxidation

In the wet oxidation technique, water vapour is reacted with the Si layer and the
chemical reaction is expressed as
Si + 2H 2 O ↑ → SiO 2 + 2H 2 ↑ (16.31)

In the thermal growth process, O2 or H2O diffuses

through SiO2, and reacts with Si at the interface to
form more SiO2 layers. The reaction takes place in
the temperature range from 700°C to 1100°C. To tox t
form a SiO2 layer of thickness (tox) 1 µm, it consumes
Si layer of thickness 0.44 µm (May and Sze, 2004).
t
Initially, as oxide starts to grow, the grown oxide
thickness (tox ) linearly increases with time (t). After t
a certain thickness is grown, the growth becomes Fig. 16.16  Oxide thickness as
parabolic. This is illustrated in Fig. 16.16. a function of time

16.5.3  Chemical Vapour Deposition

Chemical vapour deposition (CVD) is another technique by which the SiO2 layer
can be grown. But it does not produce high quality oxide as in the thermal oxida-
tion technique. The oxide grown using CVD technique is utilized for metal level
isolation, as a mask during photolithography.
Temperature range:
n 300°C–500°C for SiH4 (silane)
n 500°C–800°C for TEOS (tetraethylorthosilicate)
 VLSI Process Technology  515

Process:
n Precursor gases dissociate at the wafer surface to form SiO2
n No Si on the wafer surface is consumed
n Film thickness is controlled by the deposition time

The chemical reactions are given by

700° C
Si(C2 H 5O)4 + 2H 2 O → SiO 2 + 4 C2 H 6 O (16.32)

450° C
SiH 4 + O 2 → SiO 2 + 2H 2 (16.33)

In the CVD technique, oxide thickness grows linearly

with time as indicated in Fig. 16.17.
tox
t
16.5.4  Thin Oxide
An oxide having thickness 20 nm or lesser is called
thin oxide. Thin oxides are used as a gate oxide layer t
in the MOSFET structure. Thin oxides are grown us- Fig. 16.17  Oxide thickness
ing the dry oxidation technique, as dry oxidation pro- as a function of time in the
duces a very good quality oxide. But the dry oxidation CVD process
process is very slow compared to the wet oxidation
technique.

16.5.5  Thick Oxide

An oxide having thickness 20 nm or more is called thick oxide. Thick oxides are
grown using the wet oxidation technique. It is fast as compared to the dry oxida-
tion technique, but the quality of oxide is not as good as that produced in the dry
oxidation technique. Thick oxides are used as field oxide.

16.6  Diffusion
The introduction of doping atoms into the semiconductor can be done by two tech-
niques: (a) diffusion and (b) ion implantation. Diffusion is a process of displace-
ment of particles or atoms from a high concentration region to a low concentration
region. Using the diffusion process, dopants are introduced into the wafer. An am-
bient is created of the dopant atoms at the surface of the wafer and the temperature
is raised to 800°C–1200°C.
For n-type material, arsenic (As) and phosphorus (P) are used as dopants, and
for p-type material, boron (B) is used as a dopant.

16.6.1  Fick’s Law

The basic diffusion mechanism is expressed by using the Fick’s law of diffusion.
It is given by
∂C ∂ 2C
= D 2 (16.34)
∂t ∂x
where D is the diffusion coefficient and C is the dopant concentration.
516  VLSI Design

16.6.2  Diffusion Profile

The diffusion profile is a function of the initial and boundary conditions of dop-
ing. Based on the boundary conditions, the diffusion process is classified into two
processes:
n Constant surface concentration
n Constant total dopant

In the constant surface concentration diffusion process, the dopant supply is

maintained so that dopant concentration at the surface of the substrate is kept
constant, whereas in the constant total dopant diffusion process, the total num-
ber of dopant atoms is fixed. Applying the boundary conditions, for these cases
to the Fick’s diffusion law yields two solutions, and two profiles of dopants
distribution. For the constant surface concentration diffusion, the profile follows
an error function. For the constant total dopant diffusion, the profile follows the
Gaussian distribution. The diffusion depth is dependent on the time and tem-
perature used for diffusion.
Readers are suggested to refer May and Sze (2004) for details.

16.7  Ion Implantation

Ion implantation is another technique for introduction of impurities into the surface of
the Si wafer or substrate. Individual dopant atoms are first ionized and they are accel-
erated. The accelerated ions impinge on the surface and penetrate into the substrate.
Advantages of ion implantation:
n Very precise control of impurity numbers is possible
n Low processing temperature
n Short processing time
n Low penetration depth of the implanted ions
n Implantation through thin layers (e.g. SiO2, Si3N4) is possible.

16.7.1  Ion Stopping

When the projected ions travel inside the substrate, they undergo several colli-
sions with the electrons and the nucleus of the host atoms. During the collision
process, they lose their energy and finally come to rest. This mechanism is called
ion stopping.

16.7.2  Ion Channelling

When the projected ions enter into the substrate, they get aligned with the gap
between the host atoms, and they travel a large distance before finally coming to
rest. This phenomenon is called ion channelling. Due to the ion channelling ef-
fect, the ions become uncontrollable and hence, the junction depth goes beyond
control. There are several mechanisms to avoid the ion channelling effect. These
are given as follows:
n Using an amorphous blocking layer
n Disorienting the wafer
n Creating a damaged layer at the wafer surface
 VLSI Process Technology  517

16.7.3  Implantation Damage and Annealing

In the ion implantation process, when the highly energetic ions enter into the lat-
tice, they suffer several collisions with the host atoms. Due to the collision mecha-
nism, the host atoms are displaced from their original positions. If the number of
displaced atoms per unit volume becomes comparable to the atomic density of the
material, it loses its crystalline property and becomes amorphous material. This
fact is known as lattice damage.
To rectify the damage caused by ion implantation, a methodology is used which
is known as annealing. Annealing heals most of the damage. In this process, the
wafer is treated alternately in very high and low temperature for a long time.

16.8  Etching
Etching is the process of selective removal of some portions of a layer. The photoli-
thography technique is used to create patterns on the Si wafer. It involves the etch-
ing process which removes the selected portion of a layer. Etching is of two types:
n Isotropic—etch rate is same in all directions
n Anisotropic—etch rate is not same in all directions

Figure 16.18 illustrates the anisotropic and isotropic etching process.

Slow etching
(111) crystal plane
Etch mask

l v

Anisotropic Isotropic
Fig. 16.18  Anisotropic and isotropic etching
The degree of anisotropy is defined as
l
A = 1− (16.35)
v
where l is the lateral etch distance and v is the vertical etch distance.

16.8.1  Wet Chemical Etching

An etchant is a chemical solution that reacts with the layer that needs to be etched
out. Depending on the material to be etched out, the chemical solution differs. The
etchant solution is either sprayed on the wafer, or the wafer is dipped into the etchant
solution. This type of etching is known as wet chemical etching. Wet chemical etch-
ing is isotropic in nature. In this process, the etch rate is the same in all directions.
An example of anisotropic etching is the etching of <111> crystal plane which
results in V-shaped sidewalls when etched a hole in a <10 0> Si wafer in potassium
hydroxide (KOH) solution. This is illustrated in Fig. 16.18.
518  VLSI Design

16.8.2  Dry Etching

There are three types of dry etching process: (a) reactive ion etching (RIE),
(b) sputter etching, and (c) vapour phase etching. Dry etching process is expen-
sive compared to wet etching. Dry etching is used when vertical side walls are
required, or when thin films with small feature resolution are to be obtained. Dry
etching is also known as plasma etching. Plasma is a mixture of ionized and union-
ized gas molecules. It is produced by applying a very high electric field to a gas.

Reactive Ion Etching

In reactive ion etching (RIE), the substrate is placed inside a reactor in which several
gases are injected. Plasma is created in the gas mixture using an RF power source,
breaking the gas molecules into ions. The plasma ions move towards the surface and
react with the material being etched to form another gaseous material. This is known
as the chemical process of reactive ion etching. There is another part which is called
the physical part, which is similar in nature to the sputtering deposition process. If the
ions have high energy, they can knock out atoms of the material to be etched without
a chemical reaction. The chemical process is isotropic, and the physical process is an-
isotropic in nature. Combining the physical and chemical processes, it is possible to
control the anisotropy of the etching to form sidewalls that have shapes from rounded
to vertical. A schematic of a reactive ion etching system is shown in Fig. 16.19.
Wafers RF signal
insulator
Upper electrode

Plasma Lower electrode

Wafer holder

Diffuser nosles
Gas Pump Gas
Fig. 16.19  Plasma etching
Sputter Etching
Sputter etching is basically RIE without reactive ions. The process is very similar
to the sputtering deposition process. The only difference is that substrate is now
subjected to the ion bombardment instead of the material target used in sputter
deposition.

16.9  Epitaxial Growth

In this growth technique, thin layers of material can be grown on a substrate. A
material with similar lattice structure other than the substrate material can also
be grown using this technique. As thin layers are grown on a substrate wafer, this
technique is known as epitaxial growth or simple epitaxy.
There are several methods of epitaxial growth as follows:
n Chemical vapour deposition (CVD)
n Liquid phase epitaxy (LPE)
 VLSI Process Technology  519

n Physical vapour deposition (PVD)

n Molecular beam epitaxy (MBE)
For epitaxial growth, the important requirement is that the lattice constant of the
substrate layer and the lattice constant of the layer to be grown should match.
For example, the lattice constant of GaAs and AlAs are ~5.65 Å. Hence, the
epitaxial layer of AlxGa1–x As can be grown on the GaAs substrate for any com-
position x (0 ≤ x ≤ 1.0).
Advanced epitaxial growth is used to grow very thin layers of lattice with slightly
mismatched crystals. The grown layer is formed with a substrate lattice constant and
hence, the atoms in the grown layer are either compressed or elongated. So they are
called strained layer. Such a structure is called strained-layer super-lattice (SLS).

16.9.1  Chemical Vapour Deposition

Chemical vapour deposition (CVD) is also called vapour phase epitaxy (VPE).
In this process, the chemical compounds of the material to be grown is reacted
with other gas molecules and the released material is deposited on the sub-
strate. For example, for Si epitaxial growth, four different compounds of Si can
be used in the CVD process. They are silane (SiH4), trichlorosilane (SiHCl3),
dichlorosilane (SiH2Cl2), and silicon tetrachloride (SiCl4). A typical reaction is
expressed as
1200°C
SiCl 4↑ + 2 H 2↑ ← → Si + 4 HCl ↑ (16.36)

Diborane (B2H6) is used for p-type dopant, and phosphine (PH3) and arsine (AsH3)
are used for n-type dopant.
Advantages of CVD are as follows:
n Uniform step coverage
n Precise control of the composition and structure
n Fast deposition rate
n High throughput
n Low processing cost

16.9.2  Metalorganic CVD (MOCVD)

Metalorganic CVD (MOCVD) or organometalic CVD (OMCVD) is a technique
to grow epitaxial layers from metalorganic compounds. For example, GaAs is
grown from its chemical compound trimethylgallium [(CH3)3Ga].

(CH3 )3 Ga + AsH3 → GaAs + 3CH 4 (16.37)

700°C

Trimethylgallium (TMGa) reacts with Arsine (AsH3), and produces GaAs and
methane. The epitaxial layer of GaAs is achieved of very high quality. Similarly,
­diethylzinc [DEZn, (C2H5)2Zn] and diethylcadmium [DECd, (C2H5)2Cd] are
used to introduce for p-type dopants in GaAs, and trimethylaluminium [TMAl,
(CH3)3Al] is used along with TMGa to grow AlGaAs.
Several thin layers of different material can be grown using this technique. The
arrangement of the MOCVD system is shown in Fig. 16.20. MOCVD is used to
grow hetero-structured and nano-structured devices.
520  VLSI Design

H2
Growth line

Mass-flow TMGa
controller Heated
RF wafer
coil
TMAI

DEZn
AsH3
Dopant Vent line
Exhaust

Fig. 16.20  MOCVD system

16.9.3  Molecular Beam Epitaxy

Molecular beam epitaxy (MBE) is a very useful technique to grow epitaxial layer
on a substrate. It can be used to grow epitaxial layers composed of different mate-
rials. It is done in an evacuated chamber at very low pressure. The doping profile
and the chemical compositions of the epitaxial layer can be precisely controlled. It
is a very popular technique to grow hetero-structure and nano-structured devices.
Figure 16.21 illustrates the arrangement of the MBE system.

Heater
Wafer

Heating Shutter
coil
Effusion
cells

Dopant
Dopant
Al As
Ga Vacuum
chamber

Fig. 16.21  MBE system

16.9.4  Physical Vapour Deposition

One of the PVD techniques is known as sputtering. It is used to deposit metal (Al)
films required for metallization. Highly energetic Argon (Ar) ions hit the surface
of a metal target, knocking atoms loose, which then land on the surface of the
­wafer. Sometimes the substrate is heated to ~300°C. Gas pressure is kept between
1 to 10 mTorr. The deposition rate is proportional to the ion current (I) and the
sputtering yield (S). Figure 16.22 illustrates the sputtering technique.
 VLSI Process Technology  521

Negative bias
I
Al target

Al Ar + Ar + Al
Ar plasma
Al

Al film

Wafer
Fig. 16.22  PVD technique

16.10  Metallization
After completion of all the device fabrication, the next important step is the metalli-
zation process. In this process, the contacts between different layers and the intercon-
nect layers are formed. Metallization is done using the CVD and PVD techniques.
The photolithography technique is used to create patterns of interconnect layers.
The gate electrode of the MOSFET is often fabricated using poly-Si which is
the polycrystalline form of Si. The CVD technique is used to grow poly-Si layers
(see Fig. 16.23).
600°C
SiH 4 → Si + 2H 2 ↑ (16.38)

The wafer is heated to ~600°C and Si-containing gas silane (SiH4) is injected into
the furnace.
Si film made up of crystallites

SiO2

Silicon wafer

Fig. 16.23  Poly-Si deposition using the CVD technique

Poly-Si is used for gate electrode of MOSFET because of the following advantages:
n Easy to deposit poly-Si layer on SiO2 layer as they have similar lattice
constants.
n Similar thermal expansion coefficient gives rise to similar thermal expansion
and hence, better mechanical stability.
Metal is used for interconnects because of high conductivity. Aluminium (Al) and
copper (Cu) are mostly used materials for interconnects. Poly-Si is used for short
interconnects. In VLSI circuits, interconnects cannot be completed in one or two
metal levels. They use multilevel metallization, as shown in Fig. 16.24.
Metallization of interconnects imposes the following considerations for deep
submicron technologies:
n Must not exceed maximum current density to be limited to avoid electromigration
problem.
522  VLSI Design

Metal 3
Via 2
Metal 2
Via 1
Metal 1

(a) (b)

M6

Via5
Cu
M5
Low-k between wires Via4
Via1 M4
Via3
M1 M3
Via2
Contact (W)
M2
Silicon

(c)
Fig. 16.24  Multilevel metallization: (a) 3-level metal connection to n-active without stacked vias;
(b) 3-level metal connection to n-active with stacked vias;
(c) 6-level metal interconnect (see Plate 8)

n However small, the interconnect has some resistance, giving rise to ohmic drop
or IR drop which must be managed.
n Two metal interconnects separated by an insulator or dielectric introduce
parasitic capacitances, which must be managed to avoid the crosstalk problem.
n Interconnects from high to low level metals require connections to each level of
metal through vertical interconnects called via.
n Stacked vias are permissible in some processes.
n Silicides are used to reduce resistance, however, silicides are not used when
interconnects are used as resistors.

16.11  Packaging
Packaging is the last step of the IC manufacturing process. The VLSI circuit (all
the devices and their interconnections) is fabricated on a die. The die is packaged
in a suitable compound material. A package provides
n Protection to the die from the environmental damage
n Interface to the outside world, i.e., system
n Power to the internal circuits
n Cooling of heat generated due to power dissipation
 VLSI Process Technology  523

(a) (b) (c)

(d) (e) (f)

Fig. 16.25  IC packages: (a) PDIP—plastic dual in-line; (b) SOIC—small outline integrated circuit;
(c) TSSOP—thin shrink small outline package; (d) PLCC—plastic lead chip carrier;
(e) TQFP—thin quad flat package; (f) BGA—ball grid array

Figure 16.25 shows different IC package types.

Packaging involves two phases: (i) package design and (ii) package modelling.
These are discussed in detail in Chapter 13.

16.11.1  Die Separation

ICs are manufactured in a batch. In a single wafer there are a number of dies. Each die
has the complete VLSI circuit fabricated on it. After the die is fabricated, the dies are to
be separated from each other. This is called die separation. Typically, a diamond tipped
scriber is used to draw scribe lines along the boundary of the die. Modern technologies
use a diamond saw to separate the dies from the wafer. The dies are then packaged.

16.11.2  Package Types

Depending on the material used for packaging and the structure of package pins,
the IC packages are classified as follows:
n Pin-through-hole (PTH)—dual in-line package (DIP)
n Surface mount technology (SMT)—quad flat pack (QFP)
n Pin grid array (PGA)
n Ball grid array (BGA)
n Flip-chip

Figure 16.26 describes the package classifications in detail.

Most common IC packaging materials are plastic, ceramic, laminates (fiber-
glass, epoxy resin), metal, etc.
Chips are often ‘pad-limited’. Chip area increases as the square of the number
of pads. Hence, package design is the equally important as the circuit design.
The bond pads of the die are connected to the package pins by three ­well-defined
methods as follows:
n Wire bonding
n Tape-automated bonding (TAB)
n Flip-chip bonding