HT23C256

CMOS 32K×8-Bit Mask ROM

Features
• Operating voltage 2.7V~5.5V • 32768×8 bits of mask ROM
• Low power consumption • Mask options: chip enable CE/CE/OE1/OE1 and
– Operation: 25mA max. (V CC=5V) output enable OE/OE/NC
10mA max. (VCC=3V) • TTL compatible inputs and outputs
– Standby: 30µA max. (VCC=5V) • Tristate outputs
10µA max. (VCC=3V) • Fully static operation
• Access time:150ns max. (VCC=5V) • Package type: 28-pin DIP/SOP
250ns max. (VCC=3V)

General Description
The HT23C256 is a read-only memory with essors, but also eliminates bus contention in
high performance CMOS storage device whose multiple bus microprocessor systems. An addi-
256K of memory is arranged into 32768 words tional feature of the HT23C256 is its ability to
by 8 bits. enter the standby mode whenever the chip en-
For application flexibility, the chip enable and able (CE/CE) is inactive, thus reducing current
output enable control pins can be selected as consumption to below 30µA. The combination of
active high or active low. This flexibility not these functions makes the chip suitable for high
only allows easy interface with most microproc- density low power memory applications.

Block Diagram

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Pin Assignment

Pin Description
Pin Name I/O Description
A0~A14 I Address inputs
D0~D7 O Data outputs
CE/CE/OE1/OE1 I Chip enable/Output enable input
OE/OE/NC I Output enable input
VSS I Negative power supply
VCC I Positive power supply
NC — No connection

Operation Truth Table

Mode CE/CE OE/OE A0~A14 D0~D7
Read H/L H/L Valid Data Out
Deselect H/L L/H X High Z
Standby L/H X X High Z

Note: H=VIH, L=VIL, X=VIH or VIL

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Absolute Maximum Ratings*

Supply Voltage ................................ –0.3V to 6V Storage Temperature ................ –50°C to 125°C
Input Voltage ....................... –0.3V to VCC+0.3V Operating Temperature .............. –40°C to 85°C

*Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maxi-
mum Ratings” may cause substantial damage to the device. Functional operation of this
device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Supply voltage: 2.7V~3.6V Ta=–40°C to 85°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VCC Conditions
VCC Operating Voltage — — 2.7 — 3.6 V
O/P Unload,
ICC Operating Current 3V — — 10 mA
f= 5MHz
VIL Input Low Voltage 3V — VSS — 0.4 V
VIH Input High Voltage 3V — 2.0 — VCC V
VOL Output Low Voltage 3V IOL= 2.1mA — — 0.4 V
VOH Output High Voltage 3V IOH= –0.4mA 2.4 — VCC V
ILI Input Leakage Current 3V VIN= 0 to VCC — — 10 µA
ILO Output Leakage Current 3V VOUT= 0 to VCC — — 10 µA
CE=VIL
ISTB1 Standby Current 3V — — 500 µA
CE=VIH
CE≤0.2V
ISTB2 Standby Current 3V — — 10 µA
CE≥VCC-0.2V
CIN Input Capacitance (See note) — f= 1MHz — — 10 pF
COUT Output Capacitance (See note) — f= 1MHz — — 10 pF

Note: These parameters are periodically sampled but not 100% tested.

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Supply voltage: 4.5V~5.5V Ta=–40°C to 85°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VCC Conditions
VCC Operating Voltage — — 4.5 — 5.5 V
O/P Unload,
ICC Operating Current 5V — — 25 mA
f=5MHz
VIL Input Low Voltage 5V — VSS — 0.8 V
VIH Input High Voltage 5V — 2.2 — VCC V
VOL Output Low Voltage 5V IOL=3.2mA — — 0.4 V
VOH Output High Voltage 5V IOH=–1mA 2.4 — VCC V
ILI Input Leakage Current 5V VIN=0 to VCC — — 10 µA
ILO Output Leakage Current 5V VOUT=0 to VCC — — 10 µA
CE=VIL
ISTB1 Standby Current 5V — — 1.5 mA
CE=VIH
CE ≤ 0.2V
ISTB2 Standby Current 5V — — 30 µA
CE ≥ VCC–0.2V
CIN Input Capacitance (See note) — f=1MHz — — 10 pF
COUT Output Capacitance (See note) — f=1MHz — — 10 pF

Note: These parameters are periodically sampled but not 100% tested.

A.C. Characteristics Ta=–40°C to 85°C

VCC=2.7V~3.6V VCC=4.5V~5.5V
Symbol Parameter Unit
Min. Max. Min. Max.
tCYC Cycle Time 250 — 150 — ns
tAA Address Access Time — 250 — 150 ns
tACE Chip Enable Access Time — 250 — 150 ns
tAOE Output Enable Access Time — 150 — 80 ns
tOH Output Hold Time — — 10 — ns
tOD Output Disable Time (See Note) — — — 70 ns
tOE Output Enable Time (See Note) — — 10 — ns

Note: These parameters are periodically sampled but not 100% tested.

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A.C. test conditions

Output load: see figure right

Input rise and fall time: 10ns
Input pulse levels: 0.4V to 2.4V
Input and output timing reference levels:
0.8V and 2.0V (VCC=5V), 1.5V (VCC=3V)

Output load circuit

Functional Description
The HT23C256 has two modes, namely data • Data read mode
read mode and standby mode, controlled by When both the chip enable (CE/CE/OE/OE1)
CE/CE/OE1/OE1 and OE/OE/NC inputs. and the output enable (OE/OE/NC) are active,
• Standby mode the chip is in data read mode. Otherwise,
active CE/CE and inactive OE/OE/NC result
The HT23C256 has lower current consumption,
in deselect mode. The output will remain in
controlled by the chip enable input (CE/CE).
Hi-Z state.
When a low/high level is applied to the CE/CE
input regardless of the output enable
(OE/OE/NC) states the chip will enter the
standby mode.

Timing Diagrams
• Propagation delay due to address (CE/CE/OE1/OE1 and OE/OE are active)

• Propagation delay due to chip enable and output enable (address valid)

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Characteristic Curves

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HT23C256 MASK ROM ORDERING SHEET

Custom:

Input Medium:
EPROM DISK File (Mail Address: romfile@holtek.com.tw) OTHER

Memory Address
User No. Type/Ref. Name Q’ty Check Sum
Start End

Control Pin and Package Form Option:

(a) 28 Pin Type Pin 20: (1) CE (2) CE (3) OE1 (4) OE1
Pin 22: (1) OE (2) OE (3) NC
(b) Package Form: (1) Chip Form (2) 28 DIP (3) 28 SOP

Companion User No.

Package Marking :

Delivery Date : Q’ty:

CUSTOM CONFIRMED BY:

(NAME, DATE, POSITION & CO. CHOP)

HOLTEK CONFIRMED BY:

(SALES) (SALES MANAGER)

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